JPH07282593A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To attain the high speed of the access time of a memory device by improving the charging and discharging operation of a bit line at the time of switching an address. CONSTITUTION:At the time of switching an address, discharging transistors TD1, TD2 are turned ON with respect to memory transi stors TM1, TM 2...TMm selected by a column decoder 20 with a signal from an address transition detecting circuit 50 to ground memory transistors TM1, TM2...TMm and a bit line Cl and then electric charges charged on their parastic capacitances are made to bc discharged. At the time of a read-out thereafter, a charging transistor TC1 is turned ON to charge memory transistors TM1, TNT..., TMm form the direction opposite to a sense-amplifier 30. A data discrimination is performed by detecting the potential change of the bit line C1 due to the charging with the sense-amplifier 30.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to discharging the electric charges charged in the parasitic capacitance of a semiconductor memory transistor and then charging the memory transistor to speed up the data access time. About what you did.

[0002]

2. Description of the Related Art Conventionally, as this type of semiconductor memory device, there is a NAND type structure shown in FIG. In FIG. 4, TB1, TM1, TM2, ... TMm represent a row of memory transistors formed in a matrix, and TB1 is a block selection transistor, TM1, T.
M2 ... TMm are memory transistors. Mask R
In the case of the OM, the information to be stored is determined depending on whether each memory transistor is the enhancement type or the depletion type. Note that the memory transistors in the other columns and the column decoder that selects the columns are omitted.

The operation of this product will be briefly described below.
The D-type memory sets the word line RMI to H during read operation.
The word line connected to the gate electrode of the memory transistor to be read is set to the LO level while being set to the IGH level.
Set to W level. When the memory transistor turns on in the depletion type, the discharge path is formed by the memory transistor in that column, and therefore the potential of the bit line C1 does not rise and the sense amplifier 30 determines that the data is 0. On the contrary, when the memory transistor to be read is enhancement type and is turned off, the discharge path of the memory transistor of the column is not formed, and the potential of the bit line C1 rises due to the charge by the bit line charge circuit 40. When the sense amplifier 30 detects that the potential exceeds the determination threshold voltage (threshold level), the data is determined to be 1.

Here, there are parasitic capacitances, on-resistances of memory transistors, etc. on the paths for performing the charging and discharging, and the charging / discharging time is determined by the parasitic capacitances, time constants due to the on-resistances, etc. . That is, the charge is stored in the bit line charging circuit from the state in which the charge is accumulated to the time when the potential of the bit line C1 is set to be equal to or lower than the determination threshold voltage of the sense amplifier 30, or the state in which the charge is discharged,
The time for which 1 is equal to or higher than the determination threshold voltage of the sense amplifier 30 is a major factor in determining the access time of the entire memory.

On the other hand, unnecessary charges accumulated in the parasitic capacitance of the bit line are discharged once, and then the memory transistor is charged to reduce the above-mentioned influence due to the fluctuation of the bit line potential, thereby reducing the access time. It has been proposed that the speedup of the above is attempted (Japanese Patent Laid-Open No. 162597/1990).
Issue).

[0006]

However, the charging in this one is similar to that in FIG.
The bit line charging circuit 40 provided between 0 and the sense amplifier 30 is used. Therefore, the output of the bit line charging circuit 40 is connected to the input of the sense amplifier 30, and the input transistor (not shown) of the sense amplifier 30 is connected.
Therefore, the parasitic capacitance is also charged, which delays the data determination in the sense amplifier 30.

The present invention has been made in view of the above problems, and an object of the present invention is to improve the operation of charging a bit line as compared with the above-mentioned conventional one so as to further speed up the memory device.

[0008]

In order to achieve the above object, the present invention provides, in the invention described in claim 1, the storage state of a memory transistor selected from a plurality of memory transistors at the time of address switching. In a semiconductor memory device configured to read using a sense amplifier that detects a potential change of a bit line connected to an output end side of the memory transistor, in the address switching, the input end side of the memory transistor and the bit The charging circuit includes a discharging circuit for grounding the line to discharge the electric charge charged in the parasitic capacitance thereof, and a charging circuit for charging the memory transistor after the electric charge is discharged by the discharging circuit. Is connected to the input end side of the memory transistor, and charges the memory transistor from the input end side. It is characterized in Ukoto.

According to a second aspect of the present invention, the plurality of memory transistors are arranged in a matrix, and the memory transistors are selected by selecting a column for the plurality of memory transistors. It is performed by a column selection circuit and a row selection circuit that selects a row, and the column selection circuit is located between the bit line and the sense amplifier.

According to a third aspect of the present invention, the discharge circuit is arranged in the column and a first discharge circuit connected to the output terminal side of the memory transistor arranged in the column and the bit line. And a second discharge circuit connected to the input end side of the memory transistor. The invention according to claim 4 is characterized in that a charge permitting circuit for permitting charging by the charging circuit is provided for the selected memory transistor.

[0011]

According to the invention described in claims 1 to 3, at the time of address switching, the selected memory transistor and the bit line connected to the output end side thereof are grounded and their parasitic capacitances are charged. The generated electric charge is discharged, and then the memory transistor is charged from its input end side.

Therefore, the potential of the bit line is initially at the ground level, and by charging this from the input end side of the memory transistor, that is, in the direction opposite to the sense amplifier, the potential of the bit line is turned off when the memory transistor is off. If there is no change and the memory transistor is on, the potential of the bit line rises. In this way, by charging from the opposite direction to the sense amplifier, the phenomenon such as charge rearrangement due to the parasitic capacitance of the transistor in the sense amplifier does not occur, and whether the sense amplifier changes the potential on the bit line or not. The data can be judged with, and as a result, the access time can be shortened.

According to the invention of claim 4,
Since the charging time discrimination circuit that allows the charging circuit to charge the selected memory transistor is provided, only the selected memory transistor can be charged, and other unnecessary memory is charged. This has the effect of eliminating the operation.

[0014]

EXAMPLE FIG. 1 shows a structural example of this example. In this embodiment, the memory transistors TM1, TM2 ... TMm,
The block selection transistor TB1, the discharging transistors TD1 and TD2 that form the first and second discharging circuits, the charging transistor TC1 that forms the charging circuit, the address transition detection circuit 50 that detects the charging / discharging timing, and the memory transistor. A row decoder 10 as a row selection circuit for making a selection, a column decoder 20 as a column selection circuit, and a sense amplifier 30 for making a 1/0 determination of data.

Memory transistors TM1, TM2 ...
TMm is connected in series with the block selection transistor TB1 to form a NAND memory. The gates of these transistors are connected to the row decoder 10 by the word line R.
B1, RM1, RM2 ... Connected by RMm,
The output end of the NAND memory is connected to the bit line C1, and the bit line C1 is connected to the discharging transistor TD1 and the column decoder 20. The column decoder 20 is connected to the sense amplifier 30.

The input end side of the NAND type memory is connected to the charging transistor TC1 and the discharging transistor TD2. The charging transistor TC1 and the discharging transistors TD1 and TD2 are the address transition detection circuit 50.
Controlled by the output from. That is, a pulse signal is output from the address transition detection circuit 50 at the time of address switching, and when it is at the HIGH level, the discharge transistors TD1 and TD2 are turned on to form the discharge path of the bit line CI, and the discharge signal of the LOW level is set. At some time, the charging transistor TC1 is turned on so that the bit line C1 is charged.

Further, the output from the column decoder 21 (the LOW level is output when the column is selected) is applied to the charging transistor TC1 via the OR circuit 60, and the column corresponding to the read operation is provided. The charging operation is performed only for the memory, and the charging operation is not performed for the unnecessary memory. That is, the column decoder 21 constitutes a charging time determination circuit that allows the charging operation of the charging transistor TC1.

Incidentally, also in FIG. 1, as in FIG.
Although the memory transistors of other columns and the column decoders for selecting columns are omitted, the memory transistors are arranged in a matrix, and the memory transistors for reading data are selected by the row decoder and the column decoder. I am trying. Next, the operation of the above configuration will be described.

When the address is switched, the address transition detection circuit 50 first generates a pulse for a certain period of time. This signal causes the memory transistors TM1, TM2 ... TMm.
The block selection transistor TB1 discharges the electric charge charged in the parasitic capacitance through the discharging transistors TD1 and TD2. Further, at the time of read operation, the row decoder 10 outputs LOW to the memory transistor to be read.
In addition to applying a level signal, a HIGH level signal is applied to the gate of the block selection transistor TB1, and a HIGH level signal is applied to the other memory transistors. After the pulse output by the address transition detection circuit 50 disappears, the discharge transistors TD1 and T
D2 is turned off and the charging transistor TC1 is turned on. As a result, when the memory transistor to be read is of the depletion type, it is turned on, so that the potential of the bit line C1 rises, and conversely, when the memory transistor of the enhancement type is turned on, it is turned off.
The potential of does not change.

In the NAND type memory as shown in FIG. 4,
The potential of the bit line shows a complicated change such as rising, falling, rising and falling. This is a phenomenon that occurs in the process of redistributing the charge stored in the parasitic capacitance of the memory transistor at the time of address switching, which causes a long access time of the NAND memory.

On the other hand, in the configuration shown in FIG.
At the time of address switching, the bit line C1 from which unnecessary charges of the bit line C1 should be discharged is grounded once before data determination.
Therefore, since the bit line C1 is discharged once and then charging is started, the potential of the bit line C1 is initially at the GND (ground) level. By charging this from the direction opposite to the sense amplifier 30 (source side of the n-type memory transistor),
The potential of the bit line C1 does not change when the memory transistor is off, and the potential of the bit line rises when the memory transistor is on. As described above, by charging from the direction opposite to the sense amplifier 30, the phenomenon such as charge rearrangement due to the parasitic capacitance of the transistor in the sense amplifier 30, the decoder 20, etc. does not occur.

Therefore, when the memory transistor is turned on, the charge on the bit line monotonically increases, and when the memory transistor is turned off, the potential on the bit line does not change. Therefore, the sense amplifier 30 changes the potential on the bit line C1. Data can be determined depending on whether it has occurred or not, and the access time can be shortened by setting the determination threshold value low.

FIG. 2 shows the timing of signals. (A) shows the address signal, (b) shows the output of the address transition detection circuit 50, (c) shows the potential of the word line, and (d) shows the potential of the bit line. After the address is switched, a pulse signal indicating an address transition (a high level indicates a charging process, a low level indicates a discharging process) and a row decoder 10 determines a decoded word line signal.
It is not necessary to determine either of these two signals first, but the word line must be determined and the discharge process must be terminated after a predetermined time. The predetermined time is a time sufficient for the channels of the individual memory transistors to be formed and the electric charges stored in the parasitic capacitance to be discharged. After that, charging is started, and the bit line potential rises or does not change. The sense amplifier 30 determines data 1 when the bit line potential rises and exceeds the determination threshold voltage, and determines data 0 when the bit line potential does not change.

Although the NAND type memory has been described with reference to FIG. 1, the NOR type memory shown in FIG. Here, in the NOR type, there are no block selecting transistors, and the memory transistors TM1 are arranged in a matrix.
During the read operation, the word line R from the row decoder 10
By setting M1 to a HIGH level signal (LOW level signal for other memory transistors), the memory transistor TM1 is turned on if it is a depletion type and charges the bit line C1, and is turned off if it is an enhancement type. Then, the bit line C1 is discharged as shown in FIG.
Data determination can be performed in the same manner as.

Further, a mask RO for storing the memory transistor in the enhancement type or the depletion type.
Although the present invention is applied to M, the present invention may be applied to EPROM. In that case, it is necessary to lower the charging voltage than that of FIG. 1 so as to prevent discharge of stored charges. Further, in the present invention, charging and discharging are performed by the transistors TC1, TD1 and TD2.
However, other types may be used as long as they are a charging circuit and a discharging circuit for discharging and charging the memory transistor.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a signal waveform diagram of each part shown in FIG.

FIG. 3 is a circuit diagram showing another embodiment of the present invention.

FIG. 4 is a circuit diagram showing a conventional configuration.

[Explanation of symbols]

 10 row decoder 20, 21 column decoder 30 sense amplifier 50 address transition detection circuit TM1 to TMm memory transistors TD1 and TD2 discharging transistor TC1 charging transistor

Claims (4)

[Claims] 1. A sense amplifier is used for detecting a memory state of a selected memory transistor among a plurality of memory transistors at the time of address switching, and detecting a potential change of a bit line connected to an output end side of the memory transistor. In a semiconductor memory device configured to read by reading, a discharge circuit for grounding the input terminal side of the memory transistor and the bit line to discharge the charges charged in their parasitic capacitances at the time of the address switching, and the discharge circuit A charging circuit for charging the memory transistor after discharging electric charge, wherein the charging circuit is connected to an input end side of the memory transistor and charges the memory transistor from the input end side. A semiconductor memory device characterized by the above. 2. The plurality of memory transistors are arranged in a matrix, and the memory transistors are selected by selecting a column selection circuit and a row for selecting a column for the plurality of memory transistors. 2. The semiconductor memory device according to claim 1, wherein a row selection circuit is used, and the column selection circuit is located between the bit line and the sense amplifier. 3. The discharge circuit includes a first discharge circuit connected to the output end side of the memory transistor arranged in the column and the bit line, and an input end side of the memory transistor arranged in the column. The semiconductor memory device according to claim 2, wherein the semiconductor memory device is configured by a connected second discharge circuit. 4. A charging time determination circuit is provided which allows the selected memory transistor to be charged by the charging circuit and prohibits the charging by the charging circuit when the memory transistor is not selected. The semiconductor memory device according to any one of claims 1 to 3.