JP5263144B2 - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor system in which a data transfer rate equal to one chip LSI is attained at low cost. <P>SOLUTION: This semiconductor device includes: an internal clock generating circuit which receives a clock signal from the outside as an input signal and supplies internal clock signals; a clock transmission terminal which is arranged at one side of a chip and outputs the internal clock signals; a plurality of input/output terminals which are arranged at one side of the chip; a control clock generating circuit which generates input/output control clock signals based on the internal clock signals; a plurality of input/output circuits which outputs the data to the outside and receives the date from the outside through the input/output terminals, synchronizing with the input/output control clock signals; and a plurality of connection wirings with the same length which connect the control clock generating circuit to each of the plurality of input/output circuits. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention generally relates to semiconductor devices and semiconductor systems, and more particularly to a device (MCP: Multi-Chip Package) in which a memory chip and a logic chip are mixedly mounted in one package.

  Conventionally, when connecting a logic device and a memory device, both devices are generally connected via a common bus. FIG. 24A shows a conventional example of connection between a logic device and a memory device via a common bus. As shown in FIG. 24A, a logic device 501 and a memory device 502 are connected to a common bus 503, and data transfer between the logic device 501 and the memory device 502 is performed via this bus 503. .

  In order to increase the data processing speed, it is necessary to improve the data transfer speed between the logic device and the memory device. For this purpose, the number of signal lines of the bus 503 is increased in FIG. In addition, it is conceivable to increase the clock frequency for data transfer. The method of increasing the number of bus signal lines is not preferable because there is a problem that the area occupied by the bus signal lines and power consumption increase. In addition, the method of increasing the clock frequency for data transfer is problematic due to the limitation of the signal transmission capability of the bus signal line and the limitation of the data input / output speed of each device, and it is difficult to increase the frequency beyond these limitations. .

  As a technique for dealing with these problems, there is a one-chip LSI in which a logic device and a memory device are mounted on the same chip. FIG. 24B shows an example of a one-chip LSI in which a logic device and a memory device are integrated into one chip. As shown in FIG. 24B, a memory unit 511 and a logic unit 512 are mounted on the one-chip LSI 510. Since the memory portion 511 and the logic portion 512 are connected by wiring in the chip, high-speed data transfer can be performed.

  However, in order to manufacture a one-chip LSI, it is necessary to develop a new process technology for manufacturing the memory unit 511 and the logic unit 512 in the same process, resulting in an increase in cost. In addition, the memory unit 511 and the logic unit 512 manufactured by a common process are more likely to deteriorate in performance as compared to the case where each is manufactured by a dedicated process.

  When logic devices and memory devices are connected by a common bus in this way, it is difficult to increase the data transfer speed between both devices, and the logic unit and memory unit are mounted on the same chip. In a chip LSI, problems such as an increase in cost and a decrease in performance occur.

Accordingly, an object of the present invention is to provide a semiconductor device that is a logic chip or a memory chip used in a semiconductor system that achieves a data transfer speed equivalent to that of a one-chip LSI at a low cost.

The semiconductor device is disposed and the internal clock generating circuit for supplying an internal clock signal received clock signal received from the outside as an input, a clock transmission pin disposed on one side of the chip and outputs the internal clock signal, to the one side a plurality of input and output terminals, and a control clock generator circuit for generating an output control clock signal based on the internal clock signal, the outside via the input-output terminal in synchronization with the output control clock signal characterized in that it comprises a plurality of input and output circuits and a plurality of connection wirings same length which connects with each of said control clock generating circuit of the plurality of output circuits for performing data acquisition from the data output and external to the And

  According to at least one embodiment of the present invention, an input / output terminal necessary for data transfer and a clock transmission terminal for supplying a clock signal to the other party are arranged on one side of the chip. When arranged adjacent to each other, connection for data transfer can be easily performed, and the other chip can use the same clock signal. In addition, since the control clock generation circuit and the input / output circuit are connected by equal length wiring, the input / output circuit can ensure the synchronization related to data output and data capture. In addition, the control clock generation circuit performs phase control using a feedback loop that takes into account signal delay due to equal-length wiring, etc., so that a clock signal having a phase suitable for data capture and a phase suitable for data output can be obtained. A clock signal can be generated. Further, by dividing the frequency of the data capturing clock signal by 1 / N and performing N sets of data capturing operations, the data transfer frequency can be made N times the operating frequency inside the semiconductor device. In addition, by receiving the clock signal sent back to the chip on the other side and returning as it is, the synchronization of the data capture operation is performed based on this clock signal, thereby performing synchronization control taking into account the signal propagation delay between the chips I can do it.

It is a figure which shows the Example which mounted the logic chip and the memory chip in the same package by this invention. It is a circuit diagram which shows the circuit structure of the output circuit and input circuit of a high-speed I / O circuit. It is a figure which shows another Example which mounted the logic chip and the memory chip in the same package by this invention. It is a figure which shows another Example which mounted the logic chip and the memory chip in the same package by this invention. It is a figure which shows another Example which mounted the logic chip and the memory chip in the same package by this invention. FIG. 2 is a block diagram illustrating a configuration example of a memory chip in FIG. 1. FIG. 2 is a block diagram illustrating a configuration example of the memory chip in FIG. 1 when an external storage device I / O unit is provided. FIG. 2 is a block diagram illustrating a configuration of a memory / logic I / O unit including the high-speed I / O circuit of FIG. 1. FIG. 9 is a timing chart for explaining the operation of the high-speed I / O circuit on the memory chip side in FIG. 8. It is a block diagram which shows the structure of a DLL circuit. It is a circuit diagram which shows an example of the circuit structure of a phase comparator. It is a circuit diagram which shows an example of a circuit structure of a delay control circuit. It is a circuit diagram which shows an example of a circuit structure of a variable delay circuit. It is a block diagram which shows the structure of the phase shift circuit of FIG. It is a block diagram which shows another structural example of the I / O part between a logic chip and a memory chip of a memory chip. It is a block diagram which shows another example of a structure of the I / O part between a memory chip and a logic chip and a memory chip. FIG. 17 is a timing diagram for explaining an operation of the memory chip of FIG. 16. FIG. 3 is a diagram illustrating an example of an I / O terminal disposed on a side facing a logic chip in a memory chip. FIG. 2 is a diagram for explaining an ESD protection circuit of the semiconductor system of FIG. 1 according to the present invention. It is a figure which shows the Example at the time of using MOSFET as an ESD protection circuit. It is a figure which shows the Example at the time of using field MOSFET as an ESD protection circuit. It is a figure which shows the Example at the time of using a bipolar transistor as an ESD protection circuit. It is a figure which shows the Example at the time of using a diode as an ESD protection circuit. (A) is a figure which shows the prior art example of the connection of a logic device and a memory device via a common bus, (B) shows the example of the one-chip LSI which made the logic device and the memory device into one chip. FIG.

  Embodiments of the present invention will be described below with reference to the accompanying drawings.

  FIG. 1 shows an embodiment in which a logic chip and a memory chip are mounted in the same package according to the present invention. A semiconductor system 1 in FIG. 1 includes a logic chip 11 and a memory chip 12 mounted on a package 10. The logic chip 11 and the memory chip 12 are arranged adjacent to each other so that one side faces each other. The package 10 includes an external terminal 13 for signal input / output with the outside, a connection terminal 14 connected to the logic chip 11 and the memory chip 12, and the external terminal 13 and the connection terminal 14 are electrically connected ( Not shown).

  The package 10 further includes an I / O circuit power supply terminal 15, and the I / O circuit power supply terminal 15 receives the power supply voltage VCC and the ground voltage VSS from the outside via the connection terminal 14. An I / O circuit power supply line 16 that transmits the power supply voltage VCC and the ground voltage VSS extends from the I / O circuit power supply terminal 15 and is wired between the logic chip 11 and the memory chip 12. A terminal 17 is provided on the I / O circuit power supply line 16.

  The connection terminal 14 is electrically connected to the connection terminal 24 of the logic chip 11 and the memory chip 12 or the external storage device terminal 32 of the memory chip 12 by wire bonding or the like. Each of the logic chip 11 and the memory chip 12 includes a memory / logic I / O unit 20. The memory / logic I / O unit 20 includes a high-speed I / O circuit 21, an I / O terminal 22, and an I / O power supply terminal 23. The I / O terminal 22 and the I / O power supply terminal 23 are disposed on opposite sides of the logic chip 11 and the memory chip 12 that face each other. The I / O terminal 22 is electrically connected by wire bonding 25 between the logic chip 11 and the memory chip 12 so that opposing terminals correspond to each other. The I / O power supply terminal 23 is connected to a terminal 17 provided on the I / O circuit power supply line 16 by wire bonding or the like.

  Between the logic chip 11 and the memory chip 12, the I / O terminals 22 are connected so as to have the same wiring length, and are configured so as not to cause a timing shift between data. Further, since the terminals facing each other are connected as described above, the I / O terminals 22 are wired with the shortest wiring length. As will be described later, the high-speed I / O circuit 21 is configured by a CMOS type circuit, and enables high-speed data transfer between the logic chip 11 and the memory chip 12. The high-speed I / O circuit 21 is driven by the power supply voltage VCC and the ground voltage VSS supplied to the I / O power supply terminal 23. In the logic chip 11 and the memory chip 12, circuit portions other than the high-speed I / O circuit 21 are connected to the power supply voltage from the connection terminal 14 through the connection terminal 24 as a power supply path different from the I / O power supply terminal 23. And a ground voltage is supplied.

  By making the power supply of the high-speed I / O circuit 21 common between the logic chip 11 and the memory chip 12, the signal amplitude is made the same between the logic chip 11 and the memory chip 12, and reliable signal transmission is realized. Is possible. The common I / O power supply is supplied as a dedicated power supply as described above so that a difference from the power supply voltage of other circuit portions may occur. By supplying as a dedicated power supply, a stable power supply voltage can be supplied to the high-speed I / O circuit 21.

  Instead of connecting via the bus 503 as shown in FIG. 24A, the I / O terminals 22 are connected by wire bonding 25, so the wiring capacity between the logic chip 11 and the memory chip 12 is small and high speed. Data transfer can be realized. In addition, since it is not necessary to increase the drive capability of the output circuit of the high-speed I / O circuit 21, the area of the high-speed I / O circuit 21 can be reduced, and a large number of I / O terminals 22 are opposed to each other. Can be arranged.

  FIG. 2 is a circuit diagram showing the circuit configuration of the output circuit and the input circuit of the high-speed I / O circuit 21. As shown in FIG. 2, the output circuit of the high-speed I / O circuit 21 includes a PMOS transistor 26 and an NMOS transistor 27, and the input circuit includes a PMOS transistor 28 and an NMOS transistor 29. The reason why the input / output circuit is configured by the CMOS type circuit is as follows. In the conventional configuration shown in FIG. 24A, when the clock frequency for data transfer increases, the influence of signal reflection on the bus 503 increases. In order to reduce this influence, it is necessary to reduce the signal amplitude and to provide a bus termination resistor, which makes it difficult to use a CMOS type circuit. On the other hand, in the configuration of the present invention shown in FIGS. 1 and 2, since the output circuit and the input circuit are connected by the wire bonding 25, there is no need to consider the influence of reflection, and the CMOS type circuit. Therefore, a signal having a large amplitude can be used. Further, since the wiring capacity of the wire bonding 25 is small, high-speed data transfer is possible even if the current drive capability of the output circuit is not so high. Therefore, in the output circuit, the gate widths of the PMOS transistor 26 and the NMOS transistor 27 can be made relatively small, the area of the high-speed I / O circuit 21 is reduced, and a large number of I / O terminals 22 are arranged. I can do it. Further, since the power consumption per output circuit is small, even if a large number of I / O terminals 22 are arranged and the logic chip 11 and the memory chip 12 are connected by a large number of signal lines, a large power consumption may be required. In addition, high-speed data transfer can be realized by expanding the bus width.

  Referring back to FIG. 1, the memory chip 12 may further include an external storage device I / O unit 30 that performs data input / output with another storage device outside the package 10. The external storage device I / O unit 30 includes an external storage device I / O circuit 31 and an external storage device terminal 32. The external storage device terminal 32 is electrically connected to the external terminal 13 of the package 10 via the connection terminal 14 on the package 10 side. The external storage device terminal 32 is provided on the memory chip 12 on a side different from the side on which the I / O terminal 22 is provided. The external storage device I / O circuit 31 may be a normal I / O circuit that is compatible with the bus to which the semiconductor system 1 is connected, and performs high-speed data transfer similar to the high-speed I / O circuit 21. There is no need to be possible.

  FIG. 3 shows another embodiment in which a logic chip and a memory chip are mounted in the same package according to the present invention. 3, the same reference numerals as those in FIG. 1 are used to refer to the same components as those in FIG. A semiconductor system 1A of FIG. 3 includes a package 10A, a logic chip 11A, and a memory chip 12A. The embodiment of FIG. 3 differs from the embodiment of FIG. 1 in the way of supplying I / O power to the logic chip 11A and the memory chip 12A.

  The logic chip 11A of FIG. 3 includes a step-down circuit 33 that receives a power supply voltage and steps down the power supply voltage to generate a step-down voltage. The step-down circuit 33 receives the power supply voltage VCC from the terminal 17 that supplies the power supply voltage VCC via the I / O power supply terminal 23a, and supplies the step-down voltage VCCl to the I / O power supply terminal 23b. The I / O power supply terminal 23b on the logic chip 11A side is electrically connected to the I / O power supply terminal 23b on the memory chip 12A side via wire bonding or the like. The ground voltage VSS is directly supplied from the terminal 17 via the I / O power supply terminal 23 to each of the logic chip 11A and the memory chip 12A, as in the embodiment of FIG.

  With this configuration, when the high-speed I / O circuit 21 is driven using the step-down voltage VCCl obtained by stepping down the power supply voltage VCC, the voltage level of the step-down voltage VCCl is the same between the logic chip 11A and the memory chip 12A. It can be. Therefore, it is possible to realize reliable signal transmission by making the signal amplitude the same between the logic chip 11A and the memory chip 12A.

  Although the step-down circuit 33 is provided on the logic chip 11A side in FIG. 3, it goes without saying that it may be provided on the memory chip 12A side instead. Note that the configuration of the step-down circuit 33 is the same as that of a step-down circuit used in a conventional semiconductor system, and thus detailed description thereof is omitted. FIG. 4 shows still another embodiment in which a logic chip and a memory chip are mounted in the same package according to the present invention. 4, the same reference numerals as those in FIG. 1 are used to refer to the same components as those in FIG.

  The semiconductor system 1B of FIG. 4 includes a package 10B, two logic chips 11, and a memory chip 12B. The two logic chips 11 are arranged on both sides of the memory chip 12B, and an I / O circuit power supply line 16 is wired between each logic chip 11 and the memory chip 12B. The point that two logic chips 11 are mounted in the package 10B instead of one logic chip 11 is different from the case of the embodiment of FIG.

  As can be seen from FIG. 4, since the I / O terminals 22 are arranged on the left and right sides of the memory chip 12B, the external storage device I / O unit 30 for inputting / outputting data to / from other storage devices outside the package 10B. The memory chip 12B is provided on the lower side of the drawing. FIG. 5 shows still another embodiment in which a logic chip and a memory chip are mounted in the same package according to the present invention. In FIG. 5, the same numbers as those in FIG. 1 are used to refer to the same components as those in FIG.

  The semiconductor system 1C of FIG. 5 includes a package 10C, a logic chip 11C, and two memory chips 12. The two memory chips 12 are arranged on both sides of the logic chip 11C, and an I / O circuit power supply line 16 is wired between each memory chip 12 and the logic chip 11C. 1 is different from the embodiment of FIG. 1 in that two memory chips 12 are mounted in the package 10C instead of one memory chip 12.

  FIG. 6 is a block diagram illustrating a configuration example of the memory chip 12 of FIG. The memory chip (DRAM) 12 includes a clock buffer 41, a command decoder 42, a bank selection buffer 43, an address buffer 44, a data buffer 45, and a plurality (two in the figure) of banks 50. Each bank 50 includes a memory cell array 46, a row decoder 47, a sense amplifier / write amplifier 48, and a column decoder 49. The configuration of the DRAM in FIG. 6 is the same as the configuration of the conventional DRAM, and a buffer that simply transmits signals to and from the logic chip 11 such as the data buffer 45 has a high-speed input / output circuit shown in FIG. It differs from the conventional DRAM in that it is configured using the I / O circuit 21. Therefore, in the following description, the operation relating to the operation of the memory chip 12 will be the minimum necessary description.

  The clock buffer 41 supplies the supplied clock signal CLK to the command decoder 42, the bank selection buffer 43, the address buffer 44, and the data buffer 45. The command decoder 42 receives and decodes the command signals PD, / RAS, / CAS, and / WE in synchronization with the clock signal CLK. The operation of the memory chip 12 is controlled according to the decoding result. The bank selection buffer 43 takes in the address signal A in synchronization with the clock signal CLK. In response to the address signal A, one of the two banks 50 is selected. The address buffer 44 takes in the address signals A0 to Am in synchronization with the clock signal CLK, and supplies the row address and the column address to the row decoder and the column decoder.

  The row decoder 47 of the selected bank 50 accesses the designated row address of the memory cell array 46. In the case of data reading, this row address data is held in the sense amplifier / write amplifier 48. The column decoder 49 reads the data at the designated column address from the sense amplifier / write amplifier 48. The read data is supplied to the logic chip 11 via the data buffer 45. In the case of data writing, data supplied from the logic chip 11 to the data buffer 45 is stored in the memory cell array 46 via the sense amplifier / write amplifier 48.

  FIG. 7 is a block diagram illustrating a configuration example of the memory chip 12 when the external storage device I / O unit 30 is provided. In FIG. 7, the same elements as those of FIG. 6 are referred to by the same numerals, and a description thereof will be omitted. The memory chip 12 of FIG. 7 includes a transfer control circuit 55 and an external storage device data buffer 56 in addition to the bank 50 being replaced with the bank 50A in the memory chip of FIG. The bank 50A includes the same memory cell array 46, row decoder 47, sense amplifier / write amplifier 48, and column decoder 49 as the bank 50 of FIG. 6, in addition to a serial address counter 51, a serial decoder 52, and a serial access memory (SAM). 53 and a transfer gate 54. The serial address counter 51, serial decoder 52, serial access memory 53, and transfer gate 54 are serial data between the external memory device provided outside the semiconductor system 1 (FIG. 1) and the memory chip 12. In order to perform the transfer, it is provided in the bank 50A. Here, the external storage device data buffer 56 corresponds to the external storage device I / O unit 30 of FIG.

  The serial address counter 51 sequentially outputs consecutive addresses by counting up the addresses based on the addresses supplied from the address buffer 44. The serial decoder 52 decodes the addresses sequentially supplied from the serial address counter 51 and supplies them to the serial access memory 53. In the case of data writing, data supplied from the outside to the external storage device data buffer 56 is sequentially written to successive addresses in the serial access memory 53. At the timing controlled by the transfer control circuit 55, the transfer gate 54 is opened, and the data in the serial access memory 53 is transferred to the memory cell array 46 in parallel. The operation for data reading is the reverse of that for data writing.

  The configuration of the memory chip 12 in FIG. 7 is the same as the configuration used in a conventional dual port memory or the like, and a detailed description of each component is omitted. FIG. 8 is a block diagram showing a configuration of the memory-logic I / O unit 20 including the high-speed I / O circuit 21 of FIG. In FIG. 8, the same components as those in FIG. 1 are referred to by the same numerals, and a description thereof will be omitted.

  The memory chip 12 includes a T-CLK generation circuit 100, an R-CLK generation circuit 101, an equal length wiring 102, and a data buffer 103. The T-CLK generation circuit 100, the R-CLK generation circuit 101, the equal-length wiring 102, and the data buffer 103 constitute a high-speed I / O circuit 21, and the high-speed I / O circuit 21 and a plurality of I / O terminals 22 The memory-logic I / O unit 20 on the memory chip side is configured.

  The T-CLK generation circuit 100 generates a clock signal T-CLK for writing data to the memory chip 12 based on the clock signal I-CLK supplied from the logic chip 11 to the node N1 (I / O terminal 22). Circuit. The T-CLK generation circuit 100 includes a DLL (delay latch cicuit) circuit 111, a phase shift circuit 112, and a dummy isometric wiring 113. The DLL circuit 111 gives a phase delay of about 360 degrees to the signal N1 of the node N1 in consideration of the signal delay caused by the equal-length wiring 102 from the T-CLK generation circuit 100 to the data buffer 103. The phase-delayed signal N2 is further delayed in phase by 180 degrees by the phase shift circuit 112, and is supplied to the plurality of data buffers 103 via the equal-length wiring 102 as the write clock signal T-CLK. The dummy equal length wiring 113 is used in the DLL circuit 111 to simulate the influence of the phase delay caused by the equal length line 102.

  FIG. 9 is a timing chart for explaining the operation of the high-speed I / O circuit 21 on the memory chip side in FIG. The operation of the high-speed I / O circuit 21 will be described below with reference to FIGS. Let x be the phase delay due to the equal-length wiring 102. The signal N4 output from the DLL circuit 111 of the T-CLK generation circuit 100 is a signal having the same phase as the signal N2. When the signal N4 is input to the dummy equal length wiring 113, the signal N3 output from the dummy equal length wiring 113 becomes a signal delayed by the phase x from the signal N2. The DLL circuit 111 adjusts the phase of the signal N4 so that the signal N3 and the signal N1 have the same phase. Accordingly, the signal N2 having the same phase as the signal N4 is a signal delayed in phase by 360 degrees -x compared to the signal N1 (clock signal I-CLK). The signals N1 and N2 are shown in (F) and (G) of FIG. The phase of the signal N2 is delayed by 180 degrees by the phase shift circuit 112 to become the signal N5 (FIG. 9 (H)). The signal N5 is output from the T-CLK generation circuit 100, propagates through the equal-length wiring 102, and is supplied to the data buffer 103 as the signal N11. As shown in FIG. 9I, the signal N11 is a signal that is exactly 180 degrees out of phase with the clock signal I-CLK (signal N1) due to the phase delay x of the equal-length wiring 102.

  From the logic chip 11, a data signal having the same phase as the clock signal I-CLK is supplied to the memory chip 12. The signal N12 supplied to the node N12 (I / O terminal 22) of the memory chip 12 is shown in FIG. Since the signal N11 (FIG. 9 (I)) supplied to the data buffer 103 is exactly 180 degrees out of phase with the signal N12, the signal N12 is effective by using the signal N11 as a synchronization signal for data capture. It becomes possible to capture data at exactly the midpoint of the period. This makes it possible to perform highly reliable data writing even when a high-speed clock frequency is used.

  The R-CLK generation circuit 101 reads the data read clock signal R- when reading data from the memory chip 12 based on the clock signal I-CLK supplied from the logic chip 11 to the node N1 (I / O terminal 22). This is a circuit for generating CLK. The R-CLK generation circuit 101 includes a DLL circuit 114, a dummy isometric wiring 115, a dummy data buffer 116, and a dummy node 117. The DLL circuit 114 gives a phase delay of about 360 degrees to the signal N1 of the node N1 in consideration of the signal delay from the R-CLK generation circuit 101 to the I / O terminal 22. The phase-delayed signal N6 is supplied as a read clock signal R-CLK to the plurality of data buffers 103 via the equal-length wiring 102. The dummy equal length wiring 115 is used in the DLL circuit 114 to simulate the influence of the phase delay caused by the equal length line 102. The dummy data buffer 116 and the dummy node 117 are used to simulate the delay between the data buffer 103 and the I / O terminal 22, respectively.

  The total phase delay due to the equal-length wiring 102, the data buffer 103, and the I / O terminal 22 is y. The signal N7 output from the DLL circuit 114 of the R-CLK generation circuit 101 is a signal having the same phase as the signal N6. When the signal N7 is propagated to the dummy isometric wiring 115, the dummy data buffer 116, and the dummy node 117, the signal N9 output from the dummy node 117 is delayed by the phase y from the signal N7. The DLL circuit 114 adjusts the phase of the signal N7 so that the signal N9 and the signal N1 have the same phase. Therefore, the signal N6 having the same phase as the signal N7 is a signal delayed in phase by 360 degrees-y compared to the signal N1 (clock signal I-CLK). The signal N1 and the signal N6 (= N7) are shown in (A) and (B) of FIG. The phase of the signal N6 is delayed by the equal-length wiring 102 to become a signal N10 (= N8: FIG. 9C). The signal N10 is used as a synchronization signal in the data buffer 103, and the signal N12 (FIG. 9E) is output from the data buffer 103 to the I / O terminal 22. Since the signal N12 is delayed by the phase y with respect to the signal N6, the signal N12 has the same phase as the signal N9 shown in FIG. Since the signal N9 is in phase with the clock signal I-CLK (signal N1), the signal N12 output from the I / O terminal 22 is also in phase with the clock signal I-CLK.

  By using the R-CLK generation circuit 101 in this manner, read data can be read from the memory chip 12 with the same phase as the clock signal I-CLK supplied from the logic chip 11. In FIG. 8, the logic chip 11 includes a clock buffer 120, a DLL circuit 121, a phase shift circuit 122, a dummy equal length wiring 123, a DLL circuit 124, a dummy equal length wiring 125, a dummy data buffer 126, a dummy node 127, and A data buffer 128 is included. The clock buffer 120 receives a clock signal CLK input from the outside via the connection terminal 24 and outputs a clock signal I-CLK. The clock signal I-CLK is supplied to the memory chip 12 via the I / O terminal 22 and also supplied to the logic chip 11. In FIG. 8 showing the I / O unit 20 between the memory and logic, the components of the logic chip 11 other than the clock buffer 120 are the same as the components of the memory chip 12, and the operations at the time of reading and writing are also the same. Therefore, detailed description thereof is omitted.

  FIG. 10 is a configuration diagram showing the configuration of the DLL circuit 111. As shown in FIG. 10, the DLL circuit 111 includes a frequency divider 131, variable delay circuits 132 and 133, a phase comparator 134, and a delay control circuit 135. The signal input to the terminal IN is frequency-divided by the frequency divider 131 and converted into a frequency-divided signal suitable for phase comparison. The frequency-divided signal from the frequency divider 131 is delayed by the variable delay circuit 133, further delayed by the dummy equal-length wiring 113, and input to the phase comparator 134. The phase comparator 134 compares the phase of the frequency-divided signal directly supplied from the frequency divider 131 with the delayed frequency-divided signal, and sets the delay control circuit 135 so that the phases of both signals are the same. Control. The delay control circuit 135 is a circuit that sets the delay amount of the variable delay circuit 133.

  The signal input to the terminal IN is delayed by the variable delay circuit 132 and output from the terminal OUT. The delay amount of the variable delay circuit 132 is set to the same delay amount as that of the delay control circuit 133 by the delay control circuit 135. When the delay amount of the dummy equal-length wiring 113 is x, the phase delay amount of the variable delay circuit 133 is adjusted to 360 degrees -x. Therefore, the signal output from the terminal OUT is also delayed in phase by 360 degrees -x compared to the signal input to the terminal IN.

  FIG. 11 is a circuit diagram showing an example of the circuit configuration of the phase comparator 134. The signals S1 and S2 input to the phase comparator 134 are the frequency-divided signal supplied from the frequency divider 131 and the delayed frequency-divided signal supplied from the dummy equal length wiring 113 in FIG. . The phase comparator 134 includes NAND circuits 141 to 145, inverters 146 to 149, NAND circuits 150 and 151, inverters 152 and 153, a binary counter 154, an inverter 155, NAND circuits 156 and 157, and inverters 158 and 159. The NAND circuits 144 and 145 form a latch, and as shown in FIG. 11, in the initial state, two inputs are LOW and two outputs are HIGH. When the rising edge of the signal S1 is earlier than the rising edge of the signal S2, the output of the NAND circuit 143 becomes HIGH before the output of the NAND circuit 142. Therefore, the output of the NAND circuit 145 becomes LOW, and the output of the NAND circuit 144 remains HIGH. Since this state is latched, the state does not change even if the output of the NAND circuit 142 becomes HIGH thereafter by the rising edge of the signal S2. Therefore, when the phase of the signal S1 is advanced, the output of the inverter 149 becomes HIGH. Conversely, when the phase of the signal S2 is advanced, the output of the inverter 155 becomes HIGH.

  Here, the signal from the inverter 148 serves to return the latch state to the initial state by simultaneously setting the outputs of the NAND circuits 142 and 143 to LOW at an appropriate timing. Without such a configuration, when the phase of the signal S1 is advanced, the output of the NAND circuit 143 becomes HIGH, and then the output of the NAND circuit 142 becomes HIGH, and then the signal S1 becomes higher than the signal S2. By returning to LOW first, the state of the latch is reversed, and the output of the NAND circuit 144 becomes LOW. In order to avoid this, the outputs of the NAND circuits 142 and 143 are simultaneously set to LOW.

  The output signal of the inverter 148 is supplied to the binary counter 154. The two outputs of the binary counter 154 are signals that alternately become HIGH for each cycle of the input divided signals S1 and S2. The binary counter 154 includes NAND circuits 161 to 168 and inverters 169 to 171. Since the operation is within the range of the prior art, the description is omitted.

  Two outputs of the binary counter 154 are supplied to one input of the NAND circuits 150 and 151. The output from the inverter 149 is supplied to the other inputs of the NAND circuits 150 and 151. Further, the two outputs of the binary counter 154 are supplied to one input of the NAND circuits 156 and 157. The output from the inverter 155 is supplied to the other inputs of the NAND circuits 156 and 157.

  Therefore, when the phase of the signal S1 is ahead of that of the signal S2, HIGH pulses are alternately output from the inverters 152 and 153 that invert the outputs of the NAND circuits 150 and 151. Conversely, when the phase of the signal S2 is advanced, HIGH pulses are alternately output from the inverters 158 and 159 that invert the outputs of the NAND circuits 156 and 157.

  HIGH pulses alternately output from the inverters 152 and 153 or the inverters 158 and 159 are supplied to the delay control circuit 135 of FIG. 10 to adjust the delay amounts of the variable delay circuits 132 and 133. FIG. 12 is a circuit diagram showing an example of the circuit configuration of the delay control circuit 135. The delay control circuit 135 includes NOR circuits 201-0 to 201-n, inverters 202-1 to 202-n, NAND circuits 203-1 to 203-n, NMOS transistors 204-1 to 204-n, and NMOS transistor 205-1. Through 205-n, NMOS transistors 206-1 through 206-n, and NMOS transistors 207-1 through 207-n. When the reset signal R is set to LOW, the delay control circuit 135 is reset. That is, when the reset signal R becomes LOW, the outputs of the NAND circuits 203-1 to 203-n become HIGH, and the outputs of the inverters 202-1 to 202-n become LOW. Each pair of the NAND circuits 203-1 to 203-n and the inverters 202-1 to 202-n forms a latch by using the outputs of each other as inputs. Therefore, the initial state set by the reset signal R is maintained even when the reset signal R returns to HIGH.

  In this initial state, as shown in FIG. 12, the output P (0) of the NOR circuit 201-0 is HIGH, and the outputs P (1) to P (n) of the NOR circuits 201-1 to 201-n are LOW. That is, only the output P (0) is HIGH. When it is necessary to increase the delay amount, HIGH pulses are alternately supplied to the signal lines A and B. First, when a HIGH pulse is supplied to the signal line B, the NMOS transistor 204-1 is turned on. At this time, since the NMOS transistor 206-1 is on, the output of the NAND circuit 203-1 is connected to the ground, and is forcibly changed from HIGH to LOW. Therefore, the output of the inverter 202-1 becomes HIGH, and this state is held in the latch composed of the NAND circuit 203-1 and the inverter 202-1. At this time, the output P (0) changes from HIGH to LOW, and the output P (1) changes from LOW to HIGH. Therefore, in this state, only the output P (1) becomes HIGH.

  Next, when a HIGH pulse is supplied to the signal line A, the NMOS transistor 204-2 is turned on. At this time, since the NMOS transistor 206-2 is turned on, the output of the NAND circuit 203-2 is connected to the ground and is forcibly changed from HIGH to LOW. Therefore, the output of the inverter 202-2 becomes HIGH, and this state is held in the latch composed of the NAND circuit 203-2 and the inverter 202-2. At this time, the output P (1) changes from HIGH to LOW, and the output P (2) changes from LOW to HIGH. Accordingly, in this state, only the output P (2) becomes HIGH.

  Thus, by supplying HIGH pulses alternately to the signal lines A and B, it is possible to shift only one HIGH output from the outputs P (0) to P (n) to the right one by one. I can do it. When it is necessary to reduce the delay amount, HIGH pulses are alternately supplied to the signal lines C and D. Since the operation in this case is the reverse of the above-described operation, detailed description is omitted.

  By alternately supplying HIGH pulses to the signal lines C and D, only one of the outputs P (0) to P (n) can be shifted to the left one by one. By supplying these output signals P (1) to P (n) to the variable delay circuits 132 and 133 in FIG. 10, the delay amount of the signal is adjusted.

  FIG. 13 is a circuit diagram showing an example of the circuit configuration of the variable delay circuit 132. The configuration of the variable delay circuit 133 is the same as the configuration of the variable delay circuit 132. The variable delay circuit 132 includes an inverter 210, NAND circuits 211-1 to 211-n, NAND circuits 212-1 to 212-n, and inverters 213-1 to 213-n. Here, the NAND circuits 212-1 to 212-n and the inverters 213-1 to 213-n constitute a delay element array.

  An inverted signal of the input signal SI is supplied from the inverter 210 to one input of the NAND circuits 211-1 to 211-n, and signals P (1) to P (n) are supplied to the other input. Of the signals P (1) to P (n), a signal that is only HIGH is P (x). Among the NAND circuits 211-1 to 211-n, those other than the NAND circuit 211-x have a high level because one input is LOW. Of the NAND circuits 212-1 to 212-n that receive this HIGH level at one input, those other than the NAND circuit 212-x function as an inverter for the other input.

  Therefore, the delay element array on the left side of the NAND circuit 212-x transmits a fixed HIGH level applied to one input of the NAND circuit 212-n. Therefore, one input of the NAND circuit 212-x is HIGH. An input signal SI is supplied to the other input of the NAND circuit 212-x via the inverter 210 and the NAND circuit 211-x. Therefore, the delay element array from the NAND circuit 212-x to the inverter 213-1 propagates the input signal SI while delaying, and a delayed signal is obtained as the output signal SO. The output signal SO in this case is delayed from the input signal SI by a delay time corresponding to x delay elements.

  Thus, the phase comparator 134 shown in FIG. 11 compares the phases of the frequency-divided signals, and based on the comparison result, the delay control circuit 135 shown in FIG. 12 outputs the output signals P (1) to P (n ), The position of the only HIGH signal is controlled, and the delay amount of the variable delay circuit 132 (133) shown in FIG. 13 is set by the signals P (1) to P (n). Thus, the DLL circuit 111 of FIG. 10 can generate and output a signal having a desired delay amount.

  FIG. 14 is a configuration diagram showing the configuration of the phase shift circuit 112 of FIG. As shown in FIG. 14, the phase shift circuit 112 includes variable delay circuits 250 and 251, a phase comparator 252, and a delay control circuit 253. The signal input to the input terminal IN is delayed by the delay amount T by the variable delay circuit 250. The signal having the delay amount T output from the variable delay circuit 250 is further delayed by the variable delay circuit 251 by the same delay amount T as the delay amount of the variable delay circuit 250. The phase of the signal having the delay amount 2T output from the variable delay circuit 251 is compared with the signal input to the input terminal IN by the phase comparator 252. The phase comparator 252 controls the delay amount T of the variable delay circuits 250 and 251 via the delay control circuit 253 so that both signals have the same phase.

  Therefore, the delay amounts of the variable delay circuits 250 and 251 are adjusted so that the delay amount 2T is equal to 360 degrees in phase. As a result, a signal obtained by delaying the input signal in phase by 180 degrees is obtained at the output terminal OUT of the phase shift circuit 112. The configurations of the variable delay circuits 250 and 251, the phase comparator 252, and the delay control circuit 253 are the same as the configurations of the variable delay circuits 132 and 133, the phase comparator 134, and the delay control circuit 135 of the DLL circuit 111, respectively. is there.

  When the signal frequency is fixed, the phase shift circuit 112 may be a fixed delay circuit that delays the signal by a fixed delay amount. FIG. 15 is a block diagram illustrating another configuration example of the memory-logic I / O unit 20 of the logic chip 11 and the memory chip 12. In FIG. 15, the same components as those of FIG. 8 are referred to by the same numerals, and a description thereof will be omitted.

  Compared with the configuration of FIG. 8, the configuration of FIG. 15 has a configuration in which the clock signal I-CLK supplied from the logic chip 11 to the memory chip 12 is returned from the memory chip 12 to the logic chip 11 via the wire bonding 25 a. Has been. The returned clock signal I-CLK is used to generate a clock signal T-CLK used when the data read from the memory chip 12 is taken into the logic chip 11.

  The configuration of FIG. 8 is a configuration on the condition that there is no signal propagation delay or is negligibly small in the wire bonding 25 between the logic chip 11 and the memory chip 12. In this case, even when there is a non-negligible delay in the wire bonding 25, the clock signal I-CLK is returned in order to perform reliable data transfer.

  Here, the signal delay due to the wire bonding 25 or 25a is T1. The clock signal I-CLK supplied from the logic chip 11 to the memory chip 12 has a delay amount T1 due to the wire bonding 25. In the case of data writing to the memory chip 12, the data signal propagated from the logic chip 11 to the memory chip 12 is also delayed by the delay amount T 1 by the wire bonding 25. Therefore, there is no problem in taking data having the delay amount T1 into the memory chip 12 using the write clock signal T-CLK obtained from the clock signal I-CLK having the delay amount T1.

  However, the data read from the memory chip 12 in synchronization with the clock signal I-CLK having the delay amount T1 is further delayed by the delay amount T1 before reaching the logic chip 11. Therefore, compared with the clock signal I-CLK without delay, the data reaching the logic chip 11 is delayed by the delay amount 2T1. Therefore, as in the configuration of FIG. 8, if the data of the delay amount 2T1 is captured in the logic chip 11 using the write clock signal T-CLK obtained from the clock signal I-CLK without the delay amount, the data capture is related. It will not be synchronized.

  In the configuration of FIG. 15, the clock signal I-CLK transmitted from the logic chip 11 to the memory chip 12 is further returned to the logic chip 11 through the wire bonding 25a, whereby the clock signal I-CLK with a delay amount 2T1 is returned. Can be obtained. The logic chip 11 takes in the data of the delay amount 2T1 sent from the memory chip 12 using the write clock signal T-CLK obtained from the clock signal I-CLK of the delay amount 2T1 as a synchronization signal. With such a configuration, even when the signal delay between the logic chip 11 and the memory chip 12 cannot be ignored, reliable and high-speed data transfer can be performed.

  FIG. 16 is a block diagram showing still another configuration example of the memory-logic I / O unit 20 of the logic chip 11 and the memory chip 12. In FIG. 16, the same components as those of FIG. 8 are referred to by the same numerals, and a description thereof will be omitted. In the configuration of FIG. 16, the data write clock signal T-CLK (A) obtained by dividing the frequency of the data write clock signal T-CLK used in the configuration of FIG. And T-CLK (B) are generated, and external data is fetched using the data write clock signals T-CLK (A) and T-CLK (B).

  Since the data thus captured is switched at a half frequency compared to the original clock signal I-CLK, the operating frequency of the internal circuits of the logic chip 11 and the memory chip 12 is halved. I can do it. That is, while the logic chip 11 and the memory chip 12 are operated at a speed that can be conventionally achieved, high-speed data transfer is realized between the logic chip 11 and the memory chip 12 using a high-speed clock having a frequency higher than the operating frequency. I can do it. That is, in the configuration in which the logic chip 11 and the memory chip 12 are mounted on the same package 10 and the opposing I / O terminals 22 are connected to each other by wire bonding 25 as shown in FIG. You can save it.

  In the memory chip 12, the frequency divider 301 of the T-CLK generation circuit 100a divides the signal N5 (clock signal T-CLK) by ½. The frequency-divided clock signal T-CLK (A) is supplied to the latch-A 305 through the equal-length wiring 102a. The frequency-divided clock signal T-CLK (B) is supplied to the latch B306 via the equal-length wiring 102a. The latch-A 305 and the latch-B 306 are latches for fetching data from the logic chip 11, and the data output buffer 304 is used for data transmission.

  FIG. 17 is a timing chart for explaining the operation of the memory chip 12 of FIG. As shown in FIG. 17, the clock signals N21 and N22 divided by 1/2 are generated, and the clock signals N21 and N22 are delayed by the equal-length wiring 102a, and the data signals are generated. Capture N12. In this way, the data taken into the latch-A 305 and the latch-B 306 is switched at a frequency half that of the clock signal I-CLK (signal N1).

  In the examples of FIGS. 16 and 17, the frequency divider 301 is divided by 2, but N divided by 2 instead of divided by 2 and N clock signals whose phases are shifted by 360 degrees / N from each other. It is good also as composition to generate. In this case, N latches for data capture are provided for each I / O terminal 22. Returning to FIG. 16, in the logic chip 11, the frequency divider 302 divides the signal N <b> 5 ′ (clock signal T-CLK) by ½. Since operations related to data capture and data transmission are the same as the operations of the memory chip 12, description thereof will be omitted.

  The logic chip 11 in FIG. 16 further includes a PLL circuit 303. The PLL circuit 303 multiplies the frequency of the clock signal CLK supplied from the outside via the connection terminal 24 to generate a high-frequency clock signal I-CLK. Since the clock signal CLK supplied from the outside is supplied to the semiconductor system 1 of FIG. 1 via the bus, a signal frequency as high as that cannot be used. Therefore, with the configuration as shown in FIG. 16, a high-frequency clock signal I-CLK can be generated inside the semiconductor system 1, and high-speed data transfer can be performed between the logic chip 11 and the memory chip 12. Note that the circuit configuration of the PLL circuit 303 is within the scope of the prior art, and thus description thereof is omitted.

  8, 15, and 16, the chip that receives the clock signal CLK from the outside is the logic chip 11. Conversely, the memory chip 12 receives the clock signal CLK from the outside. It may be a configuration. FIG. 18 is a diagram illustrating an example of the I / O terminal 22 arranged on the side facing the logic chip 11 in the memory chip 12.

  When the memory chip 12 is a memory chip having a 2 M power bit × N word × 2 L power bank configuration, the I / O terminal 22 has one clock reception terminal (or clock transmission terminal) CLK, M Address signal terminals and L bank selection signal terminals A00 to A19, N data input / output terminals DQ00 to DQ31, three command selection terminals WE, CAS and RAS, one power-down signal Terminal PD, DM signal terminals DM0 to DM7 prepared in byte units, power supply terminals VSS, VCC, VSSQ, and VCCQ. Furthermore, the memory chip 12 may include a clock return terminal RCLK that returns the supplied clock signal to the logic chip 11 (or receives the supplied clock signal from the logic chip 11). Here, the signals received by the DM signal terminals DM0 to DM7 are signals for masking each byte so as not to write data.

  Some of the power supply terminals VSS, VCC, VSSQ, and VCCQ may be dedicated power supply terminals for the DLL circuits 111, 114, 121, and / or the PLL circuit 303. Since the operation of the DLL circuit and the PLL circuit is delicate and vulnerable to disturbances, it is possible to perform reliable clock control by providing a dedicated power source for the DLL circuit and / or the PLL circuit.

  19 is a diagram for explaining an ESD protection circuit of the semiconductor system of FIG. 1 according to the present invention. In FIG. 19, the same components as those in FIG. 1 are referred to by the same numerals, and a description thereof will be omitted. Normally, an ESD protection circuit is provided at a terminal of a semiconductor chip in order to prevent device destruction due to ESD (electrical-static discharge). ESD includes discharge that occurs when a charged metal contacts the device during wire bonding, discharge that occurs when a charged human body touches the device, and discharge that occurs when the device package is charged and contacts other objects, etc. Is mentioned.

  As shown in FIG. 1 or FIG. 19, when the logic chip 11 and the memory chip 12 are mounted on the package 10, the I / O terminal 22 (pad) for connecting between the logic chip 11 and the memory chip 12 is the package 10. It is covered with and is not touched by a charged human body. Therefore, the ESD protection circuit 402 provided for the logic chip / memory chip I / O may be relatively small as compared with the ESD protection circuit 401 provided for the external terminal 13. That is, the ESD protection circuit 402 only needs to be able to pass a relatively small amount of current.

  Thus, if the ESD protection circuit 402 can be reduced, there is an advantage that the chip area can be reduced. In addition, since the parasitic capacitance can be reduced, the signal switching speed can be increased. FIG. 20 is a diagram illustrating an embodiment in which a MOSFET is used as an ESD protection circuit.

  The ESD protection circuit 401 or 402 includes an NMOS transistor 410. When a voltage equal to or higher than the signal level is applied to the pad (connection terminal 24 or I / O terminal 22), the NMOS transistor 410 is turned on to prevent device destruction. In the case of the ESD protection circuit 401, that is, the circuit used for the connection terminal 24 connected to the external terminal 13, the gate width of the NMOS transistor 410 may be about 1000 μm. In the case of the ESD protection circuit 402, that is, in the case of a circuit used for the I / O terminal 22, the gate width of the NMOS transistor 410 may be about 500 μm.

  FIG. 21 is a diagram showing an embodiment in which a field MOSFET is used as an ESD protection circuit. The ESD protection circuit 401 or 402 includes a field MOSFET 411 having a high threshold voltage. When a voltage equal to or higher than the signal level is applied to the pad (connection terminal 24 or I / O terminal 22), the field MOSFET 411 is turned on to prevent device destruction. In the case of the ESD protection circuit 401, that is, a circuit used for the connection terminal 24 connected to the external terminal 13, the gate width of the field MOSFET 411 may be about 1000 μm. In the case of the ESD protection circuit 402, that is, in the case of a circuit used for the I / O terminal 22, the gate width of the field MOSFET 411 may be about 500 μm.

FIG. 22 is a diagram showing an embodiment in which a bipolar transistor is used as an ESD protection circuit. The ESD protection circuit 401 or 402 includes a bipolar transistor 412. When a voltage equal to or higher than the signal level is applied to the pad (connection terminal 24 or I / O terminal 22), the bipolar transistor 412 conducts to prevent device destruction. In the case of the ESD protection circuit 401, that is, a circuit used for the connection terminal 24 connected to the external terminal 13, the emitter area of the bipolar transistor 412 may be about 300 μm ² . In the case of the ESD protection circuit 402, that is, the circuit used for the I / O terminal 22, the emitter area of the bipolar transistor 412 may be about 100 μm ² .

FIG. 23 is a diagram illustrating an embodiment in which a diode is used as an ESD protection circuit. The ESD protection circuit 401 or 402 includes a diode 413. When a voltage equal to or higher than the signal level is applied to the pad (connection terminal 24 or I / O terminal 22), the diode 413 is turned on to prevent device destruction. In the case of the ESD protection circuit 401, that is, a circuit used for the connection terminal 24 connected to the external terminal 13, the junction area of the diode 413 may be about 300 μm ² . In the case of the ESD protection circuit 402, that is, in the case of a circuit used for the I / O terminal 22, the junction area of the diode 413 may be about 100 μm ² .

  As mentioned above, although this invention was demonstrated based on the Example, this invention is not limited to the said Example, A various deformation | transformation is possible within the range as described in a claim.

1 Semiconductor system 1
10 Package 11 Logic Chip 12 Memory Chip 13 External Terminal 14 Connection Terminal 15 I / O Circuit Power Supply Terminal 16 I / O Circuit Power Supply Line 17 Terminal 20 Memory / Logic I / O Unit 21 High-Speed I / O Circuit 22 I / O Terminal 23 I / O power supply terminal 24 Connection terminal 25 Wire bonding 30 External storage device I / O unit 31 External storage device I / O circuit 32 External storage device terminal 33 Step-down circuit 41 Clock buffer 42 Command decoder 43 Bank selection buffer 44 address buffer 45 data buffer 46 memory cell array 47 row decoder 48 sense amplifier / write amplifier 49 column decoder 50, 50A bank 51 serial address counter 52 serial decoder 53 serial access memory 54 transfer gate 55 transfer control circuit 56 external storage Device data buffer 100 T-CLK generation circuit 101 R-CLK generation circuit 102 Equal length wiring 103 Data buffer 111 DLL circuit 112 Phase shift circuit 113 Dummy equal length wiring 114 DLL circuit 115 Dummy equal length wiring 116 Dummy data buffer 117 Dummy node 128 data buffer 120 clock buffer 121 DLL circuit 122 phase shift circuit 123 dummy equal length wiring 124 DLL circuit 125 dummy equal length wiring 126 dummy data buffer 127 dummy node 128 data buffer 401 ESD protection circuit 402 ESD protection circuit 501 logic device 502 memory device 503 bus

Claims (12)

An internal clock generating circuit for supplying an internal clock signal received clock signal received from the outside as an input, a clock transmission pin disposed on one side of the chip and outputs the internal clock signal, a plurality of input disposed on the one side an output terminal, and a control clock generator circuit for generating an output control clock signal based on the internal clock signal, the data output in synchronization with the output control clock signal to the outside through the input-output terminal and a semiconductor device which comprises a plurality of connection wires of the same length which connects the plurality of input and output circuits for performing data acquisition, and each of the said control clock generating circuit a plurality of input and output circuits from the outside . Said internal clock generating circuit, a semiconductor device according to claim 1, wherein the by multiplying the frequency of the received clock signal to generate the internal clock signal. 2. The semiconductor device according to claim 1, wherein the control clock generation circuit includes a first clock generation circuit that generates a data output clock signal as the input / output control clock signal. The first clock generation circuit outputs a signal whose phase is shifted from the internal clock signal by a total delay of a first delay of the plurality of connection wirings and a second delay of the plurality of input / output circuits. 4. The semiconductor device according to claim 3, wherein the semiconductor device outputs the data output clock signal. The first clock generation circuit, a phase adjustment circuit for outputting a delayed signal by adjusting the phase of the internal clock signal, outputting a first signal by the phase delay the from the delayed signal a first delay amount first means for including a second means for outputting a second signal delayed in the first the from the signal of the second delay amount corresponding phase, said phase adjusting means and the second signal and the the semiconductor device according to claim 4, wherein in which the internal clock signal and outputs the delayed signal to adjust the phase of the delayed signal such that the same phase as the data output clock signal. 2. The semiconductor device according to claim 1, wherein the control clock generation circuit includes a second clock generation circuit that generates a data capture clock signal as the input / output control clock signal. The second clock generation circuit uses a signal whose phase is shifted from the internal clock signal by the total delay of the first delay and the second delay of the plurality of connection wirings as the data capture clock signal. 7. The semiconductor device according to claim 6, wherein the semiconductor device is output. Said second clock generating circuit, said phase adjustment circuit for outputting a delayed signal by adjusting the phase of the internal clock signal, outputting a first signal delayed in the first delay amount by a phase from the delay signal first means for including a second means for delaying said delayed signal by the second delay amount, so that the phase adjusting means comprises the first signal and the internal clock signal are in phase adjusts the phase of the delay signal, said second means semiconductor according to claim 7, wherein the output as the data capture clock signal by delaying the delayed signal by the second delay amount apparatus. 9. The semiconductor device according to claim 8, wherein the second means is a phase shift circuit that delays the delay signal by a phase of 180 degrees. 9. The semiconductor device according to claim 8, wherein the second means is a fixed delay circuit that delays the delay signal by a predetermined fixed delay amount. The second clock generation circuit further includes a 1 / N frequency divider, and generates a plurality of frequency-divided clock signals whose phases are mutually shifted by 360 degrees / N at a frequency of 1 / N of the frequency of the internal clock signal. each of said plurality of input and output circuits includes N input circuits, said N input circuits corresponding semiconductor device according to claim 8, wherein the use of the divided clock signal as a synchronization signal . Further comprising the clock return terminals provided on one side for receiving the internal clock signal sent from the clock transmission pin after a predetermined delay time, said control clock generating circuit, before using the internal clock signal a first clock generating circuit for generating a clock signal for data output as fill the output control clock signal, a clock signal for data capture as the output control clock signal with a clock signal received on the clock return terminal 2. The semiconductor device according to claim 1, further comprising second clock generation means for generating.

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