JP5262185B2 - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device for suppressing deterioration in a yield relating to formation of an alignment mark, and to provide a method of manufacturing the semiconductor device. <P>SOLUTION: An opening 6 reaching the surface of an insulating board 1 is formed in a GaN layer 2 and an n-type AlGaN layer 3. An Ni layer 8 connected to a source electrode 4s is formed as a conductive etching stopper in the opening 6, and the alignment mark 8a is formed on the n-type AlGaN layer 3. A photoresist film is formed on the back of the insulating board 1, and a photomask in which a light-shielding section for vias and that for alignment are provided is aligned with the alignment mark 8a as a reference. The photomask is used to form a resist pattern for forming via holes from the photoresist film. The resist pattern for forming via holes is used to form a via hole 1s reaching the Ni layer 8 from the back side of the insulating board 1 on the insulating board. Then, via wiring 16 is formed. <P>COPYRIGHT: (C)2009,JPO&amp;INPIT

Description

The present invention, GaN-based (gallium nitride) high electron mobility transistors: about (HEMT high electron mobility transistor)) The method of manufacturing a semiconductor equipment provided with a like.

  In recent years, GaN-based semiconductor devices such as GaN-based HEMTs are expected to be applied as high breakdown voltage / high-speed devices due to their physical characteristics. In order to improve the high-frequency characteristics of the GaN-based semiconductor device, a via wiring structure for reducing source inductance and radiating heat is necessary.

  In the GaN-based semiconductor device, a GaN layer and an AlGaN layer are formed on a silicon carbide (SiC) substrate by crystal growth. For this reason, in order to form the via wiring structure portion, it is necessary to process a SiC substrate made of a difficult-to-etch material and particularly difficult to wet-etch by a dry etching method. In controlling the depth of the via hole, a metal film made of nickel (Ni) or the like having a high etching selectivity with respect to SiC is formed on the surface side of the substrate, and this is used as an etching stopper. This is because over-etching is preferable in order to obtain a high yield. If the depth of the via hole is to be controlled by the etching time, the dry etching etching rate is likely to vary within the plane of the wafer and also varies depending on the via diameter (aspect ratio), so that it is difficult to obtain a high yield.

  Further, conventionally, in order to align the etching stopper and the via hole with high accuracy, an alignment mark is formed on the surface side of the substrate simultaneously with the formation of the etching stopper. Then, using this alignment mark as a reference, alignment of a photomask used for forming a via hole is performed using a double-side aligner.

  Here, a conventional method for forming a via hole in the via wiring structure will be described. 10A to 10E are cross-sectional views illustrating a conventional method of forming a via hole in the order of steps.

  First, as shown in FIG. 10A, an etching stopper 108e and an alignment mark 108a are formed on the SiN layer 105 through the seed layer 107 from the same Ni layer. The planar shape of the etching stopper 108e is a circle having a diameter of 200 μm, and the planar shape of the alignment mark 108a is a cross shape. Note that the GaN layer 102 and the AlGaN layer 103 are formed on the SiC substrate 101, and the SiN layer 105 is formed on the AlGaN layer 103. Although not shown, a semiconductor element such as HEMT is already formed in the active region. In addition,

  Next, a surface protective layer (not shown) is formed on the entire surface of the SiC substrate 101 and the front and back of the SiC substrate 101 are reversed. Thereafter, as shown in FIG. 10B, seed layer 112 is formed on the back surface of SiC substrate 101. Subsequently, a photoresist film 155 f is formed on the seed layer 112.

  Next, as illustrated in FIG. 10C, the photoresist film 155f is exposed and developed using the photomask 121 including the light transmitting portion 121a, the via light shielding portion 121b, and the alignment light shielding portion 121c, thereby forming a photoresist film. A resist pattern 155 is formed from 155f. The planar shape of the via light shielding portion 121b is a circle having a diameter of 100 μm, and the planar shape of the alignment light shielding portion 121c is a cross shape. In addition, the margin between the alignment mark 108a and the alignment light shielding portion 121c is about 10 μm in any direction. In this exposure, alignment between the alignment mark 108a and the alignment light-shielding portion 121c is performed using a double-side aligner.

  Thereafter, as shown in FIG. 10D, a Ni layer 113 is formed on the seed layer 112 in a region excluding the resist pattern 155 by electroplating.

  Subsequently, as shown in FIG. 10E, the resist pattern 155 is removed. Next, the seed layer 112 exposed from the Ni layer 113 is removed by performing ion milling.

Thereafter, as shown in FIG. 10F, via holes 101s are formed by performing dry etching of the SiC substrate 101, the GaN layer 102, and the AlGaN layer 103 using the Ni layer 113 as a metal mask. At this time, an opening 101h reaching the alignment mark 108a is also formed. In dry etching of SiC substrate 101, a mixed gas of sulfur hexafluoride (SF ₆ ) gas and oxygen (O ₂ ) gas is used. In the dry etching of the GaN layer 102 and the AlGaN layer 103, a Cl ₂ gas is used.

  In such a method, since the diameter of the etching stopper 108e is 200 μm and the diameter of the via light shielding portion 121b is 100 μm, a margin between them is sufficient. On the other hand, since the alignment accuracy of a general double-sided aligner is ± 1 to 5 μm, the margin between the alignment mark 108a and the alignment light shielding portion 121c is about 10 μm in any direction as described above. . Therefore, the edge of the opening 101h and the edge of the alignment mark 108a are close to each other. For this reason, when a slight shift occurs during alignment, or when etching spread (side etching, bowing) occurs during dry etching of the SiC substrate 101, the GaN layer 102, and the AlGaN layer 103, as shown in FIG. As described above, the edge of the opening 101h may be displaced from the alignment mark 108a. In such a case, the alignment mark 108a is subsequently removed to cause contamination, or an acid or the like may permeate from the place where the alignment mark 108a is present, causing a failure in the HEMT. That is, it is difficult to obtain a sufficient yield.

  Although it is conceivable to simply increase the margin, this will reduce the alignment accuracy, and the yield will decrease at that point.

Japanese Patent Laid-Open No. 6-244073 JP-A-7-66384

An object of the present invention is to provide a semiconductor equipment manufacturing method capable of suppressing the reduction in yield associated with the formation of the alignment mark.

  As a result of intensive studies to solve the above-mentioned problems, the present inventor has come up with the following aspects of the invention.

  In the first method for manufacturing a semiconductor device, a compound semiconductor layer is formed on a substrate, and then a gate electrode, a source electrode, and a drain electrode are formed on the compound semiconductor layer. Next, an opening reaching at least the surface of the substrate is formed in the compound semiconductor layer. Next, a conductive etching stopper connected to the source electrode is formed in the opening, and an alignment mark is formed on the compound semiconductor layer. Next, a photoresist film is formed on the back surface of the substrate. Next, the alignment of the photomask provided with the via pattern and the alignment pattern is performed using the alignment mark as a reference. Next, a via hole forming resist pattern is formed from the photoresist film using the photomask. Next, using the via hole forming resist pattern, a via hole reaching the conductive etching stopper from the back surface side is formed on the substrate. Then, via wiring is formed from the via hole to the back surface of the substrate.

  According to the semiconductor device manufacturing method and the like described above, the opening formed in the substrate with the formation of the alignment mark is difficult to reach the alignment mark, so that the separation of the alignment mark caused by the opening is suppressed. be able to. A decrease in yield associated with the formation of alignment marks can be suppressed.

  Hereinafter, embodiments of the present invention will be specifically described with reference to the accompanying drawings.

(First embodiment)
First, a first embodiment of the present invention will be described. 1A to 1Y are cross-sectional views illustrating a method of manufacturing a GaN-based HEMT (semiconductor device) according to the first embodiment in the order of steps.

  First, as shown in FIG. 1A, a GaN layer 2 and an n-type AlGaN layer 3 are formed in this order on the surface of an insulating substrate 1 made of silicon carbide (SiC). The insulating substrate 1 has a thickness of about 350 μm, the GaN layer 2 has a thickness of about 2 μm, and the n-type AlGaN layer 3 has a thickness of about 25 nm. Next, boron, helium, or the like is injected into the region to be the inactive region 92, thereby eliminating the two-dimensional electron gas. As a result, the inactive region 92 and the active region 91 are partitioned. Next, a source electrode 4 s, a gate electrode 4 g, and a drain electrode 4 d are selectively formed in the active region 91 on the n-type AlGaN layer 3. Thereafter, a SiN layer 5 is formed on the n-type AlGaN layer 3 to cover the source electrode 4s, the gate electrode 4g, and the drain electrode 4d. In forming the source electrode 4s, the gate electrode 4g, and the drain electrode 4d, for example, a Ti layer is formed, and then an Al layer is formed on the Ti layer.

  After the formation of the SiN layer 5, as shown in FIG. 1B, a resist pattern 51 having an opening 51s corresponding to the source electrode 4s and an opening 51d corresponding to the drain electrode 4d is formed on the SiN layer 5. The thickness of the resist pattern 51 is about 1 μm.

Next, as shown in FIG. 1C, by patterning the SiN layer 5 using the resist pattern 51 as a mask, a contact hole 5s that matches the opening 51s is formed on the source electrode 4s, and a contact hole that matches the opening 51d. 5d is formed on the drain electrode 4d. In patterning the SiN layer 5, for example, SF ₆ and CHF ₃ are supplied into the chamber at a flow rate ratio of 2:30, the antenna power is set to 500 W, and the bias power is set to 50 W to perform dry etching. In this case, the etching rate is about 0.24 μm / min.

Thereafter, the resist pattern 51 is removed, and a resist pattern 52 having an etching stopper opening 52 s located in the inactive region 92 is formed on the SiN layer 5 as shown in FIG. 1D. The thickness of the resist pattern 52 is about 10 μm. The diameter of the opening 52s is, for example, about 200 μm. Even if the thickness of the resist pattern 52 is about 10 μm, the opening 52 s having a diameter of about 200 μm can be formed with high accuracy. Subsequently, by patterning the SiN layer 5 using the resist pattern 52 as a mask, the opening 6 that matches the opening 52 s is formed in the inactive region 92. In patterning the SiN layer 5, for example, SF ₆ and CHF ₃ are supplied into the chamber at a flow rate ratio of 2:30, the antenna power is set to 500 W, and the bias power is set to 50 W to perform dry etching.

Next, as shown in FIG. 1E, the opening 6 reaches the insulating substrate 1 by performing dry etching of the n-type AlGaN layer 3 and the GaN layer 2 using the resist pattern 52 as a mask. In this dry etching, a chlorine-based gas such as Cl ₂ gas is used. Further, using an ICP dry etching apparatus, the antenna power is set to 100 W, and the bias power is set to 20 W. In this case, the etching rate of the n-type AlGaN layer 3 and the GaN layer 2 is about 0.2 μm / min.

  Note that the opening 6 may reach the inside of the insulating substrate 1.

  Thereafter, the resist pattern 52 is removed, and as shown in FIG. 1F, a Ti layer and Ni layer stack or a Ti layer and Cu layer stack is formed as a seed layer 7 on the entire surface of the insulating substrate 1. It is formed by a sputtering method. The thickness of the Ti layer is about 10 nm, the thickness of the Ni layer is about 100 nm, and the thickness of the Cu layer is about 200 nm.

  Subsequently, as shown in FIG. 1G, a resist pattern 53 having an opening 53 s that exposes the entire opening 6 and an opening 53 a for alignment marks is formed on the seed layer 7. Note that the openings 53 s and 53 a are positioned in the inactive region 92. Further, the thickness of the resist pattern 53 is about 3 μm.

  Next, as shown in FIG. 1H, the Ni layer 8 is formed on the seed layer 7 as a conductive etching stopper in the opening 53s by electroplating, and the alignment mark 8a is formed in the opening 53a. The thickness of the Ni layer 8 and the alignment mark 8a is about 3.2 μm. The Ni layer 8 is formed, for example, in a hot bath at 50 ° C to 60 ° C. In this case, the plating rate is about 0.5 μm / min. The planar shape of the opening 53a is a cross shape, and the length of each of the four linear portions extending from the center is 50 μm and the width is 40 μm. Therefore, the planar shape of the alignment mark 8a also has a cross shape as shown in FIG. 2A.

  Thereafter, as shown in FIG. 1I, the resist pattern 53 is removed. Subsequently, ion milling is performed to remove the seed layer 7 exposed from the Ni layer 8 and the alignment mark 8a. At this time, the Ni layer 8 and the alignment mark 8a are also slightly scraped to a thickness of about 3 μm. The distance between the surface of the n-type AlGaN layer 3 and the surface of the Ni layer 8 is about 1 μm. The milling rate of the Ti layer constituting the seed layer 7 is about 15 nm / min, the milling rate of the Ni layer is about 25 nm / min, and the milling rate of the Cu layer is about 53 nm / min.

  Next, as shown in FIG. 1J, a laminate of a Ti layer, a Pt layer, and an Au layer is formed as a seed layer 9 on the entire surface of the insulating substrate 1 by a sputtering method. The thickness of the Ti layer is about 10 nm, the thickness of the Pt layer is about 50 nm, and the thickness of the Au layer is about 200 nm.

  Thereafter, as shown in FIG. 1K, a resist pattern 54 having an opening surrounding the whole of the source electrode 4s and the Ni layer 8 and an opening corresponding to the outer edge of the drain electrode 4d is formed on the seed layer 9. The thickness of the resist pattern 54 is about 1 μm. Subsequently, the Au layer 10 having a thickness of about 1 μm is formed on the seed layer 9 in each opening of the resist pattern 54 by electroplating. The Au layer 10 is formed in, for example, an Au plating bath at 55 ° C. to 65 ° C. In this case, the plating rate is about 0.5 μm / min.

  Next, as shown in FIG. 1L, the resist pattern 54 is removed. Thereafter, the seed layer 9 exposed from the Au layer 10 is removed by performing ion milling. At this time, the Au layer 10 is also slightly scraped, and the thickness becomes about 0.6 μm. The milling rate of the Ti layer constituting the seed layer 9 is about 15 nm / min, the milling rate of the Pt layer is about 30 nm / min, and the milling rate of the Au layer is about 50 nm / min.

  Subsequently, as shown in FIG. 1M, the surface protective layer 11 is formed on the entire surface of the insulating substrate 1 and the front and back of the insulating substrate 1 are reversed. Next, by polishing the back surface of the insulating substrate 1, the thickness of the insulating substrate 1 is set to about 150 μm.

  Next, as shown in FIG. 1N, a laminated body of a Ti layer 12a and a Cu layer 12b is formed as a seed layer 12 on the back surface of the insulating substrate 1 by a sputtering method. Instead of this laminate, a laminate of a Ti layer and a Ni layer may be formed. The thickness of the Ti layer 12a is about 10 nm, the thickness of the Ni layer is about 100 nm, and the thickness of the Cu layer 12b is about 200 nm.

  Thereafter, as shown in FIG. 1O, a photoresist film 55f is formed on the seed layer 12. The thickness of the photoresist film 55f is about 3 μm.

  Subsequently, as shown in FIG. 1P, a photoresist using a photomask (reticle) 21 including a translucent portion 21a, a via light shielding portion 21b (via pattern), and an alignment light shielding portion 21c (alignment pattern). By exposing and developing the film 55f, a resist pattern 55 for forming a via hole is formed from the photoresist film 55f. The planar shape of the via light shielding portion 21b is a circle having a diameter of 100 μm, the planar shape of the alignment light shielding portion 21c is a cross shape, the length of each of the four linear portions extending from the center is 40 μm, and the width is 20 μm. To do. Accordingly, the margin between the alignment mark 8a and the alignment light shielding portion 21c is about 10 μm in any direction. In this exposure, as shown in FIG. 2B, alignment between the alignment mark 8a and the alignment light shielding portion 21c is performed using a double-side aligner.

  Next, as shown in FIG. 1Q, a Ni layer 13 having a thickness of about 3.2 μm is formed on the seed layer 12 in a region excluding the resist pattern 55 by electroplating. The Ni layer 13 is formed in, for example, a hot bath at 50 ° C to 60 ° C. In this case, the plating rate is about 0.5 μm / min.

  Thereafter, as shown in FIG. 1R, the resist pattern 55 is removed. Subsequently, the seed layer 12 exposed from the Ni layer 13 is removed by performing ion milling. At this time, the Ni layer 13 is also slightly scraped, and the thickness becomes about 3 μm. The milling rate of the Ti layer 12a constituting the seed layer 12 is about 15 nm / min, the milling rate of the Ni layer is about 25 nm / min, and the milling rate of the Cu layer 12b is about 53 nm / min.

Next, as shown in FIG. 1S, via holes 1s are formed by performing dry etching of the insulating substrate 1 using the Ni layer 13 as a metal mask. In this dry etching, a fluoride gas, for example, a mixed gas of sulfur hexafluoride (SF ₆ ) gas and oxygen (O ₂ ) gas is used. Further, using an ICP dry etching apparatus, the antenna power is 2 kW and the bias power is 0.2 kW. In this case, the etching selectivity between the insulating substrate 1 and the Ni layer 13 is about 100. The etching selectivity between the insulating substrate 1 and the GaN layer 2 is about 47.

  Since the in-plane distribution of the dry etching rate of the insulating substrate 1 made of SiC is large, it is preferable to perform over-etching here. For example, it is estimated that the variation (in-plane distribution) of the dry etching rate of the insulating substrate 1 is about ± 3%, and 5% overetching (7.5 μm Equivalent to the etching amount of SiC).

  When forming the via hole 1s, an opening 1h extending toward the alignment mark 8a is also formed. However, while the Ni layer 8 functioning as an etching stopper is located in the immediate vicinity of the insulating substrate 1, the GaN layer 2 and the n-type AlGaN layer 3 exist between the alignment mark 8a and the insulating substrate 1. Therefore, even if 5% overetching is performed, the opening 1h does not reach the alignment mark 8a. This is because even if 3% in-plane distribution and 5% overetching are taken into consideration, the theoretical etching amount of the SiC substrate 1 is about 162 μm at the maximum, and between the insulating substrate 1 and the GaN layer 2. This is because the etching selectivity of the GaN layer 2 is only about 0.26 μm at the maximum because the etching selectivity ratio is about 47.

  After the formation of the via hole 1s, as shown in FIG. 1T, a resist layer 56 is formed in the via hole 1s, the opening 1h, and the Ni layer 13.

  Next, as shown in FIG. 1U, the resist layer 56 is exposed and developed to leave the resist layer 56 only in the via hole 1s and the opening 1h. The remaining resist layer 56 functions as a protective layer.

  Thereafter, as shown in FIG. 1V, the Ni layer 13 and the seed layer 12 are removed by performing ion milling using argon ions and / or wet etching using dilute nitric acid. The milling rate of the Ni layer 13 is about 25 nm / min, and the wet etching rate using dilute nitric acid is about 50 nm / min.

  Subsequently, as shown in FIG. 1W, the resist layer 56 is removed. Thereafter, ion milling is performed to remove the seed layer 7 exposed from the via hole 1s and the opening 1h. The milling rate of the Ti layer constituting the seed layer 7 is about 15 nm / min, the milling rate of the Ni layer is about 25 nm / min, and the milling rate of the Cu layer is about 53 nm / min. Next, a laminated body of a Ti layer, a Pt layer, and an Au layer is formed as a seed layer 14 on the entire back surface of the insulating substrate 1 by a sputtering method. The thickness of the Ti layer is about 10 nm, the thickness of the Pt layer is about 50 nm, and the thickness of the Au layer is about 200 nm.

  Thereafter, as shown in FIG. 1X, an Au layer 15 having a thickness of about 10 μm is formed on the seed layer 14 by electroplating. The Au layer 15 is formed in, for example, an Au plating bath at 55 ° C. to 65 ° C. In this case, the plating rate is about 0.5 μm / min. A via wiring 16 is composed of the Au layer 15 and the seed layer 14. When the Au layer 15 is formed in the via hole 1s having a diameter of about 100 μm and a depth of about 150 μm by electroplating, the Au layer 15 is formed only on the bottom and side portions of the via hole 1s, and the via hole 1s is completely formed. It is not embedded in.

  Subsequently, as shown in FIG. 1Y, the front and back of the insulating substrate 1 are reversed, and the surface protective layer 11 is removed. Then, if necessary, wiring (not shown) or the like is formed to complete the GaN-based HEMT.

  In such a manufacturing method, when the via hole 1s is formed, the bottoms of the seed layer 7 and the Ni layer 8 functioning as an etching stopper are in contact with the region where the via hole 1s of the insulating substrate 1 is formed. Since the GaN layer 2 and the n-type AlGaN layer 3 do not intervene, the GaN layer 2 and the n-type AlGaN layer 3 are not excessively etched even if overetching is performed. Since the Ni layer 8 is thick, the Ni layer 8 does not disappear due to overetching, and the Ni layer 8 functions reliably as an etching stopper.

  Further, as described above, since the opening 1h does not reach the alignment mark 8a, the alignment mark 8a will not be detached due to misalignment or spread of etching. . Therefore, it is possible to prevent a decrease in yield due to the separation of the alignment mark 8a.

  Therefore, according to the present embodiment, the Ni layer 8 can reliably function as an etching stopper while ensuring a high yield obtained by overetching. For this reason, it becomes possible to obtain a high yield and to reduce manufacturing costs.

  After the surface protective layer 11 is removed, the layout viewed from the front surface side of the insulating substrate 1 is as shown in FIG. 3A, and the layout viewed from the back surface side is as shown in FIG. 3B. That is, although not shown in FIG. 1Y, there is also an Au layer 10 connected to the gate electrode 4g as shown in FIG. 3A. Note that the layout shown in FIG. 3A is simple, but if a multi-finger gate structure is employed, output can be improved. In addition, a resistor, a capacitor, and the like may be mounted to form a monolithic microwave integrated circuit (MMIC).

( Reference example )
Next, a reference example will be described. SiC or the like has a property that the depth of an opening formed by etching for a predetermined time depends on the size of the opening. In the reference example , such a property is used.

  Here, an experiment related to the above-described properties performed by the present inventors will be described. In this experiment, a metal mask having line-shaped opening patterns of various widths was formed on a SiC substrate, and etching was performed for a predetermined time. Then, the relationship between the width of the opening pattern (line width) and the etching depth was investigated. The result is normalized and shown in FIG. 4A. The etching depth was 106 μm when the predetermined etching time was t1 and the line width was 150 μm, and the etching depth was 149 μm when the predetermined etching time was t2 and the line width was 150 μm. The vertical axis in FIG. 4A indicates the ratio of the etching depths of various line widths to the etching depths (106 μm and 149 μm described above) when the line width is 150 μm.

  As shown in FIG. 4A, the etching depth ratio gradually decreased as the line width narrowed. This indicates that the etching depth becomes shallower as the line width becomes narrower.

  Then, when the horizontal axis of the graph shown in FIG. 4A is converted into an aspect ratio, the graph shown in FIG. 4B is obtained. The aspect ratio here refers to the ratio of the depth to the width of the opening formed in the SiC substrate.

  As shown in FIG. 4B, the etching depth ratio decreased as the aspect ratio increased. This indicates that the etching depth becomes shallower as the aspect ratio becomes larger. Further, when the aspect ratio is about 5 to 10, the etching depth ratio is about 0.92. This means that when the aspect ratio is 5 or more, the opening cannot penetrate the SiC substrate having a thickness of 150 μm even if 8% overetching is performed. When the aspect ratio is 10 or more, the etching depth ratio is 0.9 or less. This means that the opening does not easily penetrate the Si substrate even if the amount of overetching is further increased. Therefore, the ratio of the width of the linear opening to the thickness of the substrate is preferably 1/5 or less, and more preferably 1/10 or less.

As described above, this property is used in the reference example . 5A to 5E are cross-sectional views illustrating a method of manufacturing a GaN-based HEMT (semiconductor device) according to a reference example in the order of steps.

  First, similarly to the first embodiment, processing up to the formation of the contact holes 5s and 5d using the resist pattern 51 is performed (FIGS. 1A to 1C). Next, the resist pattern 51 is removed, and a seed layer 7 is formed on the entire surface of the insulating substrate 1 as shown in FIG. 5A.

  Thereafter, as shown in FIG. 5B, a resist pattern 53 having an opening 53 s and an alignment mark opening 53 b is formed on the seed layer 7. Note that the openings 53 s and 53 b are positioned in the inactive region 92. The planar shape of the opening 53b is a cross shape, and the length of each of the four linear portions extending from the center is 45 μm and the width is 35 μm. That is, the opening 53b is smaller than the opening 53a in the first embodiment.

  Subsequently, as shown in FIG. 5C, the Ni layer 8 is formed on the seed layer 7 as an etching stopper in the opening 53s by electroplating, and the alignment mark 8b is formed in the opening 53b. Since the opening 53b is smaller than the opening 53a, the alignment mark 8b is also smaller than the alignment mark 8a.

Next, similarly to the first embodiment, processes from the removal of the resist pattern 53 to the formation of the photoresist film 55f are performed (FIGS. 1I to 1O). In addition, since the opening 6 is not formed in this reference example , as shown in FIG. 5D, a larger step is generated in the Au layer 10 than in the first embodiment.

  Thereafter, as shown in FIG. 5D, exposure and development of the photoresist film 55f using a photomask (reticle) 21 having a light transmitting portion 21a, a via light shielding portion 21b, and an alignment light shielding portion 21d (alignment pattern). As a result, a resist pattern 55 for forming a via hole is formed from the photoresist film 55f. The planar shape of the alignment light-shielding portion 21d is a cross shape, and the length of each of the four linear portions extending from the center is 35 μm and the width is 15 μm. That is, the alignment light-shielding part 21d is smaller than the alignment light-shielding part 21c in the first embodiment. Further, the margin between the alignment mark 8b and the alignment light-shielding portion 21d is about 10 μm in any direction, as in the first embodiment. In this exposure, alignment between the alignment mark 8b and the alignment light shielding portion 21d is performed using a double-side aligner.

  Subsequently, similarly to the first embodiment, processes from the formation of the Ni layer 13 to the selective removal of the seed layer 12 are performed (FIGS. 1Q to 1R). Next, as shown in FIG. 5E, via holes 1s are formed by performing dry etching of the insulating substrate 1 using the Ni layer 13 as a metal mask. At this time, an opening 1i extending toward the alignment mark 8b is also formed. However, even if 5% overetching is performed, the opening 1i does not reach the alignment mark 8b. This is because even if the width of the opening formed in the Ni layer 13 is 15 μm, the thickness of the insulating substrate 1 is 150 μm, and the opening 1 i penetrates the insulating substrate 1, the aspect ratio is 10 Because it becomes. That is, the depth of the opening 1i is 146 μm at the maximum even considering the in-plane distribution of 3% and the overetching of 5%, so that the opening 1i does not reach the alignment mark 8b. Even if the width of the opening 1i is 30 μm (aspect ratio: 5), the depth is 149 μm at the maximum, and thus the opening 1i does not reach the alignment mark 8b.

For example, in dry etching of the insulating substrate 1, a mixed gas of sulfur hexafluoride (SF ₆ ) gas and oxygen (O ₂ ) gas is used, and in dry etching of the GaN layer 2 and the n-type AlGaN layer 3, Cl _{Use 2} gas.

  After the formation of the via hole 1s, the subsequent processing from the formation of the resist layer 56 is performed in the same manner as in the first embodiment to complete the GaN-based HEMT (FIGS. 1T to 1Y).

  In such a manufacturing method, the opening 1i is formed along with the formation of the via hole 1s. However, the opening 1i does not reach the alignment mark 8b unless excessive over-etching is performed. Even if misalignment or spreading of etching occurs, the alignment mark 8b does not leave due to this. Therefore, it is possible to prevent a decrease in yield due to the separation of the alignment mark 8b.

  Further, in order to suppress the extension of the opening 1i, the alignment light-shielding portion 21d is made smaller than the alignment light-shielding portion 21c, but the alignment mark 8b is also made smaller than the alignment mark 8a in anticipation of this. It is also possible to perform alignment with the same degree of accuracy as in the first embodiment.

Therefore, also in this reference example, it is possible to obtain a high yield, production cost can be reduced.

  Note that the upper limit of the width of the opening 1i and the alignment light-shielding portion 21c with respect to the thickness of the insulating substrate 1 depends on the depth of the via hole 1s and the resolution of the double-sided aligner, and 200 when considering the conventional depth and resolution. Degree. However, the aspect ratio can be further increased by using a stepper or an electron beam exposure apparatus with a double-side aligner mechanism that can obtain a higher resolution. And the effect that the difference of the above-mentioned etching depth becomes large becomes so high that an aspect ratio becomes high.

(Second Embodiment)
Next, a second embodiment will be described. The second embodiment is a combination of the first embodiment and a reference example . 6A to 6D are cross-sectional views illustrating a method of manufacturing a GaN-based HEMT (semiconductor device) according to the second embodiment in the order of steps.

First, similarly to the first embodiment, processing up to formation of the seed layer 7 is performed (FIGS. 1A to 1F). Next, as shown in FIG. 6A, a resist pattern 53 having an opening 53s and an opening 53b is formed on the seed layer 7 in the same manner as in the reference example .

  Thereafter, as shown in FIG. 6B, the Ni layer 8 is formed on the seed layer 7 as an etching stopper in the opening 53s by electroplating, and the alignment mark 8b is formed in the opening 53b. Since the opening 53b is smaller than the opening 53a, the alignment mark 8b is also smaller than the alignment mark 8a.

Subsequently, similarly to the first embodiment, processing from the removal of the resist pattern 53 to the formation of the photoresist film 55f is performed (FIGS. 1I to 1O). Next, as shown in FIG. 6C, in the same manner as in the reference example , exposure of the photoresist film 55f using a photomask (reticle) 21 including a light transmitting portion 21a, a via light shielding portion 21b, and an alignment light shielding portion 21d is performed. Then, a resist pattern 55 is formed from the photoresist film 55f by performing development. During this exposure, alignment between the alignment mark 8b and the alignment light shielding portion 21d is performed using a double-side aligner.

  Thereafter, similarly to the first embodiment, processes from the formation of the Ni layer 13 to the selective removal of the seed layer 12 are performed (FIGS. 1Q to 1R). Subsequently, as shown in FIG. 6D, the via hole 1s is formed by performing dry etching of the insulating substrate 1 using the Ni layer 13 as a metal mask. At this time, an opening 1j extending toward the alignment mark 8b is also formed. In the present embodiment, since the width of the opening formed in the Ni layer 13 is 15 μm, the opening 1j is shallower than the opening 1h in the first embodiment.

  After the formation of the via hole 1s, the subsequent processing from the formation of the resist layer 56 is performed in the same manner as in the first embodiment to complete the GaN-based HEMT (FIGS. 1T to 1Y).

  In such a manufacturing method, the opening 1j is formed along with the formation of the via hole 1s. However, the extension of the opening 1j is suppressed as compared with the extension of the opening 1h in the first embodiment. Accordingly, it is possible to more reliably avoid the opening 1j from reaching the alignment mark 8b. Therefore, it is possible to prevent a decrease in yield due to the separation of the alignment mark 8b.

In the second embodiment, the alignment mark opening may be formed in the GaN layer 2 and the n-type AlGaN layer 3 simultaneously with the formation of the opening 6. Even in this case, as shown in FIG. 7, the opening 1j does not reach the alignment mark 8b. Further, the step between the alignment mark 8b and the SiN layer 5 is relaxed.

Further, instead of the GaN layer 2 and the n-type AlGaAs layer 3, an SiC-based MESFET (Metal Semiconductor Field Effect Transistor) may be configured using an SiC layer. In this case, since it is difficult to ensure a large etching selection ratio between the insulating substrate 1 and the SiC layer, it is preferable to perform the same processing as in the reference example as shown in FIG. Note that, in the first embodiment and the second embodiment as well, such a SiC MESFET can be configured if the depth of the opening 6 can be controlled. Moreover, you may comprise MOSFET (Metal Oxide Semiconductor Field Effect Transistor).

  Further, the compound semiconductor layer on the insulating substrate 1 may be made of another material. In addition, a sapphire substrate or the like may be used as the insulating substrate 1, and a conductive substrate or a semi-insulating substrate may be used instead of the insulating substrate 1 as the substrate.

  Further, materials such as wiring and seed layer are not limited. In particular, for the seed layer, it is preferable to use Ta instead of Ti when the via hole 1s is formed at an etching rate of 2 μm / min or more. This is because when Ti is used, an insulating deteriorated layer may be formed at the upper end and lower end of the via hole 1s, but when Ta is used, formation of the deteriorated layer is suppressed.

  In any of the embodiments, the alignment mark 58 may be provided for each shot of the stepper with respect to the wafer 51, as shown in FIG. 9A. In this case, the alignment mark 58 is included for each one-shot region 52 formed by one shot. Therefore, it is preferable to provide an alignment light-shielding portion that aligns with each alignment mark 58 on the photomask (reticle). Further, as shown in FIG. 9B, the alignment mark 58 may be provided only on a specific shot of the stepper with respect to the wafer 51. In this case, the alignment mark 58 is included in a part of the one-shot area 52. Therefore, it is preferable to provide an alignment light-shielding portion that matches the alignment marks 58 on the photomask (reticle). Two or more alignment marks may be formed in one shot.

It is sectional drawing which shows the method of manufacturing GaN-type HEMT which concerns on 1st Embodiment. FIG. 1B is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 1A. FIG. 2B is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 1B. 1C is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 1C. 2D is a cross-sectional view illustrating a method of manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 1D. 2E is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 1E. 1F is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 1F. FIG. 2 is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 1G. FIG. 2 is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 1H. FIG. 2 is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 1I. FIG. 2 is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 1J. FIG. 2 is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 1K. FIG. 2 is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 1L. FIG. 2B is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 1M. 1N is a cross-sectional view illustrating a method of manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 1N. FIG. 10 is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 10. FIG. 2 is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 1P. FIG. 2 is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 1Q. 1R is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 1R. FIG. 2 is a cross-sectional view illustrating a method of manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 1S. FIG. 2B is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 1T. FIG. 2 is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 1U. FIG. 2B is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 1V. FIG. 2C is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 1W. FIG. 2 is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 1X. It is a figure which shows the planar shape of the alignment mark 8a. It is a figure which shows alignment with the alignment mark 8a and the light shielding part 21c for alignment. It is a figure which shows the layout of the surface side in 1st Embodiment. It is a figure which shows the layout of the back surface side in 1st Embodiment. It is a graph which shows the relationship between ratio of line width and etching depth. It is a graph which shows the relationship between an aspect-ratio and the ratio of etching depth. It is sectional drawing which shows the method of manufacturing GaN-type HEMT which concerns on a reference example . It is sectional drawing which shows the method of manufacturing the GaN-type HEMT which concerns on a reference example following FIG. 5A. FIG. 5B is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the reference example , following FIG. 5B. 5C is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the reference example , following FIG. 5C. FIG. 5D is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the reference example , following FIG. 5D. It is sectional drawing which shows the method of manufacturing GaN-type HEMT which concerns on 2nd Embodiment. FIG. 6B is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the second embodiment following FIG. 6A. FIG. 6B is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the second embodiment following FIG. 6B. 6C is a cross-sectional view illustrating a method of manufacturing the GaN-based HEMT according to the second embodiment, following FIG. 6C. It is sectional drawing which shows the modification of 2nd Embodiment . It is sectional drawing which shows the modification of a reference example . It is a figure which shows the relationship between 1 shot and an alignment mark. It is a figure which shows the other relationship of 1 shot and an alignment mark. It is sectional drawing which shows the conventional method of forming a via hole. FIG. 10B is a cross-sectional view illustrating a conventional method for forming a via hole following FIG. 10A. FIG. 10B is a cross-sectional view illustrating a conventional method for forming a via hole subsequent to FIG. 10B. FIG. 10C is a cross-sectional view illustrating a conventional method for forming a via hole subsequent to FIG. 10C. FIG. 10D is a cross-sectional view illustrating a conventional method for forming a via hole following FIG. 10D. FIG. 10E is a cross-sectional view illustrating a conventional method for forming a via hole following FIG. 10E. It is a figure which shows the problem in the conventional method.

Explanation of symbols

1: Insulating substrate 1s: Via hole 1h, 1i, 1j: Opening 2: GaN layer 3: n-type AlGaN layer 4d: Drain electrode 4g: Gate electrode 4s: Source electrode 6: Opening 8: Ni layer 8a, 8b: Alignment mark 10: Au layer 15: Au layer 16: Via wiring 21: Photomask 21a: Translucent part 21b: Light shielding part for via 21c, 21d: Light shielding part for alignment 31: SiC layer

Claims (4)

Forming a compound semiconductor layer on the substrate;
Forming a gate electrode, a source electrode and a drain electrode on the compound semiconductor layer;
Forming an opening that reaches at least the surface of the substrate in the compound semiconductor layer;
Forming a conductive etching stopper connected to the source electrode in the opening, and forming an alignment mark on the compound semiconductor layer;
Forming a photoresist film on the back surface of the substrate;
A step of aligning a photomask provided with a via pattern and an alignment pattern based on the alignment mark;
Forming a via hole forming resist pattern from the photoresist film using the photomask; and
Using the via hole forming resist pattern, forming a via hole reaching the conductive etching stopper from the back side of the substrate;
Forming via wiring from the via hole to the back surface of the substrate;
A method for manufacturing a semiconductor device, comprising:   2. The method of manufacturing a semiconductor device according to claim 1, wherein a ratio of a width of the alignment pattern to a thickness of the substrate is 1/5 or less. The method of manufacturing a semiconductor device according to claim 1 or 2, characterized in that to form the conductive etching stopper and the alignment mark from the same conductive layer to each other. The SiC substrate used as the substrate, a manufacturing method of a semiconductor device according to any one of claims 1 to 3, characterized in that a nitride semiconductor layer as the compound semiconductor layer.

Images