JP5261450B2 - Game machine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a game machine which can reinforce measures for preventing illicit action while reconfirming whether or not an electronic part is truly illicit even if it is determined that the electronic part is illicit. <P>SOLUTION: A first inherent number register 116 stores a first inherent number assigned at the manufacturing of a one-chip microcomputer 110m, and the first inherent number is outputted by a command from a main CPU 110a. Meanwhile, a second inherent number storage part 119a stores a second inherent number different from the first inherent number which is assigned at the manufacturing of the one-chip microcomputer 110m, and second inherent number information is outputted when reading prescribed information from an input terminal. <P>COPYRIGHT: (C)2012,JPO&amp;INPIT

Description

  The present invention relates to a gaming machine that gives a player a predetermined profit, and more particularly to a gaming machine that can determine the validity of an electronic component involved in a process for giving a predetermined profit.

  Conventionally, pachinko machines are configured to control a special game (big hit) when a winning ball is won at the start opening provided on the game board and when a big hit lottery is won. Has been. In such special games, the big prize opening provided on the game board is opened to facilitate the winning of the game ball, and the prize ball corresponding to the game ball won in the big prize opening is paid out to the player. It is like that.

  In such a gaming machine, a program for performing a lottery lottery process or the like is illegally altered, or a legitimate electronic component (such as a ROM or a one-chip microcomputer on which a ROM is mounted) is changed to an illegal electronic component. There is a rampant act of deliberately paying out game balls by exchanging them.

  For this reason, conventionally, a game for determining the legitimacy of a one-chip microcomputer by adding unique information (ID code) to a one-chip microcomputer (amuse chip) equipped with a CPU, ROM and RAM for controlling the game. A machine is known (see Patent Document 1).

Specifically, an ID code of the one-chip microcomputer of the gaming machine is sent from the ball rental management device that controls the ball rental machine of each game store to the ball rental machine, and the ball rental machine stores the ID code of the one-chip microcomputer. . The ball lending machine also obtains the ID code of the one-chip microcomputer from the gaming machine and determines the validity of the one-chip microcomputer of the gaming machine.
More specifically, the manufacturer's engineer, hall administrator or third-party inspector checks the ID code of the gaming machine attached to the target ball lending machine from the technical data issued by the manufacturer, and the ID. The code and the address of the gaming machine are set in the ball rental management device in each gaming store. The ball lending machine is connected to the ball lending management device through a ball lending network, reads the ID code of the one-chip microcomputer from the ball lending management device, and determines the ID code of the one-chip microcomputer read from the ball lending management device as an ID for determination. Write to the non-volatile memory as code. Then, the ball lending machine periodically acquires the ID code of the one-chip microcomputer from the gaming machine connected to the ball lending machine with a harness, compares the acquired ID code with the ID code for determination, and matches. If not, it is determined that the one-chip microcomputer is illegal.

JP 2010-57979 A (0028, 0063 paragraphs, etc.)

However, in the invention described in Patent Document 1, if noise enters the unique information (ID code) of the one-chip microcomputer that is output from the gaming machine to the ball lending machine, A one-chip microcomputer that should be legitimate may be determined to be illegal. For this reason, the one-chip microcomputer, which should be legitimate, was treated as an illegal one, and it was necessary to stop unnecessary operation of the gaming machine and to replace the main control board.
In particular, for pachinko machines that use steel game balls to play games, the game balls may experience friction in the supply path through which the game balls are supplied from the island facilities of the game store or the ball flow paths in the game machines. A game ball flowing down the board collides with a decorative member such as a game nail, and the game ball is easily charged with static electricity. For this reason, static electricity charged in the game ball is easily discharged to the gaming machine, and noise is easily generated in the control device of the gaming machine.

  Furthermore, as in the invention described in the above-mentioned Patent Document 1, if the CPU in the one-chip microcomputer only outputs the unique information of the one-chip microcomputer, an illegal one is obtained by falsification of the program stored in the ROM. Since legitimate unique information may be output from the chip microcomputer, it has been desired to strengthen measures to prevent fraud.

  The object of the present invention is to provide a measure for preventing fraud while allowing an electronic component such as a one-chip microcomputer to be confirmed again whether or not it is a fraudulent electronic component. It is to provide a gaming machine that can be strengthened.

The invention according to claim 1 is stored in the information storage unit (main ROM 110b or main RAM 110c) in which game information (program, calculation result data) for executing a predetermined game is stored, and in the information storage unit. An arithmetic processing unit (main CPU 110a) that performs arithmetic processing relating to the predetermined game according to the game information, and first specific information that is uniquely assigned to the information storage unit or arithmetic processing unit for each product unit A first unique information storage unit (first unique number register 116) that stores information, and a second unique information that stores second unique information uniquely assigned to each product unit with respect to the information storage unit or the arithmetic processing unit information storage unit (a second specific number storage unit 119a), the first unique information said stored in the storage unit the first unique information contains information of a predetermined external A first unique information output unit (output port 113) for outputting to a child, and a second unique information output unit for outputting the second unique information stored in the second unique information storage unit to a predetermined external terminal (Hardware ID output unit 119),
The arithmetic processing unit and the first specific information storage unit are connected by a signal line (internal bus) for sending a signal related to the game information, while the arithmetic processing unit and the second specific information storage unit are The arithmetic processing unit is not connected by the signal line, and the arithmetic processing unit outputs a gaming state control means (main CPU 110a) for controlling a gaming state related to the predetermined game and the first unique information to a predetermined external terminal. Sometimes, external information generation for generating state information based on the gaming state controlled by the gaming state control means and generating external information including the generated state information and the first unique information a means (the main CPU 110a), the said first specific information output unit, when there is a specific instruction from the arithmetic processing unit via the signal line, the first unique information and the state information Outputs Mareta the external information to the predetermined external terminal, the second unique information output unit has an input terminal to read the predetermined information from the external, the read predetermined information from the input terminal, The second unique information is output to the predetermined external terminal.

According to the first aspect of the present invention, when the fraud determination information from the first unique information is notified, the validity of the one-chip microcomputer can be confirmed again by referring to the second unique information. It is possible to prevent erroneous determination due to noise.
In order to create a counterfeit one-chip microcomputer, not only the program ROM must be tampered with, but the circuit board must be tampered with, and both the software and hardware must be tampered. Can be made more difficult and fraud prevention can be further strengthened.

  According to a second aspect of the present invention, in the gaming machine according to the first aspect, the first specific information output unit outputs the first specific information to a first output terminal, and outputs the second specific information. The unit outputs the second unique information to a second output terminal different from the first output terminal.

  According to a third aspect of the present invention, in the gaming machine according to the first or second aspect, the first specific information stored in the first specific information storage unit and the second specific information storage unit The information is different from the stored second unique information.

  According to the present invention, even if it is determined that an electronic component such as a one-chip microcomputer is illegal, it is possible to confirm again whether or not the electronic component is truly illegal, It can be strengthened.

It is a front view of a gaming machine. It is a system configuration diagram of a gaming machine via the Internet. It is a perspective view of the gaming machine with the glass frame opened. It is a perspective view of the back side of a gaming machine. It is a block diagram of the whole gaming machine. It is a block diagram of a one-chip microcomputer. It is a figure which shows the structure of the external information for chips output to an information management apparatus. It is a conceptual diagram of the output method of the external information for chips. It is explanatory drawing regarding the timing of the input of the data to an output buffer, and an output. It is a figure which shows a big hit determination table and a hit determination table. It is a figure which shows a symbol determination table. It is a figure which shows the main process in a main control board. It is a figure which shows the timer interruption process in a main control board. It is a figure which shows the special figure special electric control process in a main control board. It is a figure which shows the special symbol memory | storage determination process in a main control board. It is a figure which shows the data creation process in a main control board. It is a figure which shows the external information production | generation process in a main control board. It is a figure which shows the output control process in a main control board. It is a figure which shows the 2nd port output process in a main control board. It is a figure which shows the main process in an information management apparatus. It is a figure which shows the external information input analysis process in an information management apparatus. It is a figure which shows the structure of the external information for chips | tips in Embodiment 2. FIG. 10 is a conceptual diagram of a chip external information output method according to Embodiment 3. FIG. FIG. 10 is an explanatory diagram regarding timing of data input and output to an output buffer according to the third embodiment.

(Embodiment 1)
Hereinafter, Embodiment 1 of the present invention will be specifically described with reference to the drawings.

(Composition of gaming machine)
First, the configuration of the gaming machine 1000 will be specifically described with reference to FIG. FIG. 1 is a front view showing an example of a gaming machine 1000 according to the present invention.

  The gaming machine 1000 executes a game for winning a game ball in a specific winning slot, and pays out a predetermined number of game balls to the player based on the winning result. The information management apparatus 200 collects and manages external information for the chip concerned.

The gaming device 1 is connected to the information management device 200 via a wire (harness), and a “model name” indicating the model name of the gaming device 1, a “maker name” indicating the name of the manufacturer of the gaming device 1, and the gaming device 1 outputs the chip external information composed of the “first unique number” which is the unique number of the one-chip microcomputer mounted on the information management apparatus 200.
The configuration of the chip external information will be described later in detail with reference to FIG.

The information management device 200 inputs external chip information from the gaming device 1 and analyzes the input external chip information.
In addition, the information management device 200 accepts coins, banknotes, or money information media (IC card or the like), and pays out a specified number of game balls to the game device 1 according to the accepted money information or the like (amount). We also control ball lending to allow this.

(System configuration diagram of gaming machine)
The gaming machine 1000 is connected to an information collection server 400 that collects external information for chips of each gaming machine 1000 via a public line (Internet). FIG. 2 is a system configuration diagram of a gaming machine via the Internet.

Specifically, the information management device 200 of each gaming machine 1000 is connected to an information management device 300 provided in each gaming store via a relay terminal 250 (switching hub).
The information management device 300 collects the chip external information of each gaming machine 1000 in the game store, and transmits the collected chip external information to the information collection server 400 via the public line in real time.
Then, the information collection server 400 collects external information for chips of each gaming machine 1000 in game stores nationwide and performs a comprehensive analysis.
As will be described later, since it is possible to grasp the fraudulent act in which the legitimate one-chip microcomputer is replaced with the fraudulent one-chip microcomputer by the external information for chips, the fraudulent act at any amusement store is analyzed by the comprehensive analysis by the information collecting server 400. It is possible to analyze whether or not fraudulent acts are performed, and to analyze when fraudulent acts are performed. Further, it is possible to notify each game store that an illegal act has been performed through the management company of the information collection server 400.
Further, as will be described later, since the gaming state in which the illegal act is performed can be grasped by the external information for chips, the gaming state in which the gaming machine 1000 installed in the game stores nationwide is likely to perform the illegal action is analyzed. be able to. And, by feeding back information on the gaming state (problems of the gaming machine) that is likely to be fraudulent to the gaming machine manufacturer, the gaming machine manufacturer changed the design of the gaming machine and developed the next model, It is possible to strengthen the prevention of fraud and take effective measures.

(Configuration of gaming device)
Next, the configuration of the gaming apparatus 1 will be specifically described with reference to FIGS.
As described above, FIG. 1 is a front view of a gaming machine 1000 including the gaming device 1 and the information management device 200, and FIG. 3 is a perspective view of the gaming device 1 with the glass frame 50 opened. FIG. 4 is a perspective view of the back side of the gaming apparatus 1.

  The gaming apparatus 1 includes an outer frame 60 attached to an island facility of a game store, and a glass frame 50 that is rotatably supported by the outer frame 60 (see FIGS. 1 and 3). In addition, the outer frame 60 is provided with a game board 2 in which a game area 6 in which the game ball 99 flows down is formed. In the glass frame 50, an operation handle 3 for launching a game ball toward the game area 6 by being rotated, an audio output device 32 including a speaker, an effect lighting device 34 having a plurality of lamps, An effect button 35 for changing the effect mode by a pressing operation is provided.

  Further, the glass frame 50 is provided with a tray 40 for storing a plurality of game balls 99, and the tray 40 has a downward slope so that the game balls 99 flow down toward the operation handle 3 side. (See FIG. 3). A receiving opening for receiving a game ball is provided at the end of the downward slope of the tray 40, and the game ball received in the receiving opening is driven by the ball feed solenoid 4b, so that the glass frame 50 One by one is sent to the ball feed opening 41 provided on the back surface. Then, the game ball sent out to the ball feed opening 41 is guided to the end of the downward slope of the launch rail 42 by the launch rail 42 having a downward slope toward the launching member 4c. Above the end of the downward slope of the launch rail 42, a stopper 43 for stopping and stopping the game ball is provided, and the game ball 99 sent out from the ball feed opening 41 has a downward slope of the launch rail 42. One game ball is stopped at the end (see FIG. 3).

  When the player turns the operation handle 3, the launch volume 3b directly connected to the operation handle 3 also turns, and the launch volume of the game ball is adjusted by the launch volume 3b. The launch member 4c directly connected to the solenoid 4a for rotation rotates. By rotating the launch member 4 c, the game ball 99 stored at the end of the downward slope of the launch rail 42 is launched by the launch member 4 c, and the game ball is launched into the game area 6.

  When the game ball fired as described above rises between the rails 5a and 5b from the launch rail 42 and exceeds the ball return prevention piece 5c, the game ball reaches the game area 6 and then falls in the game area 6. At this time, the game ball falls unpredictably by a plurality of nails and windmills provided in the game area 6.

  The game area 6 is provided with a plurality of general winning awards 12. Each of these general winning ports 12 is provided with a general winning port detecting switch 12a. When the general winning port detecting switch 12a detects a winning of a game ball, a predetermined winning ball (for example, ten game balls) is provided. To be paid out.

  Further, in the area below the center of the game area 6, there are a first start port 14 and a second start port 15 that constitute a start area into which game balls can enter, and a second large area in which game balls can enter. A winning opening 17 is provided.

  The second starting port 15 has a pair of movable pieces 15b, a first mode in which the pair of movable pieces 15b is maintained in a closed state, and a second state in which the pair of movable pieces 15b are in an open state. The movable control is performed. When the second starting port 15 is controlled in the first mode, the winning member of the second large winning port 17 located immediately above the second starting port 15 becomes an obstacle, and the game ball Is impossible to accept. On the other hand, when the second start port 15 is controlled to the second mode, the pair of movable pieces 15b function as a tray, and it is easy to win a game ball to the second start port 15. That is, when the second start port 15 is in the first mode, there is no game ball winning opportunity, and when it is in the second mode, the game ball winning opportunity is increased.

  Here, the first start port 14 is provided with a first start port detection switch 14a for detecting the entrance of a game ball, and the second start port 15 is provided with a second start port detection switch for detecting the entrance of a game ball. 15a is provided. When the first start port detection switch 14a or the second start port detection switch 15a detects the entry of a game ball, a special symbol determination random number value is acquired, and a right acquisition lottery (to be described later) Hereinafter, “Lottery for jackpot” is performed. Also, when the first start port detection switch 14a or the second start port detection switch 15a detects the entry of a game ball, a predetermined prize ball (for example, three game balls) is paid out.

  In addition, the second grand prize winning port 17 is configured by an opening formed in the game board 2. Below the second grand prize opening 17, there is a second big prize opening / closing door 17b that can protrude from the game board surface side to the glass plate 52 side. It is controlled to move between an open state protruding to the side and a closed state buried in the game board surface. When the second grand prize opening opening / closing door 17b protrudes from the game board surface, it functions as a tray for guiding the game ball into the second big prize opening 17, and the game ball can enter the second big prize opening 17. Become. The second big prize opening 17 is provided with a second big prize opening detection switch 17a. When the second big prize opening detection switch 17a detects the entry of a game ball, a predetermined prize ball (for example, 15 game balls) are paid out.

Furthermore, in the area on the right side of the game area 6, there are provided a normal symbol gate 13 constituting a normal area through which game balls can pass and a first grand prize opening 16 through which game balls can enter.
For this reason, unless the game ball is a game ball that has been driven by a strong force by turning the operation handle 3 greatly, the normal design gate 13 and the first big winning opening 16 are configured so that the game ball will not pass or win. Yes. In particular, even if the short game state, which will be described later, is entered, if the game ball flows down to the left side of the game area 6, the game ball will not normally pass through the symbol gate 13, so that it is at the second start port 15. The pair of movable pieces 15b are not opened, and it is difficult for a game ball to win the second starting port 15.

  The normal symbol gate 13 is provided with a gate detection switch 13a for detecting the passage of the game ball. When the gate detection switch 13a detects the passage of the game ball, the normal symbol determination random number value is acquired, which will be described later. “Normal lottery” is performed.

  The first grand prize opening 16 is normally kept closed by the first big prize opening opening / closing door 16b, and it is impossible to enter a game ball. In contrast, when a special game, which will be described later, is started, the first grand prize opening opening / closing door 16b is opened, and the first big prize opening opening / closing door 16b puts the game ball in the first big winning opening 16; It functions as a receiving tray that guides the game ball and can enter the first grand prize opening 16. The first grand prize opening 16 is provided with a first big prize opening detection switch 16a. When the first big prize opening detection switch 16a detects the entry of a game ball, a predetermined prize ball (for example, 15 Game balls).

  Further, in the lowermost area of the game area 6 and the lowermost area of the game area 6, the general winning opening 12, the first starting opening 14, the second starting opening 15, the first major winning opening 16, and the second large winning opening. An out port 11 is provided for discharging game balls that have not entered any of the winning ports 17.

In addition, a decoration member 7 that affects the flow of the game ball is provided in the center of the game area 6. A liquid crystal display device (LCD) 31 is provided at a substantially central portion of the decorative member 7, and an effect driving device 33 in the form of a belt is provided above the liquid crystal display device 31.
In this embodiment, the liquid crystal display device 31 is used as a liquid crystal display. However, a plasma display may be used, a projector, a reel made of an annular structure, a so-called 7-segment LED, a dot matrix, or the like. A display device or the like may be used.

The liquid crystal display device 31 displays an image during standby when no game is being performed, or displays an image according to the progress of the game. Among them, three effect symbols 36 for informing the jackpot lottery result, which will be described later, are displayed, and a combination of specific effect symbols 36 (for example, 777) is stopped and displayed as a jackpot lottery result. A big hit is announced.
More specifically, when a game ball enters the first start port 14 or the second start port 15, the three effect symbols 36 are scroll-displayed, and the scroll is stopped after a predetermined time, The effect design 36 is stopped and displayed. Further, by displaying various images, characters, and the like during the variation display of the effect symbol 36, a high expectation that the player may win a big hit is given to the player.

  The effect driving device 33 gives a player a sense of expectation according to the operation mode. The effect driving device 33 performs, for example, an operation in which the belt moves downward or a rotating member at the center of the belt rotates. Various operational feelings are given to the player depending on the operation mode of the effect driving device 33.

  Furthermore, in addition to the above-described various production devices, the audio output device 32 outputs BGM (background music), SE (sound effects), etc., and produces productions using sound. The illumination direction and the emission color are changed to produce an effect by illumination.

  The effect button 35 is effective only when, for example, a message for operating the effect button 35 is displayed on the liquid crystal display device 31. The effect button 35 is provided with an effect button detection switch 35a. When the effect button detection switch 35a detects the player's operation, a further effect is executed according to this operation.

  In the lower right of the game area 6, a first special symbol display device 20, a second special symbol display device 21, a normal symbol display device 22, a first special symbol hold indicator 23, a second special symbol hold indicator 24, a normal A symbol hold indicator 25 is provided.

  The first special symbol display device 20 is for notifying a lottery result obtained when a game ball enters the first start port 14, and is composed of 7-segment LEDs. That is, a plurality of special symbols corresponding to the jackpot lottery result are provided, and the lottery result is notified to the player by displaying the special symbol corresponding to the jackpot lottery result on the first special symbol display device 20. I am doing so. For example, “7” is displayed when the jackpot is won, and “−” is displayed when the player wins. “7” and “−” displayed in this way are special symbols, but these special symbols are not displayed immediately, but are displayed in a stopped state after being displayed for a predetermined time. .

  Here, the “successful lottery” means that when a game ball enters the first starting port 14 or the second starting port 15, a special symbol determining random number value is acquired, and the acquired special symbol determining random value is acquired. Is a random number value corresponding to “big hit” or a random number value corresponding to “small hit”. The jackpot lottery result is not immediately notified to the player, and the first special symbol display device 20 displays a variation such as blinking of the special symbol, and when the predetermined variation time has passed, the jackpot lottery result The special symbol corresponding to is stopped and displayed so that the player is notified of the lottery result. The second special symbol display device 21 is for notifying a lottery result of a jackpot that is performed when a game ball enters the second start port 15, and the display mode is the above-described first display mode. This is the same as the special symbol display mode in the special symbol display device 20.

  Further, in this embodiment, “big hit” means that a right to win a big hit game is obtained in a big win lottery performed on condition that a game ball has entered the first start port 14 or the second start port 15 Say what you did. In the “hit game”, a round game in which the first big prize opening 16 or the second big prize opening 17 is opened is performed 15 times in total. A predetermined time is set for the maximum opening time of the first grand prize port 16 or the second grand prize port 17 in each round game, and during this time, the first grand prize port 16 or the second grand prize port 17 is set. When a predetermined number of game balls (for example, nine) enter, one round game is completed. In other words, the “big hit game” is a game in which a game ball can enter the first grand prize winning opening 16 or the second big winning prize opening 17 and the player can acquire a winning ball according to the winning prize.

  The normal symbol display device 22 is for notifying the lottery result of the normal symbol that is performed when the game ball passes through the normal symbol gate 13. As will be described in detail later, when the winning symbol is won by the normal symbol lottery, the normal symbol display device 22 is turned on, and then the second start port 15 is controlled to the second mode for a predetermined time.

  Here, “normal symbol lottery” means that when a game ball passes through the normal symbol gate 13, the normal symbol determination random number value is acquired, and the acquired normal symbol determination random value corresponds to “winning”. This is a process for determining whether or not a random value. The lottery result of the normal symbol is not always notified immediately after the game ball passes through the normal symbol gate 13, but the normal symbol display device 22 displays a variation such as blinking of the normal symbol. When the fluctuation time elapses, the normal symbol corresponding to the lottery result of the normal symbol is stopped and displayed so that the player is notified of the lottery result.

Furthermore, if a game ball enters the first start port 14 or the second start port 15 during special symbol fluctuation display or a special game to be described later, and if the big hit lottery cannot be performed immediately, a certain condition The right to win a jackpot will be withheld. More specifically, the random number value for special symbol determination acquired when the game ball enters the first start port 14 is stored as the first hold, and when the game ball enters the second start port 15 The acquired special symbol determination random number value is stored as the second hold.
For both of these holds, the upper limit hold number is set to 4, and the hold number is displayed on the first special symbol hold indicator 23 and the second special symbol hold indicator 24, respectively. When there is one first hold, the LED on the left side of the first special symbol hold indicator 23 lights up, and when there are two first holds, two LEDs on the first special symbol hold indicator 23 Lights up. In addition, when there are three first holds, the LED on the left side of the first special symbol hold indicator 23 blinks and the right LED is lit, and when there are four first holds, the first special symbol hold. Two LEDs on the display 23 blink. The second special symbol hold indicator 24 also displays the number of second hold on hold in the same manner as described above.
The upper limit reserved number of normal symbols is also set to four, and the reserved number of normal symbols is displayed in the same manner as the first special symbol hold indicator 23 and the second special symbol hold indicator 24. Displayed on the instrument 25.

  The glass frame 50 supports a glass plate 52 that covers the game area 6 so as to be visible in front of the game board 2 (player side). The glass plate 52 is detachably fixed to the glass frame 50.

  Further, the glass frame 50 is connected to the outer frame 60 via a hinge mechanism 51 on one end side in the left-right direction (for example, the left side facing the gaming device 1). The end side (for example, the right side facing the gaming apparatus 1) can be rotated in a direction to release from the outer frame 60. The glass frame 50 covers the game board 2 together with the glass plate 52, and can be opened like a door with the hinge mechanism 51 as a fulcrum to open the inner part of the outer frame 60 including the game board 2. On the other end side of the glass frame 50, a lock mechanism for fixing the other end side of the glass frame 50 to the outer frame 60 is provided. The fixing by the lock mechanism can be released by a dedicated key. The glass frame 50 is also provided with a door opening switch 133 that detects whether or not the glass frame 50 is opened from the outer frame 60.

  On the back surface of the gaming apparatus 1, a main control board 110, an effect control board 120, a payout control board 130, a power supply board 170, a game information output terminal board 30, and the like are provided. Further, a power plug 171 for supplying power to the gaming apparatus 1 and a power switch (not shown) are provided on the power board 170.

(Block diagram of the entire gaming machine)
Next, control means for controlling the progress of the game will be described with reference to an overall block diagram of the gaming machine 1000 of FIG.

  The main control board 110 is a main control means for controlling the basic operation of the game, and receives various detection signals from the first start port detection switch 14a, etc., and the first special symbol display device 20 and the first big winning port opening / closing solenoid. The game is controlled by driving 16c and the like.

  The main control board 110 includes at least a one-chip microcomputer 110m including a main CPU 110a, a main ROM 110b, and a main RAM 110c, and an input port and an output port for the main control board.

  The main control board 110 is connected to the effect control board 120, the payout control board 130, and the power supply board 170.

  Further, on the input side of the main control board 110, a general winning port detection switch 12a for detecting that a game ball has entered the general winning port 12, and detecting that a game ball has entered the normal symbol gate 13 are detected. Gate detection switch 13a, first start port detection switch 14a for detecting that a game ball has entered the first start port 14, and second start port detection for detecting that a game ball has entered the second start port 15 A switch 15a, a first grand prize opening detection switch 16a that detects that a game ball has entered the first grand prize opening 16, and a second grand prize that detects that a game ball has entered the second grand prize opening 17. The mouth detection switch 17 a is also connected, and various signals are input to the main control board 110.

  Further, on the output side of the main control board 110, a start opening / closing solenoid 15c for opening / closing a pair of movable pieces 15b of the second start opening 15 and a first large winning opening opening / closing for operating a first large winning opening / closing door 16b. Solenoid 16c, second big prize opening opening / closing solenoid 17c for operating the second big prize opening opening / closing door 17b, first special symbol display device 20 and second special symbol display device 21 for displaying special symbols, normal displaying normal symbols Symbol display device 22, first special symbol hold indicator 23 and second special symbol hold indicator 24 for displaying the number of reserved balls of special symbols, normal symbol hold indicator 25 for displaying the number of reserved balls of normal symbols, for chips It is also connected to a game information output terminal board 30 that outputs external information, external information for variation, and external information for jackpots, and various signals are output.

  The main CPU 110a reads out a program stored in the main ROM 110b based on an input signal from each detection switch or timer, performs arithmetic processing, directly controls each device or display, or determines the result of the arithmetic processing. In response, a command is transmitted to another board.

The main ROM 110b of the main control board 110 stores a game control program and data and tables necessary for determining various games.
For example, a jackpot determination table referred to in the jackpot lottery (see FIG. 10), a hit determination table referred to in the normal symbol lottery (see FIG. 10), and a symbol determination table for determining a special symbol stop symbol (see FIG. 11). A model name storage area, a manufacturer name storage area, and the like are stored in the main ROM 110b.
Note that the above-described table is merely an example of characteristic tables among the tables in the present embodiment, and a number of other tables and programs (not shown) are provided for the progress of the game. ing.

The main RAM 110c of the main control board 110 functions as a data work area during the arithmetic processing of the main CPU 110a and has a plurality of storage areas.
For example, the main RAM 110c includes a special symbol special electricity processing data storage area, a normal symbol reservation number (G) storage area, a normal symbol reservation storage area, a normal symbol data storage area, a first special symbol reservation number (U1) storage area, 2 special symbol holding number (U2) storage area, first special symbol random value storage area, second special symbol random value storage area, round game number (R) storage area, number of times released (K) storage area, winning prize Number of balls (C) storage area, game state storage area (high probability game flag storage area and short-time game flag storage area), high probability game count (X) counter, short-time count (J) counter, game state buffer, stop symbol data Storage area, transmission data storage area for production, transmission data storage area for management equipment, transmission data storage area for hall facilities, special symbol time counter, special game timer counter, output timing count , Various timer counter such output timer are provided. Note that the above-described storage area is merely an example, and many other storage areas are provided.

  The game information output terminal board 30 outputs the chip external information, the fluctuation external information, and the jackpot external information generated in the main control board 110 to the information management device 200 or the hall equipment (not shown) of the game store. It is a substrate.

  Here, the chip external information output to the information management device 200 is composed of information of a plurality of bytes by serial communication. Data exchange with the gaming apparatus 1 must be performed. Therefore, the game information output terminal plate 30 is provided with a transmission element 30a such as a photocoupler, a relay, or a photomoss. The transfer element 30a is configured to allow the information management device 200 to input the chip external information output from the gaming device 1 while the information management device 200 and the gaming device 1 are insulated.

  The power supply board 170 is provided with a backup power supply composed of a capacitor, and supplies a power supply voltage to the gaming apparatus 1 and monitors a power supply voltage supplied to the gaming apparatus 1, and when the power supply voltage becomes a predetermined value or less, An interruption detection signal is output to the main control board 110. More specifically, when the power interruption detection signal becomes high level, the main CPU 110a enters an operable state, and when the power interruption detection signal becomes low level, the main CPU 110a enters an operation stop state. The backup power source is not limited to a capacitor, and may be a battery, for example, or a capacitor and a battery may be used in combination.

  The effect control board 120 mainly controls each effect such as during a game or standby. The effect control board 120 includes a sub CPU, a sub ROM, and a sub RAM, and is connected to the main control board 110 so as to be communicable in one direction from the main control board 110 to the effect control board 120. . The sub CPU reads out the program stored in the sub ROM based on the command transmitted from the main control board 110 or the input signal from the effect button detection switch 35a and the timer and performs arithmetic processing. Based on the above, the corresponding data is transmitted to the lamp control board 140 or the image control board 150. The sub RAM functions as a data work area during the arithmetic processing of the sub CPU.

  For example, when the sub CPU in the effect control board 120 receives a fluctuation pattern designation command indicating the fluctuation pattern of the special symbol from the main control board 110, the sub CPU analyzes the content of the received fluctuation pattern designation command, and displays the liquid crystal display device 31, voice Data for causing the output device 32, the effect driving device 33, and the effect lighting device 34 to execute a predetermined effect is generated, and the data is transmitted to the image control board 150 and the lamp control board 140.

The sub-ROM of the effect control board 120 stores an effect control program and data and tables necessary for determining various games.
For example, an effect pattern determination table for determining an effect pattern based on a variation pattern designation command received from the main control board, an effect symbol determination table for determining a combination of effect symbols 36 to be stopped, and the like are stored in the sub-ROM. Has been. Note that the above-described table is merely an example of characteristic tables among the tables in the present embodiment, and a number of other tables and programs (not shown) are provided for the progress of the game. ing.

The sub-RAM of the effect control board 120 functions as a data work area when the sub-CPU performs arithmetic processing, and has a plurality of storage areas.
The sub RAM is provided with a game state storage area, an effect mode storage area, an effect pattern storage area, an effect symbol storage area, and the like. Note that the above-described storage area is merely an example, and many other storage areas are provided.

The payout control board 130 is a board that controls the payout of game balls, and includes a one-chip microcomputer including a payout CPU, a payout ROM, and a payout RAM (not shown).
The payout control board 130 is connected to the main control board 110 via a wire (harness) and also connected to the information management apparatus 200 via a ball rental connection board 134. Also, the payout control board 130 is connected to the main control board 110 and the information management apparatus 200 (the ball rental connection board 134) so as to be able to communicate bidirectionally.

Also, on the input side of the payout control board 130, a payout ball count detection switch 132 and a door opening switch 133 for detecting whether or not a game ball has been paid out are also connected.
Further, the ball lending connection board 134 is connected with a ball lending switch 135 and a return switch 136, and various input signals of the ball lending switch 135 and the return switch 136 are sent through the ball lending connection board 134 to the payout control board. 130.

  Further, a payout motor 131 of a payout device for paying out a predetermined number of game balls from the game ball storage unit is connected to the output side of the payout control board 130.

The payout CPU is stored in the payout ROM based on input signals from the payout ball count detection switch 132, the door opening switch 133, the ball lending switch 135, the return switch 136 and the like for detecting whether or not the game ball has been paid out. Read the program and perform computations.
Specifically, when the payout CPU receives a payout number designation command generated when a game ball wins a predetermined winning opening from the main control board 110, the predetermined number according to the content of the payout number designation command is received. The game ball is paid out (prize ball control), and the payout motor 131 is driven to pay out a predetermined game ball.
In addition, when the payout CPU performs connection confirmation with the information management device 200 via the ball loan connection board 134 and then inputs a ball loan signal from the ball loan switch 135 via the ball loan connection board 134, the information management device 200. While exchanging information, a control (ball lending control) for paying out a specified number of game balls is performed, and a payout motor 131 is driven to pay out a predetermined game ball.

  The lamp control board 140 controls the lighting of the effect lighting device 34 provided on the game board 2 and controls the driving of the motor for changing the light irradiation direction. In addition, energization control is performed on a drive source such as a solenoid or a motor that operates the effect driving device 33. The lamp control board 140 is connected to the effect control board 120 and performs the above-described controls based on various commands transmitted from the effect control board 120.

  The image control board 150 stores a host CPU for performing image display control of the liquid crystal display device 31, a host RAM having a temporary storage area functioning as a work area for the host CPU 150a, a control processing program for the host CPU 150a, and the like. A host ROM, a CGROM storing image data, a VRAM having a frame buffer for drawing image data, a VDP (Video Display Processor) serving as an image processor, and a sound control circuit performing sound control are provided.

The host CPU instructs the liquid crystal display device 31 to display the image data stored in the CGROM in the VDP based on the effect pattern designation command received from the effect control board 120.
The VDP draws image data stored in the CGROM in the frame buffer of the VRAM based on an instruction from the host CPU. Next, a video signal (RGB signal or the like) is generated based on the image data stored in the display frame buffer in the VRAM, and the generated video signal is output to the liquid crystal display device.

  The sound control circuit includes an audio ROM that stores a large number of audio data. The sound control circuit reads out a predetermined program based on a command transmitted from the effect control board 120, and the audio output device 32. Audio output control at.

  The launch control board 160 performs launch control of the game ball. The launch control board 160 has a touch sensor 3a and a launch volume 3b connected to the input side, and a launch solenoid 4a and a ball feed solenoid 4b connected to the output side. The firing control board 160 inputs a touch signal from the touch sensor 3a and performs control to energize the firing solenoid 4a and the ball feed solenoid 4b based on the voltage supplied from the firing volume 3b.

  The touch sensor 3a is provided in the inside of the operation handle 3, and is comprised from the electrostatic capacitance type proximity switch using the change of the electrostatic capacitance by the player touching the operation handle 3. When the touch sensor 3a detects that the player has touched the operation handle 3, the touch sensor 3a outputs a touch signal that permits energization of the firing solenoid 4a to the firing control board 160 (see FIG. 5). As a major premise, the launch control board 160 is configured not to launch the game ball 99 into the game area 6 unless a touch signal is input from the touch sensor 3a.

  The firing volume 3b is provided directly connected to a rotating portion around which the operation handle 3 rotates, and is composed of a variable resistor. The firing volume 3b divides a constant voltage (for example, 5V) applied to the firing volume 3b by a variable resistor, and supplies the divided voltage to the launch control board 160 (the voltage to be supplied to the launch control board 160). Variable). The launch control board 160 energizes the launch solenoid 4a based on the voltage divided by the launch volume 3b and rotates the launch member 4c directly connected to the launch solenoid 4a, thereby playing the game ball 99 in the game. Fire into area 6.

  The launching solenoid 4a is composed of a rotary solenoid, and a launching member 4c is directly connected to the launching solenoid 4a, and the launching member 4c is rotated by rotating the launching solenoid 4a.

  Here, the rotation speed of the firing solenoid 4a is set to about 99.9 (times / minute) based on the frequency based on the output period of the crystal oscillator provided on the firing control board 160. As a result, the number of games played per minute is about 99.9 (pieces / minute) because one shot is fired every time the firing solenoid rotates. That is, one game ball is fired about every 0.6 seconds.

  The ball feed solenoid 4b is composed of a linear solenoid, and sends out the game balls in the tray 40 one by one toward the launch member 4c directly connected to the launch solenoid 4a.

  The information management apparatus 200 includes at least a management CPU 200a, a management ROM 200b, and a management RAM 200c.

  The management ROM 200b stores a program for controlling the information management apparatus 200, various data, and a table.

  The management CPU 200a reads out a program stored in the management ROM 200b and performs arithmetic processing, and performs ball lending control, analysis control of chip external information, and the like.

The management RAM 200c is composed of a non-volatile storage unit (flash memory or the like), functions as a data work area when the management CPU 200a performs arithmetic processing, and has a plurality of storage areas.
For example, the management RAM 200c includes a determination specific information storage area, a determination type information storage area, a determination manufacturer information storage area, an error determination counter, an illegal information storage area, a new stand information storage area, various timer counters, and the like. ing. Note that the above-described storage area is merely an example, and many other storage areas are provided.
In this embodiment, the management RAM 200c is configured by a nonvolatile storage unit. However, the management RAM 200c is configured by a volatile storage unit, a battery is provided in the information management apparatus 200, and the information management apparatus 200 is powered. Even if not supplied, the data stored in the management RAM 200c may be held.

(One-chip microcomputer configuration)
Next, the configuration of the one-chip microcomputer 110m provided on the main control board 110 will be described using the block diagram of the one-chip microcomputer shown in FIG.

In addition to the main CPU 110a, main ROM 110b, and main RAM 110c, the one-chip microcomputer 110m includes an input port 111, output ports 112 to 115, a first unique number register 116, a random number generator 117, connection terminals 118a to 118f, and a hardware ID output. Part 119.
Since the main CPU 110a, the main ROM 110b, and the main RAM 110c have been described above, other configurations will be described.

The input port 111 inputs a signal from the first connection terminal 118a.
Here, the first connection terminal 118a is connected to the general winning opening detecting switch 12a, the gate detecting switch 13a, the first starting opening detecting switch 14a, and the second starting opening detecting switch 15a via the internal bus on the main control board 110. The first big prize opening detection switch 16a and the second big prize opening detection switch 17a are connected. Therefore, various signals from various devices are input to the one-chip microcomputer 110m through the input port 111.

  Note that the connection terminals 118a to 118f in the embodiment do not indicate a one-pin connector, but are described by grouping a plurality of pins distinguished according to the signal type.

The first output port 112 outputs a signal to the second connection terminal 118b.
Here, the second connection terminal 118b is connected to the start opening / closing solenoid 15c, the first big prize opening / closing solenoid 16c, the second big prize opening opening / closing solenoid 17c, the first special opening via the internal bus on the main control board 110. The symbol display device 20, the second special symbol display device 21, the normal symbol display device 22, the first special symbol hold indicator 23, the second special symbol hold indicator 24, and the normal symbol hold indicator 25 are connected. Therefore, the first output port 112 outputs various signals from the one-chip microcomputer 110m to various devices.

The second output port 113 outputs a signal to the third connection terminal 118c.
Here, the third connection terminal 118 c is connected to the game information output terminal plate 30 that outputs the chip external information via an internal bus on the main control board 110. Therefore, the second output port 113 outputs the chip external information from the one-chip microcomputer 110m to the information management device 200 via the game information output terminal board 30.

  More specifically, the second output port 113 is composed of a serial communication IC that performs serial communication, and sequentially outputs an output buffer 113a that temporarily stores information to be output and information stored in the output buffer. And an output circuit 113b for outputting.

The output buffer 113a is configured to store an information amount of 32 bytes.
As will be described later, the chip external information stored in the output buffer 113a has an information amount of 39 bytes, and the storage capacity of the output buffer 113a is smaller than the information amount of the chip external information. .

  When information is stored in the output buffer 113a, the output circuit 113b adds a start bit, a parity bit, and a stop bit in units of 1 byte to the information stored in the output buffer 113a, and outputs the information by serial communication as game information. It outputs to the terminal board 30 (refer FIG. 7).

  At this time, the output circuit 113b outputs information to the game information output terminal board 30 at an extremely slow communication speed of 200 bps. Thereby, in the transmission element 30a (photocoupler, photomoss, relay, etc.) provided in the game information output terminal plate 30, it is possible to eliminate information loss.

The third output port 114 outputs a signal to the fourth connection terminal 118d.
Here, the fourth connection terminal 118d is connected to a game information output terminal board 30 that outputs the external information for variation and the external information for jackpot, which will be described later, via an internal bus on the main control board 110. For this reason, the third output port 114 outputs the variation external information and the jackpot external information to the game information output terminal board 30.
As described above, the game information output terminal board 30 can be connected to a hall equipment device (not shown) of a game store, and the external information for variation and the external information for jackpot generated by the one-chip microcomputer 110m are stored in the game. The information is output to the hall facility equipment via the information output terminal board 30.
Even if the second output port 113 and the third output port 11 output information to the same game information output terminal board 30, the second output port 113 is a serial output port. The third output port 11 is a normal output port that simply outputs a 1-bit signal. This is because the external information for chips is 39 bytes, whereas the external information for variation and the external information for jackpot are merely 1-bit signals.

The fourth output port 115 outputs a signal to the sixth connection terminal 118f.
Here, the sixth connection terminal 118 f is connected to the effect control board 120 via an internal bus on the main control board 110. For this reason, the information (control command) from the one-chip microcomputer 110m is output to the effect control board 120 by the fourth output port 115.

The first unique number register 116 is unique information data given at the time of manufacturing the one-chip microcomputer 110m, and is a register that stores a 4-byte first unique number that is different for each one-chip microcomputer 110m.
The first unique number register 116 is connected to the main CPU 110a via the internal bus of the one-chip microcomputer 110m. That is, the first unique number can be said to be a unique number of the one-chip microcomputer 110m that can be read from the user program.

  The random number generation unit 117 is a circuit that randomly generates a random value of 0 to 65535 (16 bits). The random number generation unit 117 is configured so that the random number values of 0 to 65535 are randomly updated in a cycle of 1 minute.

The hardware ID output unit 119 is a circuit for determining the validity of the one-chip microcomputer 110m by connecting an inspection device (not shown) to a predetermined connection terminal of the main control board 110.
Here, the predetermined connection terminal on the main control board 110 to which the inspection device is connected and the fifth connection terminal 118e on the one-chip microcomputer 110m (hardware ID output unit 119) are the internal parts on the main control board 110. Connected via bus. For this reason, data is exchanged between the inspection device and the hardware ID output unit 119 via the fifth connection terminal 118e.
The hardware ID output unit 119 includes a second unique number storage unit 119a and a collation circuit 119b.

The second unique number storage unit 119a is unique information data attached at the time of manufacturing the one-chip microcomputer 110m, and is a storage unit that stores a second unique number of 8 bytes that is different for each one-chip microcomputer 110m. Here, the first unique number and the second unique number are different numbers.
Unlike the first unique number register 116, the second unique number storage unit 119a is not connected to the main CPU 110a. That is, unlike the first unique number, the second unique number can be said to be a unique number of the one-chip microcomputer 110m that cannot be read from the user program.

When the verification circuit 119b inputs a read signal from the inspection device (not shown) via the fifth connection terminal 118e, the verification circuit 119b inputs the second unique number.
Then, the inputted second unique number and the second unique number stored in the second unique number storage unit 119a are compared, and if they match, it is determined that the one-chip microcomputer 110m is valid, If they do not match, it is determined that the one-chip microcomputer 110m is illegal.
As a result, if it is determined that it is a legitimate one-chip microcomputer 110m, a legitimate signal is output to the inspection device, and if it is determined that it is an illegal one-chip microcomputer 110m, an illegal signal is output to the inspection device. .
Here, the second unique number output from the inspection device (not shown) to the verification circuit 119b is encrypted, and after combining the second unique number encrypted by the verification circuit 119b, the one-chip microcomputer It is desirable to determine the correctness of 110m.

  Thus, the first unique number for determining fraud on the so-called software and the second unique number for judging fraud on the so-called hardware are different from the first unique number. Therefore, in order to create an illegal one-chip microcomputer 110m, not only the program ROM is altered, but also the main control board must be altered, and both software and hardware must be altered. Therefore, it is possible to make it more difficult to create a counterfeited one-chip microcomputer 110m and to further prevent illegal acts.

(Configuration of external information for chip output to information management device)
Next, the configuration of the chip external information output to the information management apparatus 200 will be described with reference to FIG. FIG. 7A is a diagram showing the data configuration of the chip external information, FIG. 7B is a diagram showing the output configuration of the chip external information, and FIG. 7C is the chip external information. It is a figure which shows the communication specification of information.

  As shown in FIG. 7A, the chip external information output to the information management device 200 includes a 32-byte “model name” indicating the model name of the gaming device 1 and 3 bytes indicating the name of the manufacturer of the gaming device 1. And the 4-byte “first unique number” which is the unique number of the one-chip microcomputer 110m mounted on the gaming device 1. That is, in this embodiment, 39-byte chip external information is configured.

The 32-byte “model name” and the 3-byte “maker name” are ASCII data having a 3-byte structure, and the information management apparatus 200 having input the “model name” and the “maker name” has a predetermined value. The “model name” and “manufacturer name” can be directly displayed on the display device.
Also, the information of “model name” and “maker name” is stored in advance in a predetermined storage area of the main ROM 110b, unlike the information of “first unique number”.

As shown in FIG. 7B, the second output port 113 configured by the serial communication IC adds a start bit immediately before the first bit (BIT0) of the 1-byte external information for the chip to 1 byte. The parity bit for error determination is added immediately after the last bit (BIT7) of the chip external information, and the stop bit is added at the end to sequentially output the chip external information. Therefore, the chip external information output to the information management apparatus 200 is output by asynchronous serial communication.
Further, when outputting 1-byte chip external information, 3 bits of a start bit, a parity bit, and a stop bit are added, and a total of 11 bits of information are output.
In the present invention, a unit of information amount in which 3 bits of a start bit, a parity bit, and a stop bit are added to 1-byte external information for a chip is referred to as “one frame”. That is, the 39-byte chip external information can be said to be 39-frame chip external information.

The communication specification of the second output port 113 configured with the serial communication IC will be described with reference to FIG.
The baud rate (communication speed) of the second output port 113 is set to a low baud rate of 200 bps. Therefore, the 1-bit output completion time is 5 ms. Then, the output completion time of one frame is 55 ms (= 5 ms × 11 bits), and the output completion time of one chip external information (39 frames) is 2145 ms (= 55 ms × 39 frames).

The baud rate (communication speed) of the second output port 113 is set to a slow baud rate of 200 bps for the following reason.
The game information output terminal plate 30 is configured to transmit the chip external information output from the gaming device 1 to the information management device 200 while the information management device 200 and the gaming device 1 are insulated. Coupler, relay, photo moss, etc.). For this reason, the communication speed of data between the information management device 200 and the gaming device 1 must be determined in consideration of the specification of the transfer element 30a (minimum time for data ON and OFF), and depends on the specification of the transfer element 30a. Therefore, the data communication speed between the information management device 200 and the gaming device 1 must be reduced.
For this reason, the communication speed (baud rate) of the second output port 113 is set so as to eliminate data omission in the transfer element 30a and to cope with product changes of various transfer elements 30a (in order to improve versatility). Is set to an extremely slow communication speed of 200 bps.

(External chip output information output method to the information management device)
Next, a method for outputting the chip external information to be output to the information management apparatus 200 will be described with reference to FIG.

As described above, the chip external information output to the information management apparatus 200 has an information amount of 39 bytes (39 frames). On the other hand, the storage capacity of the output buffer 113a is 32 bytes. For this reason, all the data of the chip external information output to the information management apparatus 200 cannot be stored in the output buffer 113a at a time. Further, the communication speed (baud rate) of the second output port 113 is set to an extremely slow communication speed of 200 bps.
For this reason, the output buffer 113a has a problem that data is easily accumulated and a part of the output data overflows. Further, even when the chip external information is divided into a plurality of data and the data is stored in the output buffer 113a, blank data not having any information is not output between the divided chip external information data. You must keep in mind.
Therefore, in this embodiment, the data of the chip external information to be output to the information management apparatus 200 is stored in the output buffer 113a as shown in FIG.

  FIG. 8 shows the data configuration stored in the management device transmission data storage area of the main RAM 110c in the upper row, and the data configuration stored in the output buffer 113a in the lower row.

FIG. 8A shows a state in which the main CPU 110a first generates the chip external information output to the information management apparatus 200 and stores the generated chip external information in the management apparatus transmission data storage area. .
At this time, no data is stored in the output buffer 113a (only blank data).

FIG. 8B shows the first byte data of the chip external information stored in the management device transmission data storage area (the data of the first byte of the “model name”) in the port output processing described later by the main CPU 110a. ) Is moved to the output buffer 113a.
Therefore, the output buffer 113a stores the chip external information for the first byte. Further, each data of the chip external information stored in the transmission data storage area for the management device is shifted, and when the shift is performed, blank data is stored in the last one byte.
If there is data in the output buffer 113a, the output circuit 113b outputs the data stored in the output buffer bit by bit.

  8C, when a specific time t (12 ms) has elapsed from FIG. 8B, the main CPU 110a is stored in the management device transmission data storage area in the same manner as FIG. 8B. This shows a state when the first byte data of the chip external information (the second byte data of the “model name”) is moved to the output buffer 113a.

Thereafter, similarly, every time the specific time t (12 ms) elapses, the main CPU 110a moves 1-byte data of the chip external information stored in the transmission data storage area for the management device to the output buffer 113a. To go.
Here, the “specific time t” means that the output of the excessive information amount (39 bytes−32 bytes = 7 bytes) obtained by subtracting the storage capacity of the output buffer 113a from the information amount of the chip external information is the second output port. A specific number (39-1 = 38) obtained by subtracting 1 from the excessive output completion time (55 ms × 7 bytes = 385) completed by 113 from the number of one byte of external information for chips (the number of times stored in the output buffer 113a) Unit output completion time (55 ms, hereinafter referred to as “second time”) that is longer than the time divided by 385 (38/38 = about 10.1 ms, hereinafter referred to as “first time”) and completes the output of one byte. Shorter time (10.1 ms ≦ t ≦ 55 ms).
In other words, if the time is longer than the “first time” (about 10.1 ms), the output buffer 113a does not overflow part of the data of the chip external information.
On the other hand, if the time is shorter than the “second time” (55 ms), even if the chip external information is divided into a plurality of data and stored in the output buffer 113a, blank data having no information is stored. There is no output between the divided pieces of external information data for the chip. Details will be described later with reference to FIG.

In FIG. 8D, 1-byte data of the chip external information stored in the management device transmission data storage area is moved to the output buffer 113a, and all blank data is stored in the management device transmission data storage area. It shows the state when
Thus, the main CPU 110a finishes the process of outputting one chip external information to the second output port 113 in the port output process described later.

FIG. 8 (e) shows a state when the output circuit 113b of the second output port 113 outputs all data stored in the output buffer 113a at a communication speed (baud rate) of 200 bps.
Thereby, the output of the chip external information from the gaming device 1 to the information management device 200 is completed.

(Timing of data input and output to the output buffer)
Next, timing for storing the chip external information data to be output to the information management apparatus 200 described in FIG. 8 in the output buffer 113a will be described with reference to FIG.

FIG. 9 is a time table for explaining the timing of data input and output to the output buffer 113a.
The time table includes, in order from the left, “data set time” indicating the time for moving (storing) the data of the chip external information stored in the transmission data storage area for the management device to the output buffer 113a, and for one frame. “Output completion time for one frame” when the output of the data of the chip external information is completed, “Data target” to be moved (stored) from the transmission data storage area for the management device to the output buffer 113a, “Data target for which output has been completed” and “Number of bytes used in output buffer” indicating the amount of information stored in the output buffer 113a are described.
Here, “data set time” and “output completion time for one frame” are the time elapsed from the time when the data stored in the transmission data storage area for the management apparatus is first stored in the output buffer 113a. Show.

As shown in FIG. 9, the main CPU 110a first stores in the output buffer 113a the first byte data of the “model name” of the chip external information stored in the management device transmission data storage area.
Thereafter, every 12 ms, 1-byte data of the chip external information stored in the management device transmission data storage area is stored in the output buffer 113a.

After 48 ms from the time when the data is first stored in the output buffer 113a,
The main CPU 110a causes the output buffer 113a to store the “model name” fifth byte data of the chip external information stored in the transmission data storage area for the management device.
At this time, since the output of one frame has not been completed yet, the number of used bytes of the output buffer 113a is 5 bytes.

Further, after 55 ms has elapsed from when the data was first stored in the output buffer 113a, the first byte of the “model name” stored first in the output buffer 113a by the output circuit 113b of the second output port 113. Data output will be completed.
At this time, since the output of one frame is completed, the number of bytes used in the output buffer 113a decreases from 5 bytes to 4 bytes.

  Thereafter, the main CPU 110a stores 1-byte data of the chip external information in the output buffer 113a every 12 ms, and the output of one frame is completed every 55 ms.

Then, after 456 ms has elapsed since the data was first stored in the output buffer 113a, all the chip external information data stored in the transmission data storage area for the management device was stored in the output buffer 113a. Become.
At this time, the maximum number of bytes used in the output buffer 113a is 31 bytes.
Thereafter, the output circuit 113b of the second output port 113 completes outputting 1 byte (one frame) stored in the output buffer 113a every 55 ms, and first stores data in the output buffer 113a. After 2415 ms have elapsed from the time of storage, the output of all the external information frames for chips ends.

Thus, when the “specific time t” is set to 12 ms, the number of bytes used in the output buffer 113a does not exceed 32 bytes because it is longer than the “first time” (about 10.1 ms). In this way, part of the external information data for the chip does not overflow.
Further, 12 ms as the “specific time t” is shorter than the “second time” (55 ms), so that blank data is not output between the external information data for chips.

  Next, details of various tables stored in the main ROM 110b will be described with reference to FIGS.

(Big hit judgment table)
FIG. 10A-1 and FIG. 10A-2 are diagrams showing a jackpot determination table used for the “hit lottery”. FIG. 10A-1 is a jackpot determination table referred to in the first special symbol display device 20, and FIG. 10A-2 is a jackpot determination table referred to in the second special symbol display device 21. is there. In the tables of FIG. 10A-1 and FIG. 10A-2, the winning probabilities are different, but the jackpot probabilities are the same.

Specifically, the big hit determination table is used to determine whether “big hit”, “small hit”, or “losing” based on the current probability gaming state and the acquired random number for determining a special symbol.
For example, according to the jackpot determination table for the first special symbol display device shown in FIG. 10 (a-1), in the low probability gaming state, two special symbol determination disturbances “7” and “8”. The number is determined to be a big hit. On the other hand, in the high probability gaming state, 20 special symbol determination random numbers “7” to “26” are determined to be big hits.
Further, according to the jackpot determination table for the first special symbol display device shown in FIG. 10 (a-1), the random number value for determining the special symbol is the low probability gaming state or the high probability gaming state. In the case of four special symbol determination random numbers “50”, “100”, “150”, and “200”, it is determined as “small hit”. If the random number is other than the above, it is determined as “lost”.
Therefore, since the random number range of the special symbol determination random number value is 0 to 598, the probability of being determined to be a big hit in the low probability gaming state is 1 / 299.5, and in the high probability gaming state, the big hit The probability to be determined is 10 times up to 1 / 29.9. In the first special symbol display device, the probability of being determined to be a small hit is 1159.75 regardless of whether the game state is a low probability game state or a high probability game state.

(Winning judgment table)
FIG. 10B is a diagram showing a hit determination table used for “ordinary symbol lottery”.
Specifically, the winning determination table determines whether it is “winning” or “lost” based on the presence / absence of the short-time gaming state and the acquired random number for normal symbol determination.
For example, according to the hit determination table shown in FIG. 10B, it is determined that one specific normal symbol random number for determination of “0” is a win when in the non-time-saving gaming state. On the other hand, when in the short-time gaming state, it is determined that 65535 specific random symbols for determining normal symbols from “0” to “65534” are hit. If the random number is other than the above, it is determined as “lost”.
Accordingly, since the random number range of the normal symbol determination random number value is 0 to 65535, the probability of being determined to be hit in the non-short-time gaming state is 1/65536, and the probability of being determined to be winning in the time-short gaming state is 65535/65536 = 1 / 1.00002.

(Design determination table)
FIG. 11 is a diagram showing a symbol determination table for determining a special symbol stop symbol.
FIG. 11A is a symbol determination table that is referred to in order to determine a stop symbol at the time of a big hit, and FIG. 11B is a symbol that is referred to in order to determine a stop symbol at the time of a big hit. FIG. 11C is a symbol determination table that is referred to in order to determine a stop symbol in the event of a loss.

Specifically, according to the symbol determination table shown in FIG. 11, the type of special symbol display device (the type of the start opening in which the game ball has won) and the game ball in the first start port 14 or the second start port 15. The special symbol type (stop symbol data) is determined based on the jackpot symbol random number value or the small bonus symbol random number value acquired when the ball is entered.
For example, the first special symbol display device refers to the symbol determination table shown in FIG. 11A in the case of a jackpot, and if the acquired jackpot symbol random value is “55”, the stop symbol data is “03”. ”(Special symbol 3 (first positive variation jackpot 3)) is determined. Further, in the first special symbol display device, the symbol determination table shown in FIG. 11B is referred to at the time of the small hit, and if the acquired random number value for the small hit symbol is “50”, as the stopped symbol data “08” (special symbol B (small hit B)) is determined. In case of loss, “00” (special symbol 0 (lost)) is determined as stop symbol data without referring to any random number value.

  Then, at the time of starting the change of the special symbol, an effect designating command is generated as special symbol information based on the determined special symbol type (stop symbol data). Here, the effect designating command is composed of 2-byte data, and 1-byte MODE data for identifying the control command classification and 1-byte DATA indicating the contents of the control command to be executed. It consists of data. The same applies to a variation pattern designation command described later.

  As will be described later, since the game state after the jackpot game and the type of jackpot game are determined by the type of special symbol (stop symbol data), the type of special symbol is the game state after the jackpot game ends. It can be said that the type of jackpot game is determined.

(Description of gaming state)
Next, the gaming state when the game progresses will be described. In this embodiment, there are “low probability gaming state” and “high probability gaming state” as the states related to the jackpot lottery, and “non-short-time gaming state” is the state relating to the pair of movable pieces 15b that the second starting port 15 has. And “short-time gaming state”. The state relating to the jackpot lottery (low probability gaming state, high probability gaming state) and the state relating to the pair of movable pieces 15b (non-short-time gaming state, short-time gaming state) can be associated with each other and are independent. You can also. That means
(1) “Low probability gaming state” and “Time saving gaming state”
(2) “Low probability gaming state” and “non-temporary gaming state”
(3) “High probability gaming state” and “short time gaming state”
(4) It is possible to provide a “high probability gaming state” and a “non-temporary gaming state”.
Note that the gaming state when the game is started, that is, the initial gaming state of the gaming device 1 is “low-probability gaming state” and is set to “non-short-time gaming state”. Is referred to as a “normal gaming state”.

In the present embodiment, the “low probability gaming state” means that in the jackpot lottery performed on the condition that a game ball has entered the first starting port 14 or the second starting port 15, the winning probability of the jackpot is 1 / The game state set to 299.5. On the other hand, the “high probability gaming state” means a gaming state in which the jackpot winning probability is set to 1 / 29.95. Therefore, in the “high probability gaming state”, it is easier to win a jackpot than in the “low probability gaming state”. Note that a high-probability game flag, which will be described later, is set in this high-probability game state, and the high-probability game flag is off in the low-probability game state.
Further, the low probability gaming state is changed to the high probability gaming state after the jackpot game described later is finished.

  In the present embodiment, the “non-short game state” means that, in the normal symbol lottery performed on the condition that the game ball has passed through the normal symbol gate 13, the variation time of the normal symbol corresponding to the lottery result is 29 seconds. And a game state in which the opening control time of the second start port 15 is set to be as short as 0.2 seconds. That is, when the game ball passes through the normal symbol gate 13, the normal symbol is drawn, and the normal symbol display device 22 displays the fluctuation of the normal symbol, but the normal symbol is displayed 29 seconds after the fluctuation display is started. Stop display later. If the lottery result is a win, the second start port 15 is controlled to the second mode for about 0.2 seconds after the normal symbol stop display.

On the other hand, the “short-time gaming state” means that the normal symbol variation time corresponding to the lottery result is 3 seconds in the normal symbol lottery performed on condition that the game ball has passed through the normal symbol gate 13. , A game that is set shorter than the “non-short game state”, and the opening control time of the second start port 15 when winning in the win is 3.5 seconds, which is set longer than the “non-short game state” State. Furthermore, in the “non-short-time gaming state”, the probability of winning in the normal symbol lottery is set to 1/65536, and in the “short-time gaming state”, the probability of winning in the normal symbol lottery is set to 65535/65536. Is set. At this time, the short-time game flag, which will be described later, is set in the short-time game state, and the short-time game flag is off in the non-short-time game state.
Therefore, in the “short-time gaming state”, the second starting port 15 is more easily controlled to the second mode as long as the game ball passes through the normal symbol gate 13 than in the “non-short-time gaming state”. Thereby, in the “short-time gaming state”, the player can advance the game without consuming the game ball.
In addition, since the normal symbol gate 13 is provided in the area on the right side of the game area 6, in the “short-time game state”, the operation handle 3 is greatly rotated, and the game ball is launched with a strong launch strength. Is configured to do.
Note that the probability of winning in the normal symbol lottery may be set so that it does not change in any of the “non-short-time gaming state” and the “time-short gaming state”.

  Next, the progress of the game in the gaming apparatus 1 will be described using a flowchart.

(Main processing of main control board)
The main process of the main control board 110 will be described with reference to FIG.

  When power is supplied from the power supply board 170, a system reset occurs in the main CPU 110a, and the main CPU 110a performs the following main processing.

  First, in step S1, the main CPU 110a performs an initialization process. In this process, the main CPU 110a reads a startup program from the main ROM 110b and initializes a flag stored in the main RAM 110c in response to power-on.

In step S2, the main CPU 110a performs chip external information generation processing.
In the chip external information generation process, the data of “first unique number” is read from the first unique number register 116, and “model name” data from the model name storage area of the main ROM 110b and the manufacturer name storage area of the main ROM 110b. The “maker name” data is read out, and external information for a chip as shown in FIG. 7A is generated.

In step S3, the main CPU 110a sets the chip external information generated in step S2 in the management device transmission data storage area of the main RAM 110c three times.
That is, when the power is turned on, the chip external information generated in step S2 is output three times.
Here, “set the chip external information in the management device transmission data storage area of the main RAM 110c three times” means that the same chip external information is stored in the management device transmission data storage area in one process. May be set (ie, 39 bytes × 3 = 118 bytes), or the same chip external information may be set three times each time output of one chip external information is completed.

  In step S20, the main CPU 110a performs an effect random number update process for updating the reach determination random value and the special figure variation random value for determining the variation mode (variation time) of the special symbol.

  In step S30, the main CPU 110a updates the initial random number value for special symbol determination, the initial random number value for big hit symbol, the initial random number value for small bonus symbol, and the initial random number value for normal symbol determination. Thereafter, the processes of step S20 and step S30 are repeated until a predetermined interrupt process is performed.

(Timer interrupt processing of main control board)
The timer interrupt process of the main control board 110 will be described using FIG.

  A clock pulse is generated every predetermined period (4 milliseconds) by the reset clock pulse generation circuit provided on the main control board 110, thereby executing a timer interrupt process described below.

  First, in step S100, the main CPU 110a saves the information stored in the register of the main CPU 110a to the stack area.

  In step S110, the main CPU 110a updates the special symbol time counter, updates the special game timer counter such as the opening time of the special electric accessory, updates the normal symbol time counter, and updates the normal power release time counter. A time control process for updating various timer counters is performed. Specifically, a process of subtracting 1 from a special symbol time counter, a special game timer counter, a normal symbol time counter, and a general electricity open time counter is performed.

In step S120, the main CPU 110a performs a random number update process for the special symbol determination random number value, the big hit symbol random number value, the small hit symbol random number value, and the normal symbol determination random number value.
Specifically, each random number value and random number counter are updated by adding +1. When the added random number counter exceeds the maximum value in the random number range (when the random number counter makes one revolution), the random number counter is returned to 0, and each random number value is newly updated from the initial random number value at that time. .

  In step S130, as in step S30, the main CPU 110a updates the initial random number value for special symbol determination, the initial random number value for jackpot symbol, the initial random number value for small bonus symbol, and the initial random number value for normal symbol determination. Perform numerical value update processing.

In step S200, the main CPU 110a performs input control processing.
In this process, the main CPU 110a includes a general winning opening detection switch 12a, a first large winning opening detection switch 16a, a second large winning opening detection switch 17a, a first starting opening detection switch 14a, a second starting opening detection switch 15a, a gate. An input process for determining whether or not there is an input to each switch of the detection switch 13a is performed.

  Specifically, various detection signals from the general winning opening detecting switch 12a, the first big winning opening detecting switch 16a, the second large winning opening detecting switch 17a, the first starting opening detecting switch 14a, and the second starting opening detecting switch 15a. Is inputted, predetermined data is added to the prize ball counter used for the prize ball provided for each prize opening and updated.

  Furthermore, when a detection signal is input from the first start port detection switch 14a, if the data set in the first special symbol hold number (U1) storage area is less than 4, the first special symbol hold number ( U1) Add 1 to the storage area to obtain special symbol determination random number value, jackpot symbol random number value, small hit symbol random number value, reach determination random value, and special symbol variation random value The random number value is stored in a predetermined storage unit (0th storage unit to 4th storage unit) in the first special symbol random value storage area.

  Similarly, when a detection signal is input from the second start port detection switch 15a, if the data set in the second special symbol hold number (U2) storage area is less than 4, the second special symbol hold number (U2) 1 is added to the storage area, and a special symbol determination random number value, a big hit symbol random number value, a small hit symbol random number value, a reach determination random number value, and a special symbol variation random value are acquired. Various random numbers are stored in a predetermined storage unit (0th storage unit to 4th storage unit) in the second special symbol random number value storage area.

  When a detection signal is input from the gate detection switch 13a, if the data set in the normal symbol hold number (G) storage area is less than 4, the normal symbol hold number (G) storage area is set to 1. It adds, acquires the random number value for normal symbol determination, and memorize | stores the acquired random number value for normal symbol determination in the predetermined memory | storage part (0th memory | storage part-4th memory | storage part) in a normal symbol holding | maintenance storage area.

  Further, when a detection signal is input from the first grand prize opening detection switch 16a or the second big prize opening detection switch 17a, the number of game balls won in the first big prize opening 16 or the second big prize opening 17 is counted. 1 is added to the number of entries (C) storage area for the big winning opening to update.

  In step S300, the main CPU 110a performs a special drawing special electric control process for controlling the jackpot lottery, the special electric accessory, and the gaming state. Details will be described later with reference to FIG.

In step S400, the main CPU 110a performs a normal / normal power control process for controlling the normal symbol lottery and the normal electric accessory.
Specifically, it is first determined whether or not 1 or more data is set in the normal symbol hold count (G) storage area, and 1 or more data must be set in the normal symbol hold count (G) storage area. If this is the case, the current ordinary power transmission control process is terminated.
If 1 or more data is set in the normal symbol holding number (G) storage area, after subtracting 1 from the value stored in the normal symbol holding number (G) storage area, it is in the normal symbol holding storage area The normal symbol determination random numbers stored in the first storage unit to the fourth storage unit are shifted to the previous storage unit. At this time, the normal symbol determination random value already written in the 0th storage unit is overwritten and erased.
Then, referring to the hit determination table shown in FIG. 10B, whether or not the normal symbol determination random number value stored in the 0th storage unit of the normal symbol hold storage area is a random value corresponding to “win”. Perform the process of determining. Thereafter, the normal symbol display device 22 displays the fluctuation of the normal symbol. When the fluctuation time of the normal symbol elapses, the normal symbol corresponding to the result of the normal symbol lottery is stopped and displayed. If the random number for normal symbol determination referred to is “winning”, the start opening / closing solenoid 15c is driven to control the second start opening 15 to the second mode for a predetermined opening time.
Here, in the non-short-time gaming state, the variation time of the normal symbol is set to 29 seconds, and if it is “winning”, the second start port 15 is controlled to the second mode for 0.2 seconds. On the other hand, in the short-time gaming state, the normal symbol variation time is set to 0.2 seconds, and if it is “winning”, the second start port 15 is controlled to the second mode for 3.5 seconds. .

In step S500, the main CPU 110a performs a payout control process.
In this payout control process, the main CPU 110a refers to each prize ball counter, generates payout number designation commands corresponding to various winning ports, and transmits the generated payout number designation commands to the payout control board 130. To do.

  In step S600, the main CPU 110a, external information data, start opening / closing solenoid data, first big prize opening opening / closing solenoid data, second big prize opening opening / closing solenoid data, special symbol display device data, normal symbol display device data, the number of memories Performs data creation for the specified command. Details will be described later with reference to FIGS. 16 and 17.

In step S700, the main CPU 110a performs output control processing. In this process, a port output process is performed for outputting signals of the external information data, the start opening / closing solenoid data, the first big prize opening / closing solenoid data, and the second big prize opening / closing solenoid data created in S600.
Further, the special symbol display device data and the normal symbol display device data created in S600 are used to turn on the LEDs of the first special symbol display device 20, the second special symbol display device 21 and the normal symbol display device 22. Display device output processing is performed. Further, command transmission processing for transmitting the command set in the effect transmission data storage area of the main RAM 110c to the effect control board 120 is also performed. Details will be described later with reference to FIGS. 18 and 19.

  In step S800, the main CPU 110a restores the information saved in step S100 to the register of the main CPU 110a.

(Special figure special electric control processing of main control board)
The special figure special power control processing of the main control board 110 will be described with reference to FIG.

First, in step S301, the value of the special figure special electricity processing data is loaded, the branch address is referred to from the special figure special electric treatment data loaded in step S302, and if the special figure special electric treatment data = 0, the special symbol memory determination process (step The process proceeds to S310). If the special symbol special power processing data = 1, the process proceeds to the special symbol variation processing (step S320). If the special symbol special power processing data = 2, the special symbol stop processing (step S330) is performed. If special figure special electric processing data = 3, the process moves to jackpot game processing (step S340), and if special figure special electric processing data = 4, the process moves to big hit game end processing (step S350). If special electric processing data = 5, the process moves to the small hit game ending process (step S360).
This “special drawing special electricity processing data” is set as necessary in each subroutine of the special figure special electricity control processing as will be described later, so that the subroutine necessary for the game is appropriately processed. .

  In the special symbol memory determination process in step S310, the main CPU 110a performs a jackpot determination process, a special symbol determination process for determining a special symbol to be stopped and displayed, a variation time determination process for determining a variation time of the special symbol, and the like. Here, the specific content of the special symbol memory determination process will be described with reference to FIG.

(Special symbol memory judgment processing of the main control board)
FIG. 15 is a diagram illustrating a special symbol memory determination process of the main control board 110.

First, in step S311, the main CPU 110a determines whether one or more data is set in the first special symbol hold count (U1) storage area or the second special symbol hold count (U2) storage area.
If one or more data is not set in any storage area of the first special symbol hold count (U1) storage area or the second special symbol hold count (U2) storage area, the special figure special electricity processing data = 0. The special symbol variation process of this time is terminated while holding.
On the other hand, if one or more data is set in the first special symbol hold count (U1) storage area or the second special symbol hold count (U2) storage area, the process proceeds to step S312.

In step S312, the main CPU 110a performs a jackpot determination process.
Specifically, when one or more data is set in the second special symbol hold count (U2) storage area, 1 is calculated from the value stored in the second special symbol hold count (U2) storage area. After the subtraction, the various random numbers stored in the first to fourth storage units in the second special symbol random number storage area are shifted to the previous storage unit. At this time, various random values already written in the 0th storage unit are overwritten and deleted. Then, with reference to the jackpot determination table shown in FIG. 10 (a-2), the random number for special symbol determination stored in the 0th storage unit of the second special symbol random number storage area corresponds to the “big hit”. It is determined whether it is a numerical value or a random value corresponding to “small hit”.
In addition, when one or more data is not set in the second special symbol hold number (U2) storage area and one or more data is set in the first special symbol hold number (U1) storage area, Various random numbers stored in the first to fourth storage units in the first special symbol random number storage area after subtracting 1 from the value stored in the first special symbol hold number (U1) storage area Is shifted to the previous storage unit. Also at this time, various random numbers already written in the 0th storage unit are overwritten and deleted. Then, with reference to the jackpot determination table shown in FIG. 10 (a-1), the random number value for special symbol determination stored in the 0th storage unit of the first special symbol random number storage area corresponds to “big hit”. It is determined whether it is a numerical value or a random value corresponding to “small hit”.
In the present embodiment, the random number value stored in the second special symbol random value storage area is shifted (digested) with priority over the first special symbol random value storage area. However, the first special symbol storage area or the second special symbol storage area may be shifted in the order of winning in the starting opening, and the first special symbol storage area is given priority over the second special symbol storage area. You may let them.

In step S313, the main CPU 110a performs a special symbol determination process for determining the type of special symbol to be stopped and displayed.
In this special symbol determination process, when it is determined as “big hit” in the jackpot determination process (step S312), the first special symbol random value storage area is referred to with reference to the symbol determination table shown in FIG. The jackpot symbol (special symbol 1 to special symbol 6) is determined based on the random number value for the jackpot symbol stored in the 0th storage unit. In addition, when it is determined as “small hit” in the big hit determination process (step S312), the 0th memory of the first special symbol random value storage area is referred to with reference to the symbol determination table shown in FIG. The small hit symbol (special symbol A, special symbol B) is determined based on the random number value for the small bonus symbol stored in the section. If it is determined that the game has been determined to be “lost” in the jackpot determination process (step S312), the lost symbol (special symbol 0) is determined with reference to the symbol determination table shown in FIG.
Then, stop symbol data corresponding to the determined special symbol is stored in the stop symbol data storage area.

In step S314, the main CPU 110a performs special symbol variation time determination processing.
Specifically, the variation pattern of the special symbol is determined based on the reach determination random number value and the special diagram variation random value stored in the 0th storage unit of the first special symbol random value storage area. Thereafter, the variation time of the special symbol corresponding to the determined variation pattern of the special symbol is determined. Then, a process of setting a counter corresponding to the determined variation time of the special symbol in the special symbol time counter is performed.

In step S315, the main CPU 110a sets, in a predetermined processing area, variation display data for causing the first special symbol display device 20 or the second special symbol display device 21 to perform special symbol variation display (LED blinking). . As a result, when the variable display data is set in the predetermined processing area, the LED lighting / extinguishing data is appropriately created in step S600, and the created data is output in step S700. Variation display of the special symbol display device 20 or the second special symbol display device 21 is performed.
Further, the main CPU 110a, when the special symbol variation display is started, the special symbol variation pattern designation command (the first special symbol variation pattern designation command) corresponding to the variation pattern of the special symbol determined in step S314. Alternatively, the second special symbol variation pattern designation command) is set in the effect transmission data storage area of the main RAM 110c.

  In step S316, the main CPU 110a sets the special symbol special electricity processing data = 0 to the special symbol special electric treatment data = 1, prepares to move to the special symbol variation processing subroutine, and ends the special symbol memory determination processing.

Again, the description of the special figure special electric control process shown in FIG. 14 will be returned.
In the special symbol variation process of step S320, the main CPU 110a performs a process of determining whether or not the special symbol variation time has elapsed.
Specifically, it is determined whether or not the variation time of the special symbol determined in step S314 has elapsed (special symbol time counter = 0), and if it is determined that the variation time of the special symbol has not elapsed The special symbol variation process is terminated while the special symbol special electricity processing data = 1 is held. Note that the special symbol variation time counter set in step S314 is subtracted in step S110.
If it is determined that the variation time of the special symbol has elapsed, the special symbol determined in step S313 is stopped and displayed on the first special symbol display device 20 or the second special symbol display device 21. Thereby, the special symbol is stopped and displayed on the first special symbol display device 20 or the second special symbol display device 21, and the player is notified of the jackpot determination result.
Also, when the number of time reduction (J)> 0, 1 is subtracted from the time reduction (J) counter and updated. When the number of time reduction (J) = 0, the time reduction game flag is cleared and the number of high probability games (X )> 0 is updated by subtracting 1 from the high probability game number (X) counter, and if the high probability game number (X) = 0, the high probability game flag is cleared.
Finally, the special symbol special power processing data = 1 is set to the special symbol special power processing data = 2, preparation is made to move to a special symbol stop processing subroutine, and the special symbol variation processing is terminated.

In the special symbol stop process in step S330, the main CPU 110a performs a process of determining whether the special symbol that is stopped and displayed is a “big hit symbol”, a “small bonus symbol”, or a “losing symbol”. Do.
If it is determined that the game is a jackpot symbol, the data stored in the gaming state storage area is referred to and data (00H to 03H) indicating the current gaming state is set in the gaming state buffer. Thereafter, the data (high probability game flag and short time game flag), high probability game number (X) counter, and short time number (J) counter stored in the high probability game flag storage area and the short time game flag storage area are cleared. . Further, the special figure special power processing data = 2 is set to the special figure special electric processing data = 3, preparation is made to move to the jackpot game processing subroutine, and the special symbol stop processing is ended.
In addition, when it is determined that the small winning symbol, the data stored in the game state storage area is not cleared, and the special figure special electric processing data = 2 to the special figure special electric treatment data = 5 is set. The special symbol stop process is completed by making preparations for transferring to a winning game process subroutine.
On the other hand, if it is determined that the symbol is a lost symbol, the special symbol special electric processing data = 2 is set to special special electric symbol processing data = 0, and the special symbol memory determination processing subroutine is prepared for the special symbol stop processing. finish.

In the jackpot game process of step S340, the main CPU 110a determines which jackpot of the long hit or short hit is executed, and performs a process of controlling the determined jackpot.
Specifically, the jackpot release mode is determined based on the type of jackpot symbol (stop symbol data) determined in step S313.
Next, in order to execute the determined jackpot opening mode, an opening time corresponding to the type of jackpot is set in the special game timer counter, and the first big winning opening opening / closing solenoid 16c (or the second big winning opening opening / closing solenoid) is set. 17c) is output to open the first big prize opening / closing door 16b (or the second big prize opening / closing door 17b). At this time, 1 is added to the round game count (R) storage area.
When a predetermined number of game balls enter during the opening or when the opening time of the big prize opening has elapsed (the number of the big prize opening (C) = 9 or the special game timer counter = 0), The output of the drive data of the big prize opening / closing solenoid 16c (or the second big prize opening / closing solenoid 17c) is stopped, and the first big prize opening / closing door 16b (or the second big prize opening / closing door 17b) is closed. Thereby, one round game is completed. This round game control is repeated 15 times.
When the 15 round games are completed (round game count (R) = 15), the data stored in the round game count (R) storage area and the number of winning prize entrance (C) storage areas are cleared, The special figure special electric processing data = 3 is set to the special figure special electric treatment data = 4, preparation is made to move to the big hit game end processing subroutine, and the big hit game processing is ended.

In the big hit game ending process in step S350, the main CPU 110a determines the probability gaming state of either the high probability gaming state or the low probability gaming state, and changes the gaming state of either the short-time gaming state or the non-short-time gaming state. Perform the decision process.
Specifically, based on the data stored in the game state buffer and the type of jackpot symbol (stop symbol data) determined in step S313, the setting of the high probability game flag, the number of high probability games (X) , Time-short game flag, time-short number of times (J).
For example, if the special symbols 1 to 3 and 5 corresponding to the probability variation jackpot, the high probability game flag is set in the high probability game flag storage area, and the high probability game number (X) counter is set to 10,000 times. Further, if the special symbols 1 to 3 and 5 corresponding to the probability variation jackpot are set, the time-short game flag is set in the time-short game flag storage area, and the time-short-time (J) counter is set to 10,000 times. On the other hand, if the special symbols 4 and 6 correspond to the normal jackpot, the high probability game flag is not set and the high probability game number (X) counter is set to zero. Further, if the special symbol 4 or 6 corresponding to the normal jackpot, the short time game flag is set, and the short time number (J) counter is also set to 100 times.
After that, the special symbol special power processing data = 4 is set to the special symbol special power processing data = 0, and preparation for moving to the special symbol memory determination processing subroutine is made, and the big hit game end processing is ended.

In the small hit game processing in step S360, the main CPU 110a determines the small hit release mode based on the type of small hit symbol (stop symbol data) determined in step S313.
Next, in order to execute the determined small hit opening mode, the small hit opening time is set in the special game timer counter, and the driving data of the second big winning opening / closing solenoid 17c is output to output the second big winning prize. The mouth opening / closing door 17b is opened. At this time, 1 is added to the number-of-releases (K) storage area.
When the small hit opening time elapses (special game timer counter = 0), the output of the drive data of the second big prize opening / closing solenoid 17c is stopped and the second big prize opening opening / closing door 17b is closed. The opening / closing control of the second big prize opening opening / closing door 17b is repeated 15 times.
Then, the opening / closing control of the second grand prize opening / closing door 17b is performed 15 times, or a predetermined number of game balls enter the second big prize opening 17 (the number of times of opening (K) = 15 or the grand prize opening entrance) Number (C) = 9), in order to end the small hit game, the output of the drive data of the second large winning opening / closing solenoid 17c is stopped, the number of times of opening (K) storage area and the number of winning winning holes (C) Clear the data stored in the storage area, set special figure special electricity processing data = 5 to special figure special electricity treatment data = 0, and prepare to move to a special symbol memory judgment processing subroutine. The winning game process is terminated.

(Data creation process)
The data creation process will be described with reference to FIG.

  In step S611, the main CPU 110a performs a process of creating drive data output as a port output in order to drive the start opening / closing solenoid 15c to an open or closed state.

  In step S612, the main CPU 110a performs a process of creating drive data output as a port output in order to drive the first big prize opening / closing solenoid 16c or the second big prize opening / closing solenoid 17c to an open or closed state.

  In step S613, the main CPU 110a outputs to the first special symbol display device 20 or the second special symbol display device 21 in order to turn on or off the first special symbol display device 20 or the second special symbol display device 21. The signal data to be created is processed.

  In step S614, the main CPU 110a performs processing for creating signal data to be output to the normal symbol display device 22 in order to turn on or turn off the normal symbol display device 22.

  In step S615, the main CPU 110a switches the first special symbol hold indicator 23, the second special symbol hold indicator 24, the second special symbol hold indicator 24, or the normal symbol hold indicator 25 to turn on or off. (2) A process for creating signal data to be output to the special symbol hold indicator 24 or the normal symbol hold indicator 25 is performed.

  In step S620, the main CPU 110a performs external information generation processing for generating external information for outputting game information of the main control board 110. Details will be described with reference to FIG.

(External information generation processing)
The external information generation process will be described with reference to FIG.

  In step S620-1, the main CPU 110a subtracts 1 from the output timing counter and updates it. That is, since the external information generation process is executed by the above-described timer interrupt process every 4 ms, 1 is subtracted from the output timing counter every 4 ms.

In step S620-2, the main CPU 110a determines whether or not the output timing counter = 0.
If the output time counter = 0, the process proceeds to step S620-3, and if the output time counter = 0, the process proceeds to step S620-8.

  In step S620-3, the main CPU 110a acquires one random value from the random number generation unit 117 as the information output random value.

In step S620-4, the main CPU 110a determines whether or not the acquired information output random number value is a specific random value (for example, 0).
As described above, the random number generation unit 117 randomly updates the random value of 0 to 65535 in a cycle of 1 minute, and a specific random value is acquired at random.
If the information output random value is a specific random value (for example, 0), the process proceeds to step S620-5 to perform chip external information generation processing, and the information output random value is a specific random value (for example, If it is not 0), the processing is moved to step S620-8 because the chip external information generation processing is not performed this time.

In step S620-5, the main CPU 110a performs chip external information generation processing.
The chip external information generation process in step S620-5 is the same process as the chip external information generation process in step S2, and thus the description thereof is omitted here.

In step S620-6, the main CPU 110a sets the chip external information generated in step S620-5 in the management device transmission data storage area of the main RAM 110c.
Here, unlike the step S3, the chip external information is set only once in the management device transmission data storage area. That is, when the power is turned on, the chip external information generated in the chip external information generation process is output three times. However, in the normal time (when the power is not turned on), the chip external information generation process is performed. Thus, the generated chip external information is output only once.
Thereby, it is possible to grasp whether the external information for the chip is generated when the power is turned on or the external information for the chip generated when the power is not turned on, based on the number of times the external information for the chip is output.
In this embodiment, the number of times of output is different only when the power is turned on and when the power is not turned on, but the number of times of output is also increased during jackpot game processing or during demonstration games where special symbols are not displayed. May be different.

In step S620-7, the main CPU 110a sets a 45000 counter corresponding to 3 minutes in the output timing counter.
By the processing of step S620-1 to step S620-7, the chip external information regarding the one-chip microcomputer 110m can be periodically output. In particular, as described in step S620-4, the chip external information can be output at random on the basis of 3 minutes, and the timer interrupt process in the gaming device 1 is updated from the output time of the chip external information. The timing is not analyzed and fraudulent acts can be suppressed.

In step S620-8, the main CPU 110a loads the data stored in the special figure special electricity processing data storage area, and determines whether or not special figure special electric treatment data = 2. That is, it is determined whether the special symbol stop process is in progress.
If special figure special power processing data = 2, the process proceeds to step S620-9, and if special figure special power processing data = 2, the process proceeds to step S620-14.

  In step S620-9, the main CPU 110a performs a variation external information generation process. Specifically, the external information data for change (1 bit data) indicating the number of changes of the special symbol is generated.

  In step S620-10, the main CPU 110a sets the variation external information generated in step S620-9 in the first area of the hall facility transmission data storage area.

In step S620-11, the main CPU 110a determines whether 01 to 06 is set in the stop symbol data storage area. That is, since the stop symbol data = 01 to 06 is a jackpot symbol as shown in FIG. 11, it is determined whether or not the special symbol that is stopped and displayed is a jackpot symbol.
If stop symbol data = 01 to 06, the process proceeds to step S620-12. If stop symbol data = 01 to 06, the external information generation process ends.

In step S620-12, the main CPU 110a performs chip external information generation processing.
Since the chip external information generation process in step S620-12 is the same process as the chip external information generation process in step S620-5, the description thereof is omitted here.

  In step S620-13, the main CPU 110a sets the chip external information generated in step S620-12 in the management device transmission data storage area of the main RAM 110c, and ends the external information generation process.

In step S620-14, the main CPU 110a loads the data stored in the special figure special electricity processing data storage area, and determines whether or not special figure special electric treatment data = 3. That is, it is determined whether or not the jackpot game process is in progress.
If the special figure special power processing data = 3, the process proceeds to step S620-15, and if the special figure special power processing data = 3, the external information generation process is terminated.

  In step S620-15, the main CPU 110a performs jackpot external information generation processing. Specifically, the jackpot external information data (1-bit data) indicating that the jackpot game is being generated is generated.

  In step S620-16, the main CPU 110a sets the jackpot external information generated in step S620-15 in the second area of the hall facility transmission data storage area, and ends the external information generation process.

(Output control processing)
The output control process will be described with reference to FIG.

In step S710, the main CPU 110a performs a first port output process.
In the first port output process, the start port opening / closing solenoid 15c, the first large winning port opening / closing solenoid 16c, the second large winning port opening / closing solenoid 17c, the first special symbol display device 20, the second special symbol display device 21, and the normal symbol display are displayed. In order to drive the device 22, the first special symbol hold indicator 23, the second special symbol hold indicator 24, or the normal symbol hold indicator 25, the various signals generated in the above steps S 611 to 615 are sent to the first output port 112. Process to output to.

In step S720, the main CPU 110a performs a second port output process.
In the second port output process, a process of outputting the data (chip external information) stored in the management device transmission data storage area to the second output port 113 is performed. Details will be described later with reference to FIG.

In step S730, the main CPU 110a performs a third port output process.
In the third port output process, a process of outputting data (external information for variation, external information for jackpot) stored in the hall facility transmission data storage area to the third output port 114 is performed.

In step S740, the main CPU 110a performs command output processing.
In the command output process, in order to transmit the command to the effect control board 120, a process of outputting the command set in the effect transmission data storage area of the main RAM 110c to the fourth output port 115 is performed.

(Second port output processing)
The second port output process will be described with reference to FIG.

In step S721, the main CPU 110a determines whether or not the chip external information is stored in the management device transmission data storage area.
If the chip external information is stored, the process proceeds to step S722. If the chip external information is not stored, the second port output process is terminated.

In step S722, the main CPU 110a updates the main RAM 110c by subtracting 1 from the output timer. That is, since the second port output process is executed every 4 ms, the output timer is subtracted every 4 ms.
First, when outputting the chip external information, the output timer is 0, and even if 1 is subtracted from the output timer, the output timer remains 0.

In step S723, the main CPU 110a determines whether or not the main RAM 110c output timer is zero.
If the output timer = 0, the process proceeds to step S724. If the output timer = 0 is not satisfied, the second port output process is terminated.

In step S724, as shown in FIGS. 8 and 9, the main CPU 110a sets the 1-byte data of the chip external information stored in the management device transmission data storage area in the output buffer 113a.
That is, by repeating this step S724 39 times every time the output timer = 0, 39-byte chip external information is set in the output buffer 113a.

In step S725, the main CPU 110a determines whether all data (39 bytes) of the chip external information stored in the management device transmission data storage area is set in the output buffer 113a.
If all the data of the chip external information is set in the output buffer 113a, the second port output process is terminated. If all the data of the chip external information is not set in the output buffer 113a, the process proceeds to step S726. Move.

In step S726, the main CPU 110a sets three counters corresponding to a specific time t (12 ms) in the main RAM 110c output timer, and ends the second port output process.
As described above, the “specific time t” is such that even if the chip external information is set for each byte, a part of the data of the chip external information does not overflow from the output buffer 113a. This is the time during which blank data is not output during output of external information.
Thereby, it is possible to accurately output the chip external information exceeding the storage capacity of the output buffer 113a.

  Next, the outline of the effect control board 120 will be briefly described.

  When the effect control board 120 receives a command transmitted from the main control board 110, a command reception interrupt process of the effect control board 120 occurs, and the received command is stored in the reception buffer.

  Then, the sub CPU in the effect control board 120 analyzes the received command and generates various commands corresponding to each command in the timer interrupt process of the effect control board 120 performed every 2 ms. Thereafter, the generated various commands are transmitted to the image control board 150 and the lamp control board 140.

  For example, when the sub CPU in the effect control board 120 receives the variation pattern designation command from the main control board 110, the sub CPU analyzes the content of the received variation pattern designation command, and the liquid crystal display device 31, the audio output device 32, the effect drive. A command for causing the device 33 and the effect lighting device 34 to execute a predetermined effect is generated, and the command is transmitted to the image control board 150 and the lamp control board 140.

  Next, the outline of the lamp control board 140 and the image control board 150 will be briefly described.

  In the lamp control board 140, upon receiving the production command from the production control board 120, the production drive device operation program is read based on the received production command, and the production drive device 33 is operated and controlled. The effect lighting device control program is read based on the received effect command, and the effect lighting device 34 is controlled.

  In the image control board 150, when the production command is received from the production control board 120, the audio CPU reads out the audio output device control program from the audio ROM based on the received production command, and the audio in the audio output device 32 is read. And the host CPU 150a reads the animation control program from the image ROM and controls the image display on the liquid crystal display device 31.

  Next, processing executed by the management CPU 200a in the information management apparatus 200 will be described.

(Main processing of the information management apparatus 200)
The main process of the information management apparatus 200 will be described with reference to FIG.

  In step S1000, the management CPU 200a performs an initialization process. In this process, the management CPU 200a reads the main process program from the management ROM 200b and initializes and sets a flag stored in the management RAM 200c in response to power-on. If this process ends, the process moves to a step S1100.

In step S1100, the management CPU 200a performs gaming device connection confirmation processing.
In this gaming machine connection confirmation process, a connection confirmation with the payout control board 130 of the gaming apparatus 1 is performed, and a confirmation process such as whether or not preparation for payout is made is performed.

In step S1200, the management CPU 200a performs a ball lending control process.
In this ball lending control process, when a ball lending signal based on the ball lending switch 135 is input from the payout control board 130 of the gaming apparatus 1, the money information of the money information medium (IC card or the like) accepted by the information management device 200 is confirmed. After that, a payout permission signal permitting the game device 1 to pay out a specified number of game balls is output to the payout control board 130. At this time, the money information of the money information medium (IC card or the like) is also updated.

In step S1300, the management CPU 200a performs a card return control process.
In this card return control process, when a return signal based on the return switch 136 is input from the payout control board 130 of the gaming apparatus 1, control is performed to return a monetary information medium (such as an IC card) received by the information management apparatus 200. .

In step S1400, the management CPU 200a performs external information input analysis processing.
In this external information input analysis process, when the chip external information is input from the game information output terminal board 30 of the gaming apparatus 1, the input chip external information is analyzed. Details will be described later with reference to FIG.
Thereafter, the processes in steps S1100 to 1400 are repeated.

(External information input analysis process of information management apparatus 200)
The external information input analysis process of the information management apparatus 200 will be described with reference to FIG.
In this external information input analysis process, the management CPU 200a performs a process of analyzing the chip external information stored in the reception buffer of the management RAM 200c. The chip external information output from the gaming apparatus 1 is stored in the reception buffer of the management RAM 200c.

In step S1401, the management CPU 200a confirms whether there is external chip information in the reception buffer, and confirms whether the external chip information has been input.
If there is no external chip information in the reception buffer, the management CPU 200a terminates the external information input analysis process. If there is external chip information in the reception buffer, the management CPU 200a moves the process to step S1402.

In step S1402, the management CPU 200a determines whether various data are stored in each of the determination specific information storage area, the determination type information storage area, and the determination manufacturer information storage area in the management RAM 200c. That is, at the time of initial setting, various data are not stored in the determination specific information storage area, the determination type information storage area, and the determination manufacturer information storage area in the management RAM 200c. Determine.
If data is stored in each of the determination-specific information storage area, the determination-type information storage area, and the determination-maker information storage area, the process proceeds to step S1404, and the determination-specific information storage area, the determination-type information is stored. If no data is stored in each of the information storage area and the determination maker information storage area, the process proceeds to step S1403.

In step S1403, the management CPU 200a generates “first unique number” data, “model name” data, and “manufacturer name” data based on the input chip external information, and generates the generated “first unique number”. The data is stored in the determination specific information storage area, the generated “model name” data is stored in the determination type information storage area, and the generated “maker name” data is stored in the determination maker information storage area. That is, in response to the initial setting, various data are stored in each of the determination specific information storage area, the determination type information storage area, and the determination maker information storage area based on the chip external information input for the first time. .
Then, the management CPU 200a transmits various data stored in the determination specific information storage area, the determination type information storage area, and the determination maker information storage area to the information collection server 400 via the Internet.

In step S1404, the management CPU 200a generates “first unique number” data based on the input chip external information, and stores the “first unique number” and the “first unique number” stored in the determination unique information storage area. It is determined whether or not the “1 unique number” data matches.
If the generated “first unique number” matches the “first unique number” data stored in the determination-specific information storage area, the process proceeds to step S1405 to generate the generated “first unique number”. If the “first unique number” data stored in the determination specific information storage area does not match, the process proceeds to step S1406.

  In step S1405, the management CPU 200a has acquired the valid one-chip microcomputer 110m information from the input chip external information, and therefore resets the error determination counter in the management RAM 200c (sets the error determination counter to 0). This external information input analysis process ends.

In step S1406, the management CPU 200a generates “model name” data based on the input chip external information, and generates the “model name” and the “model name” data stored in the determination type information storage area. Are determined to match.
If the generated “model name” matches the “model name” data stored in the determination type information storage area, the process proceeds to step S1408, and the generated “model name” and determination type information are stored. If the “model name” data stored in the area does not match, the process proceeds to step S1407.

In step S1407, the management CPU 200a generates “maker name” data based on the input chip external information, and the generated “maker name” and “maker name” data stored in the determination manufacturer information storage area. Are determined to match.
If the generated “manufacturer name” matches the “manufacturer name” data stored in the determination manufacturer information storage area, the process proceeds to step S1408, and the generated “manufacturer name” and determination manufacturer information are stored. If the “maker name” data stored in the area does not match, the process proceeds to step S1411.

In step S1408, the management CPU 200a adds 1 to the error determination counter in the management RAM 200c and updates it.
That is, the “first unique number” data, the “model name” data, and the “manufacturer name” data generated based on the input chip external information are used as the determination specific information storage area, the determination type information storage area, and the determination. As a result of comparison with each data in the manufacturer information storage area, if at least one is different (except when all are different), the valid one-chip microcomputer 110m information cannot be obtained from the input external information for the chip. Therefore, 1 is added to the error determination counter. However, since there is a possibility of a communication error, it is not immediately determined that the one-chip microcomputer 110m is illegal.

In step S1409, the management CPU 200a determines whether or not the error determination counter in the management RAM 200c is 3.
If the error determination counter is 3, the process proceeds to step S1410 to generate “illegal information” to be described later. If the error determination counter is not 3, the current external information input analysis process is terminated.

In step S1410, the management CPU 200a determines that it is an illegal one-chip microcomputer 110m because the information on the valid one-chip microcomputer 110m cannot be obtained three times continuously from the input chip external information. The “illegal information” indicating that the illegal one-chip microcomputer 110m is mounted is generated, and the generated “illegal information” is stored in the illegal information storage area. Thereafter, the “illegal information” stored in the unauthorized information storage area is transmitted to the information collecting server 400 via the Internet.
Here, if the chip external information is input three times within a predetermined input time and it is determined that the chip is an unauthorized one-chip microcomputer 110m, the chip external information output when the gaming device 1 is powered on. “Unauthorized information 1” is generated as unauthorized information based on the information. On the other hand, if the chip external information is input three times with a predetermined input time and it is determined that it is an illegal one-chip microcomputer 110m, the chip that is output when the gaming device 1 is not turned on. “Unauthorized information 2” is generated as the unauthorized information based on the external information.
As a result, it is possible to feed back information (problems of the gaming machine) that is likely to be fraudulent to the gaming machine manufacturer. It is possible to strengthen the prevention of actions and take effective post countermeasures.

In step S1411, the management CPU 200a determines that each data of the “first unique number”, “model name”, and “manufacturer name” generated based on the input chip external information is a unique information storage area for determination, Since all the data stored in the model information storage area and the manufacturer information storage area for determination are all different, the game apparatus 1 is treated as having been changed, and "new machine information" data is generated from the "model name" data. Then, the generated “new machine information” data is stored in the new machine information storage area.
The “new machine information” data is connected to the information management apparatus 200 or the information management apparatus 200 when the gaming machine 1 is changed (so-called new machine replacement) by using the “model name” data that is ASCII data as it is. The displayed display device can display the model name of the new stand without any work.

In step S1412, the management CPU 200a converts each data of the “first unique number”, “model name”, and “manufacturer name” generated based on the input chip external information into the determination unique information storage area, the determination The model information storage area and the determination maker information storage area are updated and stored. That is, in response to the change of the gaming apparatus 1, the data in the determination specific information storage area, the determination type information storage area, and the determination maker information storage area are updated.
Then, the management CPU 200a transmits the data stored in each of the determination specific information storage area, the determination type information storage area, and the determination maker information storage area to the information collection server 400 via the Internet. The information input analysis process is terminated.

(Embodiment 2)
Next, a second embodiment corresponding to a modification of the first embodiment will be described. The second embodiment is different in the configuration of the chip external information of the first embodiment.

  That is, the chip external information of the first embodiment, as shown in FIG. 7A, is composed of three pieces of information of “model name”, “manufacturer name”, and “first unique number”. As shown in FIG. 22A, the chip external information in the form 2 indicates the gaming state when the “model name”, “manufacturer name”, “first unique number”, and first unique number are output. It is different in that it is composed of four pieces of information of “game state”.

  Specifically, as shown in FIG. 22A, the chip external information of the second embodiment indicates a 32-byte “model name” indicating the model name of the gaming apparatus 1 and the manufacturer name of the gaming apparatus 1. A 2-byte “maker name”, a 4-byte “first unique number” that is a unique number of the one-chip microcomputer 110m mounted on the gaming device 1, and a 1-byte indicating a gaming state when the first unique number is output. It is composed of “gaming state” and is 39-byte external information for chips.

  Similarly to the first embodiment, the external information for a chip composed of such four pieces of information is stored in the transmission data storage area for the management device every time the main CPU 110a passes a specific time t (12 ms). The external chip data is stored in the output buffer 113a byte by byte (see FIGS. 8 and 9). Then, the output circuit 113b of the second output port 113 completes outputting 1 byte (one frame) stored in the output buffer 113a every 55 ms.

Further, the “gaming state” of the external information for chips is stored in correspondence with the gaming state at each time point in the external information generation processing for chips by the main CPU 110a (step S2, step S620-5, step S620-12). Generated.
Specifically, in the chip external information generation processing at the time of power-on in step S2 in FIG. 12, data for power-on (FFH) is generated as “game state” data. Further, in the chip external information generation processing at step S620-5 and step S620-12 in FIG. 17, the data stored in the special figure special electricity processing data storage area is referred to, and the special figure special electric treatment data = 0. If there is, “00H” is generated as the “gaming state” data, and if the special figure special electric processing data = 1, “01H” is generated as the “gaming state” data, and if the special figure special electric processing data = 2. “02H” is generated as the data of “gaming state”, and “03H” is generated as the data of “gaming state” if the special figure special electric processing data = 3, and “game” if the special figure special electric processing data = 4 “04H” is generated as the “state” data, and “05H” is generated as the “game state” data if the special figure special processing data = 5.

Further, when the information management apparatus 200 inputs the chip external information of the second embodiment, the same processing as the processing shown in FIGS. 20 and 21 of the first embodiment is performed.
Furthermore, in addition to the processing of the first embodiment, in step S1410 of FIG. 21, not only “illegal information” is generated, but also “gaming state” data is generated based on the input external information for chips. The “gaming state” data is also stored in the unauthorized information storage area together with the “illegal information”. Then, the data of “illegal information” and “gaming state” stored in the unauthorized information storage area is transmitted to the information collecting server 400 via the Internet.
Here, the “illegal information” and the “gaming state” are not configured as separate data, but the “illegal information” is generated based on the generated “gaming state”. You may comprise so that it may transmit to.
As a result, it is possible to specify the state in which the illegal one-chip microcomputer 110m has been replaced more specifically. In addition, it is possible to feed back information (problems of gaming machines) that is likely to be fraudulent to the gaming machine manufacturer, and the gaming machine manufacturer changes the design of the gaming machine or develops the next model. Prevention can be strengthened, and effective post measures can be taken.

(Embodiment 3)
Next, a third embodiment corresponding to a modification of the first embodiment will be described. The third embodiment is different from the first embodiment in the method of outputting the chip external information.

  In other words, the chip external information according to the first embodiment stores the chip external information data stored in the management device transmission data storage area byte by byte in the output buffer 113a every time a specific time t (12 ms) elapses. In the third embodiment, each game information unit included in the chip external information (32-byte “model name”, 3 bytes “manufacturer name”) is configured to be stored (see FIGS. 8 and 9). A 4-byte “first unique number”) is stored in the output buffer 113a.

  FIG. 23 is a conceptual diagram of a chip external information output method according to the third embodiment, and FIG. 24 is an explanatory diagram regarding the timing of data input and output to the output buffer according to the third embodiment.

(Method for Outputting External Information for Chip in Embodiment 3)
Next, a method for outputting chip external information to be output to the information management apparatus 200 will be described with reference to FIG.

  As in FIG. 8, FIG. 23 shows the data configuration stored in the transmission data storage area for the management device of the main RAM 110c in the upper stage, and the data configuration stored in the output buffer 113a in the lower stage. .

FIG. 23A shows a state in which the main CPU 110a first generates the chip external information to be output to the information management device 200, and stores the generated chip external information in the management device transmission data storage area. .
At this time, no data is stored in the output buffer 113a (only blank data).

FIG. 23B shows that the main CPU 110a moves the 32-byte data of “model name” of the external information for chip stored in the transmission data storage area for management device to the output buffer 113a in the port output processing. Shows the state.
For this reason, the output buffer 113a stores the chip external information of 32-byte data of “model name”. Each data of the chip external information stored in the transmission data storage area for the management device is shifted, and when the shift is performed, blank data for 32 bytes is stored.
If there is data in the output buffer 113a, the output circuit 113b outputs the data stored in the output buffer bit by bit.

  In FIG. 23C, the main CPU 110a completes the output of the 3-byte data stored in the output buffer by the output circuit 113b from the state shown in FIG. The state when the stored 3-byte data of “maker name” of the external information for chip is moved to the output buffer 113a is shown.

In FIG. 23D, the output circuit 113b completes output of the 4-byte data stored in the output buffer from the state of FIG. 23C, and the main CPU 110a enters the management device transmission data storage area. This shows a state when the 4-byte data of the “first unique number” of the stored external information for chip is moved to the output buffer 113a.
Thereby, all the blank data is stored in the transmission data storage area for the management apparatus, and the main CPU 110a finishes the process of outputting one chip external information to the second output port 113 in the port output process.

FIG. 23 (e) shows a state when the output circuit 113b of the second output port 113 outputs all the data stored in the output buffer 113a at a communication speed (baud rate) of 200 bps.
Thereby, the output of the chip external information from the gaming device 1 to the information management device 200 is completed.

(Timing of data input and output to the output buffer in the third embodiment)
Next, the timing for storing the chip external information data to be output to the information management apparatus 200 described in FIG. 23 in the output buffer 113a will be described with reference to FIG.

FIG. 23 is a time table for explaining the timing of data input and output to the output buffer 113a.
In the time table of FIG. 23, as in FIG. 9, in order from the left, “data set time”, “output completion time for one frame”, “data target to be stored”, and “data for which output has been completed” “Target” and “Number of bytes used in output buffer” are described.

As shown in FIG. 23, the main CPU 110a first stores the 32-byte data of the “model name” of the chip external information stored in the transmission data storage area for the management device in the output buffer 113a.
At this time, since the output of one frame has not been completed yet, the number of bytes used in the output buffer 113a is 32 bytes.

  Thereafter, the output circuit 113b of the second output port 113 completes outputting 1 byte (one frame) stored in the output buffer 113a every 55 ms.

Then, after 165 ms has elapsed since the data was first stored in the output buffer 113a, the output circuit 113b of the second output port 113 completes the output of 3 bytes (3 frames).
At this time, the number of used bytes of the output buffer 113a is 29 bytes.

In the timer interrupt of the main CPU 110a immediately after the output of 3 bytes (3 frames) is completed (after 168 ms has elapsed since the data was first stored in the output buffer 113a), it is stored in the transmission data storage area for the management device. The 3-byte data of “maker name” of the external information for the chip is stored in the output buffer 113a.
At this time, the number of used bytes of the output buffer 113a is 32 bytes.

After 385 ms has elapsed since the data was first stored in the output buffer 113a, the output circuit 113b of the second output port 113 completes the output of 4 bytes (4 frames).
At this time, the number of used bytes in the output buffer 113a is 28 bytes.

In the timer interrupt of the main CPU 110a immediately after the output of 4 bytes (4 frames) is completed (after 388 ms has elapsed since the data was first stored in the output buffer 113a), it is stored in the transmission data storage area for the management device. The 4-byte data of the “first unique number” of the external information for the chip is stored in the output buffer 113a.
As a result, all of the chip external information data stored in the transmission data storage area for the management device is stored in the output buffer 113a.
At this time, the number of used bytes of the output buffer 113a is 32 bytes.

  Thereafter, output of 1 byte (one frame) stored in the output buffer 113a is completed every 55 ms by the output circuit 113b of the second output port 113, and data is first stored in the output buffer 113a. After 2415 ms have elapsed from the time of the application, the output of all the external information frames for chips ends.

  In this way, the 39-byte external chip information is equal to or less than the storage capacity (32 bytes) of the output buffer 113a, and the game information unit (32-byte “model name”, 3 bytes “maker name”, 4 bytes When the data for each game information unit is stored in the output buffer 113a, the data of each game information unit is stored in the output buffer 113a. Therefore, a part of the data of the chip external information does not overflow from the output buffer 113a. Further, even if the chip external information is divided into a plurality of data and stored in the output buffer 113a, blank data having no information may be output between the divided chip external information data. Disappear.

(Second port output processing in the third embodiment)
The output method as shown in FIGS. 23 and 24 is performed in the second port output process.
Therefore, the second port output processing in the third embodiment will be described with reference to FIG.

  Here, the second port output process in the third embodiment differs from the second port output process in the first embodiment (see FIG. 19) in the data target in step S724 and the counter value in step S726. Since other processes are the same, description thereof is omitted.

In step S724 of the third embodiment, the main CPU 110a sets data in a predetermined range of the chip external information stored in the management device transmission data storage area in the output buffer 113a.
That is, when the output timer = 0 first, the 32-byte data of “model name” is set in the output buffer 113a, and when the output timer = 0 becomes the second time, the 3-byte data of “maker name” is set. When the output timer is set to 0 for the third time, the 4-byte data of the “first unique number” is set in the output buffer 113a, and the 39-byte chip external information is stored in the output buffer 113a. set.
Thereby, the data is stored in the output buffer 113a in the game information unit (32-byte “model name”, 3 bytes “maker name”, 4 bytes “first unique number”) included in the external information for chips. be able to.

In step S726 of the third embodiment, the main CPU 110a sets a predetermined counter in the main RAM 110c output timer, and ends the second port output process.
Here, the “predetermined counter” means a counter corresponding to the time when the data for the information amount set in the output buffer 113a in the next step S724 is output by the output circuit 113b.
Specifically, in the first step S726, since the 3-byte data of “maker name” is set in the output buffer 113a in the next step S724, the output of 3 bytes of data from the output buffer 113a is completed 165 ms. 42 counter (168 ms) corresponding to is set. In the second step S726, since the 4-byte data of the “first unique number” is set in the output buffer 113a in the next step S724, the output of the 4-byte data from the output buffer 113a is completed at 220 ms. The corresponding 55 counter (220 ms) is set.
As a result, when there is enough data to store data for each game information unit in the output buffer 113a, the data for each game information unit can be stored in the output buffer 113a.
As described above, as shown in FIGS. 23 and 24, it is possible to accurately output the chip external information exceeding the storage capacity of the output buffer 113a.

As described above, according to the first to third embodiments, in addition to the information management apparatus 200 automatically determining the validity of the one-chip microcomputer 110m based on the first unique number, the inspection device is used based on the second unique number. Also, the validity of the one-chip microcomputer 110m can be determined.
As a result, when the fraud determination information from the first unique information is notified, the validity of the one-chip microcomputer can be confirmed again by referring to the second unique information, resulting in erroneous determination due to noise. This can be prevented.

Further, according to the first to third embodiments, the first unique number register 116 is accessible by the main CPU 110a, whereas the second unique number storage unit 119a is inaccessible by the main CPU 110a. It has become.
For this reason, in order to create a counterfeit one-chip microcomputer, not only the program ROM must be tampered with, but the circuit board must be tampered with, and both software and hardware must be tampered with. Making microcomputers more difficult makes it possible to further strengthen fraud prevention.

Further, according to the first to third embodiments, when the chip management information is input from the gaming apparatus 1 during the initial setting, the information management apparatus 200 generates a first unique number from the chip external information and stores the first unique number in the management RAM 200c. One unique number is stored. When the chip management information is newly input from the gaming device 1, the information management device 200 newly generates a first unique number from the chip external information and compares it with the first stored unique number. 110m fraud is determined.
This eliminates the need to input the first unique number of the one-chip microcomputer 110m in the information management apparatus 200, and allows the unauthorized one-chip microcomputer to be used without giving the first unique number to a large number of persons such as game shop employees and salesmen. Judgment is possible.

In addition, according to the first to third embodiments, when the external information for chips is input from the gaming apparatus 1 during the initial setting, the information management device 200 generates the first unique number, the model name, and the manufacturer name from the external information for chips. Then, the first unique number, the model name, and the manufacturer name are stored in the management RAM 200c. When the information management device 200 newly inputs the chip external information from the gaming device 1, the information management device 200 newly generates a first unique number, model name, and manufacturer name from the chip external information, and stores the first unique number and model already stored. Compare with name and manufacturer name. Different first natural number and determines that the determination to match the model name or manufacturer name one chip is invalid microcomputer 110m, first unique number, which is all the model name and manufacturer name different the exchange of new machines.
For this reason, when the gaming device 1 is replaced, the one-chip microcomputer is also changed, so that the “unique information” is different. In such a case, an erroneous determination is made so as not to determine that it is illegal. Can be prevented.

Further, according to the first to third embodiments, the gaming apparatus 1 periodically provides the information management apparatus 200 with the chip external information related to the validity of the one-chip microcomputer 110m while maintaining randomness. (3-4 minutes).
For this reason, the update timing of the timer interrupt process in the gaming apparatus 1 is not analyzed from the output timing of the external information for chips, and fraud can be suppressed.

  In the first to third embodiments, the information management device 200 is configured to perform ball lending control that allows the game device 1 to pay out a specified number of game balls, but does not perform ball lending control. In addition, a configuration that only collects and manages information related to the gaming apparatus 1 may be used.

  In the first to third embodiments, the chip external information to be output to the information management apparatus 200 is configured to be output by serial communication, but may be configured to be output by parallel communication.

  In addition, according to the first to third embodiments, the gaming machine used for the pachinko gaming machine has been described. .

1 gaming device 2 gaming board 30 gaming information output terminal board 30a transmission element 110 main control board 110a main CPU
110b Main ROM
110c Main RAM
110m One-chip microcomputer 111 Input port 112 to 115 Output port 116 First unique number register 117 Random number generator 118a to 118f Connection terminal 119 Hardware ID output 119a Second unique number storage 119b Collation circuit 200 Information management device 200a Management CPU
200b Management ROM
200c management RAM

Claims (3)

An information storage unit storing game information for executing a predetermined game ;
An arithmetic processing unit that performs arithmetic processing related to the predetermined game according to the game information stored in the information storage unit;
A first unique information storage unit that stores first unique information uniquely assigned to each product unit with respect to the information storage unit or the arithmetic processing unit;
A second unique information storage unit that stores second unique information uniquely assigned to each product unit with respect to the information storage unit or the arithmetic processing unit;
A first unique information output unit that outputs information including the first unique information stored in the first unique information storage unit to a predetermined external terminal;
A second unique information output unit that outputs the second unique information stored in the second unique information storage unit to a predetermined external terminal;
The arithmetic processing unit and the first specific information storage unit are connected by a signal line for sending a signal related to the game information, while the arithmetic processing unit and the second specific information storage unit are connected by the signal line. Not connected,
The arithmetic processing unit includes:
Game state control means for controlling a game state relating to the predetermined game;
When outputting the first unique information to a predetermined external terminal, state information is generated based on the gaming state controlled by the gaming state control means, and the generated state information and the first unique information And external information generating means for generating external information including information, and
When there is a specific command from the arithmetic processing unit via the signal line, the first unique information output unit sends the external information including the first unique information and the state information to the predetermined external Output to the terminal
The second specific information output unit has an input terminal for reading predetermined information from the outside. When the predetermined information is read from the input terminal, the second specific information output unit outputs the second specific information to the predetermined external terminal. A gaming machine characterized by that. The first unique information output unit outputs the first unique information to a first output terminal,
The gaming machine according to claim 1, wherein the second unique information output unit outputs the second unique information to a second output terminal different from the first output terminal.   The first unique information stored in the first unique information storage unit is different from the second unique information stored in the second unique information storage unit. Or the gaming machine according to claim 2.