JP5258343B2 - Semiconductor device and semiconductor integrated circuit - Google Patents

Description

  The present invention relates to a short-range non-contact communication technology between semiconductor integrated circuits stacked and mounted on a substrate. For example, a modularized semiconductor device such as a SIP (system in package), and further to the semiconductor device The present invention relates to a technology that is effective when applied to a semiconductor integrated circuit having a wireless communication interface function.

  With the progress of microfabrication technology, the performance of semiconductor integrated circuits has been improved by integrating more transistors on one chip (semiconductor substrate). However, due to the limitations of miniaturization and the increase in the cost of using cutting-edge processes, it is not always the optimal solution to proceed with integration on a single chip. Therefore, three-dimensional integration by stacking a plurality of semiconductor integrated circuits is a promising technology. In order to improve performance by three-dimensional integration (also referred to as 3D integration or 3D stacking), a mechanism for performing high-speed and large-capacity communication between stacked semiconductor integrated circuits is required. Further, the power accompanying it is at a level that cannot be ignored with respect to the power consumption of the processor. For this reason, high-speed and large-capacity communication between semiconductor integrated circuits and a technique for performing it with low power are important techniques when performing 3D stacking of semiconductor integrated circuits.

  Wired systems and wireless systems are being studied as communication systems for stacked semiconductor integrated circuits. As a wired method, there are a method of making a via (hole) in the substrate silicon of a semiconductor integrated circuit and a method of wire bonding, but the former has a scene that can be used due to a load on the manufacturing process because a via is made in the substrate silicon. In the latter case, the wiring becomes longer and the effect of 3D stacking becomes lower in terms of performance and power. The method of performing communication wirelessly is expected to be an effective method even in scenes where the above wired method cannot be used due to these problems.

  In communication between a mobile phone and a base station, or in general wireless communication used in wireless LAN, the transmitting side sends data after performing some modulation operation on the data. Sampling at a sufficiently fast rate is performed, and the data is subjected to arithmetic processing to reproduce the transmission data. However, this method increases the amount of calculation and power consumption, and increases the time until the receiving side obtains data. Therefore, although it may be an application scene where communication distance is long and communication is allowed to be costly, overhead is too large for communication between extremely short distances such as communication between stacked semiconductor integrated circuits.

  Patent Documents 1 to 4 describe a wireless communication technique with low overhead suitable for short-distance communication between 3D stacked semiconductor integrated circuits.

  In addition, in the case of communication between 3D stacked semiconductor integrated circuits, there are manufacturing variations in individual semiconductor integrated circuits, which are affected by differences in operating conditions such as temperature and operating power supply voltage. It is considered a good idea to make it possible. Patent Document 5 describes a technique that employs a configuration that corrects transmission path characteristics on the reception side, although it is wired communication.

JP 2005-228981 A JP 2006-50354 A JP 2006-173415 A JP 2006-173986 A JP 2002-223204 A

  The inventor examined timing adjustment in short-range communication between 3D stacked semiconductor integrated circuits. First, when correcting the transmission path characteristics on the receiving side as described in Patent Document 5, each wireless communication interface circuit that performs transmission / reception in bi-directional communication such as full duplex must have a timing adjustment function. In other words, it has been clarified that the circuit scale for timing adjustment is increased as a whole.

  Secondly, it is not a communication method that reproduces transmission data by sampling at a sufficiently high rate with respect to the transmission data rate as in wireless communication used in a wireless LAN or the like, but simply sends data sent from the transmission side. It has been clarified that the method in which the receiving side captures in accordance with the transmission timing requires a highly accurate timing adjustment with respect to the transmission / reception timing of the transmission / reception data. That is, in the method in which the data sent from the transmission side is captured by the reception side in accordance with the transmission timing, it is essential for the semiconductor integrated circuit on the reception side to capture the data transmitted from the transmission side at an appropriate timing, For example, in data communication by inductive coupling between 3D stacked semiconductor integrated circuits, it is necessary to capture data in the receiving circuit in accordance with the timing of current flowing through the transmitting coil. In short, the clock signal that defines the transmission timing is also transmitted together with the transmission data, and the reception side must receive the data in synchronization with the reception clock. In short-range communication between 3D stacked semiconductor integrated circuits, manufacturing variations between semiconductor integrated circuits and differences in operating conditions directly affect communication timing. In this respect, highly accurate timing adjustment is required. In any of the above-mentioned patent documents, there is no indication that such highly accurate timing adjustment is required in short-range communication between 3D stacked semiconductor integrated circuits.

  An object of the present invention is to provide a semiconductor device capable of reducing the overall scale of a circuit for adjusting communication timing in short-range communication between stacked semiconductor integrated circuits.

  Another object of the present invention is to provide a semiconductor device capable of adjusting communication timing in short-range communication between stacked semiconductor integrated circuits with high accuracy.

  Still another object of the present invention is to provide a semiconductor integrated circuit that can contribute to the realization of a semiconductor device that can adjust the communication timing in short-range communication between stacked semiconductor integrated circuits with high accuracy. .

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  That is, in a semiconductor device including a pair of stacked semiconductor integrated circuits capable of wireless communication with each other, the semiconductor integrated circuit transmits transmission data wirelessly together with a clock signal that defines transmission timing, and the wireless transmission timing is adjusted. A transmission circuit that is enabled, a reception circuit that is configured to receive data in synchronization with a clock signal received wirelessly, and that is capable of adjusting a wireless reception timing; and another circuit that is responsive to the data transmitted from the transmission circuit. And a control circuit that adjusts the timing of the transmission circuit and the reception circuit based on whether the data returned from the semiconductor integrated circuit and received by the reception circuit is correct.

  As described above, the control timing of one semiconductor integrated circuit can adjust the communication timing in the wireless communication loop returned via the wireless communication interface circuit between the other semiconductor integrated circuits. The circuit scale can be reduced as compared with the case where the timing adjustment is separately performed on the receiving side of both semiconductor integrated circuits.

  In addition, since the transmission clock signal and transmission data transmission timing, reception clock timing and data reception timing can be adjusted, even if there is a mismatch in manufacturing variations in individual semiconductor integrated circuits, the short distance between the semiconductor integrated circuits Communication timing in communication can be adjusted with high accuracy.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  In other words, the scale of the circuit for adjusting the communication timing in the near field communication between the stacked semiconductor integrated circuits can be reduced in the entire semiconductor device.

  In addition, the communication timing in the short-range communication between the stacked semiconductor integrated circuits can be adjusted with high accuracy.

1. First, an outline of a typical embodiment of the invention disclosed in the present application will be described. Reference numerals in the drawings referred to in parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

  [1] A semiconductor device according to the present invention includes a pair of semiconductor integrated circuits that are stacked and capable of wireless communication with each other. The semiconductor integrated circuit is configured to transmit transmission data wirelessly and set a wireless transmission timing that can be adjusted based on control data set to be rewritable, and to receive data wirelessly and to be rewritable A receiving circuit whose wireless reception timing can be adjusted based on the control data to be received, and whether the data received by the receiving circuit returned from another semiconductor integrated circuit in response to the data transmitted from the transmitting circuit is correct And a control circuit for adjusting the timing of the transmission circuit and the reception circuit.

  As described above, the control timing of one semiconductor integrated circuit can adjust the communication timing in the wireless communication loop returned via the wireless communication interface circuit between the other semiconductor integrated circuits. The circuit scale can be reduced as compared with the case where the timing adjustment is separately performed on the receiving side of both semiconductor integrated circuits.

  [2] In the semiconductor device of [1], the transmission circuit transmits data in synchronization with the clock signal together with, for example, a transmission clock signal, and the transmission clock signal and the transmission clock signal according to the value of the control data set in the variable delay circuit Data transmission timing is adjusted. The receiving circuit receives, for example, a clock signal and receives data in synchronization with the received clock signal, and the data reception timing by the receiving clock is adjusted according to the value of the control data set in the variable delay circuit.

  From the above, the transmission timing of the transmission clock signal and transmission data, the timing of the reception clock, and the data reception timing can be adjusted, so even if there is a mismatch in manufacturing variations in individual semiconductor integrated circuits, the temperature, power supply voltage, etc. Even if the operating conditions change, the communication timing in the short-range communication between the semiconductor integrated circuits can be adjusted with high accuracy.

  [3] In the semiconductor device of [2], the transmission circuit can individually adjust transmission timings of the transmission clock signal and data. In addition, finer timing adjustment is possible.

  [4] In the semiconductor device of [1], the control circuit is, for example, a processor unit, and the processor unit writes transmission data to be transmitted from the transmission circuit, and reads reception data received by the reception circuit.

  [5] In the semiconductor device of [4], the processor unit performs the timing adjustment in an initialization operation by a power-on reset and when a communication error occurs. The contents of timing adjustment can be defined in a programmable manner by software executed by the processor unit.

  [6] In the semiconductor device according to item 1, a pattern generator that sequentially generates transmission data and expected value data corresponding thereto, and reception data returned in response to transmission of transmission data generated from the pattern generator And a determination circuit for determining whether the data matches the expected value and storing the result. Timing adjustment can be easily performed, and the burden on the processor unit can be reduced.

  [7] In the semiconductor device of [6], the determination circuit stores the number of mismatch determination results. When an environment where an ECC (Error Checking and Correcting) function can be used for received data is taken into consideration, it becomes possible to determine whether timing adjustment is necessary in relation to the error correction capability. If an error correction function such as ECC is not considered or cannot be used, if the number of mismatches is other than 0, it will be determined that the timing adjustment is necessary.

  [8] In the semiconductor device of [6], the control circuit is a processor unit capable of reading a determination result stored in the determination circuit. The contents of the determination operation can be defined in a programmable manner by software executed by the processor unit.

  [9] In the semiconductor device of [7], the processor unit performs the timing adjustment in an initialization operation by a power-on reset and when a communication error occurs. The contents of timing adjustment can be defined in a programmable manner by software executed by the processor unit.

  [10] In the semiconductor device of [1], only one of the pair of semiconductor integrated circuits has the transmitting circuit, the receiving circuit, and the control circuit, and the other of the pair of semiconductor integrated circuits is the one semiconductor integrated circuit. A wireless communication interface circuit for receiving data from the transmitting circuit and transmitting data to the receiving circuit of the one semiconductor integrated circuit. The other semiconductor integrated circuit is a bus slave device such as a memory device.

  [11] In the semiconductor device of item 10, the wireless communication interface circuit includes a selector capable of selectively forming a direct reply path for transmitting the received data as it is. In adjusting the timing, the other semiconductor integrated circuit does not require any special operation of the internal circuit connected to the wireless communication interface circuit.

  [12] In the semiconductor device of [2], each of the pair of semiconductor integrated circuits includes the transmission circuit, the reception circuit, and the control circuit. Both semiconductor integrated circuits are bus master devices such as a microcomputer.

  [13] In the semiconductor device of item 12, each of the pair of semiconductor integrated circuits further includes a switch circuit capable of selectively forming a direct reply path for transmitting the data received by the receiving circuit as it is by the transmitting circuit. . When adjusting the timing, the semiconductor integrated circuit of the other party of the adjustment does not require any special operation of the internal circuit connected to the transmission circuit and the reception circuit.

  [14] A semiconductor device according to another aspect of the present invention includes a pair of semiconductor integrated circuits that are stacked and capable of wireless communication with each other, and the semiconductor integrated circuit wirelessly transmits transmission data together with a clock signal that defines transmission timing. A transmission circuit that can transmit and adjust transmission timing by radio; a reception circuit that receives data in synchronization with a clock signal received by radio and that can adjust reception timing by radio; and And a control circuit that adjusts the timing of the transmission circuit and the reception circuit based on the correctness of the data returned from another semiconductor integrated circuit in response to the transmitted data and received by the reception circuit.

  [15] A semiconductor product circuit according to another aspect of the present invention includes a processor unit and a wireless communication interface circuit, and the wireless communication interface circuit is set to transmit transmission data wirelessly and to be rewritable. A transmission circuit capable of adjusting the wireless transmission timing based on the control data, and a reception circuit capable of adjusting the wireless reception timing based on the control data set to be rewritable while receiving the data wirelessly Have The processor unit adjusts the timing of the transmission circuit and the reception circuit based on whether the data returned from the outside in response to the data transmitted from the transmission circuit and received by the reception circuit is correct.

  [16] In the semiconductor integrated circuit of item 15, the transmission circuit transmits data in synchronization with the clock signal together with the transmission clock signal, and the transmission clock signal and the transmission clock signal according to the value of the control data set in the variable delay circuit Data transmission timing is adjusted. The receiving circuit receives the clock signal, receives data in synchronization with the received clock signal, and adjusts the data reception timing by the receiving clock according to the value of the control data set in the variable delay circuit.

2. Details of Embodiments Embodiments will be further described in detail. DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments for carrying out the invention, and the repetitive description thereof will be omitted.

  FIG. 2 schematically illustrates an overview of a semiconductor device according to the present invention. Two semiconductor integrated circuits (LSI 1 and LSI 2) 3 and 4 are stacked on top of a package board (PKG) 2 as a wiring board, and sealed with a resin (not shown) to constitute a semiconductor device 1. For example, an array of solder balls is formed on the back surface of the package board as external connection terminals. The semiconductor integrated circuit 3 includes a transmission circuit (IDTX) 5 and a reception circuit (IDRX) 6 as an interface circuit for wireless communication. The semiconductor integrated circuit 4 includes a transmission circuit (IDTX) 7 and a reception circuit as an interface circuit for wireless communication. (IDRX) 8 is included. The receiving circuit 8 receives data and a clock signal transmitted from the transmitting circuit 5. The reception circuit 6 receives data and a clock signal output from the transmission circuit 7.

  FIG. 1 illustrates a block diagram of a semiconductor device. In the semiconductor integrated circuit 3, reference numeral 10 denotes a processing unit (PU) such as a CPU (central processing unit), and a plurality of processing units (PU) are arranged. Reference numeral 11 denotes a control circuit (3DC) for controlling the wireless communication between the semiconductor integrated circuit 4 by controlling the transmission circuit 5 and the reception circuit 6, and the transmission circuit 5 and the reception circuit 6 are connected to the control circuit 11. Is done. Reference numeral 12 denotes a peripheral circuit (PHR), which is a generic term for other peripheral circuits. Reference numeral 13 denotes an interface circuit (2DC) for communicating with other devices mounted on the surface of the system board via the external connection terminals of the package 2. The interface circuit 13, the peripheral circuit 12, the control circuit 11, and the processing unit 10 are connected to an on-chip interconnect circuit (ONCIC) 15, and can be connected to each other through this. The interconnect circuit 15 is composed of, for example, a split transaction bus and a router, and a request packet from the initiator is transferred to the target, and the target returns a response packet to the initiator of the transfer as necessary, and performs bus control by a data transfer protocol. Do. Reference numeral 16 denotes a PLL (Phase Locked Loop) circuit that generates a clock signal for internal synchronous operation of the semiconductor integrated circuit. In the figure, an internal clock signal CK3D output from the PLL circuit 16 to the control circuit 11, the transmission circuit 5, and the reception circuit 6 is illustrated.

  The semiconductor integrated circuit 4 is a memory device, for example. Reference numeral 17 denotes a control circuit (3DC) that controls the wireless communication with the semiconductor integrated circuit 3 by controlling the transmission circuit 7 and the reception circuit 8. Reference numeral 18 denotes a processing circuit (FUNCC), for example, a memory unit including a memory array and a memory control circuit. The transmission circuit 7 and the reception circuit 8 do not have a timing adjustment function for wireless communication, which will be described later. This timing adjustment function is realized by the transmission circuit 5, the reception circuit 6, the control circuit 11 and the like of the semiconductor integrated circuit 3.

  As a wireless communication system, there are a system using magnetic inductive coupling and a system using electric field capacitive coupling. Here, a magnetic inductive coupling system using a coil is selected. A receiving voltage such as VRXW can be obtained in the coil on the receiving side by applying an input current having an angled waveform such as ITXW in FIG. 6 to the coil on the transmitting side. Communication is possible by acquiring reception data in synchronization with the timing of the reception voltage. In the example of FIG. 6, the value of VRXW is acquired at the timing of the rising edge of the clock signal CLK. For this reason, the rising edge timing of the clock signal CLK needs to be adjusted to a period SWD in which information appears in VRXW. Hereinafter, such a timing adjustment function will be described.

  The control circuit 11 has a target port (TGPT) 20 for receiving access from the interconnector 15 and transmitting data to the interconnector 15. A memory circuit (DLCR) 21, a pattern generation circuit (PTGEN) 22, an error determination circuit (ERRCT) 23, a selector (SEL 1), and an error detection circuit (EDC) 25 are connected to the target port 20. The memory circuit 21 holds control data for adjusting transmission / reception timing. Control data is written from a predetermined processor unit 10 via a target port 20. The selector 24 selects transmission data output from the pattern generation circuit 22 or transmission data transferred from the interconnector 15 to the target port. The pattern generation circuit 22 is a circuit for generating a test pattern for confirming the communication status. The error determination circuit 23 compares the reception data returned from the semiconductor integrated circuit 4 in response to the transmission data generated by the pattern generation circuit 22 and the expected value data generated by the pattern generation circuit 22 to generate an error. It is a circuit that determines whether or not there is an error and accumulates the number of error determinations. The accumulated error determination count can be read by a predetermined processor unit 10 via the target port 20. The pattern generation circuit 22 and the error determination circuit 23 are circuits provided to reduce the burden on the processor unit 10 to confirm the communication status. When determining the communication status without using the pattern generation circuit 22 and the error determination circuit 23, transmission data for that purpose is supplied from the predetermined processor unit 10 to the target port 20 and returned from the semiconductor integrated circuit 4 in response thereto. The received data or the absence of a necessary response is checked by the error detection circuit 25 and returned to the predetermined processor unit 10. Even without the error detection circuit 25, the absence of a required response can be determined by the absence of a response from the target port to the predetermined processor unit over a certain period. When there is a response, the predetermined processor unit 10 can determine the communication state by determining whether or not the received data returned corresponding to the transmission data is as expected.

  The transmission circuit 5 includes a transmission driver (IDTXC) 31 for driving the wireless communication antenna 30 for clock transmission and a transmission driver (IDTXD) 33 for driving the wireless communication antenna 32 for data transmission. Connected to the transmission driver 31 is a variable delay circuit (XTDLC) 34 that provides the clock signal CK3D with an amount of delay specified by the control data of the storage circuit 21 and outputs the same to the clock transmission driver 31. The clock transmission driver 31 drives the antenna 30 using the delayed clock signal output from the variable delay circuit 34 as a transmission signal. Connected to the transmission driver 33 is a variable delay circuit (TXDLD) 35 that provides the clock signal CK3D with an amount of delay specified by the control data of the storage circuit 21 and outputs it to the data transmission driver 33. The data transmission driver 33 drives the antenna 30 according to the transmission data of the data register (FF) 36 in synchronization with the rising edge of the delayed clock signal output from the variable delay circuit 35. The driving form is as shown in FIG. 6 corresponds to the delayed clock signal output from the variable delay circuit 35. Therefore, the data transmission timing indicated by the waveform ITXW and the clock transmission timing indicated by the waveform CLK in FIG. 6 can be adjusted in a programmable manner by the control data set in the variable delay circuits 34 and 35. The content of the adjustment is determined according to a program executed by a predetermined processor unit 10. The register 36 latches data output from the selector 24 in synchronization with the clock signal CK3D. The latch timing may be synchronized with the delayed clock signal output from the variable delay circuit 35. Here, it is synchronized with the clock signal CK3D output from the PLL circuit 16. Since the control circuit 11 is operated in synchronization with the clock signal CK3D, the control circuit 11 and the transmission circuit 5 are separated if the latch clock of the first stage latch circuit (register 36) interfaced with the control circuit 11 is also set to the same clock. This is because the design of the interface timing of the transmission data is simplified when designing the transmission data.

  The reception circuit 6 includes a reception driver 41 for driving the wireless communication antenna 40 for clock reception and a reception driver 42 for driving the wireless communication antenna 42 for data reception. The clock signal received by the reception driver 41 is supplied to the variable delay circuit 45. The variable delay circuit 45 gives an amount of delay specified by the control data of the storage circuit 21 to the clock signal from the reception driver 41 and outputs it to the data reception driver 43. The data reception driver 43 receives data in synchronization with the rising edge of the delay clock signal output from the variable delay circuit 45 and supplies the reception data to the reception data register 46. Therefore, the data reception timing indicated by the waveform VRXW and the clock timing indicated by the waveform CLK in FIG. 6 can be adjusted in a programmable manner by the control data set in the variable delay circuit 45. The content of the adjustment is determined according to a program executed by a predetermined processor unit 10. The latch timing of the data register 46 is synchronized with the clock signal CK3D for the same reason as described above. The latch data of the data register 46 is supplied to the error determination circuit 23 or the error detection circuit 25.

  In the example of FIG. 1, the semiconductor integrated circuit 3 starts communication with the semiconductor integrated circuit 4, and the semiconductor integrated circuit 4 performs processing based on the transmitted information and returns the result. Hereinafter, a semiconductor integrated circuit that starts communication is also referred to as a master LSI 3, and a semiconductor integrated circuit 4 that receives communication from the master LSI 3 and returns a processing result is also referred to as a slave LSI 4.

  FIG. 3 illustrates an example of a flow for adjusting the communication timing of the semiconductor device 1. In this embodiment, the predetermined processor unit 10 generates a communication status confirmation pattern. The predetermined processor unit 10 of the master LSI 3 performs, for example, writing and reading with respect to the memory unit 18 of the slave LSI 4, and compares the written value with the read value to determine whether communication is being performed correctly. When communication is not performed correctly, the predetermined processor unit 10 changes the value of the storage circuit 21 in the control circuit 11 of the master LSI 3 to change the transmission / reception timing, and the communication is performed in the flow of writing, reading, and value comparison. Repeat until successful. When the communication is correctly performed, the predetermined processor unit 10 repeatedly performs the above-described write operation and the like a predetermined number of times while changing a write value to the memory unit 18. Adjustment is completed when communication succeeds without error for a certain number of times.

  This timing adjustment must be performed before communication is started. At the time of initial setting by power-on reset, that is, at the time of initial setting after power-on, or communication between stacked semiconductor integrated circuits 3 and 4 At another timing before starting. As a result, communication errors due to manufacturing variations of semiconductor integrated circuits can be prevented. Further, when a communication error occurs during the operation, the same timing adjustment is performed, so that it is possible to cope with a change in usage conditions such as a change in operating temperature and a change in power supply voltage. A communication error occurs when a response such as read data is not obtained for a certain period, or when a bit error is detected in the response data using the error detection circuit 25. Needless to say, the determination of the communication error may be performed by the predetermined processor unit 10 directly comparing the write data and the read data.

  FIG. 4 shows another form of a flow for adjusting the communication timing of the semiconductor device 1. Here, the self-determination mode is set for the determination of the communication status. When the self-determination mode is designated to the control circuit 11 by the predetermined processor unit 10, the operation using the pattern generation circuit 22 and the error determination circuit 23 is enabled. That is, it is set in the error determination circuit 23 that a predetermined processor unit 10 in the master LSI 3 starts counting communication errors, and then the predetermined processor unit 10 sends a pattern for a communication status test to the pattern generation circuit 22. Directs generation. As a result, the pattern generation circuit 22 generates a communication pattern, and data transmission is started from the master LSI 3 to the slave LSI 4 by the generated pattern. In response, the slave LSI 4 sends response data from the memory unit 18 to the master LSI 3. return. At this time, the error determination circuit 23 of the master LSI 3 compares the received response data with the expected value data EXP from the pattern generation circuit 22, counts the number of errors, and stores the result. After a certain period, the predetermined processor unit 10 instructs the pattern generation circuit 22 to end pattern generation, instructs the error determination circuit 23 to end the error count operation, reads the error count value from the error determination circuit 23, and an error is detected. If communication is not correctly performed, the data data of the storage circuit 21 of the master LSI 3 is changed to change the transmission / reception timing, and the same processing is repeated. The series of processing is repeated until communication is correctly performed. By using this self-determination mode, the burden on the processor unit 10 can be reduced for timing adjustment.

  FIG. 5 shows another example of the semiconductor device 1. The difference from FIG. 1 is that the direct return path can be selected for the semiconductor integrated circuit 4 as the bus slave device when the timing is adjusted by the semiconductor integrated circuit 3 as the master device. In the direct reply path, as indicated by a broken line, the data transmitted from the transmission circuit 5 in the timing adjustment operation is received by the reception circuit 8 and is not transmitted to the internal circuit (storage unit) 18 from the direct transmission circuit 7. This is a path returning to the semiconductor integrated circuit 3. Selection of the direct reply path is performed by the selector (SEL2) 50. The selection data of the selector 50 is held in the memory circuit (TMDR) 51. The storage unit 18 is in a state of selecting the direct reply path in the initial state after the power-on reset. After the adjustment of the communication timing, the processor unit 10 of the semiconductor integrated circuit 3 as the master device rewrites the selection data of the storage circuit 41, whereby the memory operation using the storage unit 18 becomes possible. As a result, the slave LSI 4 can return the data received from the master LSI 3 to the master LSI 3 as it is without performing arithmetic processing, so that the master LSI 3 can receive the transmitted data as it is and adjust the timing. The number of communications can be reduced, and efficient timing adjustment is possible. For example, in FIG. 3, the read operation of the write value can be omitted. Further, since the internal circuit 18 of the slave LSI 4 is not operated, there is an advantage that only the interface portion of the wireless communication can be inspected. In the example of FIG. 5, the error detection circuit 25 is omitted.

  According to the semiconductor device described above, the following operational effects can be obtained.

  (1) The control circuit 11 included in one semiconductor integrated circuit 3 can adjust the communication timing in the wireless communication loop returned via the wireless communication interface circuits 7 and 8 with the other semiconductor integrated circuit 4. it can. The circuit scale can be reduced as compared with the case where the timing adjustment is separately performed on the receiving side of both the semiconductor integrated circuits 3 and 4.

  (2) Circuit groups 5, 6, 10, and 11 for controlling communication timing are mounted in the semiconductor integrated circuit 3 as a master device for starting communication between the semiconductor integrated circuits 3 and 4. Usually, a processing unit is mounted on a semiconductor integrated circuit as a master device that starts communication, and timing adjustment by software is possible. In many cases, the semiconductor integrated circuit 4 that is a communication partner of the semiconductor integrated circuit 3 that is the master device is a slave device such as a memory, and it is appropriate that such a slave device is equipped with a control function for timing adjustment. Often not. Also in this respect, the load on the slave device side can be minimized by adjusting the timing on the semiconductor integrated circuit side which is the master device.

  (3) When communication between stacked semiconductor integrated circuits is performed by wireless communication, there is no communication path established before the start of wireless communication, and it is difficult for the slave device side to know the start of timing adjustment. Is also envisaged. In this respect as well, such a case can be dealt with by having a timing adjustment function on the side of the semiconductor integrated circuit which is a master and a bus.

  (4) Since the transmission timing of the transmission clock signal and transmission data, the timing of the reception clock, and the data reception timing can be adjusted, even if there is a mismatch in manufacturing variations in the individual semiconductor integrated circuits 3 and 4, the temperature and power supply Even when operating conditions such as voltage change, communication timing in short-range communication between semiconductor integrated circuits can be adjusted with high accuracy.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, a combination of stacked semiconductor integrated circuits is not limited to a combination of a master device and a slave device. A combination of a microcomputer and an accelerator or a combination of a plurality of microcomputers may be used. In such a combination, both of the semiconductor integrated circuits may have a timing adjustment function. In that case, the direct reply path described in FIG. 5 may be provided in a semiconductor integrated circuit as a master device. For example, a selector may be provided in the path from the data register 46 to the data register 35 in FIG. Further, the slave device is not limited to the memory and may be other devices. Further, the number of stacked semiconductor integrated circuits is not limited to two and may be three or more. The semiconductor integrated circuit may be individually packaged or a bare chip. The bus of the semiconductor integrated circuit is not limited to the split transaction bus, but may be an arbitration type bus in which the bus 3 is occupied by a bus acknowledge for a bus request. The wireless communication method may be another communication method such as an electric field capacity coupling method.

FIG. 1 is a block diagram illustrating a semiconductor device according to the present invention. FIG. 2 is a front view schematically illustrating an overview of a semiconductor device according to the present invention. FIG. 3 is a flowchart illustrating an example of a flow for adjusting the communication timing of the semiconductor device of FIG. FIG. 4 is a flowchart illustrating another form of a flow for adjusting the communication timing of the semiconductor device. FIG. 5 is a block diagram illustrating a semiconductor device in which a direct reply path can be selected in a semiconductor integrated circuit as a bus slave device during timing adjustment. FIG. 6 is a waveform diagram illustrating the relationship between a transmission / reception signal waveform and a clock signal in a magnetic inductive coupling method using a coil.

Explanation of symbols

1 Semiconductor device 2 Package board (PKG)
3,4 Semiconductor integrated circuits (LSI1, LSI2)
5 Transmitter circuit (IDTX)
6 Receiver circuit (IDRX)
7 Transmitter circuit (IDTX)
8 Receiving circuit (IDRX)
10 Processing Unit (PU)
11 Control circuit (3DC)
12 Peripheral circuit (PHR)
15 Interconnect circuit (ONCIC)
16 PLL circuit 18 Processing circuit 20 Target port (TGPT)
21 Memory circuit (DLCR)
22 Pattern generation circuit (PTGEN)
23 Error judgment circuit (ERRCT)
24 Selector (SEL1)
25 Error detection circuit (EDC)
30 Wireless communication antenna for clock transmission 31 Transmission driver (IDTXC)
32 Wireless communication antenna for data transmission 33 Transmission driver (IDTXD)
24 Variable delay circuit (XTDLC)
35 Variable Delay Circuit (TXDLD)
36 Data register (FF)
40 radio communication antenna for clock reception 41 reception driver 42 radio communication antenna for data reception 45 variable delay circuit 50 selector (SEL2) for selecting a direct reply path
51 Memory circuit (TMDR)

Claims (16)

A semiconductor device including a pair of first and second semiconductor integrated circuits that are stacked and capable of wireless communication with each other,
The first semiconductor integrated circuit includes a first transmission circuit for the transmission timing by the wireless based on rewritable control data and transmits the transmission data to the second semiconductor integrated circuit by radio is adjustable, data wirelessly a first reception circuit reception timing by the radio is in adjustable based on the rewritable control data while receiving from the second semiconductor integrated circuit, and transmitted from the first transmitting circuit to the second semiconductor integrated circuit Timing adjustment of the first transmission circuit and the first reception circuit is performed based on a comparison result between the data transmitted by the second semiconductor integrated circuit in response to data and received by the first reception circuit and the transmitted data. A control circuit to perform ,
The second semiconductor integrated circuit wirelessly transmits transmission data to the first semiconductor integrated circuit and receives the data wirelessly from the first semiconductor integrated circuit, and the wireless transmission timing is fixed. And a second receiving circuit in which a wireless reception timing is fixed . The first transmission circuit transmits data in synchronization with the clock signal together with the transmission clock signal, and the transmission timing of the transmission clock signal and data is adjusted according to the value of control data set in the variable delay circuit,
The first reception circuit receives a clock signal, receives data in synchronization with the received clock signal, and adjusts a data reception timing by a reception clock according to a value of control data set in the variable delay circuit. Item 14. A semiconductor device according to Item 1. The semiconductor device according to claim 2, wherein in the first transmission circuit, the transmission timing of the transmission clock signal and data can be individually adjusted. The semiconductor device according to claim 1, wherein the control circuit is a processor unit, and the processor unit writes transmission data to be transmitted from the first transmission circuit and reads reception data received by the first reception circuit.   The semiconductor device according to claim 4, wherein the processor unit performs the timing adjustment in an initialization operation by a power-on reset and when a communication error occurs.   A pattern generator that sequentially generates transmission data and corresponding expected value data, and a match between the received data returned in response to transmission of the transmission data generated from the pattern generator and the expected value corresponding to the data. The semiconductor device according to claim 1, further comprising a determination circuit for storing the result.   The semiconductor device according to claim 6, wherein the determination circuit stores the number of mismatch determination results.   The semiconductor device according to claim 6, wherein the control circuit is a processor unit capable of reading a determination result stored in the determination circuit. The semiconductor device according to claim 8 , wherein the processor unit performs the timing adjustment in an initialization operation by a power-on reset and when a communication error occurs. The second semiconductor integrated circuit transmits an internal circuit to which the reception data received by the second reception circuit is input, an internal data output from the internal circuit, or the reception data from the second transmission circuit. The semiconductor device according to claim 1 , further comprising a selector capable of selecting either of these . The first semiconductor integrated circuit compares the data transmitted from the first transmitting circuit to the second semiconductor integrated circuit and the data transmitted by the second semiconductor integrated circuit and received by the first receiving circuit, In the case of mismatch, at least one of the transmission timing of the first transmission circuit and the reception timing of the first reception circuit is adjusted, and the transmission, the reception, and the comparison are repeated until the comparison result matches. 1. The semiconductor device according to 1 . When the comparison result matches, the first semiconductor integrated circuit changes the value of data transmitted from the first transmission circuit to the second semiconductor integrated circuit, and the number of times the comparison result matches is a predetermined number of times. The semiconductor device according to claim 11, wherein the transmission, the reception, and the comparison are repeated until the value exceeds . The semiconductor device according to claim 11, wherein the first semiconductor integrated circuit performs the timing adjustment in an initialization operation by a power-on reset and when a communication error occurs .   A semiconductor device including a pair of first and second semiconductor integrated circuits that are stacked and capable of wireless communication with each other,
  The first semiconductor integrated circuit is a semiconductor integrated circuit having a processor unit and a wireless communication interface circuit,
  The wireless communication interface circuit is configured to receive and rewrite data wirelessly with a first transmission circuit that allows wireless transmission timing to be adjusted based on control data that is set to be rewritable while transmitting transmission data wirelessly. A first receiving circuit capable of adjusting a wireless reception timing based on control data set to be possible,
  The processor unit adjusts the timing of the first transmission circuit and the first reception circuit based on whether the data received from the first reception circuit is returned from the outside in response to the data transmitted from the first transmission circuit. Done
  The second semiconductor integrated circuit wirelessly transmits transmission data to the first semiconductor integrated circuit and receives the data wirelessly from the first semiconductor integrated circuit, and the wireless transmission timing is fixed. In addition, a semiconductor device includes: a second reception circuit in which a wireless reception timing is fixed; and a memory that writes data received by the second reception circuit and outputs the read data through the second transmission circuit.   The transmission circuit transmits data in synchronization with the clock signal together with the transmission clock signal, and the transmission timing of the transmission clock signal and data is adjusted according to the value of control data set in the variable delay circuit,
  15. The reception circuit receives a clock signal, receives data in synchronization with the received clock signal, and adjusts the data reception timing by the reception clock according to the value of control data set in the variable delay circuit. The semiconductor device described. The first semiconductor integrated circuit compares the data transmitted from the first transmitting circuit to the second semiconductor integrated circuit and the data transmitted by the second semiconductor integrated circuit and received by the first receiving circuit, In the case of mismatch, at least one of the transmission timing of the first transmission circuit and the reception timing of the first reception circuit is adjusted, and the transmission, the reception, and the comparison are repeated until the comparison result matches. 15. The semiconductor device according to 15 .

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