JP5253470B2 - Inverter control device - Google Patents

Description

  The present invention relates to an inverter control device.

For driving a three-phase motor, for example, various types that employ current-controlled PWM inverter control have been proposed. Among such technologies, the current value of each phase connected to the three-phase motor is detected, and information such as load torque and rotor position is calculated and controlled based on the detection result. (For example, Patent Document 1).
In the technique described in Patent Document 1, a current detector that detects a current value of each phase is arranged on a DC bus, detects a current value of each phase according to switching timing within a PWM cycle, and detects the current value. Based on the result, the three-phase motor is controlled (hereinafter also referred to as a phase current detection method using a DC bus current).

A phase current detection method using a DC bus current is employed, and further, correction for detecting the current value of each phase is performed in the first half of the PWM cycle, and the correction is offset in the second half (for example, Patent Document 2). ).
The technique described in Patent Document 2 detects the current value of each phase with 1 PWM period as the minimum period by widening the switching timing interval of PWM pulses of each phase generated by the correction, and the latter half of the PWM period. In the first half, the direction of offset is reversed with reference to the voltage value before correction, so that the influence on the drive on the load side due to the correction is suppressed.

JP-A-8-19263 (for example, see FIG. 3) Japanese Patent No. 3664040 (see, for example, pages 5 to 8, FIGS. 1 and 4)

  In the technique described in Patent Document 1, it is difficult to detect the current value because the output voltage of each phase is close to 0 or the difference between the output voltages of each phase is not sufficient. That is, the control for driving the load side with high efficiency cannot be realized based on the current value of each phase.

  In the technique described in Patent Document 2, the above-described control is adopted, and the period in which the current value of each phase can be detected more reliably is larger than the PWM period, so that the load side is driven with high efficiency. Could not be realized.

  The present invention has been made to solve the above-described problems. The period for detecting the current value of each phase is shortened, and correction for suppressing the influence on driving on the load side is performed. An object of the present invention is to provide an inverter control device that realizes control for driving the load side with high efficiency.

An inverter control device according to the present invention includes an inverter main circuit that is driven based on a sequentially updated command signal for controlling a phase current supplied to an inductive load having three phases, and a DC bus current of the inverter main circuit. In an inverter control apparatus for controlling an inverter having current detection means for detecting at a predetermined cycle, a command correction unit for correcting and outputting a command signal, and a PWM signal based on the corrected command signal output from the command correction unit And a PWM signal generation means for outputting to the inverter main circuit, and the current detection means has a detection cycle of the DC bus current that is a cycle of an integer multiple of 1 or more of a 1/2 PWM cycle, and a command correction The unit calculates a three-phase command signal calculated based on the value of the DC bus current detected at each detection cycle, in order of increasing voltage, the maximum voltage command signal, Assuming that the intermediate voltage command signal and the minimum voltage command signal are used, it is determined whether or not the offset correction is performed on the maximum voltage command signal and the minimum voltage command signal every 1/2 PWM period from the preset timing. When the voltage difference between the voltage command signal and the intermediate voltage command signal is smaller than the predetermined value, the maximum voltage instead of the intermediate voltage command signal is set so that the voltage difference between the maximum voltage command signal and the intermediate voltage command signal is equal to or greater than the predetermined value. When the first offset correction is performed on the command signal and the voltage difference between the intermediate voltage command signal and the minimum voltage command signal is smaller than a predetermined value, the voltage difference between the intermediate voltage command signal and the minimum voltage command signal is performing a second offset correction with respect to the minimum voltage command signal rather than the intermediate voltage command signal such that a predetermined value or more, the offset direction of the first offset correction, pre The value obtained by integrating a plurality of integral values corresponding to the correction amount of the plurality of first offset compensation made from the set are timing, determined by calculation to be closer to 0, the offset direction of the second offset correction Is determined by calculating so that a value obtained by integrating a plurality of integral values corresponding to a plurality of correction amounts of the second offset correction performed from a preset timing approaches 0 .

  According to the inverter control device of the present invention, the period for detecting the current value of each phase is shortened, and correction for suppressing the influence on the driving on the load side is performed, so that the load side is made highly efficient. The drive control can be realized.

It is a circuit block example figure of the inverter control apparatus which concerns on Embodiment 1 of this invention. It is a correction | amendment flowchart of the command correction | amendment part of the inverter control apparatus shown in FIG. The waveform chart of each signal of the inverter control apparatus shown in FIG. 1 will be described. The relationship of the PWM period of the inverter control apparatus shown in FIG. 1, a command signal, and an electric current detection period is demonstrated.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
Embodiment 1 FIG.
FIG. 1 is a circuit block diagram of the inverter control device according to Embodiment 1 of the present invention. FIG. 3 illustrates a waveform chart of each signal of the inverter control device shown in FIG. In addition, in the following drawings including FIG. 1, the relationship of the size of each component may be different from the actual one. In FIG. 1 to FIG. 4, the symbol * is given for convenience to indicate that it is a signal for “commanding” the inverter circuit.

[Configuration of Inverter Control Device 1]
First, the configuration of the inverter control device 1 will be described.
As shown in FIG. 1, the inverter control device 1 includes a DC power supply 2 that supplies power for driving a load, a smoothing capacitor 6 that rectifies current, an inverter main circuit 3 that uses DC current as AC current, and an inverter main circuit. 3, inductive load 5 controlled by current, current detection means 13 for detecting current, phase current calculation unit 30 for calculating the current value of each phase based on the detected current, calculation result and current command in phase current calculation unit 30 A current control unit 10 that controls the inverter main circuit 3 based on the values; a command correction unit 11 that corrects a command signal of the current control unit 10; and a PWM signal generation unit that generates a PWM signal from the signal corrected by the command correction unit 11 12.
Here, the current command value refers to a signal for controlling the rotational speed of the motor to a predetermined value, for example, when the inductive load 5 is a motor. The command signal is a signal transmitted by the current control unit 10 based on the current value calculated by the phase current calculation unit 30 and the current command value. Further, the inductive load 5 will be described as having three phases (referred to as U phase, V phase, and W phase). The command signal is updated at a 1/2 PWM cycle.

  The DC power supply 2 supplies electric power for driving the inductive load 5. The smoothing capacitor 6 rectifies the current supplied from the DC power source 2 to the inductive load 5 via the inverter main circuit 3. The inverter main circuit 3 converts a direct current supplied from the direct current power source 2 into an alternating current whose current, voltage and frequency are controlled. In the inverter main circuit 3, six switching elements 6a to 6f form a three-phase bridge circuit. The load side of this three-phase bridge circuit is connected to the U phase, V phase and W phase of the inductive load 5. These DC power supply 2, smoothing capacitor 6 and inverter main circuit 3 are connected in parallel as shown in FIG. Here, currents flowing through the U phase, the V phase, and the W phase are referred to as a phase current UI, a phase current VI, and a phase current WI, respectively. The current detection means 13 detects the current Is flowing through the DC bus L with a predetermined period T. The DC bus L is a wiring between one end P1 of the smoothing capacitor 6 and the positive electrode side of the DC power source 2 of the inverter main circuit 3.

  The phase current calculation unit 30 determines the values of the phase current UI, the phase current VI, and the phase current WI based on the current Is flowing through the DC bus L detected by the current detection unit 13 and the signal output from the PWM signal generation unit 12. Is calculated (estimated), and the calculation result is output to the current control unit 10. The phase current calculation unit 30 is connected to the current detection unit 13, the PWM signal generation unit 12, and the current control unit 10.

  The current control unit 10 generates a command signal for controlling each phase (U phase, V phase, and W phase) based on the calculation result of the phase current calculation unit 30 and the current command value given from the outside. 11 is transmitted. Here, the U phase corresponds to the command signal vu1, the V phase corresponds to the command signal vv1, and the W phase corresponds to the command signal vw1. The current control unit 10 is connected to the phase current calculation unit 30 and the command correction unit 11. Further, in the inverter control device 1, the minimum period in which the command signal vu1 to the command signal vv1 are output to the command correction unit 11 is a half cycle of the carrier of the PWM signal generation unit 12 described later.

  The command correction unit 11 corrects the command signals (vu1, vv1, and vw1) received from the current control unit 10 into corrected command signals (vu2, vv2, and vw2), and the corrected command signals (vu2, vv2, and vw2). ) Is transmitted to the PWM signal generation means 12. Here, the pre-correction command signal vu1 corresponds to the post-correction command signal vu2, the pre-correction command signal vv1 corresponds to the post-correction command signal vv2, and the pre-correction command signal vw1 corresponds to the post-correction command signal vw2. Note that how the command signals (vu1, vv1, and vw1) are corrected to the corrected command signals (vu2, vv2, and vw2) will be described later with reference to FIG. The command correction unit 11 is connected to the current control unit 10 and the PWM signal generation unit 12.

  The PWM signal generation means 12 turns on / off the switching elements 6a to 6f based on the corrected command signals (vu2, vv2, and vw2) received from the command correction unit 11 and the carrier (see the triangular wave in FIG. 4). The PWM signal for doing this is transmitted to the switching elements 6a to 6f. The PWM signal generation means 12 also transmits data related to the PWM signal to the phase current calculation unit 30. The PWM signal generation means 12 is connected to the command correction unit 11 and the switching elements 6a to 6f.

[Correction of command correction unit 11]
When the switching timing interval of the inverter main circuit 3 becomes shorter as the command correction unit 11 becomes difficult to calculate each phase current UI, phase current VI, and phase current WI from the current Is detected by the DC bus L. In addition, offset correction is performed so as to lengthen the switching timing interval. The shorter switching timing interval corresponds to the smaller voltage difference between the command signals (vu1, vv1, and vw1). Accordingly, the command correction unit 11 offsets the voltage difference of the command signals (vu1, vv1, and vw1) at a predetermined timing (described later) so as to increase the voltage difference when the voltage difference is smaller than the predetermined voltage difference Dmin. Correction is to be applied. Note that the cycle for applying the offset correction is a 1/2 PWM cycle. That is, the command correction unit 11 applies the offset correction to the command signal vu1 to the command signal UW1 transmitted every 1/2 PWM cycle, and the vu2 to the command signal UW2 obtained by applying the offset correction every 1/2 PWM cycle. Output to the inverter main circuit 3.

FIG. 2 is a correction flowchart of the command correction unit 11 of the inverter control device 1 shown in FIG. The correction of the command correction unit 11 will be described based on FIG. Here, S1 to S15 in FIG. 2 correspond to Step 1 to Step 15 described below.
(Step 1)
The magnitudes of the command signals vu1 to vw1 received from the current control unit 10 are calculated, and the maximum phase voltage command value vmax1, the second phase voltage command value vmid1, and the minimum phase voltage command value vmin1 are calculated in order from the largest. And

(Step 2)
A value obtained by subtracting the second phase voltage command value vmid1 from the maximum phase voltage command value vmax1 is defined as Δv12 ′.

(Step 3)
A value obtained by adding the difference Δv12 ′ to the integrated value Δv12 (t−1) is updated as the updated integrated value Δv12. Here, the integral value will be described. The command correction unit 11 sequentially performs the correction described in this flowchart in a carrier half cycle (1/2 PWM cycle). This command correction unit 11 performs pre-correction from the beginning of a predetermined cycle with the voltage values of the command signals vu1 to UW1 at the time of update as positive and negative references during the period (predetermined cycle T) in which the current detection unit 13 detects current. The integrated value with respect to the reference of the command signal is calculated, and this integrated value corresponds to Δv12 (t−1). Therefore, strictly speaking, the update integration value Δv12 is expressed as the update integration value Δv12 (t), but this (t) is omitted. Again, referring back to FIG. 2, the description returns to the correction flowchart of the command correction unit 11.

(Step 4)
It is calculated whether the absolute value of the update integral value Δv12 is equal to or greater than a predetermined voltage difference Dmin. Here, if the absolute value of the update integral value Δv12 is equal to or larger than the predetermined voltage difference Dmin, the process proceeds to step 6A, and if smaller than the predetermined voltage difference Dmin, the process proceeds to step 5. The predetermined voltage difference Dmin is set in advance as a value corresponding to a time interval in which the current Is flowing through the DC bus L can be detected.

(Step 5)
If the updated integrated value Δv12 is 0 or more, the process proceeds to Step 6B, and if it is smaller than 0, the process proceeds to Step 6C.

(Step 6A)
Since the absolute value of the updated integral value Δv12 is greater than or equal to the predetermined voltage difference Dmin, the value of vcmp12 that is the voltage value to be corrected is set to 0, and the process proceeds to step 7.
(Step 6B)
Since the absolute value of the updated integral value Δv12 is smaller than the predetermined voltage difference Dmin and the value of the updated integral value Δv12 is 0 or more, the value of vcmp12 is set to Dmin−Δv12 and the process proceeds to step 7. .
(Step 6C)
Since the absolute value of the updated integral value Δv12 is smaller than the predetermined voltage difference Dmin and the value of the updated integral value Δv12 is smaller than 0, the value of vcmp12 is set to −Dmin−Δv12 and the process proceeds to step 7. .

(Step 7)
A value obtained by adding vcmp12 to the maximum phase voltage command value vmax1 is updated as the maximum phase voltage command value vmax2. Further, a value obtained by adding vcmp12 to the updated integral value Δv12 is updated as a new integral value Δv12.

(Step 8)
A value obtained by subtracting the minimum phase voltage command value vmin1 from the second phase voltage command value vmid1 is defined as Δv23 ′.

(Step 9)
A value obtained by adding the difference Δv23 ′ to the integrated value Δv23 (t−1) is updated as the updated integrated value Δv23.

(Step 10)
It is calculated whether the absolute value of the update integration value Δv23 is equal to or greater than a predetermined voltage difference Dmin. Here, if the absolute value of the update integration value Δv23 is equal to or larger than the predetermined voltage difference Dmin, the process proceeds to step 12A, and if smaller than the predetermined voltage difference Dmin, the process proceeds to step 11. The predetermined voltage difference Dmin is set in advance as a value corresponding to a time interval in which the current Is flowing through the DC bus L can be detected.

(Step 11)
If the updated integrated value Δv23 is 0 or more, the process proceeds to step 12B, and if it is smaller than 0, the process proceeds to step 12C.

(Step 12A)
Since the absolute value of the updated integral value Δv23 is greater than or equal to the predetermined voltage difference Dmin, the value of vcmp23, which is the voltage value to be corrected, is set to 0, and the process proceeds to step 13.
(Step 12B)
Since the absolute value of the updated integral value Δv23 is smaller than the predetermined voltage difference Dmin and the value of the updated integral value Δv23 is 0 or more, the value of vcmp23 is set to Dmin−Δv23 and the process proceeds to step 13. .
(Step 12C)
Since the absolute value of the updated integral value Δv23 is smaller than the predetermined voltage difference Dmin and the value of the updated integral value Δv23 is smaller than 0, the value of vcmp23 is set to −Dmin−Δv23 and the process proceeds to step 13. .

(Step 13)
A value obtained by adding vcmp23 to the maximum phase voltage command value vmax1 is updated as the minimum phase voltage command value vmin2. Further, a value obtained by adding vcmp23 to the updated integral value Δv23 is updated as a new integral value Δv23.

(Step 14)
The value of the second phase voltage command value vmid1 is updated as the second phase voltage command value vmid2.

(Step 15)
The maximum phase voltage command value vmax2, the second phase voltage command value vmid2, and the minimum phase voltage command value vmin2 are set to corrected current command values (vu2, vv2, and vw2) that are transmitted to the PWM signal generating means.

[Explanation of correction timing]
FIG. 3 illustrates the correction timing of the command correction unit 11 of the inverter control device 1 shown in FIG. 3 will be described with reference to the flowchart of FIG. FIG. 3 shows an example in which the voltage values of the command signals vv1 and vw1 are close to each other. The command correction unit 11 receives vu1, vv1, and vw1 from the top of the drawing in the order of the voltage levels of the command signal vu1 to the command signal vw1 (corresponding to step 1). In the case of the example of FIG. 3, since the voltage values of the command signals vv1 and vw1 are close to each other, the correction in steps 2 to 6 is not performed, and thus the description thereof is omitted. Note that Step 6A, Step 6B, and Step 6C are collectively referred to as Step 6.

  Next, based on steps 8 to 12, the command signal vw1 corresponding to the W phase is corrected. The command signal vv1 corresponds to the second phase voltage command value vmid1, the command signal vw1 corresponds to the minimum phase command signal vmin1, and the second phase voltage command value vmid1 minus the minimum phase command signal vmin1 is calculated to calculate Δv23 ′ (step) 8). Here, the updated integrated value Δv23, which is the sum of the value of the integrated value Δv23 (t−1) before timing A in FIG. 3 and Δv23 ′ that is the difference between vv1 and vw1, is negative. (Step 9). Therefore, it can be seen that from the timing A to the timing B after ½ PWM cycle (half cycle of carrier), the command signal vv2 is offset to the upper side with respect to vw1 (steps 10 to 12). Subsequently, at the timing of the arrow B in FIG. 3, the integration value Δv12 of the positive value of the timing from the arrow A to the arrow B is integrated, so that the command signal vv2 (command signal Since vv2 is the second phase voltage command value and is not corrected, it is the same as vv1), and an offset is applied to the lower side so that the voltage value becomes lower.

  Here, it will be described that the offset is not applied to the upper side at the timing C after the timing B, but is applied to the upper side at the timing D. This is because the amount offset upward is larger than the amount offset downward from the timing A to the timing B when the command signal vw1 is used as a reference. That is, in order to cancel out the positive integrated value up to the timing B, the offset period is 1 PWM period on the lower side. This is because the period offset to the lower side is set to 1 PWM cycle (the voltage value at timing C is not changed), and the command correction unit 11 calculates so that the integrated value accumulated up to timing B approaches 0. Because it was corrected.

[Predetermined period T (current detection period) and integration interval T2]
FIG. 4 illustrates the relationship among the PWM cycle, the command signal vu1 to the command signal vw1, and the current detection cycle of the inverter control device 1 shown in FIG. In FIG. 4, for the convenience of explanation, a period T3 in which an offset is required by the command signal vu1, a period T4 in which no offset is required, and a period T5 in which the offset is required by the command signal vu1 are taken as an example. It should be noted that an offset may be required every (1/2 PWM period).

  In the inverter control device 1, as described with reference to FIG. 1, the current detection unit 13 detects the current of the DC bus at a predetermined cycle (current detection cycle). Here, the inverter control device 1 can detect the current of each phase even if the minimum value of the predetermined cycle is a 1/2 PWM cycle. That is, since the period in which the current of each phase can be detected reliably is shorter than the PWM period, it is possible to realize control for driving the load side with high efficiency. The predetermined period may be set to 1/2 PWM (see PA1 in FIG. 4), may be set to a period longer than 1/2 PWM period, or may be set to 1/2 PWM period and 1/2 PWM. A period longer than the period may be combined (see PA2 in FIG. 4).

  The inverter control device 1 performs calculations corresponding to Step 3 to Step 7 and Step 9 to Step 13 (see FIG. 2) in the integration interval T2 of a predetermined period, so that the value of the calculation approaches 0. The timing of command signal VU2 to command signal VW2 is taken. Here, the minimum value of the integration interval T2 is 1 PWM cycle, and the maximum value is not particularly limited. Since the inverter control device 1 performs the calculation (integration) corresponding to Step 3 to Step 7 and Step 9 to Step 13 for each integration section T2, and the calculation result approaches 0, the command signal vu1 Even when the command signal vw1 is corrected so that the voltage signal can be detected, the influence on the driving of the inductive load 5 is reduced.

[Effects of the inverter control device 1]
When the voltage difference between the phases arranged in the order of the voltage magnitude of the command signal vu1 to the command signal vw1 is smaller than a predetermined value, the inverter control device 1 has a voltage difference smaller than the predetermined value 2 every 1/2 PWM period. Since at least one of the two pre-correction command signals is corrected so that the voltage difference with respect to the other is greater than or equal to a predetermined value, control for driving the load side with high efficiency can be realized.
Further, in the integration interval T2, an integral value with respect to the reference of the command signal vu1 to the command signal vw1 from when the command signal vu1 to the command signal vw1 is updated until before correction is calculated, and the reference value of the corrected command signal is calculated as the integral value Since the correction timing is determined so that the value obtained by adding the integral value to 0 approaches 0, the influence on driving of the inductive load 5 is reduced even if the correction is performed.

[Others]
The inverter control device 1 uses a command signal based on a PWM duty ratio that is a value obtained by dividing a current value flowing through the DC bus and each of the command signal vu1 to the command signal vw1 instead of the command signal vu1 to the command signal vw1. Needless to say, it may be adopted.

  Needless to say, in the inverter control device 1, the phase current calculation unit, the current control unit, the command correction unit, and the PWM signal generation unit may be provided in one microcomputer. Thereby, the inverter control apparatus 1 can be made cheap and small.

  Needless to say, the microcomputer may include an A / D converter, and the phase current calculation unit may calculate the phase current of each phase of the inductive load by the A / D converter. Thereby, it is not necessary to provide an A / D converter for only the phase current calculation unit, and the inverter control device 1 can be made inexpensive and small.

  It goes without saying that the inverter main circuit 3 may be one in which three-phase six elements are sealed in one package. Thereby, the inverter control apparatus 1 can be reduced in size.

  Further, the inverter control device 1 can be employed in, for example, a brushless DC motor having a permanent magnet. In addition, home appliances that use inverters and motors (corresponding to induction load 5), such as air conditioner compressors, fans, refrigerators, washing dryers, refrigerators, dehumidifiers, heat pump water heaters, showcases, vacuum cleaners, etc. It can be used for products in general, ventilation fans, hand dryers, etc.

  DESCRIPTION OF SYMBOLS 1 Inverter control apparatus, 2 DC power supply, 3 Inverter main circuit, 3A Three-phase bridge circuit, 5 Inductive load, 6 Smoothing capacitor, 6a Switching element, 6b Switching element, 6c Switching element, 6d Switching element, 6e Switching element, 6f Switching Element, 10 Current control unit, 11 Command correction unit, 12 PWM signal generation unit, 13 Current detection unit, 20 Current control unit, 30-phase current calculation unit, Is current, L DC bus, P1 one end, UI phase current, VI phase Current, WI phase current, T predetermined period, T2 integration interval, period in which only T3 vw1 * needs to be corrected, period in which T4 is not corrected, and period in which only T5 vw1 * is required

Claims (9)

An inverter main circuit that is driven based on a sequentially updated command signal for controlling a phase current supplied to an inductive load comprising three phases, and a current detection means that detects a DC bus current of the inverter main circuit at a predetermined cycle In an inverter control device for controlling an inverter having
A command correction unit for correcting and outputting the command signal;
PWM signal generation means for generating a PWM signal based on the corrected command signal output from the command correction unit, and outputting the PWM signal to the inverter main circuit;
Have
The current detection means includes
The detection cycle of the DC bus current is a cycle that is an integer multiple of 1 or more of a 1/2 PWM cycle,
The command correction unit is
When the three-phase command signal calculated based on the value of the DC bus current detected at each detection cycle is set to a maximum voltage command signal, an intermediate voltage command signal, and a minimum voltage command signal in descending order of voltage. , Whether to perform offset correction on the maximum voltage command signal and the minimum voltage command signal every 1/2 PWM period from a preset timing,
Wherein when the voltage difference between the maximum voltage command signal and the intermediate voltage command signal is smaller than a predetermined value, the maximum voltage command signal and the voltage difference between the intermediate voltage command signal, the intermediate voltage to be equal to or greater than the predetermined value Performing a first offset correction on the maximum voltage command signal instead of the command signal ;
When the voltage difference between the intermediate voltage command signal and the minimum voltage command signal is smaller than a predetermined value, the intermediate voltage is set such that the voltage difference between the intermediate voltage command signal and the minimum voltage command signal is equal to or greater than a predetermined value. Performing a second offset correction on the minimum voltage command signal instead of the command signal;
The offset direction of the first offset correction is
A value obtained by integrating a plurality of integral values corresponding to a plurality of correction amounts of the first offset correction performed from the preset timing is determined by calculating so as to approach 0 ;
The offset direction of the second offset correction is
An inverter characterized in that a value obtained by integrating a plurality of integral values corresponding to a plurality of correction amounts of the second offset correction performed from the preset timing is calculated so as to approach zero. Control device. The inverter control device according to claim 1, wherein the command signal is a signal based on a PWM duty ratio. The inverter control device according to claim 1, wherein the current detection unit sets the predetermined period to a 1/2 PWM period. A phase current calculation unit that calculates each phase current of the inductive load based on the detection result of the DC bus current of the current detection unit and the PWM signal of the PWM signal generation unit, and outputs the calculation result;
A current control unit that generates the command signal based on a calculation result of each phase current of the phase current calculation unit and a current command value given from the outside, and outputs the command signal to the command correction unit; The inverter control device according to any one of claims 1 to 3, wherein the inverter control device is provided. The inverter control device according to claim 4, wherein the phase current calculation unit, the current control unit, the command correction unit, and the PWM signal generation unit are provided in one microcomputer. The said microcomputer has an A / D converter, The said phase current calculating part calculates the phase current of each phase of the said inductive load by this A / D converter. Inverter control device. The inverter control circuit according to any one of claims 1 to 6, wherein the inverter main circuit includes three-phase six elements sealed in one package. The inverter control device according to any one of claims 1 to 7, wherein the inductive load is a brushless DC motor having a permanent magnet. The inverter control device according to any one of claims 1 to 8, wherein the inductive load is a motor that drives a compressor.

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