JP5251953B2 - Switch circuit, semiconductor device, and portable radio - Google Patents

Abstract

A switch circuit with a unit capable of improving a margin voltage without using a negative bias generation circuit is provided. A switch comprising an N-type MOSFET is used for a switch passing a signal to an antenna and a switch comprising a P-type MOSFET is used for a shunt switch grounding a signal. A common control signal is input to the gate terminal of the MOSFET constituting each switch. The inverted signal of this control signal is coupled to a ground terminal of the switch, and thus the potential of the gate terminal of each MOSFET can be set to the ground voltage.

Description

  The present invention relates to a switch circuit used for a portable wireless device, and more particularly to prevention of spurious generation of a switch circuit used for input / output switching and switching of two or more outputs.

  Mobile phones are widely used in general. UMTS (W-CDMA) system using CDMA (Code Division Multiple Access) and GSM using Time Division Multiple Access (TDMA) system are known as main systems as a multiple access system of mobile phones.

  Integration in RF units for mobile phones is advancing, and GSM systems often use products in which antenna switches and power amplifiers are integrated in the same module (hybrid IC).

  Currently, antenna switches are often implemented using pHEMT, which is a kind of compound semiconductor. However, realization with a silicon device (CMOS) is important for cost reduction.

  US Patent Publication US7123898B2 (Patent Document 1) is given as a conventional technique. This document discloses a technology of a switch to which SOS (Silicon on Safari) CMOS is applied.

  FIG. 1 is a conceptual diagram of the technique described in Patent Document 1. Here, for simplification, an example of one transmission system and one reception system is given.

  In the example of Patent Document 1, the transmitter side switches M1 and M2 and the receiver side switches M3 and M4 are included. All the elements constituting these switches are composed of nMOSFETs with low on-resistance and low power consumption.

  In this example, the DC potential of each terminal is the ground potential. The FET gate voltage is raised to turn on the switch, and the gate voltage is lowered to turn off the switch. If the power supply voltage is 2.7 V and the threshold voltage of the FET is 0.7 V, there is a margin voltage of 2.0 V from the threshold voltage when it is turned on, and there is a margin voltage of 0.7 V when it is turned off. As described above, the margin is different between the two states, on and off. Particularly, since the off margin is small, when the input RF signal is large, the gate voltage is forcibly increased by the RF signal, and is turned on in a pseudo manner, resulting in loss. An increase is also conceivable.

  In order to prevent this, the technique described in Patent Document 1 takes a measure of generating a negative bias (eg, −3 V) for turning off and ensuring a sufficient margin voltage in the off state.

  For example, at the time of transmission, + 3V is applied to the gate terminal of the switch M1, and -3V is applied to the gate terminal of the shunt switch M2. Thereby, the transmission output is connected to an antenna (not shown). Further, -3V is applied to the gate terminal of the receiving-side switch M3, and + 3V is applied to the gate terminal of the shunt switch M4. This measure disconnects the received input from the antenna. At this time, when the off-time margin voltage is set to 3.7 V, the malfunction of the off-FET is suppressed.

  In Japanese Patent Application Laid-Open No. 2008-11120 (Patent Document 2), by using an nMOS for the through-side switches (M1, M3) and a pMOS for the shunt-side switches (M2, M4), two FETs can be connected with the same control voltage. It is disclosed to control and simplify the generation of control signals.

US Patent Publication US7123898B2 JP 2008-11120 A

  However, in the technique described in Patent Document 1, it is essential to mount a negative bias generation circuit. Therefore, if the negative bias generation circuit is integrated on the same chip as the switch, the negative bias generation circuit is likely to be a spurious generation source due to the oscillator in the negative bias generation circuit.

  In addition, a certain predetermined time is required to generate the negative bias. Therefore, it is necessary to apply a control timing that takes into account the time required for generating a negative bias. The technique described in Patent Document 2 has a problem of reducing the degree of freedom of the control sequence.

  An object of the present invention is to provide a switch circuit with means that can improve the margin voltage without using a negative bias generation circuit.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  A switch circuit according to an exemplary embodiment of the present invention determines whether to connect an antenna to an external circuit, and the switch circuit is electrically connected to a first switch that passes the output of the external circuit through the antenna. Including a capacitor located between the electrical connection of the first switch and the external circuit, and the polarity of the control signal of the first switch is inverted by an inverter and connected to a connection point between the first switch and the capacitor It is characterized by that.

  This switch circuit may include a first resistor between the connection point and the inverter.

  The switch circuit further includes a second resistor and a resistor opening / closing switch connected in parallel with the first resistor, and the resistance value connected to the inverter is variable by opening / closing the resistor opening / closing switch. good.

  The switch circuit further includes a one-shot pulse generation circuit to which the control signal of the first switch is input, and the one-shot pulse generation circuit opens and closes a resistor at a predetermined time with the change of the control signal of the first switch as a timing. The switch may be opened and closed.

  In these switch circuits, the first switch may be configured to include an N-type FET, and the control signal may be input to the gate terminal of the N-type FET configuring the first switch.

  In these switch circuits, the first switch may be configured to include an N-type FET, and the control signal may be input to the gate terminal of the N-type FET configuring the first switch.

  Another switch circuit according to an exemplary embodiment of the present invention is a switch circuit that determines whether an antenna is connected to an external circuit, and the switch circuit grounds the external circuit when disconnected from the antenna. And a second switch for inverting the polarity of the control signal of the second switch and connecting it to the ground terminal of the second switch.

  In this switch circuit, the second switch may be configured to include an N-type FET, and a control signal may be input to a gate terminal of the N-type FET configuring the second switch.

  In this switch circuit, the second switch may be configured to include an N-type FET, and a control signal may be input to a gate terminal of the N-type FET configuring the second switch.

  Another switch circuit according to a representative embodiment of the present invention is a switch circuit that determines whether an antenna is connected to an external circuit, and includes a first switch that passes the output of the external circuit through the antenna, Including a second switch for grounding the external circuit when disconnected from the antenna, and the control of the first switch and the second switch is the same. And the control signal is inverted to determine the potential of the ground terminal of the second switch.

  In this switch circuit, the first switch is configured to include an N-type FET, the second switch is configured to include a P-type FET, and the control signal includes a gate terminal of the N-type FET that configures the first switch; The signal may be input to the gate terminal of the P-type FET constituting the second switch.

  In this switch circuit, a capacitor is further included between the connection point of the first switch and the second switch and the electrical connection of the external circuit, and a signal obtained by inverting the control signal is used for charging and discharging the capacitor. It is good as a feature.

  In this switch circuit, a signal obtained by inverting a control signal may be connected to a capacitor through a resistor circuit.

  In this switch circuit, the resistor circuit may include a plurality of electrically detachable resistors connected in parallel.

  Another switch circuit according to the representative embodiment of the present invention determines whether the antenna is connected to the transmission circuit or the reception circuit, and connects the transmission circuit to the antenna or the transmission circuit. A transmission side switch circuit that determines whether to ground, and a reception side switch circuit that determines whether to connect the reception circuit to the antenna or to ground the reception circuit, the transmission side switch circuit and the reception side switch circuit Are controlled by one control signal, a control signal is input to the ground terminal of one of the transmission side switch circuit or the reception side switch circuit, and an inverted signal of the control signal is input to the other ground terminal. Features.

  This switch circuit has a first capacitor between the electrical connection between the transmission side switch circuit and the antenna, and has a second capacitance between the electrical connection between the reception side switch circuit and the antenna. It is possible to set different DC potentials for the side switch circuit and the reception side switch circuit.

  In this switch circuit, a third capacitor may be provided between the electrical connection of the transmission-side switch circuit and the transmission circuit, and a signal based on the control signal may be used for charging / discharging the third capacitor. .

  In this switch circuit, a fourth capacitor may be provided between the receiving-side switch circuit and the receiving circuit, and a signal based on a control signal may be used for charging / discharging the fourth capacitor. .

  Another switch circuit according to a representative embodiment of the present invention is a switch circuit that determines whether an antenna is connected to a transmission circuit, a first reception circuit, or a second reception circuit. A first receiving-side switch circuit that determines whether the first receiving circuit is connected to the antenna or the first receiving circuit is grounded, and the second receiving circuit is connected to the antenna, A second receiving-side switch circuit that determines whether to ground the second receiving circuit, and an antenna-side terminal of the first receiving-side switch circuit and an antenna-side terminal of the second receiving-side switch circuit It is characterized by having the same DC potential.

  Another switch circuit according to the exemplary embodiment of the present invention determines whether the transmission signal is output to the first transmission circuit or the second transmission circuit, and transmits the transmission signal to the first transmission circuit. A first transmission-side switch circuit for determining whether to output or ground the first transmission circuit, and whether to output a transmission signal to the second transmission circuit or to ground the second transmission circuit A second transmission side switch circuit, wherein the first transmission side switch circuit and the second transmission side switch circuit are controlled by one control signal, and the first transmission side switch circuit or the second transmission side The control signal is input to any one ground terminal of the switch circuit, and an inverted signal of the control signal is input to the other ground terminal.

  Another switch circuit according to the representative embodiment of the present invention determines that either the bypass signal or the amplified signal is a transmission signal, and transmits the transmission signal to either the first transmission circuit or the second transmission circuit. A first transmission-side switch circuit that determines whether to output the transmission signal to the first transmission circuit or to ground the first transmission circuit; and the transmission signal to the second transmission circuit A second transmission-side switch circuit that determines whether to output or ground the second transmission circuit, and the first transmission-side switch circuit and the second transmission-side switch circuit are controlled by one control signal. Controlling and inputting the control signal to the ground terminal of one of the first transmission side switch circuit or the second transmission side switch circuit and inputting the inverted signal of the control signal to the other one ground terminal. It is characterized by.

  A semiconductor device using the switch circuit and a portable radio using the semiconductor device also fall within the scope of the present invention.

  In the switch circuit according to the present invention, an nMOSFET is used for a through path for passing a signal, a pMOSFET is used for a shunt path that is turned on when the signal is cut, and the DC potential of the through path is set to the ground potential when the signal is passed. At this time, the direct current potential of the through path is set to the power supply potential VDD. Thus, when the nMOSFET is turned on, the margin voltage can be set to the power supply potential VDD-threshold voltage Vth, and when the pMOSFET is turned on, the margin voltage can be set to the power supply potential VDD-threshold voltage Vth.

It is a conceptual diagram about the technique of patent document 1. FIG. It is a circuit diagram showing the structure of the switch circuit in connection with the 1st Embodiment of this invention. It is a conceptual diagram showing how the switch circuit of FIG. 2 is used in an antenna switch. It is a circuit diagram showing the structure of the switch circuit in connection with the 2nd Embodiment of this invention. It is a circuit diagram showing the structure of the circuit for charge in connection with the 2nd Embodiment of this invention. It is a wave form diagram showing the voltage waveform of each measurement point of the circuit for charge at the time of a rise of an inverter. It is a wave form diagram showing the voltage waveform of each measurement point of the circuit for charge at the time of the fall of an inverter. It is a circuit diagram showing the structure of the switch circuit in connection with the 3rd Embodiment of this invention. It is a conceptual diagram showing how the switch circuit of FIG. 8 is used in an antenna switch. It is a figure showing the example which integrated the antenna switch of FIG. 9 on the integrated circuit 1 chip | tip of SOICMOS. It is a circuit diagram showing the structure of the switch circuit in connection with the 4th Embodiment of this invention. It is a circuit diagram showing the structure of the switch circuit in connection with the 4th Embodiment of this invention. It is a conceptual diagram showing how the switch circuit of FIG. 12 is used in an antenna switch. It is a figure showing the example which integrated the antenna switch of FIG. 13 on the integrated circuit 1 chip | tip of SOICMOS. It is a conceptual diagram showing the structure of the antenna switch concerning the 6th Embodiment of this invention. It is a circuit diagram showing the structure of the switch circuit in connection with the 6th Embodiment of this invention.

  In the following embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, it is not irrelevant to one another, and one is related to some or all of the other, details, supplementary explanations, and the like. Also, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except for the specific number, the number may be more than or less than the specified number.

  Further, in the following embodiments, it is needless to say that the constituent elements are not necessarily essential unless particularly specified and apparently essential in principle. The circuit elements constituting each functional block of the embodiment are not particularly limited, but are formed on a semiconductor substrate such as single crystal silicon by an integrated circuit technology such as CMOS (complementary MOS transistor). Note that in the embodiment, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor: abbreviated as a MOSFET transistor) does not exclude a non-oxide film as a gate insulating film.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 2 is a circuit diagram showing the configuration of the switch circuit according to the first embodiment of the present invention. FIG. 3 is a conceptual diagram showing how this switch circuit is used in an antenna switch.

  Similar to the conventional one, this switch circuit also adopts an SPDT (Single Pole Double Throw) configuration in which one antenna is connected to a transmission circuit and a reception circuit.

  The transmission-side switch circuit includes a through switch M1 composed of a plurality of N-type MOSFET arrays, a shunt switch M2 composed of a P-type MOSFET array, and a capacitor Cg1 for grounding one end of M2 in an alternating manner. A control circuit including peripheral circuits such as an inverter circuit is included. An antenna switching input terminal SW_IN exists as an input terminal of the switch circuit. The transmission side switch circuit is connected to a transmission side circuit (not shown) through a capacitor C3 in that the switch M1 and the switch M2 are connected.

  The antenna switching input terminal SW_IN is a selection signal for switching whether the antenna ANT is connected to a transmission side circuit (not shown) or to a reception side circuit (not shown). When the “H” level is input to the antenna switching input terminal SW_IN, the transmission side is selected, and when the “L” level is input, the antenna ANT is connected to the reception side circuit. However, although the polarity of the antenna switching input terminal SW_IN is “H” at the time of transmission and “L” at the time of reception in the figure, it may be reversed by adjusting the number of inserted inverters.

  The switch M1 is a through-side switch for sending a transmission signal, which has been subjected to transmission path encoding, output from a transmission circuit (not shown) to the antenna. In the figure, the switch M1 is composed of three N-type MOSFETs. However, the number of MOSFETs can be appropriately changed and is not limited to this.

  Each MOSFET constituting the switch M1 determines whether or not to transmit the transmission signal subjected to the above-described transmission line coding between the source terminal and the drain terminal to the antenna. The antenna switching input terminal SW_IN is input with the same polarity to the gate terminal of each MOSFET constituting the switch M1. That is, when the antenna switching input terminal SW_IN is at the “H” level, the switch M1 becomes conductive, and the transmission side circuit (not shown) and the antenna ANT are connected. Conversely, when the antenna switching input terminal SW_IN is at the “L” level, the transmission side circuit (not shown) and the antenna ANT are disconnected.

  The switch M2 is a shunt switch that determines whether a transmission side circuit (not shown) is grounded. In this figure, the switch M2 is composed of eight P-type MOSFETs. However, the number of MOSFETs can be appropriately changed and is not limited to this.

  Each MOSFET constituting the switch M2 connects between the transmission side circuit and the ground potential between the source terminal and the drain terminal via a resistor connected in parallel. And the signal input into the gate terminal of each MOSFET which comprises switch M2 turns into a control signal which opens and closes switch M2.

  Note that the MOSFETs constituting the switch in each embodiment of the present invention are connected by a resistor connected in parallel between the source and drain of the MOSFET unless otherwise specified.

  The antenna switching input terminal SW_IN is also input with the same polarity to the gate terminal of each MOSFET constituting the switch M2. That is, when the antenna switching input terminal SW_IN is at “H” level, the switch M2 is disconnected from the ground. Further, when the antenna switching input terminal SW_IN is at the “L” level, a transmission side circuit (not shown) is grounded.

  The switch M2 is grounded via the grounding capacitor Cg1.

  Between the terminal on the ground side of the switch M2 and the ground capacitor Cg1, the antenna switching input terminal SW_IN is connected with the polarity reversed. When the antenna switching input terminal SW_IN is at “H” level, the AC ground terminal of the switch M2 is set to 0V. As a result, all the DC potentials of the transmission side switch paths can be set to 0 V through the resistors connected in parallel with the switches.

  If the threshold voltage Vth of the N-type MOSFET used in the switch M1 is 0.7V, the ON state margin voltage is 2.3V.

  On the other hand, the gate terminal of the switch M2 is also set to the power supply voltage. Since the switch M2 is composed of a P-type MOSFET, the margin voltage in the off state is 3.7V.

  On the other hand, the receiving-side switch circuit includes a through switch M3 composed of a plurality of N-type MOSFET arrays, a shunt switch M4 composed of a P-type MOSFET, and a capacitor Cg2 for grounding one end of M2 in an AC manner. The control circuit includes a peripheral circuit such as an inverter circuit. In addition, as an input terminal for controlling the switch circuit, there is an antenna switching input terminal SW_IN used on the transmission side. The reception side switch circuit is electrically connected to a reception side circuit (not shown) through a capacitor C4 from a connection point between the switch M3 and the switch M4.

  The switch M3 is a through switch that determines whether or not to connect a signal received by the antenna ANT to a receiving circuit (not shown). In the figure, the switch M3 is composed of eight N-type MOSFETs. However, the number of MOSFETs can be appropriately changed and is not limited to this. In addition, although the gate width of each N-type MOSFET of the switch M3 is assumed to be 6000 μm, both the gate width and the gate length can be appropriately changed.

  Each MOSFET constituting the switch M3 transmits a signal received by the antenna ANT between the source terminal and the drain terminal to the reception side circuit. The antenna switching input terminal SW_IN is input to the gate terminal of the MOSFET after the polarity is inverted. That is, when the antenna switching input terminal SW_IN is at the “L” level, the switch M3 becomes conductive, and the antenna ANT is connected to a reception side circuit (not shown). Conversely, when the antenna switching input terminal SW_IN is at the “H” level, the antenna ANT and a receiving side circuit (not shown) are disconnected.

  The switch M4 is a shunt switch that determines whether a receiving circuit (not shown) is grounded. In this figure, the switch M4 is composed of one P-type MOSFET. However, the number of MOSFETs can be appropriately changed and is not limited to this.

  The MOSFET constituting the switch M4 connects the receiving side circuit and the ground potential between the source terminal and the drain terminal via a resistor connected in parallel. The gate terminal of this MOSFET is inputted in the form in which the polarity of the antenna switching input terminal SW_IN is inverted. That is, when the antenna switching input terminal SW_IN is at the “L” level, the switch M4 is disconnected from the ground. Further, when the antenna switching input terminal SW_IN is at the “H” level, the input terminal of the receiving circuit (not shown) is grounded.

  The switch M4 is grounded via the grounding capacitor Cg2.

  An antenna switching input terminal SW_IN is connected between the ground terminal of the switch M4 and the ground capacitor Cg2. When the antenna switching input terminal SW_IN is at the “L” level, the AC grounding portion that is a connection point between the switch M4 and the grounding capacitor Cg2 is set to 0V.

  The AC ground terminal of the receiving side switch M4 is set to 3.0V. The DC potential of the switch path on the receiving side is set to 3.0 V via a resistor provided in parallel with the MOSFET in the switch M4. Further, the gate terminal voltage of the switch M3 is set to the ground potential (= 0.0V).

  If the threshold voltage Vth of the N-type MOSFET used in the switch M3 is 0.7V, the margin voltage in the ON state is 2.3V (= 3.0V−0.7V). On the other hand, the gate terminal of the switch M4 is also set to the power supply voltage. Since the switch M4 is composed of a P-type MOSFET, the margin voltage in the on state is 2.3.

  As described above, at the same timing, the transmission-side switches M1 and M2 and the reception-side switches M3 and M4 require different DC potential settings. A means for realizing this is an increased capacity C1 disposed between the antenna ANT and the antenna ANT. By sandwiching this, it is avoided that the DC component on the transmission side occurs on the reception side or vice versa. As a result, in this switch circuit, the transmission terminal and the antenna terminal are separated from each other in terms of DC, but it is possible to maintain an AC connection.

  The capacity value of the increased capacity C1 is determined by the frequency used and the transmission / reception method.

  Next, how the switch circuit of FIG. 2 is applied to the power amplifier module will be described with reference to FIG.

  FIG. 3 is a block diagram of a power amplifier module using the switch circuit according to the first embodiment of the present invention.

  The power amplifier module shown in the figure includes an amplifier circuit 10 and an antenna switch 20.

  The amplifier circuit 10 in this figure corresponds to two frequency bands, a high frequency side (1.8 GHz) and a low frequency side (900 MHz), and three-stage amplifiers 11 and 12 are arranged in each. The amplifier circuit 10 includes a bias current and antenna switching control circuit 30. The bias current and antenna switching control circuit 30 controls a bias current supplied to each stage of the three-stage amplifiers 11 and 12 and switches 21 and 22 to be described later.

  The outputs of the three-stage amplifiers 11 and 12 are input to the antenna switch 20 via the couplers 31 and 32. The LPFs 23 and 24 exclude harmonic components from the output signals of the couplers 31 and 32 and output them to the switches 21 and 22.

  The switches 21 and 22 are switches for switching a transmission signal that is an output of the LPFs 23 and 24 and a reception signal transmitted from the antenna ANT. The switch circuit shown in FIG. 2 is applied to the switches 21 and 22.

  The diplexer 33 synthesizes the output of 900 MHz band and 1.8 GHz band with the transmission signal sent from each switch and connects to the antenna ANT.

  By adopting the configuration as described above, it is possible to change both the signal line and the potential of the gate terminal of the MOSFET used as a switch. This makes it possible to ensure a sufficient margin voltage without using a negative bias generation circuit.

(Second Embodiment)
Next, a second embodiment of the present invention will be described.

  In the first embodiment, the signal of the antenna switching input terminal SW_IN is applied to the ground point of the AC signal via the inverter. In this case, it may take time to charge and discharge the accumulated charge in the capacitor C3 (see FIG. 2 and the like) connected to the transmission-side input terminal.

  However, the GSM specification widely used mainly in Europe adopts TDMA (Time Division Multiple Access). Therefore, it is necessary to quickly terminate the charge / discharge from the request for time division control.

  In the present embodiment, not only the ground terminal but also the transmission input terminal is provided with an inverter through a resistor so that the DC potential can be set.

  FIG. 4 is a circuit diagram showing a configuration of a switch circuit according to the second embodiment of the present invention.

  As is apparent from this figure, on the transmission side, the signal connected to the gate terminals of the switches M1 and M2 according to the first embodiment is connected to the capacitor C3 via the inverter It and the resistor Rt. Yes. On the receiving side, the signal connected to the gate terminals of the switches M3 and M4 is connected to the capacitor C4 through the inverter Ir and the resistor Rr.

  In this way, the signal input to the gate terminal of the switch is inverted and directly connected to the capacitors C3 and C4, thereby speeding up the charge / discharge.

  However, it is difficult to say that this is not enough.

  That is, it is considered that the resistances Rt and Rr in the figure are set to values exceeding several hundreds KΩ in order to avoid the influence of waveform distortion. However, if such a large resistor is inserted, it may be considered that a sufficient speed for charge / discharge cannot be obtained.

  FIG. 5 is a circuit diagram showing a configuration of a charging circuit according to the second embodiment of the present invention.

  This charging circuit is provided in addition to the inverter It and the resistor Rt in FIG. Therefore, the inverter It and the resistor Rt in this figure are the same as the inverter It and the resistor Rt used in FIG.

  This charging circuit is characterized in that the resistance value is changed by opening and closing resistors Rb and Rc arranged in parallel with the resistor Rt. Complementary switches MP1 and MP2 are used to open and close the resistors Rb and Rc.

  The complementary switch MP1 is a switch circuit including a P-type MOSFET. The complementary switch MP2 is a switch circuit including an N-type MOSFET.

  A one-shot pulse generation circuit PG generates a one-shot pulse that operates these complementary switches MP1 and MP2. The operating condition of the one-shot pulse generation circuit PG is the rise and fall of the signal to the gate terminal of the input switch M1. If the operating conditions are satisfied, the one-shot pulse generation circuit PG outputs a one-shot pulse.

  (A), (B), and (C) shown in this figure represent measurement points of the voltage waveform in FIGS. 6 and 7. (A) is the output of the inverter It (= operating conditions of the one-shot pulse generation circuit PG), (B) is the gate terminal of the complementary switch MP1 composed of a P-type MOSFET, and (C) is an N-type MOSFET. Each of the gate terminals of the complementary switches MP2 is shown.

  In the figure, a resistor Rb using a P-type MOSFET as a switch and a resistor Rc using an N-type MOSFET as a switch are connected in parallel with the resistor Rt. However, there is no problem even if either one is used. There is no problem even if the same type of MOSFET is used for both the resistors Rb and Rc.

  FIG. 6 is a waveform diagram showing the voltage waveform of the charging circuit when the inverter It rises. FIG. 7 is a waveform diagram showing the voltage waveform of the charging circuit when the inverter It falls.

  As can be seen from these figures, while the one-shot pulse generation circuit PG outputs a pulse waveform, the resistance value of the entire circuit is reduced by the switch and resistors Rb and Rc connected in parallel. As a result, the time constant is reduced, and the charge / discharge of charges to the capacitor C3 is accelerated.

  Next, the operation of the upstream switch M1 will be reviewed. When the switch M1 is in the on state, the switch M1 and the capacitor C3 are biased to 0V. In order to switch off the switch M1, the connection point between the switch M1 and the capacitor C3 is “H”, that is, the connection point between the switch M1 and the capacitor C3 is switched to 3.0V. PG outputs a one-shot pulse represented by (b) and (c) in FIGS. At this time, the time length of the pulse output from the one-shot pulse generation circuit PG can be changed as appropriate. If the time length of the pulse output from the one-shot pulse generation circuit PG that governs the period of decrease in the resistance value is increased, it is possible to extend the charge / discharge promotion period.

  During a period determined by the output pulse width of the one-shot pulse generation circuit PG, the resistance value between the inverter It and the capacitor C3 becomes small. As a result, the response time can be shortened.

  In FIG. 5, the preparation of the time constant of the resistor Rt connected to the transmission side circuit is described. However, it is possible to apply the additional circuit of FIG. 5 to the resistor Rr and the inverter Ir connected to the receiving side circuit of FIG. In this figure and the subsequent FIG. 8, FIG. 12, and FIG. 16, the applicable part of FIG. 4 is surrounded by a broken line.

  In this way, by directly connecting a DC potential to the input terminal on the transmission side and the output terminal on the reception side, and reducing the resistance value for a predetermined period, the charge charge / discharge is promoted, thereby charging the capacitor.・ Discharge can be accelerated.

(Third embodiment)
Next, a third embodiment of the present invention will be described.

  In the first embodiment, the power amplification module that controls transmission and reception by switching on the 900 MHz band and the 1.8 GHz band has been described.

  In this embodiment, it is assumed that a total of 4 bands of 2 bands of 850 MHz and 900 MHz as a 1 GHz band and a total of 4 bands of 1.8 GHz and 1.9 GHz as a 2 GHz band are assumed.

  FIG. 8 is a circuit diagram showing a configuration of a switch circuit according to the third embodiment of the present invention. FIG. 9 is a conceptual diagram showing how the switch circuit of FIG. 8 is used in an antenna switch.

  In the first embodiment, the control input terminal is only the antenna switching input terminal SW_IN. On the other hand, in the present embodiment, the circuit on the receiving side includes two systems of receiving circuits, that is, low frequency system switches M3a and M4a and high frequency system switches M3b and M4b.

  On the transmission side, the power amplifiers 11 and 12 can cope with two frequencies by adjusting the bias current and the like. Therefore, the description on the transmission side is the same as in the second embodiment, and is omitted.

  It is necessary to provide an independent SAW (surface acoustic wave) filter for blocking interference waves in the circuit on the receiving side. For this reason, a dedicated output for each band is required. In FIG. 8, the low frequency system switches M3a and M4a are referred to as a low frequency side switch circuit RL, and the high frequency systems switches M3b and M4b are referred to as a high frequency side switch circuit RH.

  In the first embodiment, the input is one antenna switching input terminal SW_IN. On the other hand, in the present embodiment, there are two inputs of the transmission side antenna switching input terminal TX_SW_IN and the reception side antenna switching input terminal RX_SW_IN.

  The transmission side antenna switching input terminal TX_SW_IN is an input terminal for determining whether or not to enable the transmission side. When this terminal is at “H” level, the output of the transmission side circuit is connected to the antenna. On the other hand, when this terminal is at the “L” level, the output of the transmission side circuit is grounded via the shunt switch M2.

  The receiving antenna switching input terminal RX_SW_IN is an input terminal that determines which of the low frequency side switch circuit RL and the high frequency side switch circuit RH is to be enabled. When this terminal is at “H” level, the low frequency side switch circuit RL is effective. On the other hand, at the “L” level, the high frequency side switch circuit RH is effective.

  A transmission side circuit (not shown) takes a large amount of power of 2 W at maximum. On the other hand, the receiving side circuit passes only about 1 mW of power at the maximum. For this reason, the low frequency side switch circuit RL and the high frequency side switch circuit RH are directly connected to the capacitor C2 to have the same DC potential. Even in this case, although the on / off margin voltage is lowered, it is possible to obtain sufficient performance for reception. It is also possible to reduce the capacity for direct current cut.

  FIG. 10 is a diagram illustrating an example in which the antenna switch of FIG. 9 is integrated on one chip of an SOICMOS integrated circuit. As shown in this figure, it is possible to leave a room for selecting a component by arranging the couplers 31 and 32 and the LPFs 23 and 24 having a room for selecting a component outside the SOICMOS depending on a desired frequency used for transmission.

  Thus, by setting a plurality of reception signal systems to the same DC potential, it is possible to prevent an increase in the capacity for DC cut.

(Fourth embodiment)
Next, a fourth embodiment of the present invention will be described.

  In the embodiments so far, an N-type MOSFET having a small loss has been applied to the switches M1 and M3 for passing signals through the antenna. However, if it is not necessary to consider the loss, P-type MOSFETs may be used for the switches M1 and M3 that pass signals through the antenna.

  FIG. 11 is a circuit diagram showing a configuration of a switch circuit according to the fourth embodiment of the present invention. In this figure, the transmission side switch M1 is an N-type MOSFET, and the shunt switch M2 is a P-type MOSFET. On the other hand, in the receiving side switch circuit, a P-type MOSFET is used for the switch M3, and an N-type MOSFET is used for the shunt switch M4. In this case, even when the same DC bias is applied to the input signal system and the output signal system, it is possible to ensure the same margin voltage as in the first embodiment.

(Fifth embodiment)
Next, a fifth embodiment of the present invention will be described.

  The first to fourth embodiments have been described assuming a second generation multiple access scheme using TDMA such as GSM. On the other hand, this embodiment assumes that the output is switched by a third generation multiple connection method such as W-CDMA.

  FIG. 12 is a circuit diagram showing a configuration of a switch circuit according to the fifth embodiment of the present invention. Conventional switch circuits represent whether one antenna ANT is used for input or output. On the other hand, this switch circuit is different from the previous drawings in that it switches which of the two output terminals (Band1 output terminal and Band2 output terminal) the input signal input from the transmission signal input terminal Pin passes through. Circuit.

  This switch circuit has a switching input terminal SW_INb as a control terminal.

  When the switching input terminal SW_INb is at “H” level, the input signal input from the transmission signal input terminal Pin is output from the Band1 output. On the other hand, when the switching input terminal SW_INb is at the “L” level, the input signal input from the input signal transmission signal input terminal Pin is output from the Band2 output.

  This switching input terminal SW_INb controls the gate terminals of the switches M1, M2, M3, and M4. At this time, an N-type MOSFET is used for the switches M1 and M3 connecting the transmission signal input terminal Pin and each output terminal, a P-type MOSFET is used for the shunt switches M2 and M4, and a capacitor Cb1 inserted immediately before the output terminal, The input signal of the switching input terminal SW_INb is used for charging Cb2.

  FIG. 13 is a conceptual diagram showing how the switch circuit of FIG. 12 is used in an antenna switch. This figure assumes a dual band method using both 1 GHz band and 2 GHz band. However, the present invention can also be applied to the tri-band method and the multi-band method.

  Since W-CDMA performs band spreading, the output peak is low. Therefore, the three-stage amplification is rarely performed as in the GSM system, and generally the amplification is performed by the two-stage amplifiers 111 and 112 as shown in FIG.

  The outputs of the two-stage amplifiers 111 and 112 are input to the couplers 131 and 132 via the matching circuits 141 and 142, respectively.

  The couplers 131 and 132 detect the output voltage, and the detection circuits 151 and 152 transmit the current transmission power to a control circuit (not shown). A control circuit (not shown) performs transmission power control by adjusting the operating voltage of the two-stage amplifiers 111 and 112 and adjusting the bias current via the bias circuits 161 and 162.

  The switch circuit of FIG. 12 is applied as the switch circuits 121 and 122 of this figure. In FIG. 12, the Band1 output and the Band2 output are used. However, the switch circuit 122 inserted on the low frequency side has a Band5 / 6 output and a Band8 output, respectively.

  FIG. 14 is a diagram showing an example in which the antenna switch of FIG. 13 is integrated on an SOICMOS integrated circuit 1 chip. As described above, even in the W-CDMA system, the couplers 131 and 132 and the matching circuits 141 and 142 can be exchanged to form a single chip.

  In this way, the present invention can be applied without using a negative bias circuit not only for input / output switching in the GSM system but also in switching the output destination of the W-CDMA system.

(Sixth embodiment)
Finally, a sixth embodiment of the present invention will be described.

  When the transmission output is reduced to about 1 mW, the power consumption can be reduced by stopping the two-stage amplifiers 111 and 112 shown in FIG. 14 and outputting without amplification.

  FIG. 15 is a conceptual diagram showing a configuration of an antenna switch according to the sixth embodiment of the present invention. This antenna switch is characterized by switch circuits 191 and 192 for replacing the switch circuits 181 and 182 for providing a bypass path and the switch circuits 121 and 122 according to the fifth embodiment.

  The switch circuits 181 and 182 are switch circuits that determine whether or not a control circuit (not shown) uses a bypass according to the outputs of the detection circuits 151 and 152. Although omitted in the figure, a signal for controlling the switch is output from a control circuit (not shown).

  The switch circuits 191 and 192 are switch circuits configured such that the switch circuits 121 and 122 can be switched on the input side.

  FIG. 16 is a circuit diagram showing a configuration of a switch circuit according to the sixth embodiment of the present invention.

  This switch has two control terminals, an input side control terminal Sin and an output side control terminal Sout. An input terminal and an output terminal are selected by combining the input side control terminal Sin and the output side control terminal Sout with AND gates NAND1 and AND2.

  The output of the NAND 1 is input to the gate terminal of the switch M 1 and the switch Mb 1 newly provided in this embodiment after sandwiching the inverter. While the switch M1 is an N-type MOSFET, the switch Mb1 uses a P-type MOSFET. When the output of the NAND1 is “H”, the bypass side is used, and when the output is “L”, the two-stage amplifiers 111 and 112 are used. The amplified signal that passed through becomes the input signal.

  The output of the AND2 is also input to the gate terminal of the switch M3 and the switch Mb2 newly provided in the present embodiment after sandwiching the inverter. The switch M3 is also an N-type MOSFET, and the switch Mb2 is a P-type MOSFET. As a result, when the output of AND2 is “H”, the bypass side uses the bypass path signal through the switch circuits 181 and 182 as the input signal.

  Both NAND1 and AND2 use the input side control terminal Sin as one input.

  On the other hand, NAND1 inputs the output side control terminal Sout as it is, and AND2 inputs the output side control terminal Sout inverted by the inverter Ix. Thus, only one of the Band1 output and the Band2 output becomes an output terminal that operates.

  The input-side control terminal Sin is a control terminal that determines whether a signal on the bypass path that passes through the switch circuits 181 and 182 is used as an input signal or an amplified signal that passes through the two-stage amplifiers 111 and 112 is used as an input signal. It is. When this control terminal is “H”, the amplified signal that has passed through the two-stage amplifiers 111 and 112 is used as an input signal. On the other hand, when the control terminal is “L”, the bypass path signal through the switch circuits 181 and 182 is used as the input signal.

  On the other hand, the output side control terminal Sout is an output control terminal that determines whether to pass the Band1 output or the Band2 output. When this control terminal is “H”, the output is selected as the Band1 output, and when it is “L”, the output is selected as the Band2 output.

  By adopting the configuration as described above, it is possible to switch not only the output terminals but also the input terminals.

  At this time, in the present embodiment, the signal at the output side control terminal Sout is connected via the inverters Ir1, Ir2 and the resistors Rr1, Rr2, thereby facilitating the charge / discharge of the capacitors Cb1, Cb2 inserted immediately before the output terminal. To do. Thereby, it is possible to realize a function equivalent to the second embodiment. At this time, a form using a one-shot pulse generation circuit PG as shown in FIG. 5 may be used.

  Thus, even when using a bypass, the present invention can be applied without using a negative bias circuit. Further, the present invention can be applied not only to switching between transmission and reception but also to switching which of the two transmission terminals is used.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

ANT ... antenna, NAND1 ... Nand gate, AND2 ... AND gate,
C1 ... Increase capacity, C2 ... Capacity, C3 ... Capacity, C4 ... Capacity,
Cg1, Cg2 ... grounding capacitance, Ir, It, Ix ... inverter,
M1, M2. M3, M3a, M3b, M4, M4a, M4b ... switch,
PG ... One-shot pulse generation circuit, Rb, Rc, Rr, Rt ... resistance,
11, 12 ... 3-stage amplifier, 21, 21c, 22, 22c ... switch,
23, 24 ... LPF, 30 ... bias current and antenna switching control circuit,
31, 32 ... coupler, 100 ... bias circuit,
111, 112 ... two-stage amplifier, 121, 122 ... switch circuit,
131, 132 ... coupler, 141, 142 ... matching circuit,
151, 152 ... detection circuit, 161, 162 ... bias circuit,
171 and 172 are matching circuits.

Claims (6)

A switch circuit that determines whether an antenna is connected to an external circuit,
The switch circuit is
A first switch for passing the output of the external circuit through the antenna; and a capacitor electrically positioned between the first switch and the external circuit; and a control signal for the first switch Is inverted by an inverter and connected to a connection point between the first switch and the capacitor ,
Including a first resistor between the connection point and the inverter;
A switch circuit including a second resistor and a resistor opening / closing switch connected in parallel with the first resistor, wherein the resistance value connected to the inverter is variable by opening and closing the resistor opening / closing switch . The switch circuit according to claim 1 , further comprising a one-shot pulse generation circuit to which a control signal of the first switch is input,
A switch circuit in which the one-shot pulse generation circuit opens and closes the resistor open / close switch during a predetermined period at the timing of a change in the control signal of the first switch. 3. The switch circuit according to claim 1, wherein the first switch includes an N-type FET, and the control signal is input to a gate terminal of the N-type FET constituting the first switch. . 3. The switch circuit according to claim 1, wherein the first switch includes a P-type FET, and the control signal is input to a gate terminal of the P-type FET constituting the first switch. . The semiconductor device using a switching circuit according to claim 1 or 2. A portable radio using the semiconductor device according to claim 5 .

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