JP5240658B2 - Compound semiconductor epitaxial wafer manufacturing method, compound semiconductor epitaxial wafer, and light emitting device - Google Patents

Description

  The present invention relates to a method for manufacturing a compound semiconductor epitaxial wafer, a compound semiconductor epitaxial wafer, and a light emitting device.

US Patent No. 5,008,718 JP 2004-128452 A

The light-emitting layer portion is formed by (Al _x Ga _1-x ) _y In _1-y P mixed crystal (where 0 ≦ x ≦ 1, 0 <y ≦ 1; hereinafter also referred to as AlGaInP mixed crystal or simply AlGaInP). The light emitting device has a high brightness by adopting a double hetero structure in which a thin AlGaInP active layer is sandwiched between an n-type AlGaInP cladding layer and a p-type AlGaInP cladding layer having a larger band gap. An element can be realized.

  Specifically, an n-type GaAs buffer layer, an n-type AlGaInP cladding layer, an AlGaInP active layer, and a p-type AlGaInP cladding layer are stacked in this order by heteroepitaxy on an n-type GaAs single crystal substrate, and a double hetero A light emitting layer portion having a structure is formed. Energization of the light emitting layer portion is performed through a metal electrode formed on the element surface. Here, since the metal electrode acts as a light shield, it is formed, for example, so as to cover only the central portion of the main surface of the light emitting layer portion, and light is extracted from the surrounding electrode non-formation region.

  In this case, reducing the area of the metal electrode as much as possible can increase the area of the light leakage region formed around the electrode, which is advantageous from the viewpoint of improving the light extraction efficiency. Conventionally, attempts have been made to increase the light extraction amount by effectively spreading the current in the element by devising the electrode shape, but in this case also the increase in the electrode area is unavoidable anyway, the light leakage area On the contrary, it falls into a dilemma where the amount of light extraction is limited by the decrease. In addition, the carrier concentration of the dopant in the clad layer, and thus the conductivity, is kept somewhat low in order to optimize the light emission recombination of carriers in the active layer, and the current tends not to spread in the in-plane direction. . This leads to concentration of current density in the electrode coating region, and a substantial light extraction amount in the light leakage region is reduced.

Therefore, a method is known in which a current density is minimized by providing a thick and conductive transparent window layer (current diffusion layer) between the light emitting layer portion and the electrode (Patent Document 1). ).
In order to efficiently form a current spreading layer, a thin light emitting layer is formed by metal organic vapor phase epitaxy (hereinafter also referred to as MOVPE method), while a thick current spreading layer is formed by hydride gas. A method of forming by the phase growth method (Hydride Vapor Phase Epitaxial Growth Method: hereinafter also referred to as HVPE method) is known (Patent Document 2).

  When a GaP current diffusion layer is grown thickly using a hydride vapor phase growth method on an AlGaInP light emitting layer portion hetero-grown on a GaAs single crystal substrate, an AlGaInP light emitting layer portion (and hence a GaAs single crystal substrate), a GaP current diffusion layer, Due to the difference in strain and linear expansion coefficient due to lattice mismatch, the epitaxial wafer obtained in the process of cooling from a high temperature after growth (for example, 750 ° C.) has a concave surface on the GaAs single crystal substrate side and a convex surface on the GaP current diffusion layer side. Warp occurs in the form of The amount of warpage varies depending on the thickness of the GaP current diffusion layer. For example, a wafer having an outer diameter of about 50 mm (about 2 inches) has a thickness of 500 to 700 μm and is cracked when an element processing such as polishing or dicing is performed. There is a problem that tends to occur. In particular, a wafer (for example, a wafer disposed downstream in the gas flow direction, particularly below the container in the gas flow direction) at a position where supply of the source gas is likely to be insufficient in the hydride vapor phase growth vessel is GaP. Hole-like defects called pits are likely to be formed in the current diffusion layer, and cracks and the like based on the defects are likely to occur.

  The present invention suppresses the formation of pits in the GaP current diffusion layer when the GaP current diffusion layer is formed thick using hydride vapor phase epitaxy, and can be used as an element such as polishing or dicing in a warped state. An object of the present invention is to provide a compound semiconductor epitaxial wafer in which cracks or the like based on the pits are unlikely to occur when processing is performed, a method for manufacturing the compound semiconductor epitaxial wafer, and a light emitting device manufactured using the compound semiconductor epitaxial wafer.

Means and actions / effects for solving the problems

In order to solve the above problems, the method for producing a compound semiconductor epitaxial wafer of the present invention comprises:
(AlxGa1-x) yIn1- containing two or more group III elements on a GaAs single crystal substrate having a main axis with a <100> direction as a reference direction and an off-angle from the reference direction of 10 ° to 20 °. a metal organic chemical vapor deposition step of forming a light emitting layer portion composed of yP (where 0 ≦ x ≦ 1, 0 <y ≦ 1) and a first GaP layer in this order; and a first GaP layer A hydride vapor phase growth step for forming a second GaP layer thereon,
The second GaP layer has a GaP high-speed growth layer located on the side close to the light emitting layer portion and a GaP low-speed growth layer following the GaP high-speed growth layer. Each growth layer is grown at a second growth rate lower than the first growth rate ,
First growth rate, characterized that you have been set fast enough to prevent pits generated on the surface of the GaP high-rate growth layer.

The compound semiconductor epitaxial wafer of the present invention is
(AlxGa1-x) yIn1- containing two or more group III elements on a GaAs single crystal substrate having a main axis with a <100> direction as a reference direction and an off-angle from the reference direction of 10 ° to 20 °. A light emitting layer portion composed of yP (where 0 ≦ x ≦ 1, 0 <y ≦ 1) and a first GaP layer are formed in this order by metal organic vapor phase epitaxy, and the first GaP layer A second GaP layer is formed thereon by hydride vapor phase epitaxy; and a second GaP layer is a GaP fast growth layer located on the side closer to the light emitting layer portion; and a GaP slow growth layer following the GaP fast growth layer; Tona is,
No pit is formed in the GaP high-speed growth layer .

Furthermore, the light emitting device of the present invention is manufactured by forming an electrode on the compound semiconductor epitaxial wafer of the present invention and dicing, and includes two or more group III elements on a GaAs single crystal substrate (Al _x Ga _{1-1). x} ) _y In _1-y P (where 0 ≦ x ≦ 1, 0 <y ≦ 1), a light emitting layer portion formed by metal organic vapor phase epitaxy, and by metal organic vapor phase epitaxy The formed first GaP layer and the second GaP layer formed by the hydride vapor phase growth method are stacked in this order, and the second GaP layer is located on the side closer to the light emitting layer portion. And a GaP slow growth layer following the GaP fast growth layer.

In the method for producing a compound semiconductor epitaxial wafer of the present invention, for example, (Al _x Ga _1-x ) _y In _1-y P containing two or more group III elements (where 0 ≦ x ≦ 1, 0 <y ≦ The light emitting layer portion configured in 1) is grown on a single crystal substrate by using a metal organic vapor phase growth method (MOVPE method) (metal organic vapor phase growth step). On the other hand, it is efficient to form a current diffusion layer that needs to have a certain layer thickness in order to sufficiently expand the current in the in-plane direction by using a hydride vapor phase growth method (hydride vapor phase growth). Process). In the HVPE method, Ga (gallium) having a low vapor pressure is converted into GaCl which is easily vaporized by reaction with hydrogen chloride in a quartz reactor substituted with hydrogen gas, and the group V is formed through the GaCl as a medium. This is a method for performing vapor phase growth of a group III-V compound semiconductor layer by reacting an element source gas with Ga. The layer growth rate by the MOVPE method is about 1 μm / hr, whereas the HVPE method has a rate of about 20 μm / hr. According to the HVPE method, the layer growth rate can be made larger than the MOVPE method, Since it can be formed with very high efficiency, the raw material cost can be kept much lower than that of the MOVPE method. In the HVPE method, an expensive organic metal is not used as the group III element source, and the mixing ratio of the group V element source (AsH ₃ , PH _3, etc.) to the group III element source is much smaller (for example, 1 / This is advantageous in terms of cost.

  In the present invention, when the second GaP layer is grown by the hydride vapor phase growth method, the GaP high-speed growth layer is formed by setting a predetermined period at the start of growth as the first growth rate, A GaP slow growth layer is formed at a second growth rate lower than the first growth rate. That is, the first stage of growth of the second GaP layer is a high-speed growth mode in which the raw material supply amount is increased, thereby suppressing pits that are likely to be formed when the raw material is in short supply. On the other hand, in the high-speed growth mode, as a result of promoting lattice relaxation at the interface with the light emitting layer portion, a protruding defect called hillock tends to be formed. Therefore, as a second stage of growth, by forming a GaP slow growth layer on the GaP fast growth layer by a slow growth mode in which the raw material supply amount is reduced, hillock defects on the surface of the second GaP layer finally obtained are formed. It is possible to prevent the size and amount from becoming excessive. Thereby, simplification of the polishing process of the main surface of the epitaxial wafer formed by the second GaP layer can be achieved.

  As described above, when the second GaP layer is grown thickly using the hydride vapor phase growth method on the AlGaInP light emitting layer portion hetero-grown on the GaAs single crystal substrate, the GaAs single crystal substrate side is concave on the resulting epitaxial wafer. The warp is generated in such a manner that the second GaP layer side becomes a convex surface. If a large number of pits are formed in the second GaP layer, cracks are likely to occur in the wafer from the pits as a base point when an element processing such as polishing or dicing is performed. However, as described above, the adoption of the present invention suppresses the formation of pits in the second GaP layer that is the main component of the GaP current diffusion layer, so that the wafer is less likely to be cracked during the element processing.

  The first GaP layer and the second GaP layer desirably have a total thickness of 100 μm or more in order to effectively contribute to improving the light extraction efficiency as the GaP current diffusion layer. In consideration of productivity and the like, the total thickness is preferably 250 μm or less. On the other hand, it is appropriate that the thickness of the GaAs single crystal substrate is not less than 250 μm and not more than 350 μm in consideration of the substrate strength that can withstand handling during manufacturing.

  Among these, the first GaP layer is desirably formed to have a thickness of 1 μm or more in order to stably contribute as a growth base surface of the second GaP layer grown thereafter while maintaining lattice matching with the light emitting layer portion. However, considering that an organic metal growth method with a low growth rate is adopted, the thickness of the first GaP layer is desirably 5 μm or less from the viewpoint of manufacturing efficiency.

  Since the second GaP layer is formed as a main part of the GaP current diffusion layer by a hydride vapor phase growth method having a high growth rate, the thickness is desirably 99 μm or more. Among these, by growing the GaP high-speed growth layer to a thickness of 50 μm or more, the formation efficiency of the entire second GaP layer can be improved while sufficiently suppressing the formation of pits in the layer. The thickness of the GaP slow growth layer is preferably 5 μm or more and 49 μm or less.

  The first growth rate for forming the GaP high-speed growth layer is desirably set to a high speed that does not generate pits on the surface of the GaP high-speed growth layer. In order to prevent the formation of pits, when a GaP low-speed growth layer is further grown, the surface should be set to a high speed at which a hillock remains at a height of 5 μm to 20 μm, more specifically 25 μm / hr. It is desirable to set it to 40 μm / hr or less.

  On the other hand, the second growth rate for forming the GaP slow growth layer is preferably set to 1/5 or more and 1/2 or less of the first growth rate. When the low-speed growth layer is grown at a growth rate that is 1/2 or less that of the high-speed growth layer, it is possible to prevent a problem that excessive hillocks remain on the surface of the GaP low-speed growth layer. However, if the second growth rate is less than 1/5 of the first growth rate, it is difficult to control the growth rate, so it is desirable that the second growth rate be 1/5 or more of the first growth rate. .

  Hillock formed on the surface of the GaP slow growth layer can be removed by polishing. When hillocks remain on the surface of the GaP slow growth layer at a height of 5 μm or more and 20 μm or less, the thickness of the second GaP layer grows to a thickness within the range of 10 μm or more and 30 μm or less from the target thickness, and is set to the target thickness by polishing. A process can be adopted. In this case, the surface of the GaP slow growth layer of the obtained compound semiconductor epitaxial wafer is a polished surface.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a conceptual diagram showing an example of a compound semiconductor epitaxial wafer 100 of the present invention. The compound semiconductor epitaxial wafer 100 has a light emitting layer portion 24 formed on a first main surface of an n-type GaAs single crystal substrate (hereinafter also simply referred to as a substrate) 1 as a growth single crystal substrate. The substrate 1 has a main axis A having an off angle with respect to the reference direction of 10 ° or more and 20 ° or less with the <100> direction as a reference direction. An n-type GaAs buffer layer 2 is formed in contact with the first main surface of the substrate 1, and a light emitting layer portion 24 is formed on the buffer layer 2. A first GaP layer 7 a and a second GaP layer 7 are formed on the light emitting layer portion 24.

The light emitting layer portion 24 includes the active layer 5 made of a non-doped (Al _x Ga _1-x ) _y In _1-y P (where 0 ≦ x ≦ 0.55, 0.45 ≦ y ≦ 0.55) mixed crystal. , p-type _{(Al z Ga 1-z)} y In 1-y P ( except x <z ≦ 1) p-type cladding layer 6 and the n-type composed of _{(Al z Ga 1-z)} y In 1-y P ( However, it has a structure sandwiched between n-type cladding layers 4 made of x <z ≦ 1). In the compound semiconductor epitaxial wafer 100 of FIG. 1, the p-type AlGaInP cladding layer 6 is disposed on the first GaP layer 7a and the second GaP layer 7 side, and the n-type AlGaInP cladding layer 4 is disposed on the n-type GaAs single crystal substrate 1 side. Has been. Therefore, the current-carrying polarity when the light emitting element is obtained is positive on the first GaP layer 7a and second GaP layer 7 side. The term “non-doped” as used herein means “does not actively add dopant”, and contains a dopant component inevitably mixed in a normal manufacturing process (for example, 10 ¹³ to 10 ¹⁶ / cm 3). It is not excluded that the upper limit is about ³ ).

  The second GaP layer 7 is formed as a p-type GaP layer whose dopant is Zn. The total thickness of the first GaP layer 7a and the second GaP layer 7 is, for example, not less than 100 μm and not more than 250 μm. The second GaP layer 7 is formed by laminating a GaP high-speed growth layer 7b and a GaP low-speed growth layer 7c in this order by a hydride vapor phase growth method. The thickness of the GaP fast growth layer 7b is, for example, 50 μm or more (the upper limit is, for example, 200 μm), and the thickness of the GaP slow growth layer 7c is, for example, 5 μm or more and 49 μm or less. No pit is formed in the GaP high-speed growth layer 7b, and the surface of the GaP low-speed growth layer 7c is a mirror-polished surface.

  A p-type dopant is added to each of the first GaP layer 7a, the GaP fast growth layer 7b, and the GaP slow growth layer 7c. As the p-type dopant, Zn can be adopted for all of 7a, 7a, and 7b as in the present embodiment, but the dopant of the first layer 7a formed by MOVPE is applied to the p-type cladding layer 6 side. Mg and / or C which hardly causes diffusion may be used, and Zn may be used as a dopant for the GaP high-speed growth layer 7b and the GaP low-speed growth layer 7c formed by HVPE.

Hereinafter, a method for manufacturing the compound semiconductor epitaxial wafer 100 of FIG. 1 will be described. First, as shown in Step 1 of FIG. 2, a GaAs single crystal substrate 1 having a main axis with an off angle of 10 ° to 20 ° is prepared with the <100> direction as a reference direction. Then, as shown in step 2, the n-type GaAs buffer layer 2 is, for example, 0.5 μm on the first main surface of the substrate 1, and then the light emitting layer portion 24 is (Al _x Ga _1-x ) _y In _{A 1} μm n-type cladding layer 4 (the n-type dopant is Si), a 0.6 μm active layer (non-doped) 5, a 1 μm p-type cladding layer 6, and a p-type first GaP layer 7 a ( The p-type dopant is Mg: C from the organometallic molecule can also contribute as the p-type dopant) in this order (organic metal vapor phase growth step). Epitaxial growth of each of these layers is performed by a known MOVPE method. The following materials can be used as source gases for the source components of Al, Ga, In (indium), and P (phosphorus);
Al source gas; trimethylaluminum (TMAl), triethylaluminum (TEAl), etc .;
Ga source gas; trimethylgallium (TMGa), triethylgallium (TEGa), etc .;
In source gas; trimethylindium (TMIn), triethylindium (TEIn), etc .;
P source gas: trimethyl phosphorus (TMP), triethyl phosphorus (TEP), phosphine (PH ₃ ), etc.

  Next, proceeding to FIG. 3, a p-type GaP high-speed growth layer 7b (step 3) and a GaP low-speed growth layer 7c (step 4) are grown on the first GaP layer 7a by the HVPE method (hydride vapor phase). Growth process). In order to grow the second GaP layer 7 by the HVPE method after the first GaP layer 7a is grown by the MOVPE method, the intermediate substrate 211 formed up to the first GaP layer 7a shown in Step 2 of FIG. It is necessary to transfer from the device for the HVPE to the device for the HVPE.

  FIG. 7 is a schematic diagram showing an example of an HVPE apparatus. The apparatus 201 includes a first chamber 204 in which a crucible 208 for storing a Ga melt 209 is disposed, and a susceptor 210 (for example, quartz) that holds an intermediate substrate 211. A growth vessel having a second chamber 205 in which is accommodated, but not limited to. The first chamber 204 and the second chamber 205 are made of quartz together with the crucible 208, and are heated by individual heaters 202 and 203, respectively. That is, both the housing space (second chamber 205) of the susceptor 210 and the housing space (first chamber 204) of the crucible 208 that stores the raw metal melt of the second GaP layer 7 are individually heaters 202 and 203. Thus, the temperature can be adjusted independently.

Both the first chamber 204 and the second chamber 205 are heated to an appropriate processing temperature of 700 ° C. or higher so that the HVPE reaction proceeds sufficiently. Into the first chamber 204 in which the quartz crucible 208 in which the Ga melt 209 is accommodated is placed, from the inlet 206, HCl gas, H ₂ gas as a carrier gas, and P (group V element) source gas. PH ₃ and DM (dimethyl) Zn or DMMg as a dopant gas are introduced.

By introducing HCl onto Ga, GaCl is generated by the reaction of the following formula (1).
Ga (liquid) + HCl (gas) → GaCl (gas) + 1 / 2H ₂ (1)
GaCl is excellent in reactivity with PH _3, and the second GaP layer 7 can be efficiently grown by the reaction of the following formula (2):
GaCl (gas) + PH ₃ (gas)
→ GaP (solid) + HCl (gas) + H ₂ (gas) (2)

  The growth rate of the GaP slow growth layer 7c is set lower than the growth rate of the GaP fast growth layer 7b. More specifically, the growth rate of the GaP high-speed growth layer 7b is set to a high-speed growth in which the source gas having a growth rate of 25 μm / hr or more and 40 μm / hr or less is excessive. Since the GaP high-speed growth layer 7b is formed at a considerably high speed, the supply amount of the source gas is set higher than usual, and almost no pits are observed on the layer surface 7m after the growth. On the other hand, a minute hillock HK is formed on the surface 7m of the layer. Normally, the substrate 1 is not taken out from the hydride vapor phase growth apparatus between the GaP high speed growth layer 7b and the GaP low speed growth layer 7c, but once the substrate 1 is taken out from the hydride vapor growth apparatus, the surface of the GaP high speed growth layer 7b is obtained. There are almost no pits and small hillocks can be observed scattered.

  A plurality of intermediate substrates 211 are placed on the susceptor 210 in FIG. 7 in the gas flow direction. In particular, the intermediate substrate 211 located on the downstream side of the susceptor 210 tends to have a shortage of source gas, and pits are more easily formed. By setting the raw material gas supply amount high as described above, it is possible to remarkably suppress the formation of pits on the downstream intermediate substrate 211 as well. It is also possible to provide a plurality of susceptors 210 in the vertical direction and to arrange a plurality of intermediate substrates 211 in the vertical direction. In this case, the shortage of the source gas is likely to occur in the intermediate substrate 211 located on the lower side, but in this case as well, the formation of pits can be remarkably suppressed by setting the source gas supply amount high as described above.

Timing of supply of raw materials during the growth of the GaP high-rate growth layer 7b, while stopping the supply of the group III component at the start of growth by stopping the supply of HCl gas in the apparatus of FIG 7, V group raw material (PH ₃ ) Only, and in this state, the group III gas is allowed to flow instantaneously and steeply to further promote lattice relaxation at the interface with the light emitting layer portion. Thereby, layer growth in which a minute amount of hillock is formed can be performed with good reproducibility.

  Thereafter, the GaP slow growth layer 7c is formed at a growth rate of 1/5 or more and 1/2 or less of the GaP fast growth layer 7b. Although the height of the hillock HK is somewhat reduced, the hillock HK remains on the GaP slow growth layer 7c at a level of 5 μm to 20 μm. The thickness of the second GaP layer 7 (= GaP high-speed growth layer 7b + GaP low-speed growth layer 7c) is thickly grown in a range of 10 μm to 30 μm from the target thickness in anticipation of removal of the hillock HK by polishing.

  The GaP slow growth layer 7c grows at a temperature of 700 ° C. or higher and 800 ° C. or lower. On the other hand, the GaP high-speed growth layer 7b grows at a higher temperature than the GaP low-speed growth layer 7c, thereby making it easier to ensure a higher growth rate. In this way, the thickness from the first GaP layer 7a to the GaP slow growth layer 7c (the thickness of the GaP current diffusion layer) is 100 μm or more and 250 μm or less, the thickness of the GaP slow growth layer 7c is 5 μm or more and 50 μm or less, GaP The compound semiconductor wafer 100 having a surface state in which the high-speed growth layer 7b has a thickness of 100 μm or more, the generation of pits is suppressed, and minute hillocks remain can be obtained.

  When the above steps are completed, the process proceeds to step 5 in FIG. 4, where the surface layer portion 7g of the second GaP layer 7 is polished to the target thickness (lapping + polishing) to remove hillocks HK. Thereby, the main surface of the GaP slow growth layer 7c becomes a polished surface. Next, as shown in Step 6, the first electrode 9 and the second electrode 20 are formed on the polished surface by vacuum deposition, and baking for electrode fixing is performed at an appropriate temperature. Thereafter, the wafer is diced and separated into individual elements. Then, the second electrode 20 is fixed to a terminal electrode (not shown) that also serves as a support using a conductive paste such as an Ag paste, while a current-carrying wire is bonded to the first electrode 9 and a resin mold is formed. By doing so, the light emitting element 200 is obtained.

  As shown in FIG. 5, when the second GaP layer 7 is grown thickly on the AlGaInP light emitting layer portion 24 hetero-grown on the GaAs single crystal substrate 1 by using a hydride vapor phase growth method, the AlGaInP light emitting layer portion 24 (and thus GaAs). Due to the difference in strain and linear expansion coefficient due to lattice mismatch between the single crystal substrate 1) and the second GaP layer 7, the resulting epitaxial wafer has a concave surface on the GaAs single crystal substrate 1 side in the process of cooling from a high temperature after growth. Thus, warpage occurs in a form in which the second GaP layer 7 side becomes a convex surface. The amount of warpage varies depending on the thickness of the second GaP layer 7, but is 500 to 700 μm for a wafer having an outer diameter of about 50 mm (about 2 inches), for example.

  As shown on the left of FIG. 6, when the pit PT is formed in the second GaP layer 7, when polishing or dicing is performed while correcting the warp of the wafer by pressurization, the pit PT is used as a base point. CK is likely to occur. However, if the pit PT is not formed in the second GaP layer 7 by adopting the present invention, cracking is less likely to occur even if polishing or dicing is performed while correcting the warpage of the wafer.

The compound semiconductor wafer 200 shown in FIG. 3 is formed so that each layer has the following thickness. As the GaAs single crystal substrate, a substrate having a thickness of 280 μm with the <100> direction as the reference direction and an off-angle with respect to the reference direction set to about 15 ° is used. The n-type AlGaInP clad layer 4, the AlGaInP active layer 5, the p-type AlGaInP clad layer 6 and the first GaP layer 7a are formed using a MOVPE apparatus (metal organic vapor phase growth process), and the GaP slow growth layer 7c and the GaP fast growth layer are formed. The layer 7b is formed in a hydrogen atmosphere at about 760 ° C. using a hydride vapor phase growth apparatus (hydride vapor phase growth step) to obtain the compound semiconductor wafer 200. The growth rate of the GaP high-speed growth layer 7b was set to various values of 10 μm / hr to 40 μm / hr including the comparative example. On the other hand, the growth rate of the GaP slow growth layer 7c was fixed at about 6 μm / hr. The thickness of each layer is as follows.
N-type AlGaInP cladding layer 4 = 1 μm;
AlGaInP active layer 5 = 0.6 μm (emission wavelength 650 nm);
P-type AlGaInP cladding layer 6 = 1 μm;
First GaP layer 7a = 3 μm;
GaP high-speed growth layer 7b = 90 μm;
GaP slow growth layer 7c = 40 μm;

In each compound semiconductor wafer, when the GaP high-speed growth layer 7b had been grown, the main surface of the GaP high-speed growth layer 7b was visually observed under a fluorescent lamp to confirm the presence of pits and hillocks. In all cases, the number of pits formed per 1 cm ^{2 of} viewing area is 0, “none”, 1 to less than 100 “small”, 100 to less than 1000 “medium”, 1000 With the above as “many”, each position (upstream, middle stream, downstream) on the susceptor 210 in FIG. 7 was evaluated individually. The results are shown in Tables 1 and 2.

  It can be seen that when the growth rate of the GaP high-speed growth layer 7b is set to 25 μm / hr or more and 40 μm / hr or less, pits are hardly formed and hillocks are increased. The formation of pits when the growth rate is low is particularly remarkable in the downstream substrate, but it can be seen that if the growth rate is set to 25 μm / hr or more, pit formation is also significantly suppressed in the downstream substrate.

  In addition, after forming the GaP slow growth layer 7c on each wafer, the surface layer portion was polished by about 15 μm by lapping polishing, and it was visually confirmed whether or not the wafer was cracked during polishing. For each growth rate, 120 wafers were subjected to a polishing test, and the ratio of unbroken wafers was calculated as the soundness rate. The result is shown in FIG. According to this, when the growth rate of the GaP high-speed growth layer 7b is set to 25 μm / hr or more and 40 μm / hr or less, the soundness rate of the wafer is remarkably increased, and if the growth rate is set to 30 μm / hr, pits are formed. It can be seen that cracks are also remarkably suppressed in the downstream wafer, which is easy.

The schematic diagram which shows an example of the compound semiconductor epitaxial wafer of this invention by a laminated structure. Explanatory drawing which shows the manufacturing process of the compound semiconductor wafer of this invention. Explanatory drawing following FIG. Explanatory drawing following FIG. The schematic diagram which shows a mode that a curvature generate | occur | produces in a compound semiconductor epitaxial wafer. The figure explaining a mode that a pit becomes a crack generating factor of a wafer. The schematic diagram which shows an example of an HVPE apparatus. The graph which shows the experimental result which investigated the relationship between the growth rate of a GaP high-speed growth layer, and a wafer crack.

Explanation of symbols

1 GaAs single crystal substrate (growth substrate)
4 n-type cladding layer 5 active layer 6 p-type cladding layer 7a first GaP layer 7 second GaP layer 7b GaP high-speed growth layer 7c GaP low-speed growth layer 100 compound semiconductor epitaxial wafer 200 light emitting device

Claims (15)

(AlxGa1-x) yIn1- containing two or more group III elements on a GaAs single crystal substrate having a main axis with a <100> direction as a reference direction and an off-angle from the reference direction of 10 ° to 20 °. a metal organic vapor phase growth step of forming a light emitting layer portion composed of yP (where 0 ≦ x ≦ 1, 0 <y ≦ 1) and a first GaP layer in this order, and the first GaP A hydride vapor phase growth step of forming a second GaP layer on the layer,
The second GaP layer has a GaP high-speed growth layer positioned on the side close to the light emitting layer portion and a GaP low-speed growth layer following the GaP high-speed growth layer, and the GaP high-speed growth layer is formed at a first growth rate. Each of the GaP slow growth layers is grown at a second growth rate lower than the first growth rate ,
It said first growth rate, production method of a compound semiconductor epitaxial wafer pit on the surface of the GaP high-rate growth layer is characterized that you have been set to a high speed so as not to occur.   2. The compound semiconductor epitaxial wafer according to claim 1, wherein the thickness of the GaAs single crystal substrate is 250 μm or more and 350 μm or less, and the total thickness of the first GaP layer and the second GaP layer is 100 μm or more and 250 μm or less. Method.   The method of manufacturing a compound semiconductor epitaxial wafer according to claim 2, wherein the GaP high-speed growth layer is grown to a thickness of 50 µm or more.   4. The method for producing a compound semiconductor epitaxial wafer according to claim 2, wherein the GaP slow growth layer has a thickness of 5 μm or more and 49 μm or less. 5. Said first growth rate, according to any one of the GaP low-rate growth layer surface to a height 5μm or 20μm claims 1 to 4 is set so fast hillocks remaining in the following A method of manufacturing a compound semiconductor epitaxial wafer. The method for producing a compound semiconductor epitaxial wafer according to any one of claims 1 to 5 , wherein the first growth rate is set to 25 µm / hr or more and 40 µm / hr or less. It said second growth rate, production method of the compound semiconductor epitaxial wafer according to any one of claims 1 to 6 is set to be 1/5 to 1/2 of the first growth rate. The manufacturing method of the compound semiconductor epitaxial wafer of any one of Claim 1 thru | or 7 which removes the hillock formed in the surface of the said GaP slow growth layer by grinding | polishing process. 9. The method of manufacturing a compound semiconductor epitaxial wafer according to claim 8 , wherein the thickness of the second GaP layer is grown to be thicker than the target thickness in a range of 10 [mu] m to 30 [mu] m, and the target thickness is obtained by the polishing process. (AlxGa1-x) yIn1- containing two or more group III elements on a GaAs single crystal substrate having a main axis with a <100> direction as a reference direction and an off-angle from the reference direction of 10 ° to 20 °. A light emitting layer portion composed of yP (where 0 ≦ x ≦ 1, 0 <y ≦ 1) and a first GaP layer are formed in this order by metal organic vapor phase epitaxy, and the first GaP A second GaP layer is formed on the layer by hydride vapor phase epitaxy, and the second GaP layer is a GaP high-speed growth layer located on the side close to the light emitting layer portion and a GaP low-speed growth layer following the GaP high-speed growth layer. Ri Do from the growth layer,
A compound semiconductor epitaxial wafer characterized in that pits are not formed in the GaP high-speed growth layer . Wherein not more than 350μm thickness 250μm or more GaAs single crystal substrate, said compound semiconductor epitaxial wafer according to claim 1 0, wherein the total thickness of the first GaP layer and the second GaP layer is 100μm or more 250μm or less. Compound semiconductor epitaxial wafer according to claim 1 0 or claim 1 1, wherein the thickness of the GaP high-rate growth layer is 50μm or more. Compound semiconductor epitaxial wafer according to claim 1 2, wherein the thickness of the GaP low-rate growth layer is 5μm or more 49μm or less. The compound semiconductor epitaxial wafer according to any one of GaP low-rate growth layer surface polished surface and has been has claim 1 0 to claims 1 to 3. Produced by compound semiconductor epitaxial wafer electrode formed on the dicing according to any one of claims 1 0 to Claim 1 4, the GaAs single crystal substrate, comprising two or more Group III elements (AlxGa1 -X) A light emitting layer portion formed by metal organic vapor phase epitaxy composed of yIn1-yP (where 0 ≦ x ≦ 1, 0 <y ≦ 1), and formed by metal organic vapor phase epitaxy. The first GaP layer and the second GaP layer formed by the hydride vapor phase growth method are stacked in this order, and the second GaP layer is located on the side closer to the light emitting layer portion. And a GaP slow growth layer following the GaP fast growth layer.

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