JP5239905B2 - High frequency amplifier - Google Patents

Description

  The present invention relates to a high frequency amplifier.

In recent years, it has been desired to increase the output of a high-frequency amplifier in applications such as radar and satellite communications.
For this reason, there is a high-frequency amplifier that achieves high output by connecting a plurality of transistors in parallel.
In such a high frequency amplifier, a signal input from an input port is distributed to a plurality of transistors by a distribution circuit, and signals amplified by each of the plurality of transistors are combined by a combining circuit and output from the output port. ing.

However, in such a high-frequency amplifier, the reverse transfer characteristic (isolation) of the transistor is not sufficient.
Further, the characteristics (particularly phase characteristics) of each transistor and the characteristics of the transmission line (matching circuit) vary.
For this reason, an unbalanced mode (odd mode) occurs in the loop circuit formed by connecting the distribution circuit and the synthesis circuit via a plurality of transistors, and loop oscillation occurs depending on the oscillation conditions in the loop circuit. Note that loop oscillation is also referred to as odd-mode oscillation (oscillation in which transistors on the loop operate in opposite phases).

Therefore, there is an apparatus in which an isolator is provided between the transistor and the transmission line to improve isolation and suppress loop oscillation.
In addition, a resistor is provided in parallel in the loop so that the loop oscillation power is absorbed by the resistor so as to suppress the loop oscillation and stabilize the operation of the amplifier.

JP 2002-185273 A Japanese Patent No. 3314245 JP 2001-148616 A

  However, in the case of using the above-described isolator, the size of the amplifier becomes large. Note that the isolator has a structure in which one of the three ports of a circulator using a magnetic material such as ferrite and a magnet is terminated, so that even the microstrip transmission line type is basically large in size. Moreover, it is difficult to obtain high isolation over a wide band. In this case, the size becomes larger when matched to the low frequency side.

Further, in the case where a resistor is provided in the above-described loop, when the size of the loop circuit is increased, the loop oscillation power cannot be effectively absorbed by the inductor such as the transmission line.
Therefore, it is desirable to reliably suppress loop oscillation while preventing the size from increasing.

Therefore, the high-frequency amplifier includes a distribution circuit that distributes the input signal, a plurality of transistors that amplify the signal distributed by the distribution circuit, a synthesis circuit that combines the signals amplified by the plurality of transistors, and a distribution circuit . Connected to the bent part of the transmission line that configures the input side phase adjustment line that adjusts the phase so that the signals input to each of the transistors are in phase, and to the bent part of the transmission line that constitutes the composite circuit And an output-side phase adjustment line that adjusts the phase so that the unbalanced mode generated in the loop circuit formed by connecting the distribution circuit and the synthesis circuit via the plurality of transistors becomes the balanced mode. Is a requirement.

  Therefore, according to the present high frequency amplifier, there is an advantage that the loop oscillation can be surely suppressed while the size is not increased.

1 is a schematic plan view showing a configuration of a high-frequency amplifier according to a first embodiment. It is a figure which shows the structure of the high frequency amplifier concerning 1st Embodiment. (A), (B) is a figure for demonstrating the effect | action of the phase adjustment line provided in the high frequency amplifier concerning 1st Embodiment. (A), (B) is a figure for demonstrating the effect | action of the phase adjustment line provided in the high frequency amplifier concerning 1st Embodiment. It is a figure for demonstrating the effect | action and effect of the phase adjustment line provided in the high frequency amplifier concerning 1st Embodiment. FIG. 6 is a schematic plan view showing a configuration of a high-frequency amplifier according to a modified example of the first embodiment. It is a typical top view which shows the structure of the high frequency amplifier concerning 2nd Embodiment. It is a typical top view which shows the structure of the high frequency amplifier concerning 3rd Embodiment. It is a typical top view which shows the structure of the high frequency amplifier concerning 4th Embodiment.

Hereinafter, the high frequency amplifier according to the present embodiment will be described with reference to the drawings.
[First Embodiment]
First, the high-frequency amplifier according to the first embodiment will be described with reference to FIGS.
The high-frequency amplifier according to the present embodiment is a high-power amplifier that realizes high output by providing a plurality of transistors (amplifiers) in parallel and synthesizing outputs from these transistors.

  As shown in FIG. 1, the high-frequency amplifier includes a distribution circuit 12 that distributes an input signal (high-frequency signal; high-frequency power), a plurality of transistors 15 that amplify signals distributed by the distribution circuit 12, and a plurality of transistors 15. And a synthesizing circuit 16 for synthesizing the signals amplified by the above. Note that FIG. 1 illustrates a circuit configuration (planar circuit pattern) in the case where two transistors 15 are provided and outputs from these transistors 15 are combined (two combined).

Here, the transistor 15 is a field effect transistor (FET) such as GaN-HEMT.
In the present embodiment, the transistor 15 is an FET chip (four-cell synthesis chip) including four FETs (cells).
Each FET chip 15 is wire-bonded to an input-side conductor pad 18 connected to the distribution circuit 12 and an output-side conductor pad 19 connected to the synthesis circuit 16. That is, each FET chip 15 is connected to the distribution circuit 12 via the input-side conductor pad 18 and is connected to the synthesis circuit 16 via the output-side conductor pad 19.

Specifically, the gate of each FET cell 15 is connected to the input-side conductor pad 18 by a wire 13A. The source of each FET cell 15 is connected to the ground terminal 14 by a wire 13B. Furthermore, the drain of each FET cell 15 is connected to the conductor pad 19 on the output side by a wire 13C.
Further, the circuit patterns of the distribution circuit 12 and the synthesis circuit 16 and the input and output side conductor pads 18 and 19 are formed on a low loss dielectric substrate 10 such as alumina by a good conductor such as Au, Ag and Cu. Is formed.

Here, the source of each FET cell 15 is connected to the ground terminal 14, but is not limited to this. For example, instead of the ground terminal 14, the chip is included in the source pattern of the FET chip 15. A via hole connected to the conductor (ground) on the back side of the substrate may be provided.
In such a high-frequency amplifier, a signal is input from an input side terminal (input port; Port 1) 11, distributed to two FET chips 15 by a distribution circuit 12, and input to each of the two FET chips 15. A signal amplified by each of the two FET chips 15 and output from each FET chip 15 is combined by a combining circuit 16 and output from a terminal (output port; Port 2) 17 on the output side. .

In general, the characteristic impedance Z ₁ (see FIG. 2) of the input / output circuit connected to such a high-frequency amplifier is standardized to 50Ω.
For this reason, impedance conversion is performed using the input-side conductor pad 18, the output-side conductor pad 19, the distribution circuit 12, and the synthesis circuit 16 so as to match the input / output impedance of the FET chip 15.

That is, the impedance matching circuit is configured by the input side conductor pad 18, the output side conductor pad 19, the distribution circuit 12, and the synthesis circuit 16. Therefore, as shown in FIG. 2, the characteristic impedance Z ₀ of each transmission line 1 including the distribution circuit 12 and the input-side conductor pad 18 is 70.71Ω, and includes the synthesis circuit 16 and the output-side conductor pad 19. The characteristic impedance Z ₀ of each transmission line 2 is 70.71Ω. The length of each transmission line 1 consisting of distribution circuit 12 and the input side of the conductor pad 18 is lambda _0/4, the phase is so shifted 90 degrees. Similarly, the length of each transmission line 2 formed of a synthetic circuit 16 and the output side of the conductor pad 19 is also lambda _0/4, the phase is so shifted 90 degrees. Note that λ ₀ is the wavelength (operating wavelength) of the input signal.

Here, the characteristic impedance Z ₀ of each transmission line 1, 2 is set to 70.71 Ω, but this means that the characteristic impedance (impedance of the input / output port) Z ₁ of the input / output circuit is 50 Ω, and the input / output of the transistor This is an optimum characteristic impedance value when the impedance (or impedance at points A, B, C, and D in FIG. 2) is 50Ω. However, in the case of a high-power amplifier, since the input / output impedance of the transistor is lower than 50Ω, the input / output impedance of the transistor is Ztr, and the characteristic impedance Z ₀ of each transmission line 1 and 2 is √ (2 × Ztr × 50). It is desirable to do. In FIG. 2, an impedance converter may be provided between each of the points A, B, C, and D and the transistor.

  By the way, in such a high frequency amplifier, the characteristics (particularly phase characteristics) of each transistor 15 and the characteristics (particularly phase characteristics) of the transmission lines 1 and 2 vary. For this reason, an unbalanced mode occurs in the loop circuit (closed loop circuit) formed by connecting the distribution circuit 12 and the synthesis circuit 16 via the two transistors 15, and loop oscillation occurs due to the oscillation conditions in the loop circuit. (See FIG. 5).

Therefore, in this embodiment, as shown in FIGS. 1 and 2, the input-side phase adjustment line 6 is connected to the distribution circuit 12, and the output-side phase adjustment line 7 is connected to the synthesis circuit 16.
Here, the input-side phase adjustment line 6 adjusts the phase so that signals input to the two transistors 15 are in phase. That is, the input side phase adjustment line 6 adjusts the phase so that the phase shift of the signal input to each transistor 15 becomes zero.

The output-side phase adjustment line 7 adjusts the phase so that the unbalanced mode generated in the loop circuit formed by connecting the distribution circuit 12 and the combining circuit 16 via the two transistors 15 becomes the balanced mode. To be adjusted. That is, the output-side phase adjustment line 7 shifts the phase of the unbalanced mode generated in the loop circuit to the balanced mode.
By providing such an input side phase adjustment line 6 and an output side phase adjustment line 7, loop oscillation can be suppressed and excessive amplification can be prevented. In addition, at the frequency f ₀ to be amplified, variations in characteristics (particularly phase characteristics) of the transistor 15 can be adjusted, and distribution / combination loss can be reduced.

Next, the effect | action by a phase adjustment track | line is demonstrated, referring FIG. 3, FIG.
Here, it has a characteristic impedance of 50Ω that matches the characteristic impedance (50Ω) of the input / output circuit connected to the input port (Port 1) and the output port (Port 2), and the phase of the output signal with respect to the phase of the input signal at 10 GHz. A case where a transmission line deviating by −90 degrees is formed will be described as an example.

Despite attempts to form the transmission line as described above, the phase shift amount of the transmission line is not as designed, and the phase is shifted by only −80 degrees as shown in FIGS. 3 (A) and 3 (B). There is no time. In such a case, loop oscillation will occur.
Here, in FIG. 3B, a solid line A indicates an S parameter indicating a transmission characteristic between the input port (Port 1) and the output port (Port 2) when the frequency is changed from 100.0 MHz to 20.00 GHz. [S (2, 1) = pass characteristic amplitude / phase characteristic]. When the frequency is 10 GHz, the S parameter is a point m7 in FIG. 3B, and S (2,1) = 1.000 / −80.000. This indicates that there is no loss at 10 GHz, but the phase is shifted by -80 degrees.

In this case, as shown in FIG. 4A, a phase adjustment line having a characteristic impedance of 50Ω and having a phase of the output signal shifted by −20 degrees with respect to the phase of the input signal at 10 GHz is connected.
As a result, the phase of the output signal can be shifted by −90 degrees with respect to the phase of the input signal at 10 GHz.
Here, in FIG. 4B, a solid line A indicates an S parameter indicating transmission characteristics between the input port (Port 1) and the output port (Port 2) when the frequency is changed from 100.0 MHz to 20.00 GHz. [S (2, 1) = pass characteristic amplitude / phase characteristic]. When the frequency is 10 GHz, the S parameter is a point m7 in FIG. 4B, and S (2,1) = 0.984 / −90.314. That is, although there is a slight loss at 10 GHz, the phase is shifted by −90 degrees.

In this way, when the transmission line is not designed and loop oscillation occurs, a phase adjustment line is provided to set the phase shift amount of the output signal phase with respect to the input signal phase as designed. can do.
In this embodiment, as shown in FIGS. 1 and 2, the input-side phase adjustment line 6 and the output-side phase adjustment line 7 are provided so as to be positioned on one diagonal line of the loop circuit. That is, the input-side phase adjustment line 6 and the output-side phase adjustment line 7 are provided at positions that are asymmetric with respect to the line connecting the input terminal (Port 1) 11 and the output terminal (Port 2) 17, and the input / output side As a result, the structure is asymmetric. For this reason, it is not necessary to consider the direction of the substrate, so that mounting is facilitated.

  In addition, the position which provides the input side phase adjustment track | line 6 and the output side phase adjustment track | line 7 is not restricted to this. For example, the input-side phase adjustment line 6 and the output-side phase adjustment line 7 may be provided so as to be located on another diagonal line of the loop circuit as shown by a dotted line in FIG. Further, for example, the input-side phase adjustment line 6 and the output-side phase adjustment line 7 may be provided so as to be positioned at four locations on both diagonal lines of the loop circuit as shown by a solid line and a dotted line in FIG. Further, for example, the input-side phase adjustment line 6 and the output-side phase adjustment line 7 are positioned at two locations on one side (the lower side in FIG. 2) of the loop circuit as shown by a solid line and a dotted line in FIG. You may provide so that it may be provided, and you may provide so that it may be located in two places on the other side (upper side in FIG. 2) of a loop circuit. In these cases, the same operation and effect as in the above-described embodiment can be obtained.

Furthermore, in this embodiment, as shown in FIGS. 1 and 2, resistance circuits 3A and 3B are connected in the vicinity of each transistor 15 so that current flows into the resistors 4A and 4B (resistance value R) and is absorbed. Thus, the loop oscillation can be more reliably suppressed.
Specifically, the input-side resistor 4A is connected to the input side of each transistor 15 through the transmission line 5A so that the connection point with the distribution circuit 12 (point A and point C in FIG. 2) is short-circuited. . Further, the output-side resistor 4B is connected to the output side of the plurality of transistors 15 via the transmission line 5B so that the connection points (points B and D in FIG. 2) with the synthesis circuit 16 are short-circuited. Thereby, the unbalanced mode generated in the loop circuit can be absorbed by the resistors 4A and 4B, and the loop oscillation can be suppressed.

On the other hand, without providing the above-described input side phase adjustment line 6 and output side phase adjustment line 7, resistance circuits 3A and 3B are connected in the vicinity of each transistor 15 as shown in FIG. It is conceivable to suppress the loop oscillation by flowing into the resistors 4A and 4B (resistance value R) via 5B and absorbing them.
However, when the transmission lines 5A and 5B for connecting the resistors 4A and 4B are not as designed, or when the distance between A and C or between B and D is large, the points A, B, C, D May not be a short point. In this case, loop oscillation cannot be suppressed.

Even in such a case, loop oscillation can be suppressed by providing the input side phase adjustment line 6 and the output side phase adjustment line 7 described above.
In this embodiment, the resistors 4A and 4B are connected to the distribution circuit 12 and the synthesis circuit 16 via the transmission lines 5A and 5B, respectively, but the present invention is not limited to this, and the resistors 4A and 4B are not limited thereto. May not be connected. In this case as well, loop oscillation caused by variations in the characteristics of the transistors 15 and the characteristics of the transmission lines 1 and 2 can be suppressed.

  By the way, in this embodiment, as shown in FIG. 1, the input-side phase adjustment line 6 is provided between the plurality of conductor pads 20 and the distribution circuit 12 and all or part of the plurality of conductor pads 20. Are constituted by conductors 21 and 22 that connect each other. That is, the conductors 21 and 22 connect the conductor pads 20 closest to the distribution circuit 12 among the plurality of conductor pads 20 and the distribution circuit 12 and between all or some of the plurality of conductor pads 20. By doing so, the input side phase adjustment line 6 is formed.

  Specifically, as the plurality of conductor pads 20, three rectangular conductor pads 20 are provided in parallel. That is, the three rectangular conductor pads 20 are arranged in a row so that their long sides are opposed to each other so as to be connected to one transmission line (lower side in FIG. 1) constituting the distribution circuit 12. The conductor pad 20 is formed of a good conductor such as Au, Ag, or Cu on the low-loss dielectric substrate 10 such as alumina.

Then, between one transmission line constituting the distribution circuit 12 and the conductor pad 20 closest to the transmission line, and part of the three conductor pads 20 (here, two on the distribution circuit 12 side) The two are connected by a wire 21 (wire bonding).
Further, the conductor pads 20 of a part of the three conductor pads 20 (here, two on the side far from the distribution circuit 12) are connected to each other by a conductor paste 22 (for example, a conductive paste such as Ag; a good electrical conductor paste). ing.

  Here, the input side phase adjustment line 6 is formed by connecting all the conductor pads 20 of the three conductor pads 20 by the conductors 21 and 22, but the present invention is not limited to this. . The length of the input-side phase adjustment line 6 can be arbitrarily set depending on which conductor pad 20 is connected to the distribution circuit 12, and a plurality of (here, two) transistors can be adjusted by adjusting this length. The phase can be adjusted so that the signals input to each of the signals 15 are in phase. For this reason, it is easy to perform phase adjustment. The conductor pad 20 connected to the distribution circuit 12 functions as the input side phase adjustment line (stub) 6, and the conductor pad 20 not connected does not function as the input side phase adjustment line 6.

  Similarly, the output-side phase adjustment line 7 is configured by a plurality of conductor pads 20 and a conductor 21 that connects between the synthesis circuit 16 and all or some of the plurality of conductor pads 20. Is done. That is, the conductor 21 connects the conductor pad 20 closest to the composite circuit 16 among the plurality of conductor pads 20 and the composite circuit 16 and all or some of the plurality of conductor pads 20 by the conductor 21. Thus, the output-side phase adjustment line 7 is formed.

  Specifically, as the plurality of conductor pads 20, three rectangular conductor pads 20 are provided in parallel. That is, the three rectangular conductor pads 20 are arranged in a row so that their long sides are opposed to each other so as to be connected to one transmission line (upper side in FIG. 1) constituting the synthesis circuit 16. The conductor pad 20 is formed of a good conductor such as Au, Ag, or Cu on the low-loss dielectric substrate 10 such as alumina.

And between one transmission line which comprises the synthetic | combination circuit 16, and the conductor pad 20 nearest to this, and a part of three conductor pads 20 (here two on the synthetic circuit 16 side) of the conductor pads 20 The two are connected by a wire 21 (wire bonding).
Here, the output-side phase adjustment line 7 is formed by connecting the conductor pads 20 of some of the three conductor pads 20 with the conductors 21, but the present invention is not limited to this. The length of the output-side phase adjustment line 7 can be arbitrarily set depending on which conductor pad 20 is connected to the synthesis circuit 16, and by adjusting this length, a plurality of (here, two) transistors can be set. The phase can be adjusted so that the unbalanced mode generated in the loop circuit formed by connecting the distribution circuit 12 and the combining circuit 16 via 15 becomes the balanced mode. For this reason, it is easy to perform phase adjustment. The conductor pad 20 connected to the synthesis circuit 16 functions as the output side phase adjustment line (stub) 7, and the conductor pad 20 not connected does not function as the output side phase adjustment line 7.

  The distribution circuit 12 or the synthesis circuit 16 and all or some of the plurality of conductor pads 20 may be connected by a conductor, for example, by wire bonding alone. They may be connected using only the conductive paste, or may be connected in any combination. For example, instead of wire bonding or conductor paste, a resistor (sheet resistor) made of a conductor may be used. Thereby, the loop oscillation power can be effectively absorbed.

Therefore, the high frequency amplifier according to the present embodiment has an advantage that the loop oscillation can be surely suppressed while the size is not increased.
For example, the input side phase adjustment line 6 and the output side phase adjustment line 7 may be formed on the same substrate as the substrate 10 on which the distribution circuit 12 and the synthesis circuit 16 are formed without using an isolator. A high-power amplifier can be realized while reducing cost and size.

In the above-described embodiment and modification, the conductor pads 20 constituting the input-side phase adjustment line 6 and the output-side phase adjustment line 7 are located on either one of the loop circuit or on another diagonal line. However, the present invention is not limited to this.
For example, as shown in FIG. 6, conductor pads 20 are provided on both diagonal lines of the loop circuit, and only the conductor pads 20 on either one of the diagonal lines are connected by conductors 21 and 22, so that the input side phase adjustment line 6 and the output-side phase adjustment line 7 may be configured. In this case, the conductor pad 20 is provided in a symmetrical position with respect to a line connecting the input terminal 11 and the output terminal 17 and has a symmetrical structure. On the other hand, the input-side phase adjustment line 6 and the output-side phase adjustment line 7 formed by connecting the conductor pad 20 with the conductors 21 and 22 are connected to the line connecting the input terminal 11 and the output terminal 17. It is provided at an asymmetrical position and becomes an asymmetrical structure. In this case, the conductor pad 20 that is not connected by the conductors 21 and 22 does not function as a transmission line (stub). Moreover, in FIG. 6, the same code | symbol is attached | subjected to the same thing as the above-mentioned embodiment (refer FIG. 1). Further, FIG. 6 shows a configuration example when the resistance circuits 3A and 3B including the transmission lines 5A and 5B and the resistors 4A and 4B are not provided.

Further, in the above-described embodiments and modifications, for example, as shown by a dotted line in FIGS. 1 and 6, the resistor is connected to the tip of the input side phase adjustment line 6 (or the output side phase adjustment line 7). (For example, a thin film resistor; a sheet resistor) 8 may be provided to absorb the loop resonance power.
[Second Embodiment]
Next, a high frequency amplifier according to a second embodiment will be described with reference to FIG.

The high-frequency amplifier according to this embodiment is different from the first embodiment in the configuration of the input-side phase adjustment line 6 and the output-side phase adjustment line 7.
That is, in this high frequency amplifier, as shown in FIG. 7, the input side phase adjustment line 6 and the output side phase adjustment line 7 are open stubs (λ //) having a length L that is ¼ of the resonance wavelength λ of the loop circuit. 4 open stubs) 23. In FIG. 7, the same components as those in the first embodiment described above [see FIG. 1] are denoted by the same reference numerals.

  In this case, it is necessary to obtain the resonance wavelength λ of the loop circuit in advance. The input-side phase adjustment line 6 and the output-side phase adjustment line 7 have a length L that is ¼ of the resonance wavelength λ of the loop circuit and are open-ended transmission lines (stubs). As a result, at the connection point between the input phase adjustment line 6 and the distribution circuit 12 and the connection point between the output phase adjustment line 7 and the synthesis circuit 16 with respect to the oscillation frequency of the loop oscillation corresponding to the resonance wavelength of the loop circuit. Since this is equivalent to a short circuit, loop oscillation can be further suppressed.

Since other details are the same as those in the first embodiment, the description thereof is omitted here. FIG. 7 shows a configuration example in the case where the resistance circuits 3A and 3B including the transmission lines 5A and 5B and the resistors 4A and 4B are not provided.
Therefore, the high-frequency amplifier according to the present embodiment has an advantage that the loop oscillation can be surely suppressed while preventing the size from increasing as in the case of the first embodiment described above.

In the above-described embodiment, for example, as shown by a dotted line in FIG. 7, the resistor 8 (for example, a thin film resistor) is connected to the tip of the input side phase adjustment line 6 (or the output side phase adjustment line 7). A sheet resistor) may be provided to absorb the loop resonance power.
In the above-described embodiment, the input-side phase adjustment line 6 and the output-side phase adjustment line 7 are λ / 4 open stubs 23, but the present invention is not limited to this.

For example, as shown in FIG. 8, a short stub (λ / 2 short stub) 24 having a length L1 that is ½ of the resonance wavelength λ of the loop circuit is connected to the input side phase adjustment line 6 and the output side phase adjustment line 7. It is also good. In FIG. 8, the same components as those in the above-described embodiment [see FIG. 7] are denoted by the same reference numerals.
In this case, it is necessary to obtain the resonance wavelength λ of the loop circuit in advance as in the case of the above-described embodiment. The input-side phase adjustment line 6 and the output-side phase adjustment line 7 have a length L1 that is ½ of the resonance wavelength λ of the loop circuit, and a short-circuited transmission line (stub) whose tip is connected to the ground. And Thereby, loop oscillation can be further suppressed.

  Further, as shown in FIG. 8, a capacitor (chip capacitor) 25 that determines the capacitance between the λ / 2 short stub 24 and the ground is provided between the λ / 2 short stub 24 and the ground (substrate back side). Is preferred. In this case, a resistor (sheet resistor; not shown) is provided between the λ / 2 short stub 24 and the ground (for example, between the capacitor 25 and the ground) so that the loop resonance power is absorbed. Is preferred. Thereby, for example, even when the ground has an elongated shape, loop oscillation through the ground can be suppressed. Furthermore, since the λ / 2 short stub 24 tends to be long, it is preferable to reduce the size by forming a meander shape or a spiral shape.

Further, the input-side phase adjustment line 6 and the output-side phase adjustment line 7 need not be the λ / 4 open stub 23 or the λ / 2 short stub 24 as described above. For example, as the input-side phase adjustment line 6, a transmission line (stub) having a length capable of adjusting the phase so that signals input to each of the plurality of transistors 15 are in phase may be formed. Further, as the output side phase adjustment line 7, the phase is adjusted so that the unbalanced mode generated in the loop circuit formed by connecting the distribution circuit 12 and the synthesis circuit 16 through the plurality of transistors 15 becomes the balanced mode. What is necessary is just to form the transmission line (stub) which has the length which can adjust.
[Third Embodiment]
Next, a high frequency amplifier according to a third embodiment will be described with reference to FIG.

  The high-frequency amplifier according to the first embodiment described above includes two transistors 15, distributes signals to these transistors 15 (two distributions), and combines outputs from these transistors 15 (two combinations). In contrast, the high-frequency amplifier according to the present embodiment includes a plurality of (here, four) transistors 15, and distributes signals to these transistors 15 (multi-distribution; here, four distributions). Is different in that the output is synthesized (multiple synthesis; here, four synthesis).

In other words, as shown in FIG. 9, this high-frequency amplifier has two configurations of the above-described first embodiment (see FIG. 1), and these are connected in parallel by another distribution circuit 26 and another synthesis circuit 27. I am doing so. Thereby, higher output can be achieved. In FIG. 9, the same components as those in the first embodiment (see FIG. 1) are denoted by the same reference numerals.
For this reason, in this high frequency amplifier, another distribution circuit 26 (including the input terminal 28) is connected to the input terminal 11 of the distribution circuit 12 constituting the high frequency amplifier of the first embodiment described above. Further, another synthesis circuit 27 (including the output terminal 29) is connected to the output terminal 17 of the synthesis circuit 16 constituting the high frequency amplifier of the first embodiment. That is, the high frequency amplifier includes a plurality of distribution circuits 12 and 26 as distribution circuits and a plurality of combination circuits 16 and 27 as combination circuits.

An input side phase adjustment line 6 is provided in each of the plurality of distribution circuits 12 and 26. Further, the output-side phase adjustment line 7 is provided in each of the plurality of synthesis circuits 16 and 27.
In this case, three loop circuits are formed as a loop circuit formed by connecting the distribution circuits 12 and 26 and the synthesis circuits 16 and 27 through a plurality of (here, four) transistors 15. Become. For this reason, the input-side phase adjustment line 6 and the output-side phase adjustment line 7 are provided in each loop circuit so as to be positioned on the diagonal line of each loop circuit. Thereby, loop oscillation in each loop circuit can be suppressed.

Here, the outer large loop circuit has a lower oscillation frequency of the loop oscillation than the inner small loop circuit. In general, a transistor (amplifier) used in a high-frequency amplifier has a large gain at a low frequency, and therefore, a loop circuit is more likely to occur in the outer large loop circuit.
For this reason, the lengths of the input-side phase adjustment line 6 and the output-side phase adjustment line 7 provided in the other distribution circuit 26 and the other synthesis circuit 27 first so that no loop oscillation occurs in the outer large loop circuit. Will be adjusted. After that, the lengths of the input-side phase adjustment line 6 and the output-side phase adjustment line 7 provided in the distribution circuit 12 and the synthesis circuit 16 of the small loop circuit inside are adjusted. In such an adjustment stage, it is possible to specify in which loop circuit the loop oscillation is occurring. Thereby, for example, it can be seen that there are variations in the characteristics of the transistors, and it is possible to take measures such as replacing the transistors.

Since other details are the same as those in the first embodiment, the description thereof is omitted here.
Therefore, the high-frequency amplifier according to the present embodiment has an advantage that the loop oscillation can be surely suppressed while preventing the size from increasing as in the case of the first embodiment described above.

  In the above-described embodiment, the high frequency amplifier includes four transistors 15, distributes signals to these transistors 15 (4 distributions), and synthesizes the outputs from these transistors 15 (4 combinations). However, it is not limited to this. For example, the present invention can be widely applied to a high-frequency amplifier that includes a plurality of transistors, distributes signals to these transistors (multi-distribution), and synthesizes (multi-synthesizes) outputs from these transistors.

In addition, although the above-described embodiment has been described as a modification of the above-described first embodiment, the present invention is not limited to this, and for example, a modification of the above-described second embodiment or the above-described third embodiment. It can also be configured as a modified example.
[Others]
In the first embodiment, the second embodiment, and the third embodiment described above, the description is made independently. However, the configurations of these embodiments may be arbitrarily combined. That is, for example, in the configuration of the above-described first embodiment, any one of the input-side phase adjustment line 6 and the output-side phase adjustment line 7 is replaced with the configuration of the above-described second embodiment or the above-described third embodiment. You may replace with the structure of. Further, for example, in the configuration of the above-described second embodiment, any one of the input-side phase adjustment line 6 and the output-side phase adjustment line 7 may be replaced with the configuration of the above-described third embodiment.

  In each of the above-described embodiments, the case where an FET is used as the transistor 15 has been described as an example. However, the present invention is not limited to this. The present invention can be applied even when other transistors are used. That is, the present invention can be applied even when an HBT chip (semiconductor chip) is used instead of the FET chip.

  Note that the present invention is not limited to the configurations described in the above-described embodiments and modifications, and various modifications can be made without departing from the spirit of the present invention.

DESCRIPTION OF SYMBOLS 1, 2 Transmission line 3A, 3B Resistance circuit 4A, 4B Resistance 5A, 5B Transmission line 6 Input side phase adjustment line 7 Output side phase adjustment line 8 Resistor 10 Dielectric substrate 11 Input terminal (input port)
12 distribution circuit 13A, 13B, 13C wire 14 ground terminal 15 transistor 16 synthesis circuit 17 output terminal (output port)
18 Input side conductor pad 19 Output side conductor pad 20 Conductor pad 21 Wire (conductor)
22 Conductor paste (conductor)
23 Open stub (λ / 4 open stub)
24 short stub (λ / 2 short stub)
25 capacitors (chip capacitors)
26 Other distribution circuits 27 Other synthesis circuits 28 Input terminals 29 Output terminals

Claims (4)

A distribution circuit for distributing the input signal;
A plurality of transistors for amplifying signals distributed by the distribution circuit;
A synthesis circuit for synthesizing signals amplified by the plurality of transistors;
An input-side phase adjustment line that is connected to a bent portion of the transmission line constituting the distribution circuit and adjusts the phase so that signals input to each of the plurality of transistors are in phase,
An unbalanced mode generated in a loop circuit formed by connecting the distribution circuit and the combining circuit through the plurality of transistors and connected to a bent portion of the transmission line constituting the combining circuit is changed to a balanced mode. A high-frequency amplifier comprising: an output-side phase adjustment line that adjusts the phase so that The input-side phase adjustment line or the output-side phase adjustment line connects between a plurality of conductor pads and the distribution circuit or the synthesis circuit and between all or some of the plurality of conductor pads. The high-frequency amplifier according to claim 1, wherein the high-frequency amplifier is configured by a conductive conductor . An input-side resistor connected to the input side of the plurality of transistors via a transmission line so that a connection point with the distribution circuit is short-circuited;
The output side of the plurality of transistors, the connection point between the combining circuit is characterized in that an output-side resistor and the connected via a transmission line so as to short-circuit, according to claim 1 or 2 High frequency amplifier. The distribution circuit is a plurality of distribution circuits;
The synthesis circuit is a plurality of synthesis circuits;
The input side phase adjustment line is provided in each of the plurality of distribution circuits,
The output-side phase adjusting line is characterized in that provided in each of said plurality of combining circuits, according to any one of claims 1 to 3 high-frequency amplifier.

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