JP5238125B2 - Method for manufacturing semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device constituting various circuits and a manufacturing method thereof.

Since a conventional thin film transistor (hereinafter referred to as TFT) is composed of an amorphous semiconductor film, it is almost impossible to obtain a TFT having a field effect mobility of 10 cm ² / V · Sec or more. It was. However, TFTs composed of crystalline semiconductor films have appeared, and it has become possible to realize TFTs with high field effect mobility.

Since a TFT of a crystalline semiconductor film has high field effect mobility, various functional circuits can be manufactured over the same substrate using the TFT. For example, in a display device, a driver IC or the like was previously mounted on a display portion as a drive circuit, but a display portion, a shift register circuit, and a level shifter circuit are formed on the same substrate by using a TFT of a crystalline semiconductor film. In addition, it is possible to arrange a drive circuit including a buffer circuit, a sampling circuit, and the like. The drive circuit is formed on the basis of a CMOS circuit composed of an n-channel TFT and a p-channel TFT.

In order to form various circuits on the same substrate, it is necessary to form TFTs corresponding to each circuit. This is because the operating conditions are not necessarily the same between the TFT of the pixel portion and the TFT of the driver circuit in terms of a display device, and the characteristics required for the TFT are also different. A pixel TFT composed of an n-channel TFT is driven by applying a voltage to a liquid crystal as a switching element. The pixel TFT is required to have a sufficiently low off-current value in order to hold the charge accumulated in the liquid crystal layer during one frame period. On the other hand, since a high drive voltage is applied to the buffer circuit of the drive circuit, it is necessary to increase the breakdown voltage so that the element is not broken even when a high voltage is applied. Further, it is necessary to secure a sufficient on-current value in order to increase the on-current driving capability.

As a structure of a TFT for reducing the off-current value, there is a structure in which a low concentration drain region (hereinafter also referred to as an LDD (Light Doped Drain) region) is provided. In this structure, a region to which an impurity element is added at a low concentration is provided between a channel formation region and a source or drain region to which an impurity element is added at a high concentration. As a means for preventing the deterioration of the on-current value due to hot carriers, there is a so-called GOLD (Gate-drain Overlapped LDD) structure in which an LDD region is disposed so as to overlap with a gate electrode through a gate insulating film. With such a structure, a high electric field in the vicinity of the drain is relieved, and deterioration of the on-current value due to hot carriers can be reduced. Note that a region where the LDD region is not disposed so as to overlap the gate electrode through the gate insulating film is also referred to as a Loff region, and a region where the LDD region is disposed is also referred to as a Lov region.

Here, the Loff region has a high effect of suppressing the off-current value, but has a low effect of relaxing the electric field in the vicinity of the drain and preventing the deterioration of the on-current value due to hot carriers. On the other hand, the Lov region relaxes the electric field near the drain and is effective in preventing deterioration of the on-current value, but has a low effect of suppressing the off-current value. Therefore, it is necessary to manufacture a TFT having a structure corresponding to a required characteristic for each of various circuits.

As one method for simultaneously manufacturing TFTs having various structures on the same substrate, a so-called hat-shaped two-layer gate electrode in which the gate length of the lower layer is longer than the gate length of the upper layer is used. There is one in which a plurality of TFTs having an LDD region are manufactured at the same time (for example, see Patent Document 1). FIG. 18 shows a manufacturing method thereof.

First, a base insulating film 2, a semiconductor film 3, a gate insulating film 4, a first conductive film 5 serving as a gate electrode, and a second conductive film 6 serving as a gate electrode are sequentially stacked on the substrate 1, and the second A mask 7 made of a resist is formed over the conductive film (FIG. 18A). Next, the first conductive film and the second conductive film are etched by dry etching so that the sidewalls are inclined (tapered), and the gate electrodes 8 and 9 are formed (FIG. 18B). Subsequently, the gate electrode 9 is processed by anisotropic etching. As a result, a hat-shaped gate electrode having a hat-like cross section is formed (FIG. 18C). Thereafter, the impurity element is doped twice to form an LDD region 10a located under the gate electrode 8, a high-concentration impurity region 10b located at both ends of the semiconductor film in contact with the LDD region, and a channel formation region 10c. (FIG. 18D).
JP-A-2004-179330 (see FIGS. 5 to 8)

Currently, research on submicron TFTs is actively conducted. However, it has been difficult to form fine TFTs suitable for various circuits using the method of Patent Document 1. This is because it has been difficult to shorten the length of the LDD region in the gate length direction (also referred to as the channel length direction) (hereinafter referred to as the LDD length) to a desired value. As shown in FIG. 18, Patent Document 1 discloses a method of forming an LDD region 10a by etching a portion of the side surface of the gate electrode 9 that is tapered to form a hat-shaped gate electrode and doping. is there. Therefore, if the taper angle (θ) of the side surface of the gate electrode 9 shown in FIG. However, it is difficult to adjust the taper angle. Conversely, if θ = 90 °, the LDD region itself cannot be formed, and it is difficult to form an LDD length of a certain value or less.

If the LDD length could not be shortened, the length of the semiconductor film in the channel length direction could not be shortened, and it was inevitably impossible to form an LDD structure TFT having a size of a certain value or less.

In addition, the LDD region suppresses hot carriers and suppresses the short channel effect, but also functions as a resistance against on-current. Accordingly, each TFT has an optimum LDD length that suppresses hot carriers and the like and obtains a desired on-current. However, in the conventional method, the gate length and the length of the semiconductor film could be formed by submicron size by etching, but it was difficult to provide an LDD region having an LDD length suitable for those sizes. Therefore, it has been difficult to obtain submicron TFTs with good characteristics.

Further, when the gate length is shortened due to miniaturization, a short channel effect is likely to occur, so that the necessity for providing a Loff region is increased. Also, the Lov region contributes to the improvement of TFT reliability, and a TFT with better characteristics can be obtained. Therefore, it is highly necessary to provide an LDD region with a miniaturized TFT. In other words, even for miniaturized TFTs, it is necessary to develop a semiconductor device manufacturing method in which an LDD structure and a GOLD structure TFT having an LDD length suitable for each TFT are simultaneously formed, and various circuits are simultaneously manufactured on the same substrate. It was done.

In addition, from the viewpoint of manufacturing cost, there has been a demand for a method for manufacturing a semiconductor device in which TFTs suitable for each circuit are simultaneously manufactured by a process with a small number of steps.

In view of the above, an object of the present invention is to improve the operating characteristics and reliability of a semiconductor device by making the TFT structure suitable for various circuit functions even if the TFT is miniaturized. It is another object of the present invention to reduce the number of processes to reduce manufacturing costs and improve yield.

One feature of the present invention is that a gate insulating film, a first conductive film, and a second conductive film are sequentially formed over a semiconductor film over a substrate, a resist is formed over the second conductive film, and the resist is formed. A second conductive film etched by first etching is formed on the second conductive film as a mask, and a first gate electrode is formed by performing second etching on the first conductive film. Then, by performing the third etching, the resist is made to recede, and the etched second conductive film is etched using the receding resist as a mask so that the length in the channel length direction is larger than that of the second gate electrode. A short second gate electrode is formed.

One of the characteristics of the present invention is that the resist is retreated in the second etching.

One of the features of the present invention is that after the second gate electrode is formed, an impurity element is doped using the second gate electrode as a mask, so that the semiconductor film has a channel concentration region and a low concentration impurity region in contact with the channel formation region And sidewalls covering the side surfaces of the first gate electrode and the second gate electrode are formed, and an impurity element is doped using the sidewalls and the second gate electrode as a mask to selectively form the low concentration impurity region. Forming a high concentration impurity region.

One feature of the present invention is that doping is performed using the first gate electrode as a mask so that the low-concentration impurity region is formed under the first gate electrode portion that does not overlap the second gate electrode. It is formed so that it may be located through a film | membrane.

One feature of the present invention is that doping is performed using the first gate electrode as a mask, so that the high-concentration impurity region is formed in the semiconductor film portion that does not overlap the first gate electrode through the gate insulating film. Is Rukoto.

One of the features of the present invention is that the first low electrode positioned under the first gate electrode portion that does not overlap the second gate electrode by doping with the sidewall and the second gate electrode as a mask. A concentration impurity region and a second low concentration impurity region located under a sidewall portion in contact with the gate insulating film are formed. At this time, the sum of the widths of the first low-concentration impurity region and the second low-concentration impurity region in the channel length direction is equal to the width of the sidewall in the channel length direction. The width in the channel length direction of the first low-concentration impurity region is equal to the width in the channel length direction of the first gate electrode portion that does not overlap the second gate electrode.

One of the features of the present invention is that the first gate electrode is formed such that the taper angle θ of the side surface satisfies 80 ° ≦ θ ≦ 90 °. That is, the first gate electrode is formed to have a substantially vertical taper angle.

One of the features of the present invention is that the first conductive film is a TaN film. One of the features of the present invention is that the second conductive film is a W film. The first to third etchings are performed by a dry etching method.

The formation method of the hat-shaped gate electrode of the present invention is different from the formation method using the tapered portion of the first gate electrode in FIG. In the present invention, the gate length of the first gate electrode is etched to be smaller than the gate length of the second gate electrode by using the resist receding width at the time of etching, thereby forming a hat-shaped gate electrode. The resist receding width at the time of etching of the present invention is the resist receding width at the time of the third etching for etching the first gate electrode. Alternatively, since the resist may be etched at the same time during the second etching for forming the second gate electrode, the resist receding width is the sum of resist receding widths in the second and third etchings.

Further, various semiconductor devices having a Lov region or a Loff region can be formed over the same substrate by doping the semiconductor film with an impurity element using the above-described hat-shaped gate electrode formed in the present invention as a mask. It is characterized by.

Further, after the hat-shaped gate electrode is formed, a side wall common to the side surfaces of the second and third gate electrodes is formed so as to cover the side surfaces of both gate electrodes. A semiconductor device having both a Lov region and a Loff region is manufactured by doping an impurity element using the sidewall and the third gate electrode as a mask.

The taper angle of the side surface of the etched second conductive film formed during the first etching according to the present invention is 80 ° to 90 °.

One feature of the present invention is that a gate insulating film, a first conductive film, and a second conductive film are sequentially formed over a semiconductor film over a substrate, a resist is formed over the second conductive film, and the resist is formed. A second etched conductive film is formed by performing a first etching on the second conductive film as a mask, and an etched first conductive film is formed by performing a second etching on the first conductive film. The conductive film is formed and the third etching is performed to retract the resist, and the etched second conductive film is etched using the retracted resist as a mask, and the length in the channel length direction is etched. A first gate electrode shorter than the first conductive film is formed, an impurity element is doped using the first gate electrode as a mask, and the semiconductor film has a low concentration in contact with the channel formation region and the channel formation region. An impurity region is formed, an impurity element is doped using the etched first conductive film as a mask, a high concentration impurity region is selectively formed in the low concentration impurity region, and etching is performed using the first gate electrode as a mask. The first conductive film is etched to form a second gate electrode having a length in the channel length direction equal to that of the first gate electrode.

The LDD length of the LDD region of the present invention is 10 to 300 nm, preferably 50 nm to 200 nm. The channel length of the channel formation region of the present invention is in the range of 0.1 to 0.7 μm.

Note that in this specification, a hat-shaped gate electrode is a gate electrode having a stacked structure including at least two layers. The gate length of the lower gate electrode (length in the channel length direction) is longer than the gate length of the upper gate electrode (length in the channel length direction), and the thickness of the upper gate electrode is lower than that of the lower gate electrode. The gate electrode has a shape thicker than the thickness of the gate electrode. The lower gate electrode may have a wider cross section or a rectangular shape.

According to the present invention, a fine hat-shaped gate electrode can be formed, and an LDD region having an LDD length that has been difficult to achieve conventionally can be formed by doping an impurity element using the gate electrode as a mask. Therefore, even when miniaturized, a semiconductor device with good operation characteristics and high reliability can be realized, and a semiconductor device suitable for various circuits can be created. In addition, since a semiconductor device can be separately manufactured by a process with a small number of steps, manufacturing cost can be reduced and yield can be improved.

Further, a submicron TFT having a desired size can be formed without any lower limit, and the semiconductor device itself can be made very compact and lightweight. In addition, an LDD length suitable for each TFT can be designed, and a semiconductor device that can suppress a short channel effect, increase a breakdown voltage, and secure a desired on-current can be obtained.

Further, by forming a sidewall on the hat-shaped gate electrode and doping with an impurity element, a semiconductor device having both a Loff region and a Lov region and having high reliability and a short channel effect can be realized. .

By doping an impurity element using the hat-shaped gate electrode of the present invention as a mask, an LDD region having a very short LDD length of 10 to 300 nm, preferably 50 to 200 nm can be formed. In addition, in a fine TFT having a channel length of 0.1 to 0.7 μm, a TFT having an LDD region suitable for the TFT size can be formed.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention can be implemented in many different modes, and those skilled in the art can easily understand that the modes and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention should not be construed as being limited to the description of the embodiment modes.

Further, Embodiments 1 to 6 shown below can be freely combined within a practicable range.

(Embodiment 1)
A method for manufacturing the semiconductor device according to the first embodiment will be described below with reference to FIGS. The TFT used in the semiconductor device of this embodiment has an LDD region that is a Lov region or a Loff region.

First, the base insulating film 12 is formed to 100 to 300 nm on the substrate 11. As the substrate 11, a glass substrate, a quartz substrate, a plastic substrate, an insulating substrate such as a ceramic substrate, a metal substrate, a semiconductor substrate, or the like can be used.

The base insulating film 12 is an insulating film containing oxygen or nitrogen, such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x> y), silicon nitride oxide (SiNxOy) (x> y), or the like. A single layer structure or a stacked structure of these can be used. In particular, when there is a concern about contamination from the substrate, it is preferable to form a base insulating film.

The base insulating film 12 in contact with the semiconductor film is preferably a silicon nitride film or a silicon nitride oxide film with a thickness of 0.01 to 10 nm, preferably 1 to 3 nm. In a later crystallization process, when a method of adding a metal element to a semiconductor film to crystallize is used, it is necessary to getter the metal element. At this time, if the base insulating film is a silicon oxide film, a metal element in the silicon film reacts with oxygen in the silicon oxide film at the interface between the silicon oxide film and the silicon film of the semiconductor film to form a metal oxide. Thus, the metal element may be difficult to getter. Therefore, the base insulating film portion in contact with the semiconductor film is preferably a layer that is not a silicon oxide film.

Subsequently, a semiconductor film is formed to 10 to 100 nm. The material of the semiconductor film can be selected according to the characteristics required for the TFT, and may be any of a silicon film, a germanium film, and a silicon germanium film. As the semiconductor film, an amorphous semiconductor film or a microcrystalline semiconductor film is preferably used, and a crystalline semiconductor film crystallized by a laser crystallization method using an excimer laser or the like is preferably used. The microcrystalline semiconductor film can be obtained by glow discharge decomposition of a silicide gas such as SiH ₄ . By using the silicide gas diluted with hydrogen or a rare gas element of fluorine, the microcrystalline semiconductor film can be easily formed.

Further, as a crystallization technique, a rapid thermal annealing method (RTA method) using a halogen lamp or a technique for crystallization using a heating furnace can be applied. Further, a method may be used in which a metal element such as nickel is added to the amorphous semiconductor film and solid phase growth is performed using the added metal as a crystal nucleus.

Next, the semiconductor film is processed by etching to form an island-shaped semiconductor film 13. A gate insulating film 14 is formed to have a thickness of 10 to 200 nm, preferably 5 to 50 nm so as to cover the island-shaped semiconductor film 13.

As the gate insulating film 14, silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x> y), silicon nitride oxide (SiNxOy) (x> y), or the like is formed by CVD or sputtering. Any one of them may be appropriately combined to form a laminated structure. In this embodiment, the gate insulating film 14 has a stacked structure of a silicon nitride oxide film and a silicon oxynitride film.

Subsequently, a first conductive film 15 and a second conductive film 16 to be gate electrodes are formed on the gate insulating film 14. First, the first conductive film 15 is formed to 5 to 50 nm. As the first conductive film 15, an aluminum (Al) film, a copper (Cu) film, a film containing aluminum or copper as a main component, a chromium (Cr) film, a tantalum (Ta) film, a tantalum nitride (TaN) film, A titanium (Ti) film, a tungsten (W) film, a molybdenum (Mo) film, or the like can be used. A second conductive film 16 is formed thereon with a thickness of 150 to 500 nm. As the second conductive film 16, for example, a chromium (Cr) film, a tantalum (Ta) film, a film containing tantalum as a main component, or the like can be used. However, the first conductive film 15 and the second conductive film 16 must be combined in such a way that a selection ratio can be obtained in the mutual etching. For example, Al and Ta, Al and Ti, and TaN and W can be used as a combination of the first conductive film and the second conductive film that can be selected. In this embodiment mode, the first conductive film 15 is TaN and the second conductive film 16 is W.

Subsequently, a first resist 17 is formed using a photomask on the second conductive film and using a photolithography technique (FIG. 1A). The first resist 17 may be formed in a shape having a taper angle on the side surface. Since the first resist 17 has a taper angle, the first gate electrode 18 having the taper angle θ can be formed in the next first etching. Further, by providing the side surface of the first resist 17 with a taper angle, it is possible to suppress the reaction product in the first etching from adhering to the side surface of the first resist 17 and growing. Furthermore, the first resist 17 may be heat-treated to form the first resist 17 having a symmetrical cross-sectional shape and the same taper angle on both sides of the resist.

Subsequently, first etching is performed using the first resist 17 as a mask (FIG. 1B). In the first etching, the second conductive film 16 is etched, and a first gate electrode (etched second conductive film) 18 is formed from the second conductive film 16. At this time, the first conductive film 15 is preferably etched under etching conditions having a high selectivity so as not to etch the first conductive film 15. The first resist 17 is also etched and becomes the second resist 19. However, the receding width from the first resist 17 to the second resist 19 is not shown in the drawing. At this time, the taper angle θ of the side surface of the first gate electrode 18 is 80 ° ≦ θ ≦ 90 °, and has a substantially vertical taper angle.

In the first etching, a mixed gas of Cl ₂ , SF ₆ , and O ₂ is used as an etching gas, and the mixing ratio is Cl ₂ / SF ₆ / O ₂ = 33/33/10 (sccm). Plasma is generated by adjusting the pressure to 0.67 Pa and applying power such that ICP / Bias = 2000 W / 50 W.

Subsequently, second etching is performed on the first conductive film using the first gate electrode 18 as a mask (FIG. 1C). A second gate electrode (etched first conductive film) 20 is formed from the first conductive film by the second etching. At this time, it is preferable to perform etching under an etching condition having a high selectivity with respect to the gate insulating film 14 so as not to etch the gate insulating film 14. The second etching conditions are ICP / Bias = 2000 W / 50 W, pressure 0.67 Pa, and etching gas is Cl ₂ . Note that the second resist 19 is also etched and receded to become the third resist 21, but the receding state is not shown.

Next, third etching is performed (FIG. 1D). The third etching condition is ICP / Bias = 2000 W / 0 W, pressure 1.33 Pa, etching gas is a mixed gas of Cl ₂ , SF ₆ and O ₂ , and the mixing ratio is Cl ₂ / SF ₆ / O ₂ = 22 / 22/30 (sccm). In the third etching, the gate length of the first gate electrode 18 (also referred to as the length in the channel length direction) is shortened while the third resist 21 is retracted while using the retracted third resist 21 as a mask. Then, a third gate electrode 22 is formed. The retreated third resist 21 becomes the fourth resist 23. Thereafter, the fourth resist 23 is removed.

As another third etching condition, ICP / Bias = 750 W / 0 W, pressure 0.67 Pa, etching gas is a mixed gas of Cl ₂ , SF ₆ and O ₂ , and the mixing ratio is Cl ₂ / SF ₆ / O ₂ = It may be 20/100/30 (sccm). Under this condition, the etching selectivity between W, which is the first gate electrode material, and the gate insulating film 14 is increased, and the gate insulating film 14 can be prevented from being etched during the third etching.

In the third etching, the side surface of the third gate electrode 22 was easily etched. When the side surface of the third gate electrode 22 is etched, the gate length of the middle part becomes shorter than the gate length (length in the channel length direction) of the top and bottom surfaces, and the third gate electrode cross section is constricted at the middle part. Become a shape. Then, the coverage of the film formed on the third gate electrode 22 is deteriorated, and disconnection is likely to occur. In addition, since the third gate electrode is used as a doping mask when forming the LDD region, it becomes difficult to control the LDD length. The etching of the side surface of the third gate electrode 22 is a phenomenon that occurs because the etching rate of the first gate electrode is faster than the etching rate of the resist. Therefore, in this embodiment, the etching of the side surface of the third gate electrode 22 can be suppressed by setting the sample stage temperature to a low temperature of −10 ° C. or lower and lowering the etching rate of the first gate electrode.

Through the above steps, a hat-shaped gate electrode shape is obtained. The hat shape structure of the present invention is formed by utilizing the resist recession width during etching. Specifically, the receding width from the third resist 21 to the fourth resist 23 during the third etching is the difference between the gate length of the third gate electrode and the gate length of the second gate electrode. ing. Alternatively, the sum of the resist receding widths in the second and third etchings, that is, the receding width from the second resist 19 to the fourth resist 23 is the gate length of the third gate electrode and the second gate electrode. It is a difference with the gate length.

In the method for manufacturing a hat-shaped gate electrode according to the present invention, the difference between the gate length of the second gate electrode and the gate length of the third gate electrode can be 10 to 300 nm, preferably 50 to 200 nm. It is possible to form a fine gate electrode structure.

The first to third etchings in this embodiment can be performed by dry etching, and can be performed by using an ICP (Inductively Coupled Plasma) etching method.

Next, first doping is performed on the island-shaped semiconductor film 13 (FIG. 2A). The island-shaped semiconductor film 13 is doped with a low-concentration impurity element through the second gate electrode and the gate insulating film, and the low-concentration impurity regions 24a and 24b are formed in the island-shaped semiconductor film portions overlapping the second gate electrode. Form. At the same time, only the gate insulating film is allowed to pass through, and impurity elements are doped into both end portions of the island-shaped semiconductor film to form low-concentration impurity regions 25a and 25b (FIG. 2A). A channel formation region 26 is also formed by the first doping. The element concentration of the low-concentration impurity regions 24a, 24b, 25a, and 25b is 1 × 10 ¹⁶ to 1 × 10 ²⁰ atoms / cm ³ (preferably 1 × 10 ^{16 to} 5 × 10 ¹⁸ atoms / cm ³ ). As a doping method, an ion doping method or an ion implantation method can be used. For example, boron (B), gallium (Ga), or the like is used as an impurity element when a P-type semiconductor is manufactured, and phosphorus (P), arsenic (As), or the like is used when an N-type semiconductor is manufactured. .

The doping into the low concentration impurity regions 24a and 24b is performed not only through the gate insulating film but also through the second gate electrode 20. Therefore, the concentration of the impurity element in the low concentration impurity regions 24a and 24b is lower than that in the low concentration impurity regions 25a and 25b.

Next, second doping is performed (FIG. 2B). By the second doping, the low-concentration impurity regions 25a and 25b are doped with a high-concentration impurity element, and the high-concentration impurity regions 27a and 27b are selectively formed in the low-concentration impurity regions composed of 24a, 24b, 25a, and 25b. . Doping is performed so that the concentration of the impurity element in the high-concentration impurity regions 27a and 27b is 1 × 10 ¹⁹ to 1 × 10 ²¹ atoms / cm ³ .

In this embodiment, as the LDD region, low-concentration impurity regions 24a and 24b that overlap with the second gate electrode through the gate insulating film are formed to have a GOLD structure. Therefore, the semiconductor device manufactured in this embodiment can prevent deterioration of the on-current value and achieve high reliability. Further, an LDD region having an LDD length of 10 to 300 μm, preferably 50 μm to 200 μm can be formed. Therefore, even if the channel formation region 26 has a very fine TFT having a channel length of 0.1 to 0.7 μm, an LDD region suitable for the size can be formed.

In order to form the Loff region from the state of FIG. 2B, after the second doping, the second gate electrode 20 is etched using the third gate electrode 22 as a mask. At this time, the etching is preferably performed under the second etching condition. The second gate electrode portion having a gate length longer than that of the third gate electrode 22 is etched, and the low-concentration impurity regions 24a and 24b, which are Lov regions, become Loff regions 28a and 28b (FIG. 2C). Thus, a semiconductor device that can suppress the leakage current that is an off-current and suppress the short channel effect can be obtained.

FIG. 15 shows an SEM photograph of the cross-sectional shape of the hat-shaped gate electrode formed by the conventional method, and FIG. 16 shows an SEM photograph of the cross-sectional shape of the hat-shaped gate electrode formed by the present invention.

FIG. 15A shows a state in which the first and second conductive films are etched by dry etching, and a tapered resist, a W film and a TaN film etched in a tapered shape are shown. Since the TaN film is difficult to distinguish, only the W film is marked. FIG. 15B shows a hat-shaped shape in which the W film is anisotropically etched and the resist is removed.

FIG. 16A shows a state in which the W film is etched by the first etching, and the resist and the W film are shown. FIG. 16B shows a hat-shape type in which the third etching is performed and the resist is removed.

As can be seen from the scale at the lower right of the photograph, the TFT of FIG. 15 is larger in size than the TFT of FIG. Although the gate length of FIG. 15B is about 1.9 μm, the gate length of FIG. 16B is about 0.9 μm, and the TFT of FIG. 16B is half of the TFT of FIG. It has the following gate length.

Further, the length of the first conductive film (TaN) protruding from the second conductive film (W) in the channel length direction (hereinafter referred to as Lov length) is about 1 μm in FIG. 15B. In contrast, in FIG. 16B, the difference is about 0.07 μm, which is obvious. In the conventional method, the taper portion of the W film in FIG. 15A is long, and that portion directly contributes to the Lov length. Therefore, the Lov length becomes long. On the other hand, as shown in FIG. 16A, the present invention has almost no taper portion of the W film, and the Lov length is formed using the resist receding width without using the taper portion. Can form a length.

In addition, the side surface of the W film in FIG. 15B is slightly warped, and it can be seen that the side surface of the W film is etched. In contrast, the side surface of the W film in FIG. 16B is straight, and the side surface of the W film is not etched. This is because, in the present invention, the sample stage substrate temperature during the third etching was lowered to −10 ° C. or lower.

Further, FIG. 28 shows an SEM photograph of the hat-shaped gate electrode formed according to the present invention. FIG. 28A shows a resist, a W film as a third gate electrode, and a TaN film as a second gate electrode. FIG. 28B is an enlarged view of FIG. The third gate electrode made of the W film had a gate length of about 0.73 μm and a Lov length of about 0.07 μm.

FIG. 29 is an SEM photograph of a hat-shaped gate electrode having a smaller gate length, in which a W film is shown as the third gate electrode and a TaN film is shown as the second gate electrode. The gate length of the third gate electrode made of the W film was about 0.18 μm, and a very fine structure could be formed. On the other hand, the Lov length was about 0.1 μm.

In the present invention, the Lov length can be controlled by the shape of the first resist 17. When the side surface of the first resist 17 has a taper angle, etching becomes easier compared to a resist having no taper angle and a side surface vertical, and therefore the receding width of the resist by the third etching is increased and the Lov length is increased. Can be bigger. Conversely, when it is desired to reduce the Lov length in the present invention, the taper angle of the side surface of the first resist 17 is preferably close to 90 °.

As described above, the semiconductor device including the TFT manufactured in this embodiment can have an LDD region with a very short LDD length, and a highly reliable semiconductor device with little deterioration can be realized even in a miniaturized semiconductor device. .

(Embodiment 2)
In this embodiment mode, a method for manufacturing a semiconductor device having a Loff region is shown in FIGS.

In this embodiment mode, a TFT having a hat-shaped gate electrode is formed through the same steps as those in Embodiment Mode 1 from FIG. 1A to FIG. 1D, and the state shown in FIG.

After that, first doping is performed using the second and third gate electrodes as a mask, and an impurity element is doped into a portion of the island-shaped semiconductor film that does not overlap with the second gate electrode 20 (FIG. 3B). By this doping, the low concentration impurity regions 31a and 31b and the channel formation region 35 are formed. Doping is performed so that the concentration of the impurity element in the low-concentration impurity regions 31 a and 31 b is 1 × 10 ¹⁶ to 1 × 10 ²⁰ atoms / cm ³ , preferably 1 × 10 ^{16 to} 5 × 10 ¹⁸ atoms / cm ³ .

Next, second doping for forming a high concentration impurity region is performed (FIG. 3C). The resist 32 is formed so that the high-concentration impurity element is not doped in all the low-concentration impurity regions 31a and 31b. The resist 32 is formed so as to cover a part of the low-concentration impurity regions 31a and 31b. Using the resist 32 as a mask, an impurity element is doped so that the concentration in the high-concentration impurity regions 33a and 33b is 1 × 10 ¹⁹ to 1 × 10 ²¹ atoms / cm ³ . As a result, high-concentration impurity regions 33a and 33b and low-concentration impurity regions 34a and 34b are formed in the low-concentration impurity regions 31a and 31b. Thereafter, the resist 32 is removed.

As described above, the semiconductor device including the TFT manufactured in this embodiment can have the low-concentration impurity regions 34a and 34b as Loff regions. Even in a miniaturized semiconductor device, a short channel is suppressed by suppressing a leakage current that is an off current. The effect can be suppressed.

The TFT manufactured in this embodiment has an LDD region which is a Loff region as in FIG. The method for forming the Loff region shown in FIG. 2C has an advantage that the number of steps is small, but the channel length of the channel formation region is shortened, so that the influence of the short channel effect is somewhat increased. The Loff region formation method shown in this embodiment has an advantage that the channel length of the channel formation region can be increased and the short channel effect is suppressed. On the other hand, the number of steps for forming the resist 32 is increased by one. Which method is used to form the Loff region may be selected as appropriate.

(Embodiment 3)
In this embodiment, a method for manufacturing a semiconductor device having both a Lov region and a Loff region will be described with reference to FIGS. In this embodiment mode, a TFT having a hat-shaped gate electrode and an impurity region is formed through the same steps as those in Embodiment Mode 1 from FIG. 1A to FIG. 2A (FIG. 4A).

Next, a film 41 made of a silicon compound is formed to a thickness of 100 nm on the gate electrode by using a known film formation method (FIG. 4B). In this embodiment, a silicon oxide film is used as the film 41. Then, the film 41 made of a silicon compound is etched back to form sidewalls 42 shown in FIG. When the difference between the gate length of the second gate electrode and the gate length of the third gate electrode is very small, the sidewall 42 covers not only the side surface of the third gate electrode but also the side surface of the second gate electrode. It is formed.

Next, as shown in FIG. 4D, second doping is performed. The second doping is performed using the sidewall 42 and the third gate electrode as a mask. Thereby, the high concentration impurity regions 43a and 43b are formed in a part of the low concentration impurity regions 25a and 25b which are not covered with the sidewalls 42. At the same time, low-concentration impurity regions 44a and 44b to be Loff regions are also formed. The low concentration impurity regions 24a and 24b become Lov regions.

Through the above steps, the semiconductor device including the TFT manufactured in this embodiment can form a TFT having a Loff region and a Lov region. Therefore, even in a miniaturized semiconductor device, it is possible to suppress the short channel effect and prevent deterioration of the on-current value.

FIG. 17 shows a SEM cross-sectional photograph of the hat-shaped gate electrode in a state where the sidewall described in this embodiment is formed. FIG. 17A is an SEM photograph in which a cross section is taken from an oblique direction, and FIG. 17B is a photograph in which the magnification of FIG. 17A is further increased. The gate length of the third gate electrode made of W is 0.9 μm, which is a very small gate length. From the photograph, it is difficult to determine where the TaN film is in contact with the sidewall. However, as in the sidewall 42 shown in this embodiment, the side is covered so as to cover the side surface of the second gate electrode made of the TaN film. It was confirmed that a wall was formed. Further, it can be confirmed that the upper part of the W film side surface which is a part of the W film side surface is not covered with the sidewall.

(Embodiment 4)
In this embodiment, a method for manufacturing a display device using the TFTs having various structures described in Embodiments 1 to 3 will be described with reference to FIGS. A method for manufacturing a display device described in this embodiment is a method for manufacturing a pixel portion and a TFT of a driver circuit portion provided around the pixel portion at the same time. Note that this embodiment mode can be freely combined with Embodiment Modes 1 to 3 as long as practicable.

First, as shown in FIG. 5A, a substrate 501 having a base insulating film 502 provided on the surface is prepared. As the substrate and the base insulating film, the substrate and the base insulating film described in Embodiment 1 can be used. In this embodiment mode, a 50 nm thick silicon oxide film and a 100 nm thick silicon nitride oxide film are stacked over a glass substrate as a base insulating film. Of course, the element may be formed directly on the substrate without providing the base insulating film.

Next, an amorphous silicon film having a thickness of 66 nm is formed on the base insulating film 502 by a known film formation method. Note that the present invention is not limited to an amorphous silicon film, and may be any amorphous semiconductor film (including a microcrystalline semiconductor film) as described in Embodiment Mode 1. Further, a compound semiconductor film including an amorphous structure such as an amorphous silicon germanium film may be used.

Next, the amorphous silicon film is crystallized by a laser crystallization method. Of course, not only laser crystallization but also thermal crystallization using an RTA or furnace annealing furnace, or thermal crystallization using a metal element that promotes crystallization may be used.

The amorphous semiconductor film is crystallized by the laser crystallization described above to form a crystalline semiconductor film. Next, the crystalline semiconductor film is processed into a desired shape to form island-shaped semiconductor films 503a to 503e. Note that channel doping may be performed on the island-shaped semiconductor films 503a to 503e if necessary to control the threshold voltage of the TFT.

Next, a gate insulating film 507 is formed to cover the island-shaped semiconductor films 503a to 503e. The gate insulating film 507 is formed of an insulating film containing silicon with a thickness of 5 to 100 nm by using a plasma CVD method or a sputtering method. In this embodiment, a silicon oxynitride film is formed in contact with the island-shaped semiconductor film by a plasma CVD method, and a silicon nitride film is stacked thereover. Needless to say, the gate insulating film is not limited to the stack in this embodiment mode, and another insulating film containing silicon may be used as a single layer or a stacked structure.

When a silicon oxide film is used, TEOS (Tetraethyl Orthosilicate) and O ₂ are mixed by a plasma CVD method to obtain a reaction pressure of 40 Pa, a substrate temperature of 300 to 400 ° C., and a high frequency (13.56 MHz) power density of 0. It can be formed by discharging at 5 to 0.8 W / cm ² . The silicon oxide film thus manufactured can obtain good characteristics as a gate insulating film by thermal annealing at 400 to 500 ° C. thereafter.

Subsequently, a first conductive film 508 and a second conductive film 509 which are gate electrodes are formed over the gate insulating film 507. First, the first conductive film 508 is formed with a thickness of 5 to 50 nm, and the second conductive film 509 is formed with a thickness of 150 to 500 nm. The materials described in Embodiment 1 can be used for the first conductive film 508 and the second conductive film 509. In this embodiment, TaN is used as a combination of the first conductive film and the second conductive film. And W are used.

Resists 510a to 510e can be formed over the second conductive film by a known method (FIG. 5A).

Subsequently, first etching is performed (FIG. 5B). In the first etching, the second conductive film 509 is etched using the resists 510a to 510e as masks to form first gate electrodes 511a to 511e. Etching is performed so that the taper angle θ of the side surfaces of the first gate electrodes 511a to 511e is 80 ° ≦ θ ≦ 90 °, and has substantially vertical side surfaces. At this time, the resists 510a to 510e are also etched to become resists 512a to 512e.

Subsequently, second etching is performed as shown in FIG. Using the first gate electrodes 511a to 511e as a mask, the first conductive film 508 is etched to form second gate electrodes 513a to 513e. At this time, the resists 512a to 512e are also slightly etched.

Next, a third etching is performed. By the third etching, the resists 512a to 512e are retracted, and the gate lengths of the first gate electrodes 511a to 511e are retracted using the retracting resists 512a to 512e as a mask. Thus, as shown in FIG. 6A, third gate electrodes 514a to 514e having a gate length shorter than that of the second gate electrode are formed. The resists 512a to 512e also recede to become resists 515a to 515e. By the first to third etchings described above, the gate electrode has a hat shape structure.

The first to third etchings in this embodiment can be performed by a dry etching method, and can be performed by using an ICP (Inductively Coupled Plasma) etching method.

Next, a first doping is performed. The first doping is performed in a self-aligning manner using the resists 515a to 515e and the third gate electrodes 514a to 514e as masks, and a low concentration n-type impurity element (phosphorus in this embodiment) is added. 1 × 10 ^{16 to} 5 × 10 ¹⁸ atoms / cm ^{3 in the} low-concentration impurity regions 601a to 601e overlapping with the second gate electrode through the gate insulating film and the low-concentration impurity regions 602a to 602e not overlapping with the second gate electrode. It is preferable to add phosphorus at a concentration (typically 3 × 10 ^{17 to} 3 × 10 ¹⁸ atoms / cm ³ ). However, the concentration of the impurity element contained in the low-concentration impurity regions 601a to 601e is lower than that of the low-concentration impurity regions 602a to 602e because the low-concentration impurity regions 601a to 601e are doped through the second gate electrode.

Next, as shown in FIG. 6B, second doping is performed. Before that, a resist 604 is formed so that the low-concentration impurity regions 601c and 602c are not doped with a high-concentration impurity element. In the second doping, the resist 604, the resists 515a, 515b, 515d and 515e, the third gate electrodes 514a, 514b, 514d and 514e, and the second gate electrodes 513a, 513b, 513d and 513e are used in a self-aligning manner. Then, a high concentration n-type impurity element (phosphorus in this embodiment) is selectively added to the low concentration impurity region. The high concentration impurity regions 603a to 603d thus formed have phosphorus at a concentration of 1 × 10 ^{20 to} 5 × 10 ²¹ atoms / cm ³ (typically 2 × 10 ^{20 to} 5 × 10 ²¹ atoms / cm ³ ). It is preferable to be added.

Next, the resist 604 and the resists 515a to 515e are removed, and a resist 606 is formed as shown in FIG. Then, the fourth etching as shown in FIG. 2C of Embodiment 1 is performed. Part of the second gate electrodes 513a, 513d, and 513e is etched to obtain second gate electrodes 605a, 605b, and 605c. Thereafter, the resist 606 is removed.

Note that in the case where the resist 606 is formed without removing the resists 515a to 515e and the fourth etching is performed, Cl ₂ is used as an etching gas, the pressure in the chamber is 0.67 Pa by an exhaust system, and ICP / Bias = 2000W / 50W.

Subsequently, a resist 701 is formed and third doping is performed (FIG. 7A). The p-type impurity element is formed by ion doping using diborane (B ₂ H ₆ ) on the high-concentration impurity regions 603a and 603d and the low-concentration impurity regions 601a and 601e that have been n-type impurity regions in the third doping. (In this embodiment, boron) is added at a concentration of 3 × 10 ^{20 to} 3 × 10 ²¹ atoms / cm ³ (typically 5 × 10 ²⁰ to 1 × 10 ²¹ atoms / cm ³ ) to increase the concentration. Impurity regions 702 and 703 containing boron are formed. Thus, the impurity regions 702 and 703 function as a source region and a drain region of the p-channel TFT.

Next, as shown in FIG. 7B, the resist 701 is removed. After that, sidewalls 704a to 704e are formed on both sides of the second gate electrodes 605a to 605c, 513b and 513c and the third gate electrodes 514a to 514e. The side walls 704a to 704e are formed by forming a film made of a silicon compound as shown in Embodiment Mode 3 and performing etch back.

Next, a resist 705 is formed, followed by a fourth doping. In the fourth doping, an impurity element is added to part of the n-type low-concentration impurity region 602c using the resist 705, the sidewall 704c, and the third gate electrode 514c as a mask. Phosphorus (PH ₃ ) is used as the impurity element, and a high-concentration n-type impurity element (phosphorus in this embodiment) is 3 × 10 ^{20 to} 3 × 10 ²¹ atoms / cm ³ (typically, by ion doping). 5 × 10 ²⁰ to 1 × 10 ²¹ atoms / cm ³ ) is added to form an impurity region 706 containing phosphorus at a high concentration. At the same time, a low concentration impurity region 707 to be a Loff region is formed. The low concentration impurity region 601c becomes a Lov region.

Thereafter, the n-type or p-type impurity element added at each concentration is activated. The activation process is performed by laser annealing. When using the laser annealing method, it is possible to use the laser used for crystallization.

Next, as shown in FIG. 8A, a passivation film 801 is formed as a protective film with a thickness of 50 to 500 nm (typically 200 to 300 nm). This may be replaced by a silicon oxide film, a silicon nitride film, a silicon nitride oxide film, or a laminate thereof. By providing the passivation film 801, it is possible to obtain a blocking action that prevents intrusion of various ionic impurities including oxygen and moisture in the air.

Next, an interlayer insulating film 802 having a film thickness of 1.6 μm is formed on the passivation film 801. The interlayer insulating film 802 has a skeleton formed by bonding of polyimide, polyamide, BCB (benzocyclobutene), acrylic, siloxane (silicon (Si) and oxygen (O) applied by an SOG (Spin On Glass) method or a spin coating method. A substance having an organic group containing at least hydrogen as a substituent (for example, an alkyl group or aromatic hydrocarbon) as a substituent, a fluoro group may be used as a substituent, or at least hydrogen as a substituent An organic resin film such as an organic group and a fluoro group), an inorganic interlayer insulating film (an insulating film containing silicon such as silicon nitride or silicon oxide), a low-k (low dielectric constant) material, or the like. Can be used. The interlayer insulating film 802 is preferably a film having excellent flatness because it has a strong meaning of relaxing and flattening unevenness caused by TFTs formed over a glass substrate. Thereafter, a passivation film may be further formed on the interlayer insulating film.

Next, as shown in FIG. 8B, contact holes are formed in the gate insulating film 507, the passivation film 801, and the interlayer insulating film 802, and source and drain wirings 803a to 803i are formed. Note that in this embodiment mode, the source and drain wirings are formed using a titanium film, a first aluminum film, a three-layer structure of a second aluminum film containing carbon and a metal element, or a molybdenum film, a first aluminum film, carbon and a metal element. A three-layer structure of the second aluminum film is included. The first aluminum film may be an aluminum film mixed with another metal element. Examples of the metal element included in the second aluminum film include titanium, molybdenum, and nickel. Of course, metals other than those described above may be used for the source and drain wirings.

Subsequently, a pixel electrode 804 is formed so as to be in contact with the drain wiring 803h. The pixel electrode 804 is formed by etching a transparent conductive film. As the transparent conductive film, a compound of indium oxide and tin oxide, a compound of indium oxide and zinc oxide, zinc oxide, tin oxide, or indium oxide can be used.

When the pixel electrode 804 is a transparent conductive film, when the drain wiring 803h is made of an aluminum film, an aluminum oxide is formed at the interface. Since the resistance of aluminum oxide is high, a large resistance is generated between the pixel electrode 804 and the drain wiring 803h. However, in this embodiment, since the drain wiring 803h layer in contact with the pixel electrode 804 is the second aluminum film, no aluminum oxide is formed. This is because the metal element contained in the second aluminum film suppresses the formation of oxide. Thereby, the resistance at the interface between the drain wiring 803h and the pixel electrode 804 can be kept low.

After the pixel electrode is formed, a partition wall 805 made of a resin material is formed. The partition wall 805 is formed so as to expose a part of the pixel electrode 804 by etching an acrylic film or a polyimide film having a thickness of 1 to 2 μm. Note that a black film serving as a shielding film (not shown) may be appropriately formed below the partition wall 805.

Next, an EL (Electro Luminescence) layer 806 and an electrode (MgAg electrode) 807 are continuously formed by using a vacuum evaporation method without being released to the atmosphere. Note that the EL layer 806 may have a thickness of 100 nm to 1 μm, and the electrode 807 may have a thickness of 180 to 300 nm (typically 200 to 250 nm). In addition, the EL layer may be formed by inkjet, screen printing, or the like.

In this step, an EL layer and a cathode are sequentially formed for a pixel corresponding to red, a pixel corresponding to green, and a pixel corresponding to blue. However, since the EL layer has poor resistance to the solution, it has to be formed individually for each color without using a photolithography technique. Therefore, it is preferable to hide other than the desired pixels using a metal mask, and selectively form the EL layer and the cathode only at necessary portions. At least one color development of each color is performed with a triplet compound. Since the triplet compound is brighter than the singlet compound, it is preferable to form pixels corresponding to red that appear dark with the triplet compound and other pixels with the singlet compound.

That is, first, a mask that hides all pixels other than those corresponding to red is set in a vapor deposition apparatus, and a red light-emitting EL layer and electrodes are selectively formed using the mask by vacuum vapor deposition. Next, a mask that hides all but the pixels corresponding to green is set in a vapor deposition apparatus, and a green light-emitting EL layer and electrodes are selectively formed using the mask by vacuum vapor deposition. Next, similarly, a mask for hiding all but the pixels corresponding to blue is set in a vapor deposition apparatus, and a blue light-emitting EL layer and electrodes are selectively formed using the mask by vacuum vapor deposition. Note that although all the different masks are described here, the same mask may be used. Further, it is preferable to perform processing without breaking the vacuum until the EL layer and the electrode are formed on all the pixels.

Note that a known material can be used for the EL layer 806. As the known material, it is preferable to use an organic material in consideration of the driving voltage. For example, a four-layer structure including a hole injection layer, a hole transport layer, a light emitting layer, and an electron injection layer may be used as the EL layer. A film (OMOx) in which molybdenum oxide and α-NPD are mixed may be used as the EL layer. A hybrid layer in which an organic material and an inorganic material are combined may be used as the EL layer. When an organic material is used for the EL layer, each of a low molecular material, a medium molecular material, and a high molecular material can be used. In this embodiment, an example in which an MgAg electrode is used as a cathode of an EL element is shown, but other known materials may be used.

When the electrodes 807 are formed, the light emitting element 808 is completed. After that, a protective film 809 is provided so as to completely cover the light emitting element 808. As the protective film 809, an insulating film including a carbon film, a silicon nitride film, or a silicon nitride oxide film can be used, and these insulating films can be used as a single layer or a stacked layer.

Further, a sealing material 810 is provided to cover the protective film 809, and a cover material 811 is attached. The sealing material 810 is an ultraviolet curable resin, and it is preferable to use a substance having a hygroscopic effect or a substance having an antioxidant effect inside. In this embodiment, a glass substrate, a quartz substrate, or a plastic substrate can be used for the cover material 811. Although not illustrated, a polarizing plate may be provided between the sealing material 810 and the cover material 811. By providing a polarizing plate, a display with high contrast can be provided.

Thus, an active matrix EL display device having a structure having a p-channel TFT 812, an n-channel TFT 813, a sampling circuit TFT 814, a switching TFT 815, and a current control TFT 816 as shown in FIG. 8C is completed. In this embodiment, a p-channel TFT 812 having no LDD region, a current control TFT 816, an n-channel TFT 813 having a Lov region, a switching TFT 815 having a Loff region, and a sampling circuit TFT 814 having both a Loff region and a Lov region. Can be simultaneously formed on the same substrate. Note that the p-channel TFTs 812 and 816 are less affected by hot carriers and have a short channel effect, and thus the LDD region is not provided in this embodiment mode. However, as in other n-channel TFTs, an LDD region can be appropriately provided in the p-channel TFT by doping a p-type impurity element using a gate electrode or a sidewall as a mask. As a method thereof, a p-channel TFT having each structure can be formed by referring to the method of forming the n-channel TFT of this embodiment and using a p-type impurity element as a doping element.

Further, although the Loff region of this embodiment is formed by the method shown in FIG. 2D of Embodiment 1, the Loff region may be provided by the method of Embodiment 2.

In this embodiment mode, the EL display device that emits light downward has been described in which the pixel electrode is a transparent conductive film and the other electrode is an MgAg electrode. However, the present invention is not limited to this structure, and the pixel electrode may be formed using a light-shielding material and the other electrode may be formed using a transparent conductive film to form an upward emission EL display device. Alternatively, both electrodes may be formed of a transparent conductive film to form a vertical emission EL display device.

FIG. 9 shows a schematic diagram of a display device. A gate signal line driver circuit 1101, a source signal line driver circuit 1102, and a pixel portion 1104 including a plurality of pixels 1103 are formed over a substrate 1100. The gate signal line driver circuit 1101 and the source signal line driver circuit 1102 are connected to an FPC (flexible printed circuit) 1105. The p-channel TFT 812 and the n-channel TFT 813 in FIG. 8C can be used for a source signal line driver circuit or a gate signal line driver circuit.

The source signal line driver circuit 1102 includes a shift register circuit, a level shifter circuit, and a sampling circuit. A clock signal (CLK) and a start pulse signal (SP) are input to the shift register circuit, and a sampling signal for sampling the video signal is output from the shift register circuit. The sampling signal output from the shift register is input to the level shifter circuit, and the amplitude of the signal potential is increased. The sampling signal with the increased potential width is input to the sampling circuit. The sampling circuit samples a video signal input from the outside with a sampling signal and inputs it to the pixel portion.

Since these drive circuits are required to operate at high speed, it is preferable to use TFTs having a GOLD structure. This is because the Lov region has a function of relaxing a high electric field generated near the drain and can prevent deterioration due to hot carriers. The sampling circuit preferably has a structure having Lov and Loff regions since measures against hot carriers and measures against low off-state current are required. On the other hand, it is preferable to use a TFT having a Loff region that can reduce off-state current for the pixel switching TFT and the holding TFT that holds the gate voltage of the current control TFT.

In view of the present embodiment from the above points, the n-channel TFT in the driver circuit portion has a Lov region, the TFT for the sampling circuit has a Loff region and a Lov region, and the switching TFT in the pixel portion has a Loff region. Has a region. Therefore, the semiconductor device manufactured in this embodiment is a display device that can operate at high speed and has little leakage current. In addition, since the semiconductor device of this embodiment can be downsized, a display device that is small and easy to carry can be realized.

Needless to say, the present invention is not limited to a display device having such a structure, but can be applied to the manufacture of various display devices.

(Embodiment 5)
In this embodiment mode, a method of forming TFTs having various structures described in Embodiment Modes 1 to 3 with high-temperature polysilicon and manufacturing a liquid crystal display panel will be described with reference to FIGS. The liquid crystal display panel of this embodiment has a structure including a peripheral driver circuit and a pixel portion on the same substrate. Note that this embodiment mode can be freely combined with Embodiment Modes 1 to 4 as long as practicable.

As shown in FIG. 19A, a quartz substrate 1801 is prepared. The quartz substrate may be annealed at a high temperature of 900 to 1200 ° C. so that the substrate is not distorted in a later process.

Next, a light shielding film 1802 is formed on the quartz substrate 1801. The light shielding film is formed by forming and etching a metal film having a thickness of 100 to 400 nm by sputtering. As the metal film, a tungsten (W) film or a tungsten silicide (WSi) film is raised.

A first interlayer insulating film 1803 is formed so as to cover the light shielding film 1802. The first interlayer insulating film 1803 is formed by forming a silicon oxide film using TEOS (tetraethylorthosilicate) gas by an atmospheric pressure CVD method or a low pressure CVD method.

When the quartz substrate 1801 is subjected to a heat treatment for 60 minutes in a furnace at a temperature of 1150 ° C. after the first interlayer insulating film is formed, a tungsten silicide film can be formed when the light shielding film is a tungsten film.

Next, an amorphous semiconductor film is formed over the first interlayer insulating film 1803. In this embodiment, an amorphous silicon film is formed as an amorphous semiconductor film at a temperature of about 450 to 550 ° C. by a low pressure CVD method. Thereafter, the amorphous silicon film is crystallized by annealing at 600 to 700 ° C. for 1 to 10 hours in a nitrogen atmosphere. The polysilicon film obtained by crystallization has a thickness of 50 to 200 nm. Then, island-shaped semiconductor films 1804a to 1804c made of polysilicon are formed by a photolithography process. Note that the semiconductor film may be doped with an impurity element to reduce resistance.

Next, the island-shaped semiconductor films 1804a to 1804c were thermally oxidized at 900 to 1200 ° C., preferably 1000 to 1150 ° C., to form thermally oxidized silicon films 1805a to 1805c having a thickness of 30 nm. Further, a silicon nitride film 1806 having a thickness of 50 nm is formed by a low pressure CVD method or the like so as to cover the thermally oxidized silicon film. The thermally oxidized silicon films 1805a to 1805c and the silicon nitride film 1806 constitute a gate insulating film.

After that, as shown in FIG. 19B, a hat-shaped gate electrode is formed over the silicon nitride film 1806 by the method shown in Embodiment Modes 1 and 4. The hat-shaped gate electrode includes second gate electrodes 1807a to 1807d and third gate electrodes 1808a to 1808d.

Next, as shown in FIG. 19C, first to third doping is performed in the same manner as in the fourth embodiment, and p-type high-concentration impurity regions 1809, n-type high-concentration impurity regions 1810a, 1810b, N-type low-concentration impurity regions 1811a and 1811b are formed.

After that, a resist 1812 is formed so as to cover the peripheral driver circuit as shown in FIG. Then, using the resist 1812 and the third gate electrodes 1808c and 1808d as a mask, the second gate electrodes 1807c and 1807d are etched to form second gate electrodes 1813a and 1813b having the same gate length as the third gate electrode.

Then, as shown in FIG. 20A, a passivation film 1901 and a second interlayer insulating film 1902 are formed over the third gate electrode as in the fourth embodiment.

Next, contact holes are formed in the thermally oxidized silicon films 1805a to 1805c, the silicon nitride film 1806, the passivation film 1901, and the second interlayer insulating film 1902, and source and drain wirings 1903a to 1903e are formed (FIG. 20). (B)). At this time, when the source or drain wiring 1903d is formed using a light-blocking material and overlaps with the third gate electrode 1808c, light incident on the island-shaped semiconductor film 1804c can be blocked.

Next, as illustrated in FIG. 20C, a third interlayer insulating film 1904 is formed over the source and drain wirings 1903a to 1903e. After that, a contact hole is formed in the third interlayer insulating film so as to expose the source or drain wiring 1903e, and a pixel electrode 1905 is formed.

As described above, the p-channel TFT 1920 and the n-channel TFT 1921 constituting the peripheral driver circuit are formed over the quartz substrate 1801. An n-channel pixel TFT 1922 and a storage capacitor 1923 are formed in the pixel portion.

Thereafter, an alignment film 1906 is formed on the pixel electrode 1905. Then, a substrate 1910 on which a color filter 1907, a counter electrode 1908, and an alignment film 1909 are formed is prepared, and the quartz substrate 1801 and the substrate 1910 are bonded to each other with a sealant (not shown). Thereafter, when liquid crystal 1911 is injected, a liquid crystal display panel having a peripheral drive circuit is completed.

In the liquid crystal display panel of this embodiment mode, an n-channel TFT 1921 having a GOLD structure having a Lov region can be provided in the peripheral driver circuit, and an n-channel pixel TFT 1922 having a Loff region can be provided in the pixel portion. As a result, a liquid crystal display panel having a peripheral driver circuit with low on-current degradation and high operating speed and a pixel portion with low leakage current can be manufactured. In addition, a liquid crystal display panel formed of submicron TFTs can be provided, and a very compact and lightweight display device can be realized.

Although the LDD region is not formed in the p-channel TFT in this embodiment mode, the LDD region may be formed in the P-channel TFT as in the method of forming the LDD region in the n-channel TFT. Further, a TFT having both a Lov region and a Loff region as shown in Embodiment Mode 3 may be formed in the peripheral driver circuit. In that case, it can be formed by a method similar to that in Embodiment Mode 4. In this embodiment mode, the Loff region of the n-channel pixel TFT 1922 is formed by the method described in Embodiment Mode 1. However, it may be formed by the method described in Embodiment Mode 2.

In this embodiment mode, an example of a liquid crystal display panel integrated with a peripheral driving circuit is shown. However, not only the peripheral driving circuit but also a CPU can be formed at the same time. In that case, a more integrated liquid crystal display panel can be formed, and a compact display device can be provided.

(Embodiment 6)
This embodiment shows an example of a liquid crystal display device using the liquid crystal display panel of Embodiment 5. FIG. 21A is an external view of the liquid crystal display device viewed from the front, and FIG. 21B is a cross-sectional view of the liquid crystal display device viewed from the side, showing the internal structure. A rear projection display device 2001 shown in FIGS. 21A and 21B includes a projector unit 2002, a mirror 2003, and a screen 2004. In addition, a speaker 2005 and operation switches 2006 may be provided. The projector unit 2002 is disposed below the casing 2007 of the rear projection display device 2001, and projects projection light that projects an image based on the image signal toward the mirror 2003. The rear projection display device 2001 is configured to display an image projected from the rear surface of the screen 2004.

On the other hand, FIG. 22 shows a front projection display device 2101. The front projection display device 2101 includes a projector unit 2102 and a projection optical system 2103. The projection optical system 2103 is configured to project an image on a screen or the like disposed on the front surface.

The configuration of the projector unit applied to the rear projection display device 2001 shown in FIG. 21 and the front projection display device 2101 shown in FIG. 22 will be described below.

FIG. 23 shows a configuration example of the projector unit 2201. The projector unit 2201 includes a light source unit 2202 and a modulation unit 2203. The light source unit 2202 includes a light source optical system 2204 including lenses and a light source lamp 2205. The light source lamp 2205 is housed in the housing so that stray light does not diffuse. As the light source lamp 2205, for example, a high-pressure mercury lamp or a xenon lamp capable of emitting a large amount of light is used. The light source optical system 2204 is configured by appropriately providing an optical lens, a film having a polarization function, a film for adjusting a phase difference, an IR film, and the like. The light source unit 2202 is disposed so that the emitted light is incident on the modulation unit 2203. The modulation unit 2203 includes the plurality of liquid crystal panels 2206, the phase difference plate 2207, the dichroic mirror 2208, the mirror 2209, the prism 2210, and the projection optical system 2211 described in Embodiment 5. Light emitted from the light source unit 2202 is separated into a plurality of optical paths by the dichroic mirror 2208.

Each optical path is provided with a color filter 2212 that transmits light of a predetermined wavelength or wavelength band, and a liquid crystal panel 2206. The transmissive liquid crystal panel 2206 modulates the transmitted light based on the video signal. The light of each color transmitted through the liquid crystal panel 2206 enters the prism 2210 and displays an image on the screen through the projection optical system 2211. The Fresnel lens is disposed between the mirror 2003 and the screen 2004 in FIG. Then, the projection light projected by the projector unit 2201 and reflected by the mirror 2003 in FIG. 21B is converted into substantially parallel light by the Fresnel lens and projected onto the screen.

A projector unit 2301 shown in FIG. 24 has a configuration including the reflective liquid crystal panel shown in the fifth embodiment. The reflective liquid crystal panel 2302 has a structure in which the pixel electrode is formed of aluminum (Al), Ti (titanium), or an alloy thereof in the liquid crystal panel of the fifth embodiment.

The projector unit 2301 includes a light source unit 2303 and a modulation unit 2304. The light source unit 2303 has the same configuration as that in FIG. Light from the light source unit 2303 is divided into a plurality of optical paths by the dichroic mirrors 2304a and 2304b and the total reflection mirror 2305, and enters the polarization beam splitter. The polarization beam splitters 2306a to 2306c are provided corresponding to the reflective liquid crystal panels 2302 corresponding to the respective colors. The reflective liquid crystal panel 2302 modulates transmitted light based on the video signal. Each color light reflected by the reflective liquid crystal panel 2302 enters the prism 2307 and is projected through the projection optical system 2308.

The light emitted from the light source unit 2303 transmits only light in the red wavelength region and reflects light in the green and blue wavelength regions by the dichroic mirror 2304a. Furthermore, only light in the green wavelength region is reflected by the dichroic mirror 2304b. The light in the red wavelength region that has passed through the dichroic mirror 2304a is reflected by the total reflection mirror 2305 and is incident on the polarization beam splitter 2306a, and the light in the green wavelength region is incident on the polarization beam splitter 2306b, The light in the region enters the polarization beam splitter 2306c. The polarization beam splitter has a function of separating incident light into P-polarized light and S-polarized light, and has a function of transmitting only P-polarized light. The reflective liquid crystal panel 2302 polarizes incident light based on the video signal.

Only S-polarized light corresponding to each color is incident on the reflective liquid crystal panel 2302 corresponding to each color. The reflective liquid crystal panel 2302 operates in an electric field controlled birefringence mode (ECB). The liquid crystal molecules are vertically aligned with a certain angle with respect to the substrate. Therefore, in each reflective liquid crystal panel 2302, the liquid crystal molecules are aligned so as to reflect the incident light without changing the polarization state of the incident light when the pixel is in the off state. Further, when the pixel is in the ON state, the alignment state of the liquid crystal molecules changes, and the polarization state of incident light changes.

The projector unit 2301 shown in FIG. 24 can be applied to the rear projection display device 2001 shown in FIG. 21 and the front projection display device 2101 shown in FIG.

  The projector unit shown in FIG. 25 has a single-plate configuration. The projector unit shown in FIG. 25A includes a light source unit 2401, a liquid crystal panel 2402, a projection optical system 2403, and a phase difference plate 2404. The projection optical system 2403 is composed of one or a plurality of lenses. The liquid crystal panel 2402 is provided with a color filter.

  FIG. 25B shows the structure of a projector unit that operates in a field sequential manner. The field sequential method is a method in which light of each color such as red, green, and blue is temporally shifted and sequentially incident on a liquid crystal panel to perform color display without a color filter. In particular, when combined with a high-speed responsive liquid crystal panel, a high-definition image can be displayed. In FIG. 25B, a rotary color filter plate provided with a plurality of color filters such as red, green, and blue is provided between the light source unit 2401 and the liquid crystal panel 2402.

  The projector unit shown in FIG. 25C shows a configuration of a color separation method using a macro lens as a color display method. In this method, a microlens array 2405 is provided on the light incident side of the liquid crystal panel 2402, and color display is realized by illuminating light of each color from each direction. The projector unit that employs this method has a feature that light from the light source unit 2401 can be used effectively because light loss due to the color filter is small. The projector unit includes a B dichroic mirror 2406a, a G dichroic mirror 2406b, and an R dichroic mirror 2406c so as to illuminate the liquid crystal panel 2402 with light of each color from each direction.

As described above, various configurations of the liquid crystal display device having the liquid crystal display panel of Embodiment 5 as the liquid crystal panel have been described. Since the liquid crystal display device of the present invention can incorporate a very compact liquid crystal panel, a small and lightweight liquid crystal display device as a whole can be realized. Further, since the liquid crystal display device includes a liquid crystal panel having a structure suitable for various circuits, a liquid crystal display device with high reliability and less display deterioration can be realized.

(Embodiment 7)
In this embodiment mode, a method for manufacturing an ID chip including a TFT having a Lov region and a Loff region will be described with reference to FIGS. Note that here, an ID chip refers to a semiconductor device that includes an antenna in addition to a semiconductor integrated circuit or a thin film integrated circuit and reads out data wirelessly or the like. The ID chip has a function as a so-called electronic tag having a function of storing and reading data. This embodiment can be freely combined with Embodiments 1 to 4 as far as practicable.

First, the peeling layer 92 is formed on the glass substrate 91. As the separation layer, a layer containing silicon as a main component such as amorphous silicon or polycrystalline silicon can be used. Subsequently, a base film 93 is formed. As the base film 93, silicon oxide (SiO _x ), silicon nitride (SiN _x ), or silicon oxynitride (SiO _x N _y ) can be used. Island-shaped semiconductor films 94 a to 94 c are formed on the base film 93. The island-shaped semiconductor films 94a to 94c are formed by etching a semiconductor film by a CVD method or a sputtering method. Thereafter, the island-shaped semiconductor film is irradiated with laser light to be crystallized. Subsequently, a gate insulating film 95 is formed so as to cover the island-shaped semiconductor films 94a to 94c. Subsequently, a first conductive film 96 serving as a first gate electrode and a second conductive film 97 serving as a second gate electrode are formed. The materials described in Embodiment Mode 1 can be used for the first conductive film and the second conductive film, and a combination with a high selectivity can be used. TaN / W is used as the first conductive film / second conductive film. Then, resists 98a to 98d are formed over the second conductive films 97 on the island-shaped semiconductor films 94a to 94c (see FIG. 10A).

Subsequently, first and second etching are performed (FIG. 10B). In the first etching, the second conductive film 97 is etched using the resists 98a to 98d as masks to form first gate electrodes 99a to 99d. At this time, the resists 98a to 98d are also etched. Next, in the second etching, the first conductive film 96 is etched using the first gate electrodes 99a to 99d as a mask to form second gate electrodes 100a to 100d. Also in the second etching, the resists 98a to 98d are slightly etched.

Next, third etching is performed (FIG. 10C). In the third etching, the first gate electrodes 99a to 99d are etched. At this time, the resists 98a to 98d are simultaneously etched and receded, and the first gate electrodes 99a to 99d are also etched and receded using the receding resists 98a to 98d as a mask. As a result, third gate electrodes 101a to 101d having a gate length shorter than that of the second gate electrodes 100a to 100d are formed. The resists 98a to 98d retreat and become resists 104a to 104d.

Next, first doping is performed (FIG. 10C). An n-type impurity element (phosphorus in this embodiment) is added to form impurity regions 102a to 102d and 103a to 103g containing phosphorus. At this time, the concentration of the impurity elements in the impurity regions 102a to 102d and 103a to 103g is 1 × 10 ¹⁶ to 1 × 10 ²⁰ atoms / cm ³ (preferably 1 × 10 ^{16 to} 5 × 10 ¹⁸ atoms / cm ³ ). Since the impurity regions 102a to 102d are doped through the second gate electrode, the impurity regions 102a to 102d are doped at a concentration lower than the impurity element concentration in the impurity regions 103a to 103g. Thereafter, the resists 104a to 104d are removed. The removal of the resists 104a to 104d may be performed after the second doping in the next step or after the third etching in the previous step.

Subsequently, second doping is performed on the island-shaped semiconductor films 94a and 94b (FIG. 10D). A resist 107 is formed on the third gate electrode 101d so that the second doping is not performed on the island-shaped semiconductor film 94c. In the second doping, only the impurity regions 103a to 103e are doped with the impurity element. The concentration of phosphorus in this region is 1 × 10 ²⁰ to 1 × 10 ²¹ atoms / cm ³ (typically 2 × 10 ^{20 to} 5 × 10 ²¹ atoms / cm 2) by ion doping using phosphine (PH ₃ ). cm ³ ). By this doping, high-concentration impurity regions 105a to 105e to be source and drain regions are formed. The impurity regions 105a to 105e are already doped with a certain amount of impurity element by the first doping, but the dose amount of the second doping is much larger than the dose amount of the first doping. 105a to 105e function as a source region and a drain region.

Through the above steps, the regions of the semiconductor film where the first doping and the second doping are not performed, that is, the semiconductor films located under the resists 104a to 104d formed by the third etching are channel formation regions 106a to 106d. It becomes. Further, the impurity regions 102a to 102d become LDD regions.

Next, a resist 111 is formed as shown in FIG. Then, a fourth etching is performed on the second gate electrodes 100a and 100b using the third gate electrodes 101a and 101b as a mask. Then, the second gate electrodes 100a to 100d have the same gate length as the third gate electrodes 101a to 101d, and the second gate electrodes 112a and 112b are formed. Thereby, the impurity regions 102a and 102b which are LDD regions become Loff regions.

The first to fourth etchings in this embodiment can be performed by a dry etching method, and can be performed by using an ICP (Inductively Coupled Plasma) etching method.

Subsequently, the resist 111 is removed, and a silicon oxide film is formed by CVD to cover the third gate electrode and the second gate electrode of each TFT. Then, the silicon oxide film is etched back by etching to form sidewalls 114a to 114d on both sides of the third gate electrodes 101a to 101d and the second gate electrodes 112a, 112b, 100c, and 100d. When the difference between the gate lengths of the third gate electrodes 101c and 101d and the gate lengths of the second gate electrodes 100c and 100d is very small, such as 0.05 to 0.2 μm, the sidewall is the first gate. It is formed so as to cover not only the side surface of the electrode but also the side surface of the second gate electrode.

Then, a resist 113 is formed, and third doping is performed using the resist 113, the third gate electrode 101d, and the sidewall 114d as a mask. By this doping, high-concentration impurity regions 115a and 115b and low-concentration impurity regions 115c and 115d to be Loff regions are formed (FIG. 11B). The impurity regions 115a and 115b function as a source region and a drain region. The impurity region 102d becomes a Lov region.

Subsequently, as shown in FIG. 11C, a passivation film 116 is formed, and further, a first interlayer insulating film 117 is formed. As the passivation film 116, a silicon nitride film, a silicon oxynitride film, or the like can be used. As the first interlayer insulating film 117, an organic resin film, an inorganic insulating film, or a siloxane organic resin film can be used.

Subsequently, contact holes are formed in the first interlayer insulating film 117, the passivation film 116, and the gate insulating film 95, and the source and drain connected to the impurity regions 105a, 105c to 105e, and 115a to 115b serving as source and drain regions are formed. Drain electrodes 118a to 118f are formed (see FIG. 11D).

Next, a second interlayer insulating film 121 is formed over the first interlayer insulating film 117 and the source and drain electrodes 118a to 118f. Then, an opening is formed in a part of the second interlayer insulating film 121 so that part of the source and drain electrodes is exposed. Then, antennas 122a to 122e are formed over the second interlayer insulating film. A part of the antenna 122e is connected to the source and drain electrodes at the opening. After that, a protective layer 123 is formed over the antennas 122a to 122e and the second interlayer insulating film 121 (see FIG. 12A).

Next, as shown in FIG. 12B, a groove 124 is formed in order to separate the ID chips. The groove 124 may be formed so long as the peeling layer 92 is exposed. Dicing, scribing, or the like can be used to form the groove 124. Note that the groove 124 is not necessarily formed when the ID plate formed on the glass substrate 91 does not need to be separated.

Next, as shown in FIG. 13A, the peeling layer 92 is removed by etching. In this way, the glass substrate 91 is peeled off. In this embodiment mode, halogen fluoride gas is used as an etching gas, and this gas is introduced from the groove 124. In this embodiment, for example, a mixture of ClF ₃ or ClF ₃ gas with nitrogen may be used.

Next, as illustrated in FIG. 13B, the peeled TFTs 133, 135, and 137 and the antennas 122 a to 122 e are attached to a support 136 using an adhesive 134. As the adhesive 134, a material capable of bonding the support 136 and the base film 93 is used. As the adhesive 134, for example, various curable adhesives such as a reactive curable adhesive, a thermosetting adhesive, a photocurable adhesive such as an ultraviolet curable adhesive, and an anaerobic adhesive can be used. As the support 136, an organic material such as flexible paper or plastic can be used.

Further, after removing the protective layer 123, an adhesive 131 is applied onto the second interlayer insulating film 121 so as to cover the antennas 122a to 122e, and a cover material 132 is bonded thereto. As with the support 136, the cover material 132 can be made of a flexible organic material such as paper or plastic. The adhesive 131 is made of a material capable of bonding the cover material 132 and the second interlayer insulating film 121 together. As the adhesive 131, for example, various curable adhesives such as a reactive curable adhesive, a thermosetting adhesive, a light curable adhesive such as an ultraviolet curable adhesive, and an anaerobic adhesive can be used.

The ID chip is completed through the steps described above. Note that this embodiment mode is not limited to this manufacturing method. In this embodiment, an ID chip can be completed by freely combining a structure having a Lov region, a structure having a Loff region, or a structure having both a Lov region and a Loff region at the same time on the same substrate. Only. Therefore, an ID chip having a TFT having a structure having only a Lov region or a Loff region may be used, or an ID chip having only a TFT having a structure having both a Lov region and a Loff region may be manufactured.

That is, according to the present invention, an ID chip in which TFTs with various structures are provided over the same substrate can be manufactured, and an ID chip according to the purpose can be manufactured with a small number of processes. Therefore, the manufacturing cost can be reduced and the yield can be improved.

Although the TFT used for the ID chip is required to be finely processed, since the TFT manufactured according to the present invention can be applied to a submicron TFT, it is optimal to manufacture the ID chip according to the present invention.

In order to finely process a TFT used for an ID chip, it is preferably manufactured by a photolithography process using a stepper. However, when a stepper is used, the LDD region is formed with a resist mask, and the number of masks in all processes increases. That leads to an increase in manufacturing costs. Further, when a fine pattern is used, a margin for the fine processing is small. For example, when a 0.5 μm Lov region is formed on one side of a 2 μm gate electrode with a mask, an alignment accuracy of 0.1 μm or less is required. When the gate electrode is isotropically etched, it is difficult to optimize the etching time. Specifically, it cannot be inspected how much etching has been performed laterally from the edge of the mask. That is, the end point cannot be detected, and it is difficult to evaluate the etching rate in the horizontal direction. A stable process cannot be established unless the lateral etching rate is stable.

Therefore, the present invention is particularly suitable for manufacturing a semiconductor device having TFTs that require microfabrication, such as an ID chip, a CPU, a flash memory, and an audio signal processing circuit integrated display device. In manufacturing these semiconductor devices, it has a desired TFT structure, and it becomes possible to reduce the manufacturing cost and improve the yield.

The ID chip manufactured according to the present invention has a wide range of uses. For example, banknotes, coins, securities, bearer bonds, certificates (driver's license, resident's card, etc., see FIG. 26A), packaging supplies (Wrapping paper, bottles, etc., see FIG. 26 (B)), recording media (DVD software, videotapes, etc., see FIG. 26 (C)), vehicles (bicycles, etc., see FIG. 26 (D)), personal items (A bag, glasses, etc., see FIG. 26E), foods, clothes, daily necessities, electronic devices, etc. can be used. Electronic devices refer to liquid crystal display devices, EL display devices, television devices (also simply referred to as televisions, television receivers, television receivers), mobile phones, and the like.

The ID chip is fixed to the article by being affixed to the surface of the article or embedded in the article. For example, a book may be embedded in paper, or a package made of an organic resin may be embedded with an ID chip in the organic resin. Forgery can be prevented by providing a thin film integrated circuit for bills, coins, securities, bearer bonds, certificates, etc. Further, by providing ID chips in packaging containers, recording media, personal items, foods, clothing, daily necessities, electronic devices, etc., it is possible to improve the efficiency of inspection systems and rental store systems. Forgery and theft can be prevented by providing an ID chip in the vehicle.

Further, by applying the ID chip to a system for managing and distributing goods, it is possible to increase the functionality of the system. For example, the reader / writer 295 is provided on the side surface of the portable terminal including the display portion 294 and the ID chip 296 is provided on the side surface of the article 297 (see FIG. 27A). In this case, when the ID chip 296 is held over the reader / writer 295, the display unit 294 displays information such as the raw material and origin of the article 297, the history of distribution process, and the like. As another example, a reader / writer 295 is provided on the side of the belt conveyor (see FIG. 27B). In this case, the inspection of the article 297 can be easily performed.

(Embodiment 8)
The semiconductor device described in any of Embodiments 1 to 3 and the display device described in Embodiment 4 can be used for manufacturing various electronic devices. Examples of such electronic devices include television devices, cameras such as video cameras and digital cameras, navigation systems, sound playback devices (car audio, audio components, etc.), personal computers, game devices, portable information terminals (mobile computers, A mobile phone, a portable game machine, an electronic book, etc.), and an image playback apparatus (specifically, a digital versatile disc (DVD)) provided with a recording medium, and a display capable of displaying the image Apparatus). Specific examples of these electronic devices are shown in FIGS.

FIG. 14A illustrates a television device which includes a housing 13001, a supporting base 13002, a display portion 13003, a speaker portion 13004, a video input terminal 13005, and the like. The manufacturing method and the like of the display device described in Embodiment 4 can be used for processing the display portion 13003 and the like, so that a television device can be completed. As the display portion 13003, an EL display, a liquid crystal display, or the like can be used. Note that the television device includes all television devices for computers, for receiving television broadcasts, for displaying advertisements, and the like. With the above structure, a low-cost and compact television device with high reliability can be provided.

FIG. 14B illustrates a digital camera, which includes a main body 13101, a display portion 13102, an image receiving portion 13103, operation keys 13104, an external connection port 13105, a shutter 13106, and the like. The manufacturing method and the like of the display device described in Embodiments 4 and 5 can be used for processing the display portion 13102 and the like, and a digital camera can be completed. With the above structure, a low-cost and compact digital camera with high reliability can be provided.

FIG. 14C illustrates a computer, which includes a main body 13201, a housing 13202, a display portion 13203, a keyboard 13204, an external connection port 13205, a pointing mouse 13206, and the like. The manufacturing method and the like of the display device described in Embodiment 4 can be used for processing the display portion 13203 and the like, and the computer can be completed. With the above structure, a low-cost and compact computer with high reliability can be provided.

FIG. 14D illustrates a mobile computer, which includes a main body 13301, a display portion 13302, a switch 13303, operation keys 13304, an infrared port 13305, and the like. The manufacturing method and the like of the display device described in Embodiment 4 can be used for processing the display portion 13302 and the mobile computer can be completed. With the above structure, a low-cost, compact, and highly reliable mobile computer can be provided.

FIG. 14E shows an image reproduction device (specifically, a DVD reproduction device) provided with a recording medium, which includes a main body 13401, a housing 13402, a display portion A 13403, a display portion B 13404, and a recording medium (DVD etc.) reading portion 13405. Operation key 13406, speaker unit 13407, and the like. Although the display portion A 13403 mainly displays image information and the display portion B 13404 mainly displays character information, the method for manufacturing the display device described in Embodiment 4 is used for processing the display portion A 13403, the display portion B 13404, and the like. And an image reproducing apparatus can be completed. Note that the image reproducing device provided with the recording medium includes a game machine and the like. With the above configuration, it is possible to provide an image reproducing apparatus that is low-cost, compact, and highly reliable.

FIG. 14F illustrates a video camera, which includes a main body 13601, a display portion 13602, a housing 13603, an external connection port 13604, a remote control receiving portion 13605, an image receiving portion 13606, a battery 13607, an audio input portion 13608, operation keys 13609, and an eyepiece Part 13610 and the like. The manufacturing method and the like of the display device described in Embodiment 4 can be used for processing the display portion 13602 and the video camera can be completed. With the above structure, a low-cost and compact video camera with high reliability can be provided.

FIG. 14G illustrates a mobile phone, which includes a main body 13701, a housing 13702, a display portion 13703, an audio input portion 13704, an audio output portion 13705, operation keys 13706, an external connection port 13707, an antenna 13708, and the like. The manufacturing method and the like of the display device described in Embodiments 4 and 5 can be used for processing the display portion 13703 and the like, so that a mobile phone can be completed. Note that the display portion 13703 can suppress current consumption of the mobile phone by displaying white characters on a black background. With the above structure, a low-cost and compact mobile phone with high reliability can be provided.

In particular, a display device used for a display portion of these electronic devices has a thin film transistor for driving a pixel, and a desired TFT structure varies depending on a circuit used. By applying the present invention, a TFT having a structure suitable for various circuits can be manufactured with high accuracy, and high-quality electronic devices can be produced with high yield.

As described above, the applicable range of the present invention is so wide that it can be used for electronic devices in various fields.

1 is a diagram showing Embodiment 1 of the present invention. 1 is a diagram showing Embodiment 1 of the present invention. The figure which shows Embodiment 2 of this invention. The figure which shows Embodiment 3 of this invention. The figure which shows Embodiment 4 of this invention. The figure which shows Embodiment 4 of this invention. The figure which shows Embodiment 4 of this invention. The figure which shows Embodiment 4 of this invention. The figure which shows Embodiment 4 of this invention. The figure which shows Embodiment 7 of this invention. The figure which shows Embodiment 7 of this invention. The figure which shows Embodiment 7 of this invention. The figure which shows Embodiment 7 of this invention. The figure which shows Embodiment 8 of this invention. The SEM photograph of the section of the hat shape type gate electrode formed by the conventional method. The SEM photograph of the section of the hat shape type gate electrode formed by the present invention. FIG. 6 is an SEM photograph of a cross section of a hat-shaped gate electrode formed in Embodiment 3 of the present invention. The figure which shows a prior art example. The figure which shows Embodiment 5 of this invention. The figure which shows Embodiment 5 of this invention. The figure which shows Embodiment 6 of this invention. The figure which shows Embodiment 6 of this invention. The figure which shows Embodiment 6 of this invention. The figure which shows Embodiment 6 of this invention. The figure which shows Embodiment 6 of this invention. The figure which shows Embodiment 7 of this invention. The figure which shows Embodiment 7 of this invention. The SEM photograph of the section of the hat shape type gate electrode formed by the present invention. The SEM photograph of the section of the hat shape type gate electrode formed by the present invention.

Explanation of symbols

11 Substrate 12 Base Insulating Film 13 Semiconductor Film 14 Gate Insulating Film 15 Conductive Film 16 Conductive Film 17 First Resist 18 Gate Electrode 19 Resist 20 Second Gate Electrode 21 Resist 22 Third Gate Electrode 23 Resist

Claims (8)

A method for manufacturing a semiconductor device in which a semiconductor film, a gate insulating film, a first gate electrode, and a second gate electrode are sequentially stacked from above on a substrate,
Forming a first conductive film on the gate insulating film;
Forming a second conductive film on the first conductive film;
Forming a resist on the second conductive film;
Etching the second conductive film by performing a first etching, forming an etched second conductive film,
The taper angle of the side surface of the etched second conductive film is 80 ° or more and 90 ° or less,
Etching the first conductive film to form the first gate electrode by performing a second etching;
By performing the third etching, the etched second conductive film is etched using the receding resist as a mask while the resist is retracted, and the length in the channel length direction is larger than that of the first gate electrode. Forming the second gate electrode shorter,
A method for manufacturing a semiconductor device, wherein the sample stage temperature is set to −10 ° C. or lower when the third etching is performed. A method for manufacturing a semiconductor device in which a semiconductor film, a gate insulating film, a first gate electrode, and a second gate electrode are sequentially stacked from above on a substrate,
Forming a first conductive film on the gate insulating film;
Forming a second conductive film on the first conductive film;
Forming a first resist on the second conductive film;
Etching the second conductive film by performing a first etching, forming an etched second conductive film,
The taper angle of the side surface of the etched second conductive film is 80 ° or more and 90 ° or less,
Performing the second etching to recede the first resist and etch the first conductive film to form the second resist and the first gate electrode;
By performing the third etching, while etching the second resist, the etched second conductive film is etched using the receding resist as a mask, and the length in the channel length direction is the first length. Forming the second gate electrode shorter than the gate electrode;
A method for manufacturing a semiconductor device, wherein the sample stage temperature is set to −10 ° C. or lower when the third etching is performed. A method for manufacturing a semiconductor device in which a semiconductor film, a gate insulating film, a first gate electrode, and a second gate electrode are sequentially stacked from above on a substrate,
Forming a first conductive film on the gate insulating film;
Forming a second conductive film on the first conductive film;
Forming a resist on the second conductive film;
Etching the second conductive film by performing a first etching, forming an etched second conductive film,
The taper angle of the side surface of the etched second conductive film is 80 ° or more and 90 ° or less,
Etching the first conductive film to form the first gate electrode by performing a second etching;
By performing the third etching, the etched second conductive film is etched using the receding resist as a mask while the resist is retracted, and the length in the channel length direction is larger than that of the first gate electrode. Forming the second gate electrode shorter,
Doping an impurity element using the second gate electrode as a mask to form a channel formation region in the semiconductor film and a low-concentration impurity region in contact with the channel formation region;
Forming sidewalls in contact with side surfaces of the first gate electrode and the second gate electrode;
A method for manufacturing a semiconductor device, wherein an impurity element is doped using the sidewall and the second gate electrode as a mask to selectively form a high concentration impurity region in the low concentration impurity region. In any one of Claims 1 thru | or 3 ,
The method for manufacturing a semiconductor device, wherein the first etching uses a mixed gas of Cl ₂ , SF ₆ , and O ₂ as an etching gas. In any one of Claims 1 thru | or 4 ,
The method for manufacturing a semiconductor device, wherein the second etching uses Cl ₂ as an etching gas. In any one of Claims 1 thru | or 5 ,
The method for manufacturing a semiconductor device, wherein the third etching uses a mixed gas of Cl ₂ , SF ₆ , and O ₂ as an etching gas. In any one of Claims 1 thru | or 6 ,
A method for manufacturing a semiconductor device, wherein the first to third etchings are performed by a dry etching method. Oite to claim 3,
A method for manufacturing a semiconductor device, wherein the sample stage temperature is set to −10 ° C. or lower when the third etching is performed.