JP5235944B2 - 4-phase clock drive charge pump circuit - Google Patents

Description

  The present invention relates to a charge pump circuit driven by a four-phase clock.

  In recent LSIs (Large-Scale Integration), multiple power sources such as 3 V, 5 V, and 10 V are often required inside the circuit. Conventionally, when such multiple power supplies are required, a plurality of power supplies are generated outside the LSI and supplied to the LSI. However, recently, the power supplied to the LSI is a single power supply, and it has been required to generate multiple power supplies inside the LSI. Furthermore, in recent years, mobile devices that are easy to carry are strongly demanded for battery driving, and demands for lowering voltage have become stronger.

  Conventionally, a charge pump circuit has been used as a circuit for generating a voltage higher than an externally supplied power supply voltage Vcc inside an LSI. As a charge pump circuit, there is a charge pump circuit driven by a two-phase clock (for example, see Patent Document 1).

  A circuit configuration of a conventionally used two-phase clock drive charge pump circuit will be described with reference to FIG. FIG. 11 is a circuit diagram showing a configuration of a conventional charge pump circuit driven by a two-phase clock. However, the clock signal CLK is a signal having an amplitude of Vcc and a periodicity of a cycle T1 (half cycle t1). In this specification, the High level is abbreviated as H level, and the Low level is abbreviated as L level.

  There are N-channel transistors (hereinafter abbreviated as Nch transistors) T1 to T (n + 1) in which a gate and a drain are connected (diode-connected). The drain of the Nch transistor T1 is connected to the input terminal IN, and the source of the Nch transistor T (n + 1) is connected to the output terminal OUT. The source of the Nch transistor Ti (i = 1 to n) is connected to the drain of the Nch transistor T (i + 1). Here, the threshold value of the Nch transistor Ti (i = 1 to n + 1) is defined as a threshold value Vthi. For example, since the potential difference between the node n1 and the node n2 is substantially the threshold value Vth2, it is preferable to set the threshold values Vth1 to Vth (n + 1) to be small. Usually, the threshold value is set to 0 (V) to 0.4 (V). Set to degree.

  There are also pump capacitors C1 to Cn. One end of the capacitor Ci (i = 1 to n) is connected to a connection line (node ni) between the source of the Nch transistor Ti and the drain of the Nch transistor T (i + 1). The other end of the capacitor Ci (i: odd number of 1 to n) is connected to a clock terminal (terminal to which the clock signal CLK is input to the two-phase clock drive charge pump circuit) CIN. The other end of the capacitor Ci (i: an even number from 1 to n) is connected to the output part of the inverter circuit INV, and the input part of the inverter circuit INV is connected to the clock terminal CIN.

  Next, the operation of the two-phase clock drive charge pump circuit whose circuit configuration has been described with reference to FIG. 11 will be described with reference to FIG. FIG. 12 is a waveform diagram for explaining the operation of the charge pump circuit of FIG.

  When the clock signal CLK becomes L level, the Nch transistor T1 is turned on and the Nch transistor T2 is turned off, and the charge is transferred from the input terminal IN to the node n1.

  When the clock signal CLK becomes H level (the output of the inverter circuit INV becomes L level), the potential of the node n1 temporarily increases and the potential of the node n2 decreases accordingly. At this time, the Nch transistor T1 is OFF, the Nch transistor T2 is ON, and the Nch transistor T3 is OFF, and the charge is transferred from the node n1 to the node n2 through the Nch transistor T2, thereby reducing the potential of the node n1. The potential of the node n2 becomes high.

  When the clock signal CLK becomes L level (the output of the inverter circuit INV becomes H level), the potential of the node n2 once increases and the potential of the nodes n1 and n3 decreases accordingly. At this time, the Nch transistor T2 is turned off, the Nch transistor T3 is turned on, and the Nch transistor T4 is turned off, and the charge is transferred from the node n2 to the node n3 through the Nch transistor T3. The potential of the node n3 becomes high.

  Similar circuit operations are sequentially performed, and a boosted voltage is output from the output terminal OUT.

  Since the Nch transistors T1 to T (n + 1) are diode-connected, the pentode operation is always performed when the charge is transferred, the transfer current does not flow rapidly, and the charge is charged within the half-cycle period t1 of the clock signal CLK. Are not completely transferred, and potentials corresponding to the remaining charges that are not transferred are defined as potentials α01 to αn (n + 1). Further, a voltage drop corresponding to the threshold Vthi occurs in the Nch transistor Ti (i = 1 to n + 1). For this reason, for example, assuming that the potential difference ΔV12 between the node n1 and the node n2, ΔV12 = α12 + Vth2, which is inefficient. In particular, when the power supply voltage Vcc becomes a low voltage, the reduction in efficiency appears remarkably.

When the output voltage of the two-phase clock drive charge pump circuit of FIG. 11 is Vout, the threshold voltages Vth1 to Vth (n + 1) of the Nch transistors T1 to T (n + 1) are Vth, and the potentials α01 to αn (n + 1) are α. Vout is
Vout = (n + 1) × (Vcc−Vth−α)
It becomes.

  For example, when the power supply voltage Vcc is 1.2 (V), the threshold value Vth is 0.4 (V), and the potential α is 0.2 (V), in order to obtain the output voltage Vout of 12 (V), From the above formula, n is 19. On the other hand, when the power supply voltage Vcc is 1.8 (V), the threshold Vth is 0.4 (V), and the potential α is 0.2 (V), the output voltage Vout of 12 (V) is obtained. Is 9 from the above formula. Thus, the efficiency is very low at a low voltage, and the area becomes twice or more.

  In order to solve this problem, a charge pump circuit driven by a two-phase clock as shown in FIG. 13 is conceivable and will be described with reference to FIGS. FIG. 13 is a circuit diagram showing a configuration of a conceivable charge pump circuit driven by a two-phase clock. FIG. 14 is a waveform diagram for explaining the operation of the charge pump circuit of FIG.

  The charge pump circuit of FIG. 13 does not exist in the charge pump circuit of FIG. 11 and boosts the clock signal CLK by doubling the amplitude of the clock signal CLK to the other end of the capacitors C1, C3,. The double boosting circuits A1, A3,..., A (n-1) to be supplied are provided between the other ends of the capacitors C1, C3,..., C (n-1) and the clock terminal CIN. . Further, a double boosting circuit A2 that does not exist in the charge pump circuit of FIG. 11 and boosts the inverted signal / CLK of the clock signal CLK by double its amplitude and supplies it to the other ends of the capacitors C2, C4,. , A4, ..., An are provided between the other ends of the capacitors C2, C4, ..., Cn and the output part of the inverter circuit INV. That is, a pulse voltage having an amplitude of 2 × Vcc level is supplied to the other ends of the capacitors C1 to Cn. The other circuit configuration is basically the same as that of the charge pump circuit of FIG.

  In the charge pump circuit of FIG. 11, the nodes n1 to nn are raised by the Vcc level voltage, whereas in the charge pump circuit of FIG. 13, the nodes n1 to nn are double boosting circuits as shown in FIG. Thus, the voltage is raised by the voltages m1 to mn whose amplitude is 2 × Vcc level. Other circuit operations are basically the same as those of the charge pump circuit of FIG.

When the output voltage of the two-phase clock drive charge pump circuit of FIG. 13 is Vout, the threshold voltages Vth1 to Vth (n + 1) of the Nch transistors T1 to T (n + 1) are Vth, and the potentials α01 to αn (n + 1) are α. Vout is
Vout = Vcc−Vth−α + n × (2 × Vcc−Vth−α)
It becomes.

  For example, when the power supply voltage Vcc is 1.2 (V), the threshold value Vth is 0.4 (V), and the potential α is 0.2 (V), in order to obtain the output voltage Vout of 12 (V), From this equation, n is 6, and the same output voltage can be obtained with a smaller number of stages than the charge pump circuit of FIG.

JP-A-5-28781

  However, the amplitude of the node nn at the highest potential in the charge pump circuit of FIG. 13 is larger than that of the charge pump circuit of FIG. In general, in order to increase the breakdown voltage of elements such as transistors constituting an LSI, the gate oxide film is thickened, the junction concentration is decreased, the junction depth is increased, and the transistor gate length is increased. Although there are methods such as increasing the size, the transistor characteristics are deteriorated and the area is also increased. Therefore, in the normal process design, the breakdown voltage of the element cannot be afforded much. In short, it is set to the bare minimum required pressure. Therefore, the charge pump circuit as shown in FIG.

  Accordingly, an object of the present invention is to provide a four-phase clock drive charge pump circuit capable of avoiding element destruction caused by application of a high voltage.

The four-phase clock drive charge pump circuit according to claim 1 includes first to (n + 1) th transfer transistors, i (i = 1 to n) transfer transistors, and (i + 1) th transfer transistors connected in series. First to n-th main pump capacitors connected at one end to the transfer transistors and first to (n + 1) -th to (n + 1) -th transfer transistors connected to the gates of the first to (n + 1) -th transfer transistors. In the four-phase clock drive charge pump circuit including the auxiliary pump capacitors, the amplitudes of the pulse voltages supplied to the other ends of the first to jth (p is smaller than n) main pump capacitors are the same. The amplitude of the pulse voltage supplied to the other ends of the (j + 1) th to nth main pump capacitors is smaller than the amplitude of the pulse voltage supplied to the other ends of the first to jth main pump capacitors. Other than the first voltage supply means for supplying a pulse voltage to the other ends of the first to n-th main pump capacitors, the first to k-th (p is a value smaller than n) auxiliary pump capacitors. The amplitude of the pulse voltage supplied to the end is the same as the amplitude of the pulse voltage supplied to the other end of the first to jth main pump capacitors by the first voltage supply means, and the (k + 1) th to (k + 1) th to The pulse voltage supplied to the other end of the (n + 1) auxiliary pump capacitor has a pulse voltage smaller than the amplitude of the pulse voltage supplied to the other end of the first to kth capacitors. 2) a second voltage supply means for supplying to the other end of the auxiliary pump capacitor , wherein the value of k is one greater than the value of j, and the first voltage supply means has the (j + 1) th To nth main pump The amplitude of the pulse voltage supplied to the other end of the capacitor is sequentially reduced by the amplitude of the power supply voltage in the order of the (j + 1) main pump capacitor to the n-th main pump capacitor, and the second voltage supply means , The amplitude of the pulse voltage supplied to the other ends of the (k + 1) th to (n + 1) th auxiliary pump capacitors, in order from the (k + 1) auxiliary pump capacitor to the (n + 1) th auxiliary pump capacitor. It is characterized in that the power supply voltage is sequentially reduced by the amplitude .

Aspect
The four-phase clock drive charge pump circuit of one embodiment of the present invention is characterized in that the value of k is two or more larger than the value of j.

The four-phase clock drive charge pump circuit according to claim 2 includes first to (n + 1) -th transfer transistors, i (i = 1 to n) -th transfer transistors, and (i + 1) -th transfer transistors connected in series. First to n-th main pump capacitors connected at one end to the transfer transistors and first to (n + 1) -th to (n + 1) -th transfer transistors connected to the gates of the first to (n + 1) -th transfer transistors. In the four-phase clock drive charge pump circuit including the auxiliary pump capacitors, the amplitudes of the pulse voltages supplied to the other ends of the first to jth (p is smaller than n) main pump capacitors are the same. The amplitude of the pulse voltage supplied to the other ends of the (j + 1) th to nth main pump capacitors is smaller than the amplitude of the pulse voltage supplied to the other ends of the first to jth main pump capacitors. Other than the first voltage supply means for supplying a pulse voltage to the other ends of the first to n-th main pump capacitors, the first to k-th (p is a value smaller than n) auxiliary pump capacitors. The amplitude of the pulse voltage supplied to the end is the same as the amplitude of the pulse voltage supplied to the other end of the first to jth main pump capacitors by the first voltage supply means, and the (k + 1) th to (k + 1) th to The pulse voltage supplied to the other end of the (n + 1) auxiliary pump capacitor has a pulse voltage smaller than the amplitude of the pulse voltage supplied to the other end of the first to kth capacitors. 2) a second voltage supply means for supplying to the other end of the auxiliary pump capacitor, wherein the value of k is 2 larger than the value of j, and the first voltage supply means has the (j + 1) th To nth main pump The amplitude of the pulse voltage supplied to the other end of the capacitor is sequentially reduced by the amplitude of the power supply voltage in the order of the (j + 1) main pump capacitor to the n-th main pump capacitor, and the second voltage supply means , The amplitude of the pulse voltage supplied to the other ends of the (k + 1) th to (n + 1) th auxiliary pump capacitors, in order from the (k + 1) auxiliary pump capacitor to the (n + 1) th auxiliary pump capacitor. It is characterized in that the power supply voltage is sequentially reduced by the amplitude.

  According to the first to fourth aspects, since the amplitude of the voltage supplied to the capacitor on the high potential side is reduced, it is possible to avoid the destruction of the element caused by the application of the high voltage.

FIG. 3 is a circuit diagram showing a configuration of a charge pump circuit driven by a two-phase clock in the first embodiment. FIG. 2 is a waveform diagram for explaining the operation of the charge pump circuit of FIG. 1. The circuit diagram which shows the structure of the charge pump circuit of the two-phase clock drive in 2nd Embodiment. FIG. 10 is a circuit diagram showing a configuration of a charge pump circuit driven by a four-phase clock according to a third embodiment. FIG. 5 is a waveform diagram for explaining the operation of the charge pump circuit of FIG. 4. The circuit diagram which shows the structure of the 4-phase clock drive charge pump circuit in 4th Embodiment. The circuit diagram which shows the structure of the double booster circuit in 5th Embodiment. The circuit diagram which shows the structure of the 4 times boosting circuit in 6th Embodiment. The circuit diagram which shows the structure of the 4 times voltage booster circuit in 7th Embodiment. The circuit diagram which shows the structure of the 4 times boosting circuit in 8th Embodiment. The circuit diagram which shows the structure of the conventional charge pump circuit of a two-phase clock drive. FIG. 12 is a waveform diagram for explaining the operation of the charge pump circuit of FIG. 11. The circuit diagram which shows the structure of the conventional charge pump circuit of a two-phase clock drive. FIG. 14 is a waveform diagram for explaining the operation of the charge pump circuit of FIG. 13.

  Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

<Charge pump circuit (1)>
Hereinafter, a two-phase clock drive charge pump circuit according to the first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a circuit diagram showing a configuration of a two-phase clock drive charge pump circuit in the present embodiment. FIG. 2 is a waveform diagram for explaining the operation of the two-phase clock drive charge pump circuit of FIG.

  In the charge pump circuit shown in FIG. 1, similarly to the conventional charge pump circuit shown in FIG. 13, a clock signal is connected between the other ends of the capacitors C1 to C (n-1) and the output terminal of the clock terminal CIN or the inverter circuit INV. The circuit configuration is such that double boosting circuits A1 to A (n-1) for doubling the amplitude of CLK or its inverted signal / CLK are inserted. However, unlike the conventional charge pump circuit of FIG. 13, a double booster circuit is not inserted between the capacitor Cp corresponding to the capacitor Cn and the inverter circuit INV output unit. That is, the voltage supplied to the other end of the capacitors C1 to C (n−1) has an amplitude of 2 × Vcc, but the voltage supplied to the other end of the capacitor Cp has an amplitude of Vcc.

  The capacitances of the capacitors C1 to C (n-1) are set to be the same, and the capacitance of the capacitor Cp is set to approximately twice the capacitance of the capacitor C (n-1). In other words, it is set so that the product of the capacitances of the capacitors C1 to C (n-1) and Cp and the amplitude of the voltage supplied to the other end of the capacitor is constant. The other circuit configuration is basically the same as the circuit configuration of the conventional charge pump circuit of FIG.

  In the charge pump circuit of FIG. 13, the potentials of the nodes n1 to nn are raised by the voltage of 2 × Vcc level, whereas the charge pump circuit of FIG. The potential of -1) is raised by the voltage m1 to m (n-1) having an amplitude of 2 * Vcc level by the double booster circuit, and the potential of the node nn is raised by the voltage of the Vcc level. The other circuit operations are basically the same as those of the charge pump circuit of FIG.

  As shown in FIG. 2, the amplitude of the node n (n−1) is large, but the amplitude of the node nn at the final stage, which is the highest potential, uses a Vcc level pump, so the final stage also has 2 × Vcc. 13 is used, and the last stage capacitor is set to double the capacity. Therefore, it is smaller by Vcc than the conventional charge pump circuit of FIG. 13, and the withstand voltage is reduced by approximately Vcc. The Furthermore, since the Vcc level pump is used in only one stage of the final stage, it is possible to ensure almost the same capability as the conventional charge pump circuit of FIG.

  According to the present embodiment described above, by using the Vcc level pump only at the final stage, it is possible to avoid the destruction of the element caused by the application of a high voltage while maintaining almost the same charge pump circuit capability. Can do.

<Charge pump circuit (2)>
A two-phase clock drive charge pump circuit according to the second embodiment of the present invention will be described below with reference to FIG. FIG. 3 is a circuit diagram showing a configuration of a two-phase clock drive charge pump circuit in the present embodiment. Note that in this embodiment, differences from the charge pump circuit in FIG. 1 will be described.

  In the charge pump circuit shown in FIG. 3, between the other ends of the capacitors C1, C3,... C (n-3) and the clock terminal CIN, the clock signal CLK is boosted by a factor of 4, and the capacitors C1, C3 ,... C (n-3) are provided with quadruple boosting circuits B1, B3,. Further, between the other ends of the capacitors C2, C4,... C (n-4) and the output part of the inverter circuit INV, the inverted signal / CLK of the clock signal CLK is boosted four times to increase the amplitude of the capacitor C2, C4... C (n-4) are provided with quadruple boosting circuits B2, B4,. Further, between the other end of the capacitor Cp1 corresponding to the capacitor C (n-2) and the output part of the inverter circuit INV, the inverted signal / CLK is boosted three times and supplied to the other end of the capacitor Cp1. A triple booster circuit B (n−2) is provided. Further, a double boosting is performed between the other end of the capacitor Cp2 corresponding to the capacitor C (n−1) and the clock terminal CIN so as to boost the amplitude of the clock signal CLK twice and supply the clock signal CLK to the other end of the capacitor Cp2. A circuit B (n-1) is provided. The other end of the capacitor Cp3 corresponding to the capacitor Cp is directly connected to the output of the inverter circuit INV. That is, the voltage supplied to the other end of the capacitors C1 to C (n-3) has an amplitude of 4 × Vcc, and the voltage supplied to the other end of the capacitor Cp1 has an amplitude of 3 × Vcc. The voltage supplied to the other end of the capacitor Cp2 has an amplitude of 2 × Vcc, and the voltage supplied to the other end of the capacitor Cp3 has an amplitude of Vcc.

  The capacitances of the capacitors C1 to C (n-3) are set to be the same, and the capacitance of the capacitor Cp1 is set to 4/3 times the capacitance of the capacitor C (n-3) (Cp1 = 4/3 × C (n -3)). Further, the capacitance of the capacitor Cp2 is set to twice the capacitance of the capacitor C (n-3) (Cp2 = 2 × C (n-3)), and the capacitance of the capacitor Cp3 is set to the capacitance of the capacitor C (n-3). It is set to 4 times (Cp3 = 4 × C (n−3)). That is, it is set so that the product of the capacitances of the capacitors C1 to C (n-3) and Cp1 to Cp3 and the amplitude of the voltage supplied to the other end of the capacitor is constant.

  In the charge pump circuit of FIG. 3, the potentials of the nodes n1 to n (n-3) are raised by the quadruple booster circuit to a voltage having an amplitude of 4 × Vcc level, and the potential of the node n (n-2) is 3 The voltage is raised by a voltage whose amplitude becomes 3 × Vcc level by the double booster circuit. Further, the potential of the node n (n−1) is raised by the voltage whose amplitude is 2 × Vcc level by the double booster circuit, and the potential of the node nn is raised by the voltage of the Vcc level.

  According to the present embodiment described above, the pump magnification (the amplitude level of the voltage supplied to the other end of the capacitor) is decreased and the (n -2) The peak voltage from the stage pump to the n-th stage pump is relaxed. For this reason, it is possible to avoid the destruction of the element caused by the application of a high voltage.

  In the present embodiment, the 4 × Vcc level, 3 × Vcc level, 2 × Vcc level, Vcc level, and 1 step from the (n−3) th stage to the nth (final) stage pump. This is a case where the circuit is configured so that the Vcc level is lowered every time. However, the present invention is not limited to this. For example, toward the final stage, the 4 × Vcc level, 2 × Vcc level (or 3 × Vcc level), Vcc level The circuit may be configured so that Alternatively, two stages of 3 × Vcc levels and two stages of 2 × Vcc levels may be provided. In short, the amplitude level of the voltage supplied to the other end of the capacitor constituting the several pumps on the output side is such that the element is not destroyed due to the high voltage applied. What is necessary is just to comprise a charge pump circuit so that it may become smaller than the amplitude level of the voltage supplied to the other end.

<Charge pump circuit (3)>
Hereinafter, a four-phase clock drive charge pump circuit according to a third embodiment of the present invention will be described with reference to FIG. FIG. 4 is a circuit diagram showing a configuration of a four-phase clock drive charge pump circuit in the present embodiment.

  There are (n + 1) N-channel transistors T11 to T1 (n + 1) as main transfer transistors. Nch transistors T11, T12, T13,..., T1 (n−1) are sequentially arranged from the input side of the power supply voltage Vcc. , T1n, T1 (n + 1) are connected in series. That is, the drain of the Nch transistor T11 is connected to the input terminal IN to which the power supply voltage Vcc is input. The drain of the Nch transistor T1 (i + 1) is connected to the source of the Nch transistor T1i (i = 1 to n). The output terminal OUT is connected to the source of the Nch transistor T1 (n + 1). One end of the capacitor Csi is connected to the gate of the Nch transistor T1i (i = 1 to n), and one end of the capacitor Cq is connected to the gate of the Nch transistor T1 (n + 1).

  There are n capacitors C1 to C (n-3) and Cp1 to Cp3 as main pump capacitors. One end of capacitors C1, C2,..., C (n-3), Cp1, Cp2, Cp3 is connected to nodes n1, n2,..., N (n-3), n (n-2), n (n-1), connected to nn. Node ni (i = 1 to n) is between the connection of the source of Nch transistor T1i and the drain of Nch transistor T1 (i + 1).

  Between the other end of the capacitors C1, C3,..., C (n-3) and the clock terminal CIN1, the amplitude of the clock signal PH1 is boosted by a factor of 4, and capacitors C1, C3,. , D1 (n-3) are provided to be supplied to the other end of 3). Between the other ends of the capacitors C2, C4,..., C (n-4) and the clock terminal CIN2, the amplitude of the clock signal PH2 is increased by a factor of 4, and capacitors C2, C4,. , D1 (n-4) are provided to the other end of 4). A triple booster circuit D1 (n-2) is provided between the other end of the capacitor Cp1 and the clock terminal CIN2, and boosts the clock signal PH2 by three times and supplies it to the other end of the capacitor Cp1. Yes. A double booster circuit D1 (n-2) is provided between the other end of the capacitor Cp2 and the clock terminal CIN1 to boost the amplitude of the clock signal PH1 to the other end of the capacitor Cp2. Yes. No booster circuit is provided between the other end of the capacitor Cp3 and the clock terminal CIN2, and the other end of the capacitor Cp3 is directly connected to the clock terminal CIN2.

  There are (n + 1) Nch transistors T21 to T2 (n + 1) provided corresponding to the Nch transistors T11 to T1 (n + 1). In this specification, these transistors are appropriately referred to as auxiliary transfer transistors. An input terminal IN is connected to the drain of the Nch transistor T21. The drain of the Nch transistor T2i (i = 2 to n + 1) is connected to the node n (i−1). The source of the Nch transistor T2i (i = 1 to n + 1) is connected to the node ki and connected to the gate of the Nch transistor T1i. The gate of the Nch transistor T2i (i = 1 to n) is connected to the node ni and connected to the capacitor Ci. The gate of the Nch transistor T2 (n + 1) is connected to the output terminal OUT.

  There are (n + 1) capacitors Cs1 to Csn, Cq provided corresponding to the Nch transistors T11 to T1 (n + 1), and are referred to as auxiliary pump capacitors in this specification as appropriate. One end of capacitors Cs1, Cs2,..., Csn, Cq is connected to the gates of Nch transistors T11, T12,..., T1n, T1 (n + 1).

  Between the other ends of the capacitors Cs1, Cs3,..., Cs (n-3) and the clock terminal CIN4, the amplitude of the clock signal PH4 is increased by a factor of 4, and capacitors Cs1, Cs3,. A quadruple booster circuit D21 is provided to be supplied to the other end of 3). .., Cs (n−) between the other ends of the capacitors Cs2, Cs4,..., Cs (n−2) and the clock terminal CIN3. A quadruple booster circuit D22 is provided to be supplied to the other end of 2). Between the other end of the capacitor Cs (n-1) and the clock terminal CIN4, a triple boosting circuit that boosts the amplitude of the clock signal PH4 to three times and supplies the clock signal PH4 to the other end of the capacitor Cs (n-1). D2 (n-1) is provided. A double booster circuit D2n is provided between the other end of the capacitor Csn and the clock terminal CIN3 to boost the amplitude of the clock signal PH3 to the other end of the capacitor Csn. A booster circuit is not provided between the other end of the capacitor Cq and the clock terminal CIN4, and the other end of the capacitor Cq is directly connected to the clock terminal CIN4.

  That is, in FIG. 4, the amplitude levels of the voltages supplied to the other ends of the main pump capacitor and the auxiliary pump capacitor constituting the same pump are the same, and are sequentially supplied from the (n-2) th stage pump. The voltage amplitude is configured to decrease to the Vcc level. The auxiliary pump capacitors constituting the same pumps as the main pump capacitors C1, C2,..., C (n-3), Cp1, Cp2, and Cp3 are capacitors Cs2, Cs3,. -2), Cs (n-1), Csn, Cq.

  Next, the operation of the charge pump circuit driven by a four-phase clock whose circuit configuration is shown in FIG. 4 will be described with reference to FIG. FIG. 5 is a waveform diagram for explaining the operation of the charge pump circuit of FIG. The clock signals PH1 to PH4 have the relationship shown in FIG. 5, and are pulse signals having an amplitude of Vcc.

  When the clock signal PH1 becomes H level, the gate voltage of the Nch transistor T21 increases through the capacitor C1, and the gate voltage of the Nch transistor T11 (potential of the node k1) increases. After that, when the clock signal PH1 becomes L level after the clock signal PH1 becomes L level, the gate voltage (potential of the node k1) of the Nch transistor T11 further increases through the capacitor Cs1. When the gate voltage of the Nch transistor T11 becomes higher than the threshold voltage of the input terminal IN, the Nch transistor T11 operates between three electrodes, and the power supply voltage Vcc input to the input terminal IN does not drop the voltage corresponding to the threshold value. The data is transferred to the node n1 through the Nch transistor T11.

  Thereafter, when the clock signal PH1 is at the H level when the clock signal PH2 is at the H level, the potential of the node n1 is increased accordingly, and the gate voltage of the Nch transistor T22 is increased through the capacitor C2, and thus the Nch transistor T12. The gate voltage (potential of the node k2) of the transistor becomes higher. Thereafter, when the clock signal PH2 becomes L level and the clock signal PH3 becomes H level, the gate voltage of the Nch transistor T12 (potential of the node k2) further increases through the capacitor Cs2. When the gate voltage of the Nch transistor T12 becomes higher than the threshold value of the node n1, the Nch transistor T12 operates between three electrodes, and the potential of the node n1 passes through the Nch transistor T12 without dropping the voltage corresponding to the threshold value. transferred to n2. After that, when the clock signal PH3 becomes L level, the potential is not raised by the clock signal PH3, so that the gate voltage of the Nch transistor T12 (the potential of the node k2) decreases. After that, when the clock signal PH2 becomes H level and the clock signal PH1 becomes L level, the potential of the node n1 is lowered accordingly, and the gate voltage of the Nch transistor T22 is increased through the capacitor C2. The gate voltage (the potential at the node k2) decreases.

  After the potential of the node n1 is transferred to the node n2, when the clock signal PH2 is at the H level when the clock signal PH1 is at the H level, the potential of the node n2 is increased accordingly, and the Nch transistor T23 is connected through the capacitor C3. Since the gate voltage is high, the gate voltage (potential of the node k3) of the Nch transistor T13 is high. Thereafter, when the clock signal PH1 becomes L level and the clock signal PH4 becomes H level, the gate voltage of the Nch transistor T13 (potential of the node k3) further increases through the capacitor Cs3. When the gate voltage of the Nch transistor T13 becomes higher than the threshold voltage of the node n2, the Nch transistor T13 operates between three electrodes, and the potential of the node n2 passes through the Nch transistor T13 without dropping the voltage corresponding to the threshold voltage. transferred to n3. After that, when the clock signal PH4 becomes L level, the potential is not increased by the clock signal PH4, so that the gate voltage of the Nch transistor T13 (the potential of the node k3) decreases. After that, when the clock signal PH1 becomes H level and the clock signal PH2 becomes L level, the potential of the node n2 is lowered accordingly, and the gate voltage of the Nch transistor T23 is increased through the capacitor C3. The gate voltage (the potential at the node k3) decreases.

  The transfer operation as described above is performed at each stage, and the power supply voltage Vcc is transferred to the node nn while being boosted.

  The potential transfer from the node nn to the output terminal OUT is performed as follows. When the clock signal PH2 becomes H level, since the gate voltage of the Nch transistor T2 (n + 1) is connected to the output terminal OUT, the gate voltage of the Nch transistor T1 (n + 1) (the potential of the node k (n + 1)) is the output voltage. It is charged to a voltage lower than the threshold value of the Nch transistor T1 (n + 1). Thereafter, when the clock signal PH4 becomes H level, the gate voltage of the Nch transistor T1 (n + 1) (potential of the node k (n + 1)) is further increased through the capacitor Cq. When the gate voltage of the Nch transistor T1 (n + 1) becomes higher than the threshold value of the node nn by more than a threshold value, the Nch transistor T1 (n + 1) operates between three electrodes, and the potential of the node nn does not drop by the threshold voltage. The data is transferred to the output terminal OUT through the transistor T1 (n + 1).

  According to the present embodiment described above, the pump magnification is lowered from the (n−2) -th stage pump to the n-th stage pump where the voltage is increased, and the (n−2) -th stage pump is changed to the n-th stage pump. The peak voltage in the pump is relaxed. For this reason, it is possible to avoid the destruction of the element caused by the application of a high voltage.

  Note that in the capacitors Cp1, Cp2, Cs (n-1), and the N-channel transistors T1 (n-1) and T2 (n-1), the potential of the node n (n-2) is raised by 3 × Vcc. Since the gate voltage of the N-channel transistor T2 (n-1) (the potential of the node k (n-1)) can only be raised by 2 * Vcc, a sufficient charge cannot be transferred to the node k (n-1). Therefore, the gate voltage of the N-channel transistor T1 (n-1) is somewhat lower, and the current capability is lowered. Therefore, the gate width of the N-channel transistor T1 (n-1) is increased so that current can flow. That is an effective means. Further, since the voltage supplied to the last stage capacitor Cq is at the Vcc level, it is also an effective means to make the capacity of the capacitor Cq larger than that of other auxiliary pump capacitors. Furthermore, it is also an effective means to set the amplitude of the voltage supplied to the capacitor Cq to 2 × Vcc level.

  In the present embodiment, the 4 × Vcc level, 3 × Vcc level, 2 × Vcc level, Vcc level from the (n−3) th stage pump to the nth (final) stage pump, This is a case where the circuit is configured to lower the Vcc level for each stage, but is not limited to this. For example, toward the final stage, 4 × Vcc level, 2 × Vcc level (or 3 × Vcc level), The circuit may be configured to be at the Vcc level. Alternatively, two stages of 3 × Vcc levels and two stages of 2 × Vcc levels may be provided. The amplitude level of the voltage supplied to the other end of the capacitors for the main pump and auxiliary pump constituting the several pumps on the output side is different from the capacitors for the main pump and auxiliary pump constituting the pump on the input side. What is necessary is just to comprise a charge pump circuit so that it may become smaller than the amplitude level of the voltage supplied to an end.

<Charge pump circuit (4)>
Hereinafter, a four-phase clock drive charge pump circuit according to a fourth embodiment of the present invention will be described with reference to FIG. FIG. 6 is a circuit diagram showing a configuration of a four-phase clock drive charge pump circuit in the present embodiment. Note that in this embodiment, differences from the charge pump circuit in FIG. 4 will be described.

  One end of capacitors corresponding to capacitors Cq1, Cq2, and Cq3 corresponding to capacitors Cs (n−1), Csn, and Cq is connected to gates of Nch transistors T1 (n−1), T1n, and T1 (n + 1). .

  A quadruple booster circuit E2 (n-1) is provided between the other end of the capacitor Cq1 and the clock terminal CIN4 to boost the clock signal PH4 by four times and supply the clock signal PH4 to the other end of the capacitor Cq1. Yes. Between the other end of the capacitor Cq2 and the clock terminal CIN3, there is provided a triple boosting circuit E2n that boosts the clock signal PH3 by three times and supplies the clock signal PH3 to the other end of the capacitor Cq2. A double booster circuit E2 (n + 1) is provided between the other end of the capacitor Cq3 and the clock terminal CIN4 to boost the amplitude of the clock signal PH4 twice and supply the clock signal PH4 to the other end of the capacitor Cq3.

  In FIG. 6, in the pumps from the first stage to the (n-3) th stage, the amplitude levels of the voltages supplied to the other ends of the main pump capacitor and the auxiliary pump capacitor constituting the same pump are the same. It is configured as follows. Further, in the pumps from the (n−2) th stage to the nth stage, the amplitude level of the voltage supplied to the other end of the auxiliary pump capacitor is at the other end of the main pump capacitor constituting the same pump. It is configured to be Vcc level larger than the amplitude level of the supplied voltage. Further, the amplitude of the voltage supplied to the main pump capacitor constituting the (n-2) th stage pump in order from the (n-2) th stage pump is lowered to the Vcc level. The auxiliary pump capacitors constituting the same pumps as the main pump capacitors C1, C2,..., C (n-3), Cp1, Cp2, and Cp3 are capacitors Cs2, Cs3,. -2), Cq1, Cq2, and Cq3.

  According to the present embodiment described above, substantially the same effect as that of the charge pump circuit of FIG. 4 can be obtained, and a voltage having an amplitude of 4 × Vcc level is supplied to the other end of the capacitor Cq1, so that the circuit portion is related. Is superior to the charge pump circuit of FIG. 4 in that voltage drop is not a problem.

  In the pump from the (n−2) -th stage to the n-th stage, the difference between the amplitude levels of the voltages supplied to the main pump capacitor and the auxiliary pump capacitor is set to the Vcc level. The level is not limited to 2 × Vcc level. In this embodiment, the amplitude of the voltage supplied to the main pump capacitor from the (n-3) th stage pump to the nth stage (final stage) pump is set to 4 × Vcc level, 3 × This is a case where the circuit is configured so that the Vcc level, the 2 × Vcc level, the Vcc level, and the Vcc level are lowered for each stage. However, the present invention is not limited to this. For example, the circuit may be configured so that the 4 × Vcc level, 2 × Vcc level (or 3 × Vcc level), Vcc level, and amplitude level decrease toward the final stage. Alternatively, two stages of 3 × Vcc levels and two stages of 2 × Vcc levels may be provided.

  The circuit configuration of the booster circuit of the present invention that can be applied to the charge pump circuit whose circuit diagram is shown in FIGS. 1, 3, 4, and 6 will be described below with reference to the drawings. The clock signal CLK corresponds to the clock signals CLK and PH1 to PH4.

<Boost circuit (1)>
Hereinafter, a double booster circuit according to a fifth embodiment of the present invention will be described with reference to FIG. FIG. 7 is a circuit diagram showing a configuration of a double booster circuit according to the fifth embodiment. Note that the amplitude of the clock signal CLK to be used is Vcc.

  There is an Nch transistor NTR101 for charging whose threshold value is set to approximately zero volts. The gate of the Nch transistor NTR101 is connected to its own drain (diode connection), and the power supply voltage Vcc is supplied to the gate and drain. There is a capacitor C101, one end is connected to the source of the Nch transistor NTR101, and the other end is connected to the clock terminal CIN (terminal to which the clock signal CLK is input).

  There is an inverter circuit INV102, which includes a Pch transistor PTR102 and an Nch transistor NTR102. The base (N-Well) of the Pch transistor PTR102 is connected to its own source. The gate of the Pch transistor PTR102 and the gate of the Nch transistor NTR102 are connected, and the connection point (the input part of the inverter circuit INV102) is connected to the output part of the inverter circuit INV101, and the input part of the inverter circuit INV101 is the clock. Since it is connected to the terminal CIN, the inverted signal / CLK of the clock signal CLK is input to the input portion of the inverter circuit INV102. The drain of the Pch transistor PTR102 and the drain of the Nch transistor NTR102 are connected, and the connection point (the output part of the inverter circuit INV102) is connected to the output terminal COUT of the double booster circuit. The source of the Pch transistor PTR102, that is, the power supply terminal of the inverter circuit INV102 is connected to one end of the capacitor C101. The source of the Nch transistor NTR102 is grounded.

  Next, the circuit operation of the double booster circuit whose circuit configuration has been described with reference to FIG. 7 will be described. When clock signal CLK is at L level, inverted signal / CLK of clock signal CLK is at H level, and H level is input to the gates of Nch transistor NTR102 and Pch transistor PTR102, so that Nch transistor NTR102 is turned on and Pch transistor The PTR 102 is turned OFF, and a ground level signal is output to the output terminal COUT. At this time, the diode-connected Nch transistor NTR101 is turned ON, the capacitor C101 is charged with the power supply voltage Vcc through the Nch transistor NTR101, and the charge amount corresponding to Vcc is stored.

  Thereafter, when the clock signal CLK becomes H level, the potential of the node NV2 becomes approximately 2 × Vcc, and the diode-connected Nch transistor NTR101 is turned OFF. Further, inverted signal / CLK becomes L level, and L level is input to the gates of Nch transistor NTR102 and Pch transistor PTR102. Therefore, Nch transistor NTR102 is turned OFF and Pch transistor PTR102 is turned ON. Then, the 2 × Vcc level signal is output to the output terminal COUT through the Pch transistor PTR102 which is turned ON.

  By repeating the above operation, a clock signal in which the amplitude of the clock signal CLK is doubled is output from the output terminal COUT.

  According to the present embodiment described above, a double boosting circuit that boosts the amplitude of the clock signal CLK twice and outputs a clock signal with an amplitude of 2 × Vcc is realized with a simple configuration with a small number of elements. be able to. Since the number of elements of the double booster circuit is small, there is an advantage that the area required for the double booster circuit is small.

<Boost circuit (2)>
Hereinafter, a quadruple booster circuit according to a sixth embodiment of the present invention will be described with reference to FIG. FIG. 8 is a circuit diagram showing a configuration of a quadruple booster circuit in the sixth embodiment. However, the quadruple booster circuit of FIG. 8 is an application of the double booster circuit of FIG. Note that the amplitude of the clock signal CLK to be used is Vcc.

  The quadruple booster circuit shown in FIG. 8 includes a three-stage booster circuit unit. The first-stage booster circuit section includes a charging Nch transistor NTR101a, a capacitor C101a, and an inverter circuit INV102a. The gate of the Nch transistor NTR101a is connected to its own drain (diode connection), and the power supply voltage Vcc is supplied to the gate and drain. One end of the capacitor C101a is connected to the source of the Nch transistor NTR101a, and the other end is connected to the clock terminal CIN.

  The inverter circuit INV102a is composed of a Pch transistor PTR102a and an Nch transistor NTR102a. The base (N-Well) of the Pch transistor PTR102a is connected to its own source. The gate of the Pch transistor PTR102a and the gate of the Nch transistor NTR102a are connected, the connection point (the input part of the inverter circuit INV102a) is connected to the output part of the inverter circuit INV101, and the input part of the inverter circuit INV101 is the clock Since it is connected to the terminal CIN, the inverted signal / CLK of the clock signal CLK is input to the input portion of the inverter circuit INV102a. The drain of the Pch transistor PTR102a and the drain of the Nch transistor NTR102a are connected, and the connection point (the output part of the inverter circuit INV102a) is connected to the drain of an Nch transistor NTR101b, which will be described later, in the second stage booster circuit part. . The source of the Pch transistor PTR102a, that is, the power supply terminal is connected to one end of the capacitor C101a. The source of the Nch transistor NTR102a is grounded.

  The second-stage booster circuit section includes a charging Nch transistor NTR101b, a capacitor C101b, and an inverter circuit INV102b. The gate of the Nch transistor NTR101b is connected to its own drain (diode connection), and the output part of the inverter circuit INV102a of the first-stage booster circuit part is connected to the gate and drain. One end of the capacitor C101b is connected to the source of the Nch transistor NTR101b, the other end is connected to the output part of the inverter circuit INV101, and the input part of the inverter circuit INV101 is connected to the clock terminal CIN. An inverted signal / CLK of the clock signal CLK is supplied to the other end.

  The inverter circuit INV102b includes a Pch transistor PTR102b and an Nch transistor NTR102b. The base (N-Well) of the Pch transistor PTR102b is connected to its own source. The gate of the Pch transistor PTR102b and the gate of the Nch transistor NTR102b are connected, and the connection point (the input part of the inverter circuit INV102b) is connected to the clock terminal CIN. The drain of the Pch transistor PTR102b and the drain of the Nch transistor NTR102b are connected, and the connection point (the output part of the inverter circuit INV102b) is connected to the drain of an Nch transistor NTR101c, which will be described later, in the third stage booster circuit part. . The source of the Pch transistor PTR102b, that is, the power supply terminal is connected to one end of the capacitor C101b. The source of the Nch transistor NTR102b is grounded.

  The third-stage booster circuit section includes a charging Nch transistor NTR101c, a capacitor C101c, and an inverter circuit INV102c. The gate of the Nch transistor NTR101c is connected to its own drain (diode connection), and the output part of the inverter circuit 102b of the second-stage booster circuit part is connected to the gate and drain. One end of the capacitor C101c is connected to the source of the Nch transistor NTR101c, and the other end is connected to the clock terminal CIN.

  The inverter circuit INV102c includes a Pch transistor PTR102c and an Nch transistor NTR102c. The base (N-Well) of the Pch transistor PTR102c is connected to its own source. The gate of the Pch transistor PTR102c and the gate of the Nch transistor NTR102c are connected, and the connection point (the input part of the inverter circuit INV102c) is connected to the output part of the inverter circuit INV101, and the input part of the inverter circuit INV101 is the clock. Since it is connected to the terminal CIN, the inverted signal / CLK of the clock signal CLK is input to the input portion of the inverter circuit INV102c. The drain of the Pch transistor PTR102c and the drain of the Nch transistor NTR102c are connected, and the connection point (the output part of the inverter circuit INV102c) is connected to the output terminal COUT. The source of the Pch transistor PTR102c, that is, the power supply terminal is connected to one end of the capacitor C101c. The source of the Nch transistor NTR102c is grounded. For example, here, the threshold values of the charging Nch transistors NTR101a, NTR101b, and NTR101c are set to approximately zero volts.

  Next, the circuit operation of the quadruple booster circuit whose circuit configuration has been described with reference to FIG. 8 will be described. In the first-stage booster circuit portion, when the clock signal CLK is at the L level, the inverted signal / CLK of the clock signal CLK is at the H level, and the H level is input to the gates of the Nch transistor NTR102a and the Pch transistor PTR102a. The Nch transistor NTR102a is turned on, the Pch transistor PTR102a is turned off, and a ground level signal is output from the output section of the inverter circuit 102a. At this time, the diode-connected Nch transistor NTR101a is turned on, the capacitor C101a is charged with the power supply voltage Vcc through the Nch transistor NTR101a, and a charge amount corresponding to Vcc is stored.

  Thereafter, when the clock signal CLK becomes H level, the potential of the node NV2 becomes approximately 2 × Vcc, and the diode-connected Nch transistor NTR101a is turned off. Further, inverted signal / CLK becomes L level, and L level is input to the gates of Nch transistor NTR102a and Pch transistor PTR102a. Therefore, Nch transistor NTR102a is turned off and Pch transistor PTR102a is turned on. Then, the 2 × Vcc level signal is output from the output section of the inverter circuit 102a through the Pch transistor PTR102a which is turned on.

  That is, when the clock signal CLK is at L level, the first stage booster circuit unit outputs a ground level signal to the drain of the Nch transistor NTR101b of the second stage booster circuit unit, and when the clock signal is at H level, A 2 × Vcc level signal is output to the drain of the Nch transistor NTR101b in the second-stage booster circuit section.

  In the second-stage booster circuit portion, when the clock signal CLK is at the H level, the H level is input to the gates of the Nch transistor NTR102b and the Pch transistor PTR102b, so the Nch transistor NTR102b is turned on and the Pch transistor PTR102b is turned off. A ground level signal is output from the output section of the inverter circuit 102b. At this time, the diode-connected Nch transistor NTR101b is turned on, and the capacitor C101b is charged with a voltage of 2 × Vcc level supplied from the first-stage booster circuit section through the Nch transistor NTR101b, and a charge amount corresponding to 2 × Vcc. Is stored.

  Thereafter, when the clock signal CLK becomes L level, the potential of the node NV3 becomes approximately 3 × Vcc, and the diode-connected Nch transistor NTR101b is turned OFF. At this time, since the L level is input to the gates of the Nch transistor NTR102b and the Pch transistor PTR102b, the Nch transistor NTR102b is turned off and the Pch transistor PTR102b is turned on. Then, the 3 × Vcc level signal is output from the output section of the inverter circuit 102b through the Pch transistor PTR102b which is turned on.

  That is, when the clock signal CLK is at the H level, the second stage booster circuit unit outputs a ground level signal to the drain of the Nch transistor NTR101c of the third stage booster circuit unit, and when the clock signal is at the L level, A 3 × Vcc level signal is output to the drain of the Nch transistor NTR101c in the third-stage booster circuit section.

  In the third step-up circuit unit, when the clock signal CLK is at the L level, the inverted signal / CLK of the clock signal CLK is at the H level, and the H level is input to the gates of the Nch transistor NTR102c and the Pch transistor PTR102c. The Nch transistor NTR102c is turned on, the Pch transistor PTR102c is turned off, and a ground level signal is output from the output section of the inverter circuit 102c. At this time, the diode-connected Nch transistor NTR101c is turned on, and the capacitor C101c is charged with a voltage of 3 × Vcc level supplied from the second-stage booster circuit through the Nch transistor NTR101a. Is stored.

  Thereafter, when the clock signal CLK becomes H level, the potential of the node NV4 becomes approximately 4 × Vcc, and the diode-connected Nch transistor NTR101c is turned off. Further, inverted signal / CLK becomes L level, and L level is input to the gates of Nch transistor NTR102c and Pch transistor PTR102c. Therefore, Nch transistor NTR102c is turned off and Pch transistor PTR102c is turned on. Then, the 4 × Vcc level signal is output from the output section of the inverter circuit 102c through the Pch transistor PTR102c which is turned on.

  That is, when the clock signal CLK is at the L level, the third-stage booster circuit unit outputs a ground level signal to the output terminal COUT, and when the clock signal is at the H level, the 4 × Vcc level signal is output to the output terminal COUT. Is output.

  By repeating the above operation, a clock signal in which the amplitude of the clock signal CLK is quadrupled is output from the output terminal COUT.

  According to the present embodiment described above, a quadruple boosting circuit that boosts the amplitude of the clock signal CLK four times and outputs a clock signal having an amplitude of 4 × Vcc is realized with a simple configuration with a small number of elements. be able to. Since the number of elements of the quadruple booster circuit is small, there is an advantage that the area required for the quadruple booster circuit is small.

  Note that a triple booster circuit that outputs a clock signal having an amplitude of 3 × Vcc can be realized by using the first booster circuit unit and the second booster circuit unit. The first-stage booster circuit unit, the second-stage booster circuit unit, the third-stage booster circuit unit, the fourth-stage booster circuit unit (corresponding to the second-stage booster circuit unit), and the fifth-stage booster circuit unit Circuit part (corresponding to the second booster circuit part), sixth booster circuit part (corresponding to the second booster circuit part), seventh booster circuit part (corresponding to the second booster circuit part) ),..., An n-fold booster circuit can be realized by using the (n−1) -th booster circuit unit. Note that the outputs of the triple booster circuit, the fivefold booster circuit, the sevenfold booster circuit,... Are inverted from the clock signal CLK. Therefore, when applied to the charge pump circuit described above, an inverter that inverts the output. It is necessary to consider such as

<Boost circuit (3)>
Hereinafter, a quadruple booster circuit according to a seventh embodiment of the present invention will be described with reference to FIG. FIG. 9 is a circuit diagram showing a configuration of a quadruple booster circuit in the seventh embodiment. However, the quadruple booster circuit of FIG. 9 is an application of the double booster circuit of FIG. Note that the amplitude of the clock signal CLK to be used is Vcc.

  The quadruple booster circuit shown in FIG. 9 includes a three-stage booster circuit unit. The first-stage booster circuit section includes a charging Nch transistor NTR101d, a capacitor C101d, and an inverter circuit INV102d. The gate of the Nch transistor NTR101d is connected to its own drain (diode connection), and the power supply voltage Vcc is supplied to the gate and drain. One end of the capacitor C101d is connected to the source of the Nch transistor NTR101d, and the other end is connected to the clock terminal CIN.

  The inverter circuit INV102d is composed of a Pch transistor PTR102d and an Nch transistor NTR102d. The base (N-Well) of the Pch transistor PTR102d is connected to its own source. The gate of the Pch transistor PTR102d and the gate of the Nch transistor NTR102d are connected, and the connection point (the input part of the inverter circuit INV102d) is connected to the output part of the inverter circuit INV101, and the input part of the inverter circuit INV101 is the clock. Since it is connected to the terminal CIN, the inverted signal / CLK of the clock signal CLK is input to the input portion of the inverter circuit INV102d. The drain of the Pch transistor PTR102d and the drain of the Nch transistor NTR102d are connected, and the connection point (the output part of the inverter circuit INV102d) is connected to the other end of a capacitor C101e described later in the second stage booster circuit part. . The source of the Pch transistor PTR102d, that is, the power supply terminal is connected to one end of the capacitor C101d. The source of the Nch transistor NTR102d is grounded.

  The second-stage booster circuit section includes a charging Nch transistor NTR101e, a capacitor C101e, and an inverter circuit INV102e. The gate of the Nch transistor NTR101e is connected to its own drain (diode connection), and the power supply voltage Vcc is supplied to the gate and drain. One end of the capacitor C101e is connected to the source of the Nch transistor NTR101e, and the other end is connected to the output part of the inverter circuit INV102d of the first-stage booster circuit part.

  The inverter circuit INV102e includes a Pch transistor PTR102e and an Nch transistor NTR102e. The base (N-Well) of the Pch transistor PTR102e is connected to its own source. The gate of the Pch transistor PTR102e and the gate of the Nch transistor NTR102e are connected, and the connection point (the input part of the inverter circuit INV102e) is connected to the output part of the inverter circuit INV101. The input part of the inverter circuit INV101 is the clock. Since it is connected to the terminal CIN, the inverted signal / CLK of the clock signal CLK is input to the input portion of the inverter circuit INV102e. The drain of the Pch transistor PTR102e and the drain of the Nch transistor NTR102e are connected, and the connection point (the output part of the inverter circuit INV102e) is connected to the other end of a capacitor C101f described later in the third stage booster circuit part. . The source of the Pch transistor PTR102e, that is, the power supply terminal is connected to one end of the capacitor C101e. The source of the Nch transistor NTR102e is grounded.

  The third-stage booster circuit section includes a charging Nch transistor NTR101f, a capacitor C101f, and an inverter circuit INV102f. The gate of the Nch transistor NTR101f is connected to its own drain (diode connection), and the power supply voltage Vcc is supplied to the gate and drain. One end of the capacitor C101f is connected to the source of the Nch transistor NTR101f, and the other end is connected to the output part of the inverter circuit INV102e of the second-stage booster circuit part.

  The inverter circuit INV102f includes a Pch transistor PTR102f and an Nch transistor NTR102f. The base (N-Well) of the Pch transistor PTR102f is connected to its own source. The gate of the Pch transistor PTR102f and the gate of the Nch transistor NTR102f are connected, and the connection point (input part of the inverter circuit INV102f) is connected to the output part of the inverter circuit INV101, and the input part of the inverter circuit INV101 is the clock. Since it is connected to the terminal CIN, the inverted signal / CLK of the clock signal CLK is input to the input portion of the inverter circuit INV102f. The drain of the Pch transistor PTR102f and the drain of the Nch transistor NTR102f are connected, and the connection point (the output part of the inverter circuit INV102f) is connected to the output terminal COUT. The source of the Pch transistor PTR102f, that is, the power supply terminal is connected to one end of the capacitor C101f. The source of the Nch transistor NTR102f is grounded.

  Next, the circuit operation of the quadruple booster circuit whose circuit configuration has been described with reference to FIG. 9 will be described. When the clock signal CLK is at L level, the output of the inverter circuit INV101 becomes H level, and the H level is input to the input part of the inverter circuit INV102d. Therefore, the Pch transistor PTR102d is turned off and the Nch transistor NTR102d is turned on. A ground level signal is output from the output section of the INV 102d to the capacitor C101e. At this time, the diode-connected Nch transistor NTR101d is turned on, the capacitor C101d is charged with the power supply voltage Vcc through the Nch transistor NTR101d, and a charge amount corresponding to Vcc is stored.

  During the same period, since the H level is input to the input part of the inverter circuit INV102e, the Pch transistor PTR102e is turned OFF, the Nch transistor NTR102e is turned ON, and a ground level signal is output from the output part of the inverter circuit 102e to the capacitor C101f. The At this time, the diode-connected Nch transistor PTR101e is turned on, the capacitor C101e is charged with the power supply voltage Vcc through the Nch transistor PTR101e, and a charge amount corresponding to Vcc is stored.

  Furthermore, since the H level is input to the input part of the inverter circuit INV102f during the same period, the Pch transistor PTR102f is turned OFF, the Nch transistor NTR102f is turned ON, and a ground level signal is output from the inverter circuit 102f to the output terminal COUT. The At this time, the diode-connected Nch transistor NTR101f is turned on, the capacitor C101f is charged with the power supply voltage Vcc through the Nch transistor NTR101f, and the charge amount corresponding to Vcc is stored.

  Thereafter, when the clock signal CLK becomes H level, the potential of the node NV2 becomes approximately 2 × Vcc, and the Nch transistor NTR101d is turned off. At this time, since the L level is input to the input part of the inverter circuit INV102d, the Pch transistor PTR102d is turned on, the Nch transistor NTR102d is turned off, and the 2 × Vcc level signal is turned on and passes through the Pch transistor PTR102d. Supplied to the other end. As a result, the potential of the node NV3 becomes 3 × Vcc, and the Nch transistor NTR101e is turned off. At this time, since the L level is input to the input part of the inverter circuit INV102e, the Pch transistor PTR102e is turned on, the Nch transistor NTR102e is turned off, and the signal of the 3 × Vcc level passes through the Pch transistor PTR102e turned on. Supplied to the other end. As a result, the potential of the node NV4 becomes 4 × Vcc, and the Nch transistor NTR101f is turned OFF. At this time, since the L level is inputted to the input part of the inverter circuit INV102f, the Pch transistor PTR102f is turned on, the Nch transistor NTR102f is turned off, and the 4 × Vcc level signal is turned on and the output terminal COUT is passed through the Pch transistor PTR102f. Is output.

  As described above, according to the present embodiment, the quadruple booster circuit that boosts the amplitude of the clock signal CLK four times and outputs a clock signal having an amplitude of 4 × Vcc with a simple configuration with a small number of elements. Can be realized. Since the number of elements of the quadruple booster circuit is small, there is an advantage that the area required for the quadruple booster circuit is small. Further, since the voltage is boosted to four times the clock signal by one clock, there is an advantage that the clock signal having the quadruple amplitude can be obtained in a short time.

  Note that a triple booster circuit that outputs a clock signal having an amplitude of 3 × Vcc can be realized by using the first booster circuit unit and the second booster circuit unit. In addition, by providing (n−1) booster circuit units, an n-fold booster circuit can be realized.

<Boost circuit (4)>
The quadruple booster circuit according to the eighth embodiment of the present invention will be described below with reference to FIG. FIG. 10 is a circuit diagram showing a configuration of a quadruple booster circuit according to the eighth embodiment. Note that the amplitude of the clock signal CLK to be used is Vcc.

  There are Nch transistors NTR201 to NTR203 whose gates and drains are connected (diode-connected), and a power supply voltage Vcc is supplied to the gate and drain of the Nch transistor NTR201. The sources of the Nch transistors NTR201 and NTR202 are connected to the drains of the Nch transistors NTR202 and NTR203, respectively. The source of the Nch transistor NTR203 is connected to the source of the Pch transistor PTR204.

  There are capacitors C201 to C203. One ends of the capacitors C201 and C202 are connected to connection lines (nodes NV2 and NV3) of the sources of the Nch transistors NTR201 and NTR202 and the drains of the Nch transistors NTR202 and NTR203, respectively. One end of the capacitor C203 is connected to a connection line (node NV4) between the source of the Nch transistor NTR203 and the source of the Pch transistor PTR204. The other ends of the capacitors C201 and C203 are connected to the clock terminal CIN, and the other end of the capacitor C202 is connected to the output portion of the inverter circuit INV201. Since the input part of the inverter circuit INV201 is connected to the clock terminal CIN, the inverted signal / CLK of the clock signal CLK is supplied to the other end of the capacitor C202.

  There is an inverter circuit INV204, which includes a Pch transistor PTR204 and an Nch transistor NTR204. The base (N-Well) of the Pch transistor PTR 204 is connected to its own source. The gate of the Pch transistor PTR204 and the gate of the Nch transistor NTR204 are connected, and the connection point (the input part of the inverter circuit INV204) is connected to the output part of the inverter circuit INV201, and the input part of the inverter circuit INV201 is the clock. Since it is connected to the terminal CIN, the inverted signal / CLK of the clock signal CLK is input to the input portion of the inverter circuit INV204. The drain of the Pch transistor PTR204 and the drain of the Nch transistor NTR204 are connected, and the connection point (the output part of the inverter circuit INV204) is connected to the output terminal COUT of the quadruple booster circuit. The source of the Pch transistor PTR204, that is, the power supply terminal is connected to one end of the capacitor C203. The source of the Nch transistor NTR204 is grounded. Here, the threshold value of the diode-connected Nch transistors NTR201 to NTR203 is set to approximately zero volts.

  Next, the circuit operation of the quadruple booster circuit whose circuit configuration has been described with reference to FIG. 10 will be described. When the clock signal CLK is at L level, the diode-connected Nch transistor NTR201 is turned on, the capacitor C201 is charged through the turned-on Nch transistor NTR201, and the charge of Vcc is stored in the capacitor C201. Thereafter, when the clock signal CLK becomes H level, the potential of the node NV2 becomes 2 × Vcc level, the diode-connected Nch transistor NTR202 is turned on, and the capacitor C202 is charged through the turned-on Nch transistor NTR202, and 2 × Vcc. The charge of the minute is stored. Thereafter, when the clock signal CLK becomes L level, the potential of the node NV3 becomes 3 × Vcc level, the diode-connected Nch transistor NTR203 is turned on, and the capacitor C203 is charged through the turned-on Nch transistor NTR203, and 3 × Vcc. The charge of the minute is stored.

  At this time (the clock signal CLK is at L level), an H level signal is input to the input part of the inverter circuit INV204, the Pch transistor PTR204 is turned OFF, the Nch transistor NTR204 is turned ON, and the output part of the inverter circuit 204 is grounded. A level signal is output to the output terminal COUT. Thereafter, when the clock signal CLK becomes H level, the potential of the node NV4 becomes 4 × Vcc. At this time, L level is input to the input part of the inverter circuit INV204, the Pch transistor PTR204 is turned on, the Nch transistor NTR204 is turned off, and the output of the inverter circuit 204 passes through the Pch transistor PTR204 in which the 4 × Vcc level signal is turned on. To the output terminal COUT.

  As described above, according to the present embodiment, a quadruple booster circuit that boosts the amplitude of the clock signal CLK four times and outputs a clock signal having an amplitude of 4 × Vcc with a simple configuration having a smaller number of elements. Can be realized. Since the number of elements of the quadruple booster circuit is smaller, there is an advantage that the area required for the quadruple booster circuit is smaller.

  By providing (n-1) Nch transistors whose gates and drains are connected (diode-connected) and (n-1) corresponding capacitors, a clock signal having an amplitude of n × Vcc is output. An n-fold booster circuit can be realized. In this case, when (n−1) is an odd number, the inverted signal / CLK is supplied to the input of the inverter circuit, and when (n−1) is an even number, the clock signal CLK is input to the input of the inverter circuit. Supply. Note that the outputs of the triple booster circuit, the fivefold booster circuit, the sevenfold booster circuit,... Are inverted from the clock signal CLK. Therefore, when applied to the charge pump circuit described above, an inverter that inverts the output. It is necessary to consider such as

  The preferred embodiments of the present invention have been described above. However, the present invention is not limited to the above-described embodiments, and various design changes can be made as long as they are described in the claims.

T1-T (n + 1) N-channel transistors,
C1-C (n-3), Cp1-Cp3, Cs1-Csn, Cq capacitors,
A1 to A (n-1) double booster circuit

Claims (2)

First to (n + 1) -th transfer transistors connected in series;
First to n-th main pump capacitors having one ends connected between the i-th (i = 1 to n) transfer transistor and the (i + 1) -th transfer transistor;
First to (n + 1) th auxiliary pump capacitors connected to the gates of the first to (n + 1) th transfer transistors;
In a four-phase clock drive charge pump circuit comprising:
The amplitude of the pulse voltage supplied to the other end of the first to j-th (p is smaller than n) main pump capacitors is the same, and is supplied to the other end of the (j + 1) -th to n-th main pump capacitors. A pulse voltage whose amplitude is smaller than that of the pulse voltage supplied to the other end of the first to j-th main pump capacitors is supplied to the other end of the first to n-th main pump capacitors. First voltage supply means;
The amplitude of the pulse voltage supplied to the other end of the first to kth auxiliary pump capacitors (k is a value smaller than n) is adjusted by the first voltage supply means to the first to jth main pump capacitors. The amplitude of the pulse voltage supplied to the other end of the (k + 1) th to (n + 1) th auxiliary pump capacitors is the same as the amplitude of the pulse voltage supplied to the other end. Second voltage supply means for supplying a pulse voltage smaller than the amplitude of the pulse voltage supplied to the end to the other end of the first to (n + 1) th auxiliary pump capacitors;
Equipped with a,
The value of k is one greater than the value of j;
The first voltage supply means determines the amplitude of the pulse voltage supplied to the other end of the (j + 1) th to nth main pump capacitors from the (j + 1) main pump capacitor to the nth main pump. In order of capacitor for the power supply, the power supply voltage amplitude is reduced sequentially,
The second voltage supply means determines the amplitude of the pulse voltage supplied to the other ends of the (k + 1) th to (n + 1) th auxiliary pump capacitors from the (k + 1) th auxiliary pump capacitor. The four-phase clock drive charge pump circuit is characterized in that the amplitude of the power supply voltage is sequentially decreased in the order of the auxiliary pump capacitors . First to (n + 1) -th transfer transistors connected in series;
First to n-th main pump capacitors having one ends connected between the i-th (i = 1 to n) transfer transistor and the (i + 1) -th transfer transistor;
First to (n + 1) th auxiliary pump capacitors connected to the gates of the first to (n + 1) th transfer transistors;
In a four-phase clock drive charge pump circuit comprising:
The amplitude of the pulse voltage supplied to the other end of the first to j-th (p is smaller than n) main pump capacitors is the same, and is supplied to the other end of the (j + 1) -th to n-th main pump capacitors. A pulse voltage whose amplitude is smaller than that of the pulse voltage supplied to the other end of the first to j-th main pump capacitors is supplied to the other end of the first to n-th main pump capacitors. First voltage supply means;
The amplitude of the pulse voltage supplied to the other end of the first to kth auxiliary pump capacitors (k is a value smaller than n) is adjusted by the first voltage supply means to the first to jth main pump capacitors. The amplitude of the pulse voltage supplied to the other end of the (k + 1) th to (n + 1) th auxiliary pump capacitors is the same as the amplitude of the pulse voltage supplied to the other end. Second voltage supply means for supplying a pulse voltage smaller than the amplitude of the pulse voltage supplied to the end to the other end of the first to (n + 1) th auxiliary pump capacitors;
With
The value of k is 2 larger than the value of j;
The first voltage supply means determines the amplitude of the pulse voltage supplied to the other end of the (j + 1) th to nth main pump capacitors from the (j + 1) main pump capacitor to the nth main pump. In order of capacitor for the power supply, the power supply voltage amplitude is reduced sequentially,
The second voltage supply means determines the amplitude of the pulse voltage supplied to the other ends of the (k + 1) th to (n + 1) th auxiliary pump capacitors from the (k + 1) th auxiliary pump capacitor. The four-phase clock drive charge pump circuit is characterized in that the amplitude of the power supply voltage is sequentially decreased in the order of the auxiliary pump capacitors .

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