JP5235025B2 - Amplifier circuit - Google Patents

Description

  The present invention relates to an amplifier circuit having low noise and excellent linearity.

FIG. 4 is a circuit diagram of a conventional amplifier circuit 400 proposed as an amplifier circuit having excellent linearity (see, for example, non-patent literature).
The amplifier circuit 400 is configured to supply a bias to the power amplifier 410 from the adaptive bias generator 420.
In the power amplifier 410, a load resistor ZL is connected between the drain of the NMOS transistor M1 and the power supply VDD, an RF input terminal RFIN to which an RF input signal is input is provided at the gate, and an RF output signal is provided at the source. This constitutes a common source amplifier provided with an output RF output terminal RFOUT.

The adaptive bias generator 420 is configured such that a resistor R1 is connected between the gate of the NMOS transistor M2 and the adaptive bias input terminal G, and a diode is connected between the drain and gate of the NMOS transistor M2 via the resistor R2. ing.
Then, a bias is supplied to the power amplifier 410 so that the output from the source of the NMOS transistor M2 of the adaptive bias generator 420 is applied to the gate of the NMOS transistor M1.

  In the circuit as shown in FIG. 4, when the potential of the adaptive bias input terminal G in the adaptive bias generator 420 is Vg, it is desirable that Vg be class C biased from the viewpoint of current consumption and linearity. That is, it is ideal that Vg> V (RFIN) + Vth (M2) is set. Here, V (RFIN) is the voltage of the RF input signal at the RF input terminal RFIN, and Vth (M2) is the threshold voltage of the NMOS transistor M2.

Next, the operation of the circuit of the conventional amplifier circuit 400 will be described with reference to FIG. FIG. 5 is a diagram for explaining the operation of the circuit of FIG.
FIG. 5A is a diagram showing the relationship between the RF input voltage V (RFIN) when the amplitude of the RF input signal to the power amplifier 410 is small and the current Iadp generated in the NMOS transistor M2 of 131.
In FIG. 5A, VAVE (RFIN) is an average value of the RF input voltage. As shown in this figure, when the amplitude of the RF input signal to the power amplification unit 410 is small, the MOS diode composed of the NMOS transistor M2 and the resistor R2 of the adaptive bias generation unit 420 is class C biased. Is retained. Therefore, the current Iadp does not flow.
FIG. 5B shows the relationship between the RF input voltage V (RFIN) when the amplitude of the RF input signal to the power amplifier 410 is large and the current Iadp generated in the NMOS transistor M2 of the adaptive bias generator 420. It is.

As shown in FIG. 5B, when the RF input signal to the power amplifying unit 410 is large, a moment occurs when the potential Vg of the input terminal G of the adaptive bias generating unit 420 is pulled to the lower side. That is, when the gate-source voltage of the NMOS transistor M2 of the adaptive bias generator 420 is Vgs (M2),
Vgs (M2) = Vg−V (RFIN)> Vth (M2)
The moment when is established occurs. Only at that moment, the NMOS transistor M2 is turned on, and the current Iadp flows. Therefore, the potential of the gate of the NMOS transistor M1 of the power amplifying unit 410 is increased by the amount of charge corresponding to the flowing current Iadp, and the gate-source voltage Vgs (M1) of the NMOS transistor M1 is increased.

Here, assuming that the threshold voltage of the NMOS transistor M1 is Vth (M1), the linearity of the MOS transistor is high if Vgs (M1) −Vth (M1) is high. Therefore, according to the configuration shown in FIG. 4, the linearity of the NMOS transistor M1 is improved, and as a result, the linearity of the amplifier circuit 400 of FIG. 4 is improved.
As described above, the amplifying circuit 400 of FIG. 4 includes the power amplifying unit only when the MOS diode including the NMOS transistor M2 and the resistor R2 of the adaptive bias generating unit 420 is on, that is, when the amplitude of the RF input signal is large. The current flowing through 410 is increased. Therefore, the power amplifier circuit 400 has low noise (low distortion) and excellent power efficiency. Further, since the elements constituting the adaptive bias generator 420 are formed by elements (MOS transistors) having the same specifications as the elements constituting the power amplifier 410, there is no variation in characteristics due to process variations. Not affected.

  The adaptive bias generator 420 described with reference to FIG. 4 functions as a so-called predistorter. Since the distortion characteristic of the adaptive bias generation unit 420 has a distortion characteristic that is opposite in phase to the distortion characteristic of the power amplification unit 410, the above-described adaptive bias generation unit 420 is added to the power amplification unit 410 to increase the overall amplification circuit 400. Distortion characteristics are improved.

IEEE Microwaves & Wireless Component Letters (MWCL) 2003 "A 0.25uM10dBM1.4GHz CMOS Power Amplifier with an Integrated Diode Linearizer" Chemg-Chi Yen, Huey-Ru Chuang.

However, in the conventional amplifying circuit as described above, the threshold voltage between the NMOS transistor M1 of the power amplifying unit and the NMOS transistor M2 of the bias unit is shifted due to heat generated by the power amplifying unit, and the characteristics satisfying a certain specification are satisfied. The problem remains that it cannot be obtained.
As a measure against this problem, it is conceivable to reduce the influence by changing the layout, for example, by providing a fixed bias generator and arranging the NMOS transistor M2 of the fixed bias generator inside the NMOS transistor M1 of the power amplifier. However, especially in the case of high-frequency applications, the difference in size between the NMOS transistor M2 and the NMOS transistor M1 is significant and the resistors R1 and R2 are involved. It is not a practical measure.
The present invention has been made in view of such an unsolved problem, and corrects the difference in characteristics caused by the temperature difference between the NMOS transistor of the power amplifier and the NMOS transistor of the bias unit, and is constant over a wide temperature range. It is an object of the present invention to provide an amplifier circuit that can maintain characteristics satisfying specifications.

In order to achieve the above object, the following techniques are proposed here.
(1) An amplifying circuit configured to supply a bias to a power amplifying unit from a bias generating unit, wherein the power amplifying unit is supplied with an input signal at a gate, a load resistor is connected to a drain, and output from the drain The bias generator includes a first resistance element having a predetermined voltage supplied to one end thereof, and a second MOS transistor having a gate connected to the other end of the first resistance element. And a second resistance element having one end connected to the gate of the second MOS transistor and the other end connected to the drain of the second MOS transistor. The second MOS transistor has a gate-source voltage and a threshold voltage. Current control means for controlling the current flowing through the first resistance element according to the difference between the second MOS transistor and the source of the second MOS transistor. Is configured to supply the bias to the power amplifier from a first temperature sensor for measuring the operating temperature of the first 1MOS transistor, a second temperature sensor for measuring the operating temperature of the first 2MOS transistor, said first 2. A heating element that generates heat for adjusting the environmental temperature of the MOS transistor, an output of the first temperature sensor, and an output of the second temperature sensor 2 are compared, and the heating of the heating element is based on the comparison result. And a voltage generator for controlling the amount.

  In the amplifier circuit of (1) above, the voltage generator generates a position near the MOS transistor M2 according to the difference between the operating temperature T1 of the first MOS transistor of the power amplifier and the temperature T2 of the MOS transistor M2 of the adaptive bias generator 120. By controlling the amount of heat generated by the heating element RH arranged in the circuit, the operating temperatures of both NMOS transistors M1 and M2 are adjusted to be equal, and the NMOS transistor M1 can operate under a bias condition that can maintain linearity. To do.

(2) The amplification circuit according to (1), wherein the voltage generator controls the amount of heat generated by the heating element so that the temperatures detected by the first temperature sensor and the second temperature sensor are equal.
In the amplifier circuit of (2), in particular, the voltage generator controls the amount of heat generated by the heating element so that the detected temperatures of the first temperature sensor and the second temperature sensor are equal. Therefore, the temperature is adjusted so that the operating temperatures of both NMOS transistors M1 and M2 are equal.

(3) The voltage generator is
When the temperature detected by the second temperature sensor is lower than the temperature detected by the first temperature sensor, the power supply to the heating element is increased to increase the temperature of the second MOS transistor,
When the temperature detected by the second temperature sensor is higher than the temperature detected by the first temperature sensor, control is performed to reduce the temperature of the second MOS transistor by reducing power supply to the heating element. The amplifier circuit according to (1) or (2).
In the amplifier circuit of (3), in particular, in the amplifier circuit of (1) or (2), the voltage generator is adjusted to increase or decrease the power supply to the heating element. As a result, the temperature of the second MOS transistor Is controlled to be equal to the temperature of the first MOS transistor.

(4) The amplification circuit according to any one of (1) to (3), wherein the heating element includes a resistance element.
In the amplifier circuit of (4) above, particularly in the amplifier circuit of any one of (1) to (3), the heating element has a simple structure having a resistance element and easy control of the amount of generated heat.
(5) The amplification circuit according to (4), wherein the resistance element is a resistance element formed so as to occupy a substantially two-dimensional region on Si.
In the amplification circuit of (5), particularly in the amplification operation of (4), the resistance element of the heating element is a resistance element formed so as to occupy a substantially two-dimensional region on Si and having a predetermined resistance value. Can be manufactured relatively easily.

(6) The amplifying circuit according to (4), wherein the resistance element is a resistance element formed by a deep trench isolation structure or a shallow trench isolation structure formed so as to occupy a three-dimensional region on Si. .
In the amplification circuit of (6), particularly in the amplification operation of (4), the heat generated from such a resistance element is conducted to the depth direction of the second MOS transistor, so that the response characteristic in temperature control is excellent.
(7) The amplifier circuit according to (5) or (6), wherein the resistance element is formed of any one of polysilicon, a diffusion layer, and a well, or a combination thereof.
In the amplifier circuit of (7), particularly in the amplifier circuit of any one of (5) to (6), such a resistance element can be formed in the manufacturing process of the second MOS transistor.

(8) The amplifier according to (5) or (6), wherein the resistance element includes a combination of P-polysilicon and a diffusion layer.
In the amplifier of (8), particularly in the amplifier of (5) or (6), the resistance element is configured as a combination of P-polysilicon and a diffusion layer.
(9) The amplifier according to any one of (1) to (8), further comprising a DC blocking capacitor element that blocks a DC component of the input signal and applies the input signal to a gate of the first MOS transistor. circuit.
In the amplifier of (9), in particular, in the amplifier circuit of any one of (1) to (8), it is possible to realize an amplifier that is not easily affected by fluctuations in the DC component of the input signal by the DC blocking capacitance element.

(10) The amplifier circuit according to any one of (1) to (9), further including a fixed bias generator that generates a fixed bias current supplied to the gate of the first MOS transistor.
In the amplifier circuit of (10) above, particularly in the amplifier circuit of any one of (1) to (9),
The fixed bias generator generates a fixed bias current to be supplied to the gate of the first MOS transistor, and the generated fixed bias current is superimposed on the bias current generated by the adaptive bias generator.

(11) The fixed bias generator includes a bias current source, a third MOS transistor in which a current is supplied to the drain from the bias current source and a gate connected to the drain, and a bias connected to the gate of the third MOS transistor. The amplifier circuit according to (10), further comprising: a bias inductor that applies a current to an input signal.
In the amplifier circuit of (11), particularly in the amplifier circuit of (10), the fixed bias current from the bias current source is applied to the gate of the first MOS transistor via the bias inductor using the current mirror effect by the third MOS transistor. To supply. Thereby, the bias current when the RF input signal is small can be accurately controlled.

  According to the amplifier circuit of the present invention, the characteristic variation parameter of the MOS transistor due to heat generation is controlled by directly measuring the temperature of the MOS diode, and the characteristic caused by the temperature difference between the NMOS transistor of the power amplifier and the NMOS transistor is controlled. An amplifier circuit capable of correcting the difference and maintaining characteristics satisfying a certain specification in a wide temperature range is realized.

It is a circuit diagram showing the structure of the amplifier circuit as the 1st Embodiment of this invention. FIG. 2 is a diagram illustrating an example of a configuration of a main part of the amplifier circuit of FIG. FIG. 3 is a diagram illustrating another example of the configuration of the main part of the amplifier circuit in FIG. 1. It is a circuit diagram showing the structure of the conventional amplifier circuit. FIG. 5 is a diagram for explaining the operation of the amplifier circuit of FIG. 4.

Hereinafter, the present invention will be clarified by describing embodiments of the present invention in detail with reference to the drawings.
(First embodiment)
FIG. 1 is a circuit diagram showing a configuration of an amplifier circuit as one embodiment of the present invention.
The amplifier circuit 100 of FIG. 1 is configured to supply a bias from the fixed bias generator 130 in addition to a configuration to supply a bias from the adaptive bias generator 120 to the power amplifier 110.

  In the power amplifier 110, a load resistor ZL is connected between the drain of the NMOS transistor M1 and the power supply VDD, an RF input terminal RFIN to which an RF input signal is input is provided at the gate, and an RF output signal is provided at the source. This constitutes a common source amplifier provided with an output RF output terminal RFOUT. Note that, in order to obtain output characteristics that are not affected by fluctuations in the DC component in the input signal, the RF input terminal RFIN is connected to the gate of the NMOS transistor M1 via the DC blocking capacitive element CIN. A temperature sensor TS1 for measuring the operating temperature of the NMOS transistor M1 is disposed near the NMOS transistor M1.

  The adaptive bias generator 120 has an adaptive bias input terminal G to which a bias input voltage Vg is applied, and this input terminal G is connected to the gate of the NMOS transistor M2 via a resistor R1. The source and gate of the NMOS transistor M2 are diode-connected via the resistor R2. The source of the NMOS transistor M 2, which is the output terminal of the adaptive bias generator 120, is connected to the gate of the NMOS transistor M 1 of the common source amplifier that constitutes the power amplifier 110. Further, a heating element RH and a temperature sensor TS2 are arranged in the vicinity of the NMOS transistor M2. The heating element RH is for adjusting the environmental temperature of the NMOS transistor M2. The temperature sensor TS2 is for measuring the operating temperature of the NMOS transistor M2.

Furthermore, the adaptive bias generator 120 includes a voltage generator 121 that compares the output T2 of the temperature sensor TS2 with the output T1 of the temperature sensor TS1 and controls the supply voltage to the heating element RH based on the comparison result. ing.
The voltage generator 121 supplies a predetermined voltage according to the control rule shown in the following Table 1 to the heating element RH. As a result of controlling the amount of heat generated by the heating element RH based on the control rule of Table 1, the characteristic difference between the two NMOS transistors M1 and M2 can be reduced to a matching level depending on the device size.

  In Table 1, the principle of control is to make the output T1 of the temperature sensor TS1 equal to the output T2 of the temperature sensor TS2. In general, the device size of the NMOS transistor M1 of the power amplifying unit 110 is large and the power consumption is also large. Therefore, during normal operation, the temperature of the NMOS transistor M1 is higher than the temperature of the NMOS transistor M2. That is, the output T1 of the temperature sensor TS1 is larger than the output T2 of the temperature sensor TS2. When the temperature of the NMOS transistor M2 is low, that is, when the output T2 of the temperature sensor TS2 is small, the voltage generator 121 increases its output voltage VR and increases the power supply to the heating element RH, so that the environment of the NMOS transistor M2 is increased. Increase the temperature. On the contrary, when the temperature of the NMOS transistor M2 becomes higher than the temperature of the NMOS transistor M1 due to the heat generation of the heating element RH, that is, when the output T2 of the temperature sensor TS2 becomes larger than the output T1 of the temperature sensor TS1, The voltage generator 121 decreases the output voltage VR, decreases the power supply to the heating element RH, and decreases the environmental temperature of the NMOS transistor M2.

  Therefore, the voltage VR, which is a control signal supplied to the heating element RH in the vicinity of the NMOS transistor M2 of the adaptive bias generator 120, is controlled by dynamically monitoring the temperature of the operating state of the NMOS transistors M1 and M2. If the operating temperatures of the transistors M1 and M2 are adjusted to be equal, the NMOS transistor M1 can operate under a bias condition capable of maintaining linearity.

In addition, the event essential for control is only the dynamic temperature in the operating state of the NMOS transistors M1 and M2, and does not require any information regarding other events. Therefore, there is no restriction on the signal band related to the stability of the control, so there is no problem when dealing with a wide band of communication.
The heating element RH has a resistance element, is simple, and can easily control the amount of heat generation.
In the present embodiment, as described above, by applying the temperature sensor, the operating environment temperature of the NMOS transistors M1 and M2 to be controlled can be directly measured, so that the control error is small.
Therefore, it is possible to perform control in consideration of errors due to secondary factors such as charge mobility in the NMOS transistor. Therefore, the characteristic parameter difference between the NMOS transistors M1 and M2 due to the temperature difference between the NMOS transistors M1 and M2 can be reduced, and a predetermined output characteristic can be maintained over a wide temperature range.

  On the other hand, in the fixed bias generator 130, the bias current source Ibias is connected between the drain of the NMOS transistor M3 and the power supply VDD, the drain and gate of the NMOS transistor M3 are diode-connected with a short circuit, and further the gate Is connected to the gate of the NMOS transistor M1 of the power amplifier 110 via the gate bias inductor L3. The NMOS transistor M3 supplies its drain current as a bias current of the power amplification unit 110 by the current mirror effect.

  That is, in the fixed bias generator 130, the inductor L3 is used to separate the bias current, and the fixed bias current Ibias from the bias current source Ibias is passed through the inductor L3 using the current mirror effect by the NMOS transistor M3. To the gate of the NMOS transistor M1. By adopting the circuit configuration as described above, the bias current when the RF input signal is small can be accurately controlled, and the efficiency of the power amplifying unit 110, and thus the amplifying circuit 100, can be improved. Furthermore, since the DC bias current of the power amplifier 110 can be set by the current mirror effect, it is possible to realize the amplifier circuit 100 that stably satisfies a certain specification over a wide frequency range.

(Configuration example related to heating element)
Next, with reference to FIG. 2, the structure regarding the heat generating body which is the principal part of embodiment of FIG. 1 is demonstrated.
FIG. 2 is a conceptual diagram illustrating an example of a configuration related to a heating element that is a main part of the amplifier circuit of FIG.
In the example of FIG. 2, the heating element RH1 is formed on Si of the semiconductor device as a resistance element formed so as to occupy a substantially two-dimensional region formed in a planar shape. This resistance element is arranged in the vicinity of the NMOS transistor M2. As a more specific form, it is also possible to arrange so as to surround the periphery. Since it is formed so as to occupy a roughly two-dimensional region in this way, it can be manufactured with a predetermined resistance value relatively easily.
As the resistance element applied here, any one of polysilicon, diffusion layer, and well may be used individually, or a combination thereof may be used. Such a resistance element can be formed in the manufacturing process of the second MOS transistor.

FIG. 3 is a conceptual diagram illustrating another example of a configuration relating to a heating element that is a main part of the amplifier circuit of FIG. 1.
In the example of FIG. 3, a resistance element inside the Si substrate of the semiconductor device is used as a heating element as a three-dimensional heating element. As the resistance element, an element for Deep Trench Isolation (DTI, deep trench isolation structure) is used. Here, in the DTI, a SiO2 film is formed inside a Si trench (groove), and a polysilicon as a resistor is filled therein so as to be covered with the SiO2 film. As the resistance element as a heating element, an element for Shallow Trench Isolation (STI, Shallow Trench Isolation Structure) formed only of SiO 2 may be used. When a resistance element of DTI is used as a heating element, it is preferable to STI from the viewpoint of electrical characteristics and heat generation efficiency. In addition, Trench Isolation elements such as DTI and STI are preferable from the viewpoint of matching with the NMOS transistor M1 because they transmit heat to the depth direction of the NMOS transistor M2 and thus have excellent response characteristics in temperature control.

When a resistor is used as a heating element, there are cases where the variation in the amount of heat generated due to the temperature coefficient of the resistor may be taken into account, but the above fluctuation is mitigated by using a combination of resistors having different positive and negative temperature coefficients. be able to.
Representative resistors and their temperature coefficients are shown in Table 2 below (Source: Didac Gomez, Milosz Sroka, and Jose Luis Gonzalez Jimenez "Process and Temperature Compensation for RF Low-Noise Amplifier and Mixers" IEEE CAS-1 Jun. 2010 pp1204-1211).

  From the example illustrated in Table 2, it is understood that the temperature coefficient can be made small.

Claims (11)

An amplifier circuit configured to supply a bias from a bias generation unit to a power amplification unit,
The power amplifying unit includes a first MOS transistor that is supplied with an input signal at a gate, has a load resistor connected to a drain, and outputs an output signal from the drain;
The bias generator includes a first resistance element having one end supplied with a predetermined voltage, a second MOS transistor having a gate connected to the other end of the first resistance element, and one end connected to the gate of the second MOS transistor. And a second resistance element connected to the drain of the second MOS transistor. The second MOS transistor flows to the first resistance element in accordance with a difference between a gate-source voltage and a threshold voltage. Forming a current control means for controlling a current, configured to supply the bias from the source of the second MOS transistor to the power amplifier;
A first temperature sensor for measuring an operating temperature of the first MOS transistor;
A second temperature sensor for measuring an operating temperature of the second MOS transistor;
A heating element for generating heat for adjusting the environmental temperature of the second MOS transistor;
A voltage generator that compares the output of the first temperature sensor with the output of the second temperature sensor 2 and controls the amount of heat generated by the heating element based on the comparison result;
An amplifier circuit comprising:   2. The amplifier circuit according to claim 1, wherein the voltage generator controls the amount of heat generated by the heating element so that the temperatures detected by the first temperature sensor and the second temperature sensor are equal. The voltage generator is
When the temperature detected by the second temperature sensor is lower than the temperature detected by the first temperature sensor, the power supply to the heating element is increased to increase the temperature of the second MOS transistor,
When the temperature detected by the second temperature sensor is higher than the temperature detected by the first temperature sensor, control is performed to reduce the temperature of the second MOS transistor by reducing power supply to the heating element. The amplifier circuit according to claim 1 or 2.   The amplification circuit according to claim 1, wherein the heating element includes a resistance element.   5. The amplifier circuit according to claim 4, wherein the resistance element is a resistance element formed so as to occupy a substantially two-dimensional region on Si.   5. The amplifier circuit according to claim 4, wherein the resistance element is a resistance element formed by a deep trench isolation structure or a shallow trench isolation structure formed so as to occupy a three-dimensional region on Si.   The amplifier circuit according to claim 5, wherein the resistance element is formed of any one of polysilicon, a diffusion layer, and a well, or a combination thereof.   7. The amplifier according to claim 5, wherein the resistance element is composed of a combination of P-type polysilicon and a P-type diffusion layer.   9. The amplifier circuit according to claim 1, further comprising a DC blocking capacitor element that blocks a DC component of the input signal and applies the input signal to a gate of the first MOS transistor. 10.   10. The amplifier circuit according to claim 1, further comprising a fixed bias generation unit that generates a fixed bias current supplied to the gate of the first MOS transistor. 11.   The fixed bias generator includes a bias current source, a third MOS transistor whose drain is supplied with current from the bias current source and a gate connected to the drain, and a bias current connected to the gate of the third MOS transistor. The amplifier circuit according to claim 10, further comprising a bias inductor applied to the signal.

Images