JP2010114793A - Fet bias circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a FET bias circuit for reducing variations of bias fluctuation characteristics among a plurality of high frequency amplifiers in temperature change. <P>SOLUTION: A high frequency amplifier 1 is provided with: a first stage amplifier 10; a second stage amplifier 20 connected to the post-stage of the first stage amplifier 10; a third stage A amplifier 31 and a third stage B amplifier 41 (A and B are called a third stage amplifier 30) connected in parallel with the post-stage of the second stage amplifier 20; and an A/D converter 13, a CPU 12 and D/A amplifier 11 for controlling the third stage amplifier 30. In this case, the third stage A amplifier 31 is provided with: a FET 32; a resistor Rd for measuring a drain current Vdsdc; a temperature sensor 34; an arithmetic amplifier 33 for controlling a gate voltage Vgs; and capacitors C1 and C2. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a bias circuit of an FET (Field Effect Transistor).

  Conventionally, a high-frequency amplifier using an FET is generally used in a high-frequency circuit of a wireless communication device, and is often used particularly in a mobile phone, a mobile phone base station, and the like. In recent years, with the widespread use of mobile phones, the output of base stations, the number of lines and the communication speed (such as W-CDMA) have been improved, and the output of high-frequency amplifiers has been increased.

  There are class A, class AB and class B as operating points of the high-frequency amplifier, and in order to realize each operation, it is set by a gate voltage for controlling the drain current during idling. For example, in class A operation, the gate voltage is set so that the drain current during idling is in the middle between the pinch-off point and the saturation point. In the case of class B operation, a bias is set near the pinch-off point. Similarly, in the case of class AB operation, a bias is set between the class A bias point and the class B bias point. Become.

  However, an FET which is a field effect transistor has a variation in pinch-off voltage in the manufacturing process, and this variation becomes a variation in drain current, resulting in a variation in high-frequency characteristics. For this reason, it is necessary to adjust the gate voltage so that the drain current becomes a predetermined current value.

  The applicant of the present application uses a temperature-sensitive element in the reference voltage generation circuit as shown in Patent Document 1, and performs closed loop control for controlling the voltage applied to the gate of the FET so that the gate voltage of the FET becomes equal to a predetermined reference voltage. An application was made regarding the bias circuit to be performed.

  The circuit of FIG. 6 is a high frequency amplifier disclosed in Patent Document 1, and shows a configuration of a high frequency amplifier using an FET bias circuit. By adopting the circuit configuration as shown in FIG. 6, the gate side circuit and the drain side circuit of the FET can be separated, so that the drain current can be set more freely. This prevents bias point fluctuations due to gate signal fluctuations caused by input signals and temperature changes, enables the FET to operate in any of class A, class AB, and class B, and further prevents thermal breakdown of the FET. .

  Further, in Patent Document 2, in order to realize closed-loop control using a computer, a gate voltage for obtaining a predetermined drain current is estimated from a current value measured by a drain current measuring unit by an analog / digital converter, and digitally A technique for reducing bias fluctuation by controlling the output level of the analog / analog converter is disclosed.

JP 2003-8358 A Japanese Patent Laid-Open No. 10-290129

  In Patent Document 1 described above, the FET can be operated in any of class A, class AB, and class B by the configuration that performs the closed loop control for controlling the voltage applied to the gate of the FET. However, since it is necessary to check the characteristics of the temperature sensitive element and adjust the volume of the idle current setting of the FET as an initial setting, adjustment work to reduce the variation in high frequency amplification characteristics is required when multiple high frequency amplifiers are connected in parallel. Met.

  In Patent Document 2, it is possible to reduce bias fluctuation by closed loop control using a computer. However, as in Patent Document 1, control for operating FETs in any of Class A, Class AB, and Class B. Was not done.

  Accordingly, an object of the FET bias circuit of the present invention is to provide an FET bias circuit capable of reducing variations in bias fluctuation characteristics among a plurality of high-frequency amplifiers due to temperature fluctuations.

  In order to achieve the above object, the FET bias circuit according to the present invention is a high frequency amplifier that inputs a high frequency signal amplified by a previous stage amplifier to the gate of the last stage FET and obtains the amplified signal from the drain. In the FET bias circuit provided, drain current measuring means for measuring the drain current of the FET, temperature measuring means for measuring the ambient temperature of the FET, gate bias setting means for the FET, and control for controlling a plurality of high-frequency amplifiers The control means has an idle current determined in advance based on the drain current during idling obtained from the current value of the drain current measuring means and the ambient temperature of the temperature measuring means. The gate voltage of each high-frequency amplifier is controlled.

  In the FET bias circuit according to the present invention, the control means obtains the consumption current at the time of FET operation and the drain current at the time of idle from the drain current measurement means, and the drain current based on the temperature compensation table stored in advance. Is controlled to a predetermined value to compensate for the temperature.

  In the FET bias circuit according to the present invention, the gate voltage of each high-frequency amplifier is controlled by a control means, and the control means reduces variations in high-frequency characteristics of each high-frequency amplifier by each FET bias circuit.

  Furthermore, in the FET bias circuit according to the present invention, the control means reduces variation in high frequency characteristics of each high frequency amplifier in order to prevent overheating when the ambient temperature acquired from the temperature measurement means becomes higher than a preset temperature. However, the gate voltage is lowered.

  By using the present invention, it is possible to reduce bias fluctuations by closed loop control by a computer and to control the FET to operate in any of class A, class AB, and class B. In addition, the FET bias circuit of the present invention has an effect that variation in bias fluctuation among a plurality of high frequency amplifiers due to temperature fluctuation can be reduced.

Hereinafter, the best mode for carrying out the present invention (hereinafter referred to as an embodiment) will be described with reference to the drawings.
(Example)

  FIG. 1 shows a configuration of a multistage high-frequency amplifier 1 using an FET bias circuit. The high-frequency amplifier 1 includes a first stage amplifier 10, a second stage amplifier 20 connected to the subsequent stage of the first stage amplifier 10, a third stage A amplifier 31 connected in parallel to the subsequent stage of the second stage amplifier 20, and A three-stage B amplifier 41 (A and B are referred to as a third-stage amplifier 30) and a part of the figure are omitted, but the A / D converter 13 that controls the third-stage amplifier 30, the CPU 12, and the D / A converter 11. The third stage A amplifier 31 includes an FET 32, a resistor Rd for measuring drain current, a temperature sensor 34, an operational amplifier 33 for controlling the gate voltage Vgs, and capacitors C1 and C2. ing.

  An input signal obtained at the input terminal IN of the high frequency amplifier 1 is amplified by the first stage amplifier 10 and the second stage amplifier 20 and input to the third stage amplifier 30. The input signal input to the third stage A amplifier 31 is supplied to the gate of the FET 32 which is an amplifying element via the capacitor C1. A GaAaFET having excellent high frequency characteristics is used for the FET 32, and a resistor Rg which is an application circuit for the gate voltage Vgs and an operational amplifier 33 for amplifying the output of the D / A converter 11 are connected to the gate of the FET 32. The source of the FET 32 is grounded, and the drain of the FET 32 is connected to the output terminal OUT via the capacitor C2.

  A resistor Rd for measuring the drain current Idsdc is connected to the drain of the FET 32, and the power supply VDD is supplied to the drain of the FET 32 via the resistor Rd. The A / D converter 13 measures the drain current Idsdc via the resistor Rd and outputs the measured value to the CPU 12. The CPU 12 includes a calculation unit such as a microcomputer and a storage unit, and acquires the drain current value from the A / D converter 13 and the temperature data from the temperature sensor that measures the ambient temperature of the FET 32.

  FIG. 3 shows a control flow of the high frequency amplifier. The initial setting in step S1 and the actual temperature compensation operation in step S3 are subroutines. The control of the high-frequency amplifier is mainly related to the high-power third-stage amplifier. In step S1, the third-stage amplifier should be put in a thermostatic chamber capable of changing the ambient temperature and output from the change in the drain current Idsdc with respect to the temperature. The temperature compensation data for calculating the gate voltage Vgsrf is created.

  When the temperature compensation data is obtained in step S1, a temperature compensation data load for storing the data in the storage means of the CPU 12 is executed in step S2. Thereafter, in the temperature compensation actual operation in step S3, the FET ambient temperature of the high-frequency amplifier in operation is measured, and the gate voltage Vgs is controlled so that the drain current Idsdc during idling becomes a predetermined value.

  FIG. 2 shows a characteristic diagram of the temperature compensation operation of the third stage amplifier, in which the horizontal axis indicates the FET substrate temperature, and the vertical axis indicates the drain current Idsdc. The dotted line in the figure indicates the characteristic when there is no temperature compensation, and it is possible to obtain a certain characteristic by performing temperature compensation so as to maintain the characteristic at room temperature.

  In the case of a FET of several hundred watts, as the FET ambient temperature approaches 80 degrees, for example, the performance deterioration of the FET becomes remarkable. Therefore, it is necessary to perform not only temperature compensation but also overheat protection. Therefore, as shown in FIG. 2, the high-frequency characteristics of the third-stage A amplifier and the third-stage B amplifier may not match in the control for each FET separately subjected to temperature compensation and overheat protection. If the high-frequency characteristics do not match, the load of each FET may be biased in a configuration in which FETs are connected in parallel in order to achieve high output.

  In general, since the gate voltage Vgs is controlled for each FET, a variation in high-frequency characteristics occurs for each FET. Therefore, in the present embodiment, a plurality of FETs are controlled in order to reduce the load bias of each FET and match the final characteristics of FIG.

  FIG. 4 shows a flow of a subroutine for initial setting of the high frequency amplifier. In order to start the initial setting, in step S10, the third stage amplifier 30 of FIG. 1 is installed in the thermostat, the drain current Idsdc is measured by the A / D converter 13, and the ambient temperature of the FET is measured by the temperature sensor 34. And the gate voltage Vgs is adjusted so that a predetermined drain current (idle current) is obtained.

  Next, in step S12, the inside of the thermostatic chamber is set to room temperature (for example, 25 degrees), the drain current Idsdc is measured by the A / D converter 13, the ambient temperature of the FET is measured by the temperature sensor 34, and predetermined. The gate voltage Vgs is adjusted so that the drain current (idle current) is obtained, and the adjusted gate voltage Vgs and the ambient temperature are stored.

  In step S14, the inside of the thermostatic chamber is set to a minimum temperature (for example, −20 degrees), the drain current Idsdc is measured by the A / D converter 13, the ambient temperature of the FET is measured by the temperature sensor 34, and is determined in advance. The gate voltage Vgs is adjusted so as to be the drain current (idle current), and the adjusted gate voltage Vgs and the ambient temperature are stored.

  In step S16, the inside of the thermostatic chamber is set to the maximum temperature (for example, 50 degrees), the drain current Idsdc is measured by the A / D converter 13, the ambient temperature of the FET is measured by the temperature sensor 34, and predetermined. The gate voltage Vgs is adjusted to be a drain current (idle current), and the adjusted gate voltage Vgs and the ambient temperature are stored.

  In step S18, the gradient of the gate voltage with respect to the temperature is calculated from the measurement results at the minimum temperature, the normal temperature, and the maximum temperature to create a temperature compensation table, and the process returns to the flowchart of FIG. In step S2 of FIG. 3, the temperature compensation data obtained in this way is incorporated as statistical data, and, for example, a polynomial approximate expression is obtained by applying the least square method to create a representative value. For mass production, only the representative values of completed temperature compensation data are loaded. Note that it is possible to grasp the characteristics of each lot by statistically grasping the variation in the idle current set value during the initial setting. Here, in this embodiment, one of the characteristic matters is to finely adjust the characteristic variation in the actual temperature compensation operation in step S3. By this fine adjustment, the temperature compensation data at the initial setting only needs to obtain an approximate characteristic, and it is not necessary to store each characteristic in the CPU.

  FIG. 5 shows a flow of a subroutine of the temperature compensation actual operation of the high frequency amplifier. In step S20 of actual operation, the FET ambient temperature is measured by the temperature sensor. In step S22, the CPU acquires the drain current Idsdc from the A / D converter and temporarily stores it. Next, in step S24, after outputting a gate voltage corresponding to the measured temperature from the D / A converter based on the temperature compensation data, the drain current Idsdc is obtained from the A / D converter and temporarily stored. The difference from the value is compared with the difference of the other FETs, and the bias voltage is adjusted again so that the difference is minimized. In step S26, the gate bias voltage serving as the adjusted control signal is output from the D / A converter, and the process returns to the beginning.

  As described above, the FET bias circuit according to the present embodiment reduces bias fluctuation by closed loop control using a computer, and controls to operate the FET in any of class A, class AB, and class B. It becomes possible to do. In addition, the FET bias circuit can reduce variations in bias fluctuation among a plurality of high-frequency amplifiers due to temperature fluctuation. The high-frequency amplifier described in the present embodiment is disposed near or at a high place in the base station antenna, and can be heated by sunlight, so a high-frequency amplifier with good temperature characteristics is important.

It is a circuit diagram which shows the structure of the high frequency amplifier using the FET bias circuit which concerns on embodiment of this invention. It is a characteristic view which shows the temperature compensation operation | movement in embodiment of this invention. It is a flowchart figure which shows the flow of control of the high frequency amplifier which concerns on this embodiment. It is a flowchart figure which shows the flow of the initial setting of the high frequency amplifier which concerns on this embodiment. It is a flowchart figure which shows the flow of the actual operation | movement of the high frequency amplifier which concerns on this embodiment. It is a circuit diagram which shows the structure of the high frequency amplifier using the conventional FET bias circuit.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 High frequency amplifier, 10 1st stage amplifier, 11 D / A converter, 12 CPU, 13 A / D converter, 20 2nd stage amplifier, 30 3rd stage amplifier, 31 3rd stage A amplifier, 32 FET, 33 Operational amplifier, 34 temperature sensor, 41 3rd stage B amplifier, C1, C2 capacitor, Rd, Rg resistance, Vgsdc, Vgsrf gate voltage, Vdsdc drain voltage, Idsdc, Idsrf drain current.

Claims (4)

In the FET bias circuit provided in the high frequency amplifier that inputs the high frequency signal amplified by the amplifier in the previous stage to the gate of the FET in the final stage and obtains the amplified signal from the drain,
Drain current measuring means for measuring the drain current of the FET;
Temperature measuring means for measuring the ambient temperature of the FET;
FET gate bias setting means;
Control means for controlling a plurality of high-frequency amplifiers;
Have
The control means sets the gate voltage of each high-frequency amplifier so that the idle current is determined in advance based on the drain current during idling obtained from the current value of the drain current measuring means and the ambient temperature of the temperature measuring means. An FET bias circuit characterized by controlling. The FET bias circuit of claim 1, wherein
The control means obtains the current consumption during FET operation and the drain current during idle operation from the drain current measurement means, and controls the drain current to a predetermined value based on a pre-stored temperature compensation table. An FET bias circuit characterized by temperature compensation. The FET bias circuit according to claim 1 or 2,
An FET bias circuit characterized in that the gate voltage of each high-frequency amplifier is controlled by control means, and the control means reduces variation in high-frequency characteristics of each high-frequency amplifier by each FET bias circuit. The FET bias circuit according to claim 1 or 2,
The control means is characterized in that when the ambient temperature acquired from the temperature measurement means becomes higher than a preset temperature, the gate voltage is lowered while reducing the variation in the high frequency characteristics of each high frequency amplifier in order to prevent overheating. FET bias circuit.

Images