JP5232410B2 - Display device driving circuit, display device, and electronic apparatus - Google Patents

Description

  The present invention relates to a display device that has a controllable light source and performs display by controlling a transmittance control element that controls the transmittance of light disposed in front of the light source, and a driving circuit for the display device. The present invention relates to a driving circuit (eg, LSI) of a display device using an element, a display device using the same, and an electronic device.

  In a small liquid crystal display used in a cellular phone or the like, it is important to keep power consumption small. The liquid crystal display illuminates a liquid crystal screen capable of controlling light transmittance from the rear with a backlight, and displays an image with the transmitted light. In the liquid crystal display, most of the power consumption is consumed by the backlight. Therefore, keeping the power consumption of the backlight small is very effective in reducing the power consumption of the liquid crystal display. Therefore, as shown in Japanese Patent Laid-Open No. 11-65531 (hereinafter referred to as Patent Document 1), the maximum gradation value X of the display image is acquired, and the maximum gradation value X of the display image is obtained from the liquid crystal display screen. The data of the entire image is expanded so that the maximum gradation (255 gradations for 8-bit RGB) is obtained, and the luminance value at the maximum gradation (255 gradations) is the maximum gradation of the display image. There has been proposed a method of reducing power consumption by reducing the amount of light of the backlight so that the luminance value becomes the value.

Further, in order to reduce power consumption, Patent Document 1 takes a histogram of the gradation of a display image, and in the histogram, the cumulative value of the histogram from the maximum gradation of the display image is a certain number of pixels. The image data is expanded with the tone value P1 as the maximum gradation, and the amount of power of the backlight is reduced so that the luminance value of the gradation P1 becomes the luminance value at the time of display of the maximum gradation: X. The idea to lower is made.
JP-A-11-65531

  As shown in FIG. 15, a television image or the like often has a peak protruding to the maximum gradation (255 gradations) in the gradation histogram, and other gradations change gently. Due to such a prominent peak at the maximum gradation, a certain number of pixels from the maximum gradation of the display image is almost occupied by the number of pixels indicating the maximum gradation. As a result, the peak of the distribution of gradation becomes the maximum gradation or a value very close to the maximum gradation, and there is a problem that the amount of light of the backlight cannot be reduced and the power consumption cannot be reduced.

  In order to solve such a problem, the present invention, when calculating the histogram cumulative value from the maximum gradation, excludes pixels of a plurality of gradations including a certain gradation (for example, the maximum gradation) from the accumulation object and performs the calculation. It is an object of the present invention to provide a means for excluding a predetermined ratio of accumulation targets at the time of pixel expansion.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  The display device driving circuit according to the present invention controls a light source capable of controlling the amount of light and a transmittance control element for controlling the transmittance of light arranged in front of the light source. Measure the number of pixels for each pixel, and expand the display image data using the threshold grayscale that has reached a certain percentage of the total number of pixels as the cumulative value from the maximum grayscale to be accumulated. The light source is controlled to have the same luminance as the display luminance of the threshold gradation.

  The maximum gradation of the display image may be excluded from the cumulative target of the display device driving circuit. Further, the maximum gradation of the display image may be included in the accumulation target. In addition, it may be possible to switch whether or not to include the highest gradation of the display image as a cumulative target.

  A display device driving circuit according to the present invention drives a histogram cumulative value calculation circuit that calculates a histogram of a display image frame, a coefficient calculation circuit that calculates a pixel expansion coefficient, a light source including the pixel expansion circuit, and a display device. The histogram cumulative value calculation circuit sums and outputs the number of pixels of each gradation for each display image frame, and the coefficient calculation circuit derives and outputs a pixel expansion coefficient from the total value of each gradation. Is characterized in that the gradation of the display image frame is expanded so that the gradation below the pixel expansion coefficient becomes all gradations.

  The histogram cumulative value calculation circuit of the display device driving circuit may not output the number of pixels of the highest gradation of the display image, or may output the number of pixels of the highest gradation. Furthermore, the histogram cumulative value calculation circuit may have a mode switching register, and the number of pixels of the highest gradation may be output by setting the mode switching register.

  The histogram cumulative value calculation circuit of the display device driving circuit may simultaneously output the number of pixels of each gradation through different signal lines. Further, the histogram cumulative value calculation circuit of the display device driving circuit may sequentially output the number of pixels of each gradation through the same signal line.

  The coefficient calculation circuit of this display device driving circuit includes a threshold determination value storage register for holding a threshold determination value, and sequentially adds the number of pixels of each gradation from the one with the highest gradation, and displays it in comparison with the threshold determination value. A pixel expansion coefficient for each image frame is determined.

  The coefficient calculation circuit of the display device driving circuit may derive a pixel expansion coefficient for each of a plurality of display image frames and output the average value as the pixel expansion coefficient.

  The pixel expansion circuit of the display device driving circuit is characterized by linearly expanding gradations less than the pixel expansion coefficient.

  The display device driving circuit may further include a CPU and an illuminance sensor, and the CPU may rewrite the value of the threshold determination value storage register according to the illuminance acquired by the illuminance sensor.

  The display device driving circuit may further include a backlight and a backlight controller, and the backlight controller may control the backlight according to the derived pixel expansion coefficient.

  The present invention can also be applied to a display device or an electronic device including these display device driving circuits.

  The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

  According to the present invention, the power consumption can be greatly reduced by ignoring the number of pixels of the maximum gradation such as a light source (sun or fluorescent lamp) that is not important in terms of video reflected in the screen.

  According to the present invention, when the number of pixels of the maximum number of gradations is equal to or larger than a certain value, the luminance reduction of the display portion having high luminance in the binary image is performed by calculating by adding the number of pixels of the maximum gradation to the cumulative value of the histogram. Can be displayed beautifully.

  According to the present invention, even in an overall whitish image such as a cloud, the gradation does not deteriorate because the gradation immediately below the maximum gradation has a large number of pixels.

  The drive circuit of the display device of the present invention has a mode register in the display drive circuit that determines whether or not the number of pixels of a certain gradation is included in the cumulative value of the histogram. As a result, according to the present invention, when displaying an image with many natural images such as a moving image, the CPU determines the application, removes the maximum gradation from the histogram, and displays an image with many binary images such as a document file. Since the maximum gradation can be included in the histogram, the image can be displayed more clearly.

  In the driving circuit of the display device of the present invention, the CPU can set a threshold value for the maximum number of pixels that determines whether the maximum number of pixels is included in the cumulative histogram value. As a result, according to the present invention, it is possible to set an optimum threshold value based on gradation luminance characteristics of liquid crystal or the like, and the image display can be made more beautiful.

  Furthermore, according to the present invention, the CPU can set a threshold value for the maximum number of pixels for determining whether the maximum number of pixels is included in the cumulative histogram value or not. As a result, even when the brightness decreases due to the aging of the backlight, the image can be displayed more clearly by setting the optimum threshold value.

(Premise of the present invention)
The prominent peak of the maximum gradation (255 gradations) occurs mainly due to the following two causes.
(1) A light source is shown in the screen.
(2) When an original image having a wide luminance range is photographed and digitized, all the portions of luminance higher than the maximum gradation (255 gradations) are aligned to 255 gradations.

  The light source of (1) is reflected when a light source such as a fluorescent lamp or the sun enters the screen as shown in FIG. 16, and such a light source is not important in the screen configuration. In many cases, there is no problem even if the brightness changes slightly.

  In the case of (2), as shown in FIG. 17, it is a peak generated because a portion having a luminance equal to or higher than the maximum gradation is aligned to the maximum gradation. An error has already occurred in the original image during digitization. Therefore, there is no problem even if the brightness changes slightly.

  Therefore, in order to solve the above-described problem, the present invention calculates the cumulative value of the histogram from the maximum gradation, excluding the number of pixels of a certain gradation (for example, the maximum gradation or its vicinity).

  Next, image expansion processing performed to improve the contrast targeted by the present invention will be described with reference to FIGS.

  FIG. 1 is a conceptual diagram of a pixel expansion coefficient x and a threshold determination value y.

  In FIG. 1, the term pixel expansion factor x is used. This means a gradation x in which the cumulative number of pixels having a gradation value equal to or lower than the maximum gradation to be accumulated in the display image is y% of the total number of pixels included in one frame of the image.

  As shown in FIG. 1B, the pixel gradation coefficient x gradation is assigned to 255 gradations, and display data from 0 gradation to x gradation is linearly displayed as shown in FIG. Assign to output tone. On the other hand, the output gradation is uniformly assigned to the maximum value (255 gradations) for x gradations or more.

  Thus, in the invention described in this specification, the contrast can be increased by extending the gradation of 0 to x to 0 to 255.

  As described above, in the present invention, the x gradation in which the number of pixels whose gradation value is greater than or equal to the x gradation and equal to or less than the maximum −γ (255−γ) gradation is y% of the total number of pixels is called a pixel expansion coefficient. This gradation is assigned to the maximum (255) gradation, and the image is expanded. The value of y% is defined as a threshold judgment value in the present invention. Note that this threshold determination value is a design matter and is appropriately determined by a circuit designer. It is desirable that the threshold determination value is set to a value such that pixels that are equal to or larger than the pixel expansion coefficient of the formed image are not sufficiently conspicuous with respect to the entire image.

  On the other hand, FIG. 2 shows an example in which the image information is concentrated in the low gradation, and the “lower limit value” of the pixel expansion coefficient will be described using this.

  When image information is concentrated at low gradations, the pixel expansion coefficient x obtained by the above method is a small value. As a result, as shown in FIG. 2B, the expansion ratio becomes too large, and the distortion of the output image also increases. In order to cope with such a case, a gradation (1402 in FIG. 1) that does not further reduce the pixel expansion coefficient is determined as a design item. This is hereinafter referred to as “lower limit value”.

  In this document, the data handled is described as 8-bit data with 255 gradations, but there is no problem even with 10-bit data (1023 gradations).

  Based on the above assumptions, each embodiment of the present invention will be described below with reference to the drawings.

(First embodiment)
FIG. 3 is a block diagram of the display device according to the first embodiment.

  The display device 100 includes a display device drive circuit 101, a central processing unit (CPU) 102, a display memory 103, an internal bus 104, a backlight 111, and a liquid crystal screen 112.

  The display device driving circuit 101 is a circuit for driving the backlight 111 and the liquid crystal screen 112. The display device drive circuit 101 includes an input / output interface circuit 105, a histogram cumulative value calculation circuit 106, a coefficient calculation circuit 107, a backlight controller 108, a pixel expansion circuit 109, a liquid crystal controller 110, a drive circuit memory 113, and a timing control circuit 114. Consists of including.

  The CPU 102 is a processor that transmits data to the display device driving circuit 101 and causes the liquid crystal screen 112 to display the data.

  A memory 103 is a memory for holding attributes about luminance, hue, and saturation in order to display on a liquid crystal screen. In the present invention, it is connected on the internal bus 104 outside the display device driving circuit 101. However, the display device driving circuit 101 may be directly connected to be used exclusively for the display device driving circuit 101 or may be built in the display device driving circuit 101. Moreover, you may design so that this may be shared with CPU102.

  The internal bus 104 refers to a bus used for transferring data between modules in the display device 100.

  The backlight 111 is a light source for improving the visibility of the liquid crystal screen 112 by irradiating the liquid crystal screen 112 that does not emit light.

  The liquid crystal screen 112 is an image display device incorporating a liquid crystal element.

  Next, the modules inside the display device drive circuit 101 will be described.

  An input / output interface circuit (input / output IF circuit) 105 is an interface unit that receives data transmitted from the internal bus 104. The input / output interface circuit 105 includes a “display start register” (not shown) that indicates whether or not liquid crystal display is being performed (display start mode).

  The histogram cumulative value calculation circuit 106 is a circuit that obtains the number of pixels for each gradation from the highest gradation (255 gradations) to the lower limit value from the display data for one frame and forms a histogram.

  The coefficient calculation circuit 107 calculates the sum of the number of pixels from the output of the histogram cumulative value calculation circuit 106 to each gradation. Thereby, “x gradation” which is a pixel expansion coefficient is derived.

  Note that the histogram cumulative value calculation circuit 106 and the coefficient calculation circuit 107 are attached to characteristic portions of the present invention and will be described in detail later.

  The backlight controller 108 has a function of adjusting the illuminance and the like of the backlight 111. By adjusting the illuminance, power consumption by the backlight 111 can be reduced.

  The pixel expansion circuit 109 is a circuit that performs expansion processing on the gradation of the display image based on the pixel expansion coefficient.

  The liquid crystal controller 110 is a controller for displaying on the liquid crystal screen 112 based on the output data of the pixel expansion circuit 109.

  The drive circuit internal memory 113 is a memory for temporarily storing display data sent via the input / output interface circuit 105. The capacity of the drive circuit memory 113 varies depending on the system, but a system having a frame memory for one frame is generally used. However, in the present invention, there is no particular problem even with a FIFO memory of several bytes.

  The timing control circuit 114 outputs a SYNC signal indicating the start position of the display data for the display data sent via the input / output interface circuit 105. In synchronization with the SYNC signal, display data is output from the memory 113 in the drive circuit to the histogram cumulative value calculation circuit 106 and the pixel expansion circuit 109.

  The operation of this display device will be described below.

  When displaying data on the liquid crystal screen 112, the CPU 102 writes a value indicating display start in a “display start register” (not shown) in the input / output interface circuit 105. Thereafter, display data is transferred from the display memory 103 to the drive circuit memory 113 via the input / output interface circuit 105.

  In the display start mode, the timing control circuit 114 of the display device drive circuit 101 outputs a frame SYNC signal indicating the start position of display data. In synchronization with the frame SYNC signal, the display data is output from the drive circuit memory 113 to the histogram cumulative value calculation circuit 106 and the pixel expansion circuit 109.

  The display data output from the drive circuit memory 113 is converted into a histogram by the histogram cumulative value calculation circuit 106. An example of this histogram is shown in FIG.

  In FIG. 4, the cumulative value (histogram) of pixels for each gradation from the maximum gradation value of 255 gradation to the lower limit value is obtained. Note that it is a design matter whether to count the gradation near the 255 gradation that is the maximum gradation value at this stage. A process that does not output to the coefficient arithmetic circuit 107 even when counted, or a design that ignores the coefficient arithmetic circuit 107 even if output to the coefficient arithmetic circuit 107 is also conceivable.

  Histogram data derived by the histogram cumulative value calculation circuit 106 is transmitted to the coefficient calculation circuit 107. The coefficient calculation circuit 107 obtains a pixel expansion coefficient from the histogram data.

  Here, a method of deriving the pixel expansion coefficient by the coefficient calculation circuit 107 will be described with reference to FIG. In the example of this embodiment, the maximum gradation value of 255 gradations and the subsequent 254 gradations are not used for deriving the pixel expansion coefficient (not included in the accumulation target). Since addition cannot be performed only with the upper limit of 253 gradations to be accumulated, 255-2 (255 gradations and 254 gradations) -1, that is, 252 is set as the initial value of the variable a which is a processing counter.

  First, the sum of the number of pixels of 253 gradations or less and variable a gradations or more is obtained. If the sum of the number of pixels is smaller than a predetermined threshold determination value, 1 is subtracted from the value of a, and the sum of the number of pixels is obtained again. That is, in this example, a = 251, and the sum of the number of pixels from 251 to 253 gradations is obtained. This is repeated until the lower limit is reached or the sum of the number of pixels becomes larger than the threshold determination value.

  On the other hand, if the sum of the number of pixels is larger than a predetermined threshold determination value, a value obtained by adding 1 to the value of a at that time is determined as the pixel expansion coefficient. If the variable a reaches the lower limit without the sum of the number of pixels becoming larger than a predetermined threshold determination value, the lower limit (220 in FIG. 4) is handled as the pixel expansion coefficient.

  If the pixel expansion coefficient is determined, the coefficient calculation circuit 107 outputs the determined pixel expansion coefficient to the backlight controller 108 and the pixel expansion circuit 109.

  Next, the operation of the backlight controller 108 and the gradation luminance characteristics of the liquid crystal screen 112 will be described with reference to FIG.

  FIG. 5 is a graph showing the correspondence between the operation of the backlight controller 108 and the gradation luminance characteristics of the liquid crystal screen 112.

The horizontal axis of FIG. 5 indicates the gradation of the display pixel. On the other hand, the left vertical axis indicates the luminance of the backlight, and the unit is Kantera (cd / m ² ). The right vertical axis represents the gradation luminance characteristic of the liquid crystal screen 112.

  The luminance 701 in FIG. 5 is the backlight luminance when the maximum gradation is 255 gradations. Similarly, the luminance 702 is the backlight luminance so that the maximum gradation is the luminance of the gradation indicated by the pixel expansion coefficient A, and the luminance 703 is the luminance of the gradation whose maximum gradation is the pixel expansion coefficient B. The backlight luminance when the backlight luminance is controlled to be as follows.

  Further, the gradation luminance characteristic when the highest gradation is 255 gradation, the backlight luminance is 701, is the gradation luminance characteristic 704, and the gradation luminance characteristic of the liquid crystal or the like when the backlight luminance is 702 is The gradation luminance characteristic 705 and the gradation luminance characteristic of the liquid crystal or the like when the backlight luminance is 703 are the gradation luminance characteristic 706.

  Generally, when the backlight luminance is lowered, the current consumption is also lowered. Also in the present invention, it is more advantageous in terms of power consumption to turn on the backlight with the brightness 702 than to turn on the backlight with the brightness 701, and it is more advantageous to turn on the backlight with the brightness 703. The backlight controller of the present invention performs the following processing by paying attention to this point.

  That is, the backlight luminance is fixed to 703 (luminance when the maximum gradation is the pixel expansion coefficient B). On the other hand, the gradation luminance characteristic 704 is used as the gradation luminance characteristic of the liquid crystal or the like from 0 gradation to B. On the other hand, in the range from the B gradation to the 255 gradation, the gradation luminance characteristic 709 is the maximum so that the gradation luminance characteristic 709 has the same luminance 710 as the luminance at the B gradation of the gradation luminance characteristic 704. Fix to gradation. By controlling in this way, power consumption can be significantly reduced.

  The pixel expansion circuit 109 performs conversion indicated by the characteristic 707 in FIG. 6 with respect to the gradation of the display image. FIG. 6 is a conceptual diagram regarding pixel expansion in the pixel expansion circuit 109.

  A characteristic 708 in FIG. 6 is an input / output characteristic of the pixel expansion circuit when the expansion is not performed.

  In the pixel expansion circuit 109 according to the present invention, as described above, all portions of the display image having the pixel expansion coefficient (B gradation) or more are processed as 255 gradations, and the portion having the pixel expansion coefficient (B gradation) of 0 or more is processed. Is converted linearly as indicated by a characteristic 707.

  By converting the backlight luminance and the gradation of the image in this way, the luminance displayed on the liquid crystal screen 112 becomes a characteristic 709 in FIG. Since the threshold determination value is set to a value that is sufficiently small and inconspicuous with respect to the entire image, even if the pixel expansion coefficient or more collapses to a certain luminance as in the characteristic 709, the image as a whole does not stand out. Will not deteriorate significantly. Further, as described above, the case where there is a peak in the 255 gradation is when the light source enters the screen or when more gradations are seen as 255 gradation upon digitization. Therefore, even if the location of 255 gradations collapses to the brightness of the pixel expansion coefficient, the image quality does not deteriorate significantly.

  By the way, in the case of the method using the cumulative value of the histogram including the highest gradation, if the same threshold determination value determination method is used, the pixel expansion coefficient shifts to the high gradation side. This is because the normal peak comes to 255 gradations. In the case of the method using the cumulative value of the histogram including the highest gradation, the pixel expansion coefficient is shifted from B to A on the 255 gradation side as shown in FIG. In the backlight controller 108, the backlight luminance is lowered 702 so that the gradation luminance characteristic 705 has the same luminance as the A gradation when the pixel expansion coefficient is the highest gradation. In this way, the pixel sum is higher than that obtained when the highest gradation is excluded. From the opposite viewpoint, power consumption can be significantly reduced by calculating a histogram excluding the highest gradation by the pixel expansion circuit 109.

  Next, detailed block diagrams and operations of the histogram cumulative value calculation circuit 106 and the coefficient calculation circuit 107 according to the first embodiment will be described with reference to FIGS.

  FIG. 7 is a detailed block diagram of the histogram cumulative value calculation circuit 106 and the coefficient calculation circuit 107. FIG. 8 shows a setting example of the histogram boundary setting register 502, which includes a counter, a histogram boundary register setting value, and a count-up range as setting items.

  The histogram cumulative value calculation circuit 106 includes an RGB maximum value extraction circuit 501, a histogram boundary setting register 502, a selector 503, and a histogram counter 504.

  On the other hand, the coefficient calculation circuit 107 includes a threshold value storage register 521, a selector 522, a threshold determination value storage register 523, a selector 524, adders 525 to 539, registers 540, 542, 544, and 546, adders 541, 543, and 545, It consists of a divider 547.

  The RGB maximum value extraction circuit 501 selects the maximum gradation value among the red (R), green (G), and blue (B) data of one pixel (pixel) transmitted from the input / output interface 105, and selects the selector. This is a circuit for outputting to 503.

  The histogram boundary setting register 502 is a register set by the CPU 102 via the input / output interface 105, and plays a role of setting which counter is counted up according to the output value of the RGB maximum value extraction circuit 501.

  The selector 503 is a selector that determines the output to the histogram counter 504 by comparing the output of the RGB maximum value extraction circuit 501 or the output of the histogram boundary setting register 502. In the present embodiment, the histogram counter 504 is a counter composed of 16 counters 505 to 520. Although the number of counters is 16 here, the number of counters is determined in consideration of the lower limit value of the pixel expansion coefficient and the count-up range in FIG. That is, in the present embodiment, the lower limit value is set to 220, but if it is set to a lower value, the number of counters is required accordingly. Further, if the count-up range which is a setting item of the histogram boundary setting register 502 is wide, the number of counters is reduced accordingly.

  The threshold storage register 521 does not add the value of the counter 505 to the histogram accumulated value when the value of the counter 505 is smaller than the value of the threshold storage register, and when the value of the counter 505 is larger than the value of the threshold storage register, the counter 505 It is a register for setting a threshold value for adding the value of.

  The selector 522 outputs “0” when the value of the counter 505 is smaller than the value of the threshold value storage register 521, and outputs the value of the counter 505 when the value of the counter 505 is equal to or larger than the value of the threshold value storage register 521. It is. As a result, when the cumulative value of the highest gradation is less than or equal to a certain value, that value can be ignored. On the contrary, if the highest gradation is always output, the value of the threshold value storage register 521 may be set to “0”.

  The threshold determination value storage register 523 is a register for storing a threshold determination value.

  The selector 524 compares the accumulated values 526 to 539 from the highest gradation to be accumulated to the corresponding gradation with the value of the threshold determination value storage register 523, and selects an accumulated value smaller than the value of the threshold determination value storage register 523. Among them, the selector outputs a gradation value corresponding to the maximum gradation. The output of the selector 524 is a pixel expansion coefficient obtained from display data for one frame.

  The adder 525 adds the output of the selector 522 and the register 506 in the histogram counter 504 and outputs the result to the selector 524 and the adder 526. That is, when the value of the counter 505 is greater than or equal to the value of the threshold value storage register 521, the sum of the values of the counter 505 and the counter 506 is obtained, and when the value of the counter 505 is less than the value of the threshold value storage register 521, the value of the counter 506 is obtained.

  Similarly, when the value of the counter 505 is equal to or greater than the value of the threshold value storage register 521, the values of the adders 526 to 539 are cumulative values from the 255th gradation to the gradation corresponding to the corresponding counter, and the value of the counter 505 is the threshold value. When the value is less than the value of the storage register 521, the accumulated value from the gradation 253 to the gradation corresponding to the corresponding counter, excluding the gradations 255 and 254, is obtained.

  Registers 540, 542, 544, and 546 are registers for holding cumulative values of pixel expansion coefficients for the latest four frames. In addition, adders 541, 543, and 545 and a divider 547 are present to average the pixel expansion coefficients of the latest four frames.

  The adder 541 is an adder that adds the output of the selector 524 and the output of the register 540 and outputs the result to the register 542. The adder 543 is an adder that adds the output of the selector 524 and the output of the register 542 and outputs the result to the register 544. The adder 545 adds the output of the selector 524 and the output of the register 544 and outputs the result to the register 546. It is an adder.

  In this embodiment, the divider 547 is a divider that divides by four. This is divided by 4 in order to obtain the average value of the latest four frames. If the accumulation target of the pixel expansion coefficient of the latest frame is increased, the divisor is increased accordingly.

  The operation of the histogram cumulative value calculation circuit 106 will be described below based on the above circuit configuration.

  When the frame SYNC signal is input to the histogram cumulative value calculation circuit 106, the histogram counter 504 is reset. That is, the 16 counters 505 to 520 in the histogram counter 504 become zero.

  Next, display data is transferred pixel by pixel from the input / output interface circuit 105 to the RGB maximum value extraction circuit 501. The RGB maximum value extraction circuit 501 selects the maximum value of the gradation in the R (red), G (green), and B (blue) data of one pixel and outputs it to the selector 503.

  The selector 503 compares the output of the RGB maximum value extraction circuit 501 with the value of the histogram boundary setting register 502. Here, a setting example of the histogram boundary setting register 502 will be described with reference to FIG.

  After obtaining the output of the RGB maximum value extraction circuit 501, the selector 503 examines in which range of the count-up value the output value is present. Then, an output signal is determined so as to count up the counter corresponding to the range.

  In the setting of FIG. 8, when the output of the RGB maximum value extraction circuit 501 is 254 or 255, the output 548 of the selector 503 is active. The counter 505 in the histogram counter 504 is counted up. On the other hand, the output signal lines 549 to 563 are not activated, and the counters 506 to 520 in the histogram counter 504 are not counted up.

  On the other hand, when the output of the RGB maximum value extraction circuit 501 is 253 or 252, the output 549 of the selector 503 is activated, and the other output signal lines 548 and 550 to 563 are not activated. As a result, only the counter 506 in the histogram counter 504 is counted up.

  Further, when the output of the RGB maximum value extraction circuit 501 is less than “200” (the minimum count-up range of the counter 520), none of the outputs 548 to 563 becomes active, and the counters 505 to 520 are not counted up.

  As described above, the output of the selector 503 is determined according to the set value of the histogram boundary setting register 502 and the output of the RGB maximum value extraction circuit 501. As a result, each counter in the histogram counter 504 is counted up as appropriate.

  In this way, when display data for one frame is input, the number of pixels for each boundary set in the histogram boundary register 502 is accumulated in the histogram counter 504.

  Next, the operation of the coefficient calculation circuit 107 will be described.

  The coefficient calculation circuit 107 derives a pixel expansion coefficient by calculation based on the value of each counter obtained by the histogram cumulative value calculation circuit 106. A detailed calculation method will be described below.

  The selector 522 outputs “0” when the value of the counter 505 is smaller than the value of the threshold value storage register 521, and outputs the value of the counter 505 when the value of the counter 505 is equal to or larger than the value of the threshold value storage register 521. Therefore, the output of the adder 525 is the sum of the values of the counter 505 and the counter 506 when the value of the counter 505 is greater than or equal to the value of the threshold storage register 521, and the counter 506 when the value of the counter 505 is less than the value of the threshold storage register 521. It becomes the value of.

  Similarly, when the value of the counter 505 is equal to or greater than the value of the threshold value storage register 521, the values of the adders 526 to 539 are cumulative values from the gradation 255 to the gradation corresponding to the corresponding counter, and the value of the counter 505 is the threshold value. When the value is less than the value of the storage register 521, the accumulated value from the 253 gradation to the gradation corresponding to the corresponding counter excluding the gradations 255 and 254 is obtained.

  The selector 524 compares the accumulated values 526 to 539 from the 253 gradation to the gradation corresponding to the corresponding counter with the value of the threshold determination value storage register 523, and the accumulated value smaller than the value of the threshold determination value storage register 523. Among them, the gradation value corresponding to the maximum gradation is output. The output of the selector 524 becomes the pixel expansion coefficient of the frame obtained from the display data for one frame.

  However, determining the pixel luminance coefficient and the backlight luminance and gradation luminance characteristics derived from the pixel expansion coefficient in only one frame is accompanied by fluctuations in luminance and causes flicker.

  The registers 540, 542, 544, and 546 add the pixel expansion coefficients of the latest four frames, and an average of the pixel expansion coefficients is derived by the divider 547. As a result, the variation in luminance for each frame is reduced, the occurrence of flicker is suppressed, and a good display state can be obtained.

  The averaged pixel expansion coefficient is output to the backlight controller 108 and the pixel expansion circuit 109 as the final pixel expansion coefficient.

  Consider that the circuit according to the first embodiment is applied to a binary image in which characters are written in black on a white background. For binary values such as black and white images, the histogram is as shown in FIG. In this case, since the number of pixels of 255 gradation is sufficiently large, in the present invention, the selector 522 outputs the value of the register 505, and the value of the adder 525 is larger than the value of the threshold judgment value storage register 523. Become. Therefore, the selector 524 outputs the maximum gradation value 255 as the pixel expansion coefficient. As a result, the brightness of the white background is not lowered and the screen is not darkened.

  Further, in the case of an image with a high luminance but a delicate shadow such as a cloud or snow image, the histogram is as shown in FIG. In this case, since the number of pixels of 253 gradations is sufficiently large, the value of the adder 525 is larger than the value of the threshold determination value storage register 523. Therefore, the selector 524 outputs the maximum gradation value 255 as the pixel expansion coefficient, so that the brightness of the white background is not lowered and the screen is not darkened.

  In this embodiment, by setting the setting value of the threshold storage register 521 to “0”, the output of the selector 522 is always the value of the register 505 if the register 505 contains a value of 1 or more. Therefore, the threshold value storage register 521 can also be used as a register for designating whether or not to calculate the number of pixels of 255 gradation and 254 gradation.

  It is also conceivable that the CPU 102 can rewrite the threshold value storage register 521 of the present invention. For example, in the case of document data having a large number of binary images, the value of the threshold value storage register 521 is made smaller, and in the case of an image with a lot of reflection of a light source such as a television image display, the value of the threshold value storage register 521 is set to a larger value. By setting, it is possible to reduce the power without degrading the image quality.

  Further, since the threshold determination value storage register 523 can be rewritten by the CPU 102, as shown in FIG. 11, when the gradation-luminance characteristic is a characteristic that is convex upward in the vicinity of the maximum gradation (255 gradations), By increasing the set value of the threshold determination value storage register 523, the power can be further reduced.

  Further, even when the backlight brightness decreases due to deterioration over time, the CPU measures the date from the start of use, and the value of the threshold determination value storage register 523 is reached when the use date has exceeded a certain level. By reducing the value, it is possible to prevent the brightness of the screen from being excessively lowered.

  In this embodiment, the RGB maximum value extraction circuit 501 selects the maximum value from the R, G, and B data and forms a histogram. However, this does not limit the present invention, and R, G , B data may be used to calculate a histogram, or all R, G, B data may be used as a histogram. Furthermore, the histogram may be configured with only colors (generally G (green)) that the color characteristics of the high gradation have a great influence on the visual perception according to the color characteristics of the display system. Thus, the histogram construction method does not limit this patent.

  In addition, a histogram is created for each of R, G, and B, and a pixel of a specific gradation including the highest gradation only for a color (generally B (blue)) whose color characteristics of high gradation do not significantly affect the visual sense. The number may not be added to the cumulative value of the histogram, and a plurality of colors (for example, B (blue) and R (not including the number of pixels of a specific gradation including the highest gradation) may be added to the cumulative value of the histogram. Red)). With this configuration, it is possible to reduce the power consumption in accordance with the display characteristics of the display device without further affecting the image quality.

(Second Embodiment)
Next, a second embodiment of the present invention will be described. The overall configuration of the display device of the present embodiment is the same as that of the first embodiment. In this embodiment, the configurations of the histogram cumulative value calculation circuit 106 and the coefficient calculation circuit 107 in the display device driving circuit 101 are different from those of the first embodiment. However, the input / output interface 105, the pixel expansion circuit 109, the back The light controller 108, the liquid crystal controller 110, the drive circuit memory 113, the timing control circuit 114, and the like perform the same operation. In addition, the same operation as that of the first embodiment is performed for portions other than the display device driving circuit 101.

  FIG. 12 shows a detailed block diagram of the histogram cumulative value calculation circuit 1060 and the coefficient calculation circuit 1070 according to the second embodiment.

  The histogram cumulative value calculation circuit 1060 includes an RGB maximum value extraction circuit 501 and a histogram counter 504. On the other hand, the coefficient calculation circuit 1070 includes a mode setting register 1101, a selector 1102, an adder 1103, a selector 1104, a counter 1105, a threshold determination value storage register 1106, and an averaging circuit 1107.

  The RGB maximum value extraction circuit 501 is a circuit that selects the maximum value among the red (R), green (G), and blue (B) data of one pixel transmitted from the input / output interface circuit 105 and outputs it to the selector 503. There is a circuit configuration similar to that of the first embodiment.

  A histogram counter 5040 creates a histogram from display data for one frame. When the creation of the histogram is completed, the frame end signal 1108 is output to the adder 1103 and the counter 1105, which is different from the histogram counter 504 of the first embodiment.

  The mode setting register 1101 is a register for selecting a mode for determining whether or not to include the count value of the maximum gradation in the coefficient calculation. When this register is “1”, it indicates that the count value of the maximum gradation is not included in the histogram, and when it is “0”, it indicates that the count value of the maximum gradation is included. This mode setting register 1101 is assumed to be rewritten with a register write signal as a trigger.

  The selector 1102 is a selector that outputs the histogram data 1109 as it is when the mode register 1101 is mode “1” and the counter 1105 is 256, and the output is “0”.

  When the output of the selector 1104 is “0”, the adder 1103 is an adder that adds and holds the output of the selector 1102 to the currently held value using an internal clock (not shown) as a trigger.

  The selector 1104 outputs “0” when the output of the adder 1103 is less than the value of the threshold determination value storage register 1106, and when the output of the adder 1103 is greater than or equal to the value of the threshold determination value storage register 1106. , “1”.

  The counter 1105 is a decrement counter that is preset to 256 by the frame end signal 1108, decrements by 1 in synchronization with the internal clock when the output of the selector 1104 is “0” and the frame end signal 1108 is “1”. The counter 1105 operates with the rising edge of the internal clock as a trigger.

  The threshold determination value storage register 1106 is a register for storing a determination value in which the smallest gradation among the cumulative values of the histogram smaller than the value of the threshold determination value storage register 523 is the threshold gradation. This has the same function as the threshold determination value storage register 523 of the first embodiment. As with the mode setting register 1101, it is assumed that rewriting is performed using a register write signal as a trigger.

  The averaging circuit 1107 obtains the average value of the pixel expansion coefficients of the most recent frames in order to prevent flicker, and registers 540, 542, 544, and 546, adders 541, 543, and 545 according to the first embodiment, and division. The configuration of the calculator 547 is the same.

  FIG. 13 is a timing chart illustrating the operation of the coefficient calculation circuit 1070 according to the second embodiment. The operation of the second embodiment will be described based on the above configuration and the timing chart of FIG.

  When the histogram counter 5040 completes the creation of the histogram, it outputs a frame end signal 1108. The histogram data 1109 is output to the selector 1102 step by step in synchronization with the internal clock in order from the 255th gradation.

  As described above, the counter 1105 is preset to 256 by the frame signal, and when the output of the selector 1104 is “0” and the frame end signal 1108 is “1”, the counter 1105 is decremented by 1 in synchronization with the internal clock.

  When the frame end signal 1108 becomes active (“1”), the output of the selector 1104 is “0”. Therefore, when the frame end signal 1108 becomes active (“1”), the counter 1105 starts decrementing one by one from 256 at the rising timing of the internal clock.

  Under the operating conditions of FIG. 13, the value of the mode setting register 1101 is “1”. That is, the count value of the maximum gradation is not included in the accumulated value of the pixel expansion coefficient. Therefore, when the counter 1105 is 256, the output of the selector 1102 is “0”, and the histogram value 255D for 255 gradations is not output. On the other hand, the histogram value of 254 gradations or less has the operation condition of the selector 1102 because the counter 1105 is 255 or less. Accordingly, the selector 1102 outputs the histogram counter output in synchronization with the rising timing of the internal clock, such as the histogram value 254D of 254 gradation, the histogram value 253D of 253 gradation,.

  When the output of the selector 1104 is “0”, the adder 1103 adds the output of the selector 1102 to the currently held value, holds it, and outputs it. Therefore, the output of the adder 1103 is “0” because the output of the selector 1102 is “0” at the first clock, and “254D” because the output of the selector 1102 is “254D” at the second clock. Since the output of the selector 1102 is “253D”, it increases to “254D + 253D”.

  Here, it is assumed that the value of the threshold determination value storage register 1106 is larger than “254D + 253D + 252D + 251D + 250D” and smaller than “254D + 253D + 252D + 251D + 250D + 249D”. The selector 1104 outputs “1” because the operation condition is satisfied when the output of the adder becomes “254D + 253D + 252D + 251D + 250D + 249D”.

  Since the change in the output value of the selector 1104 does not satisfy the operating condition of the counter 1105, the counter 1105 stops decrementing. Further, since the operation condition of the adder 1103 is not satisfied, the addition is also stopped and the current value is kept. The value of the counter 1105 at this time (“249” in FIG. 13) is output as a pixel expansion coefficient for one frame.

  The pixel expansion coefficient for one frame is output to the averaging circuit 1107. A value obtained by averaging the pixel expansion coefficients of a plurality of frames is output as a pixel expansion coefficient to the backlight controller 108 and the pixel expansion circuit 109 in FIG.

  By operating in this way, in the second embodiment, in the case of a binary image such as a black character on a white background, the CPU 102 determines “0” in the mode setting register 1101 by determining the application. Since the pixel expansion coefficient is determined by writing and including the histogram value of 255 gradations, even in the case of a binary image, it is possible to maintain good image quality without lowering the luminance.

  When displaying a digital camera image with many natural images, the CPU 102 determines the application by writing “1” in the mode register 1101 and determining the pixel expansion coefficient by removing the histogram value of 255 gradations. Since the peak at 255 gradations is not included in the calculation, power consumption can be reduced without much deterioration in image quality.

(Third embodiment)
Next, a third embodiment will be described.

  FIG. 14 is a block diagram of the third embodiment.

  In the third embodiment, an illuminance sensor 1301 for measuring the illuminance of the backlight 111 and an illuminance sensor control circuit 1302 for controlling the illuminance sensor 1301 are provided for the display device of the first embodiment. The display driving device 101 is different from the first embodiment in that it is included in the display driving device 101.

  In the third embodiment, when the CPU 102 issues a backlight illuminance acquisition command through the input / output interface circuit 105, the backlight illuminance is acquired and reported to the CPU 102. The CPU 102 acquires the backlight illuminance at the time of system startup or the like, and when the backlight illuminance is large, increases the value of the threshold determination value storage register 523 to obtain good power saving characteristics. In addition, when the backlight illuminance decreases due to deterioration over time or the like, the value of the threshold determination value storage register 523 can be decreased to prevent the screen brightness from being excessively decreased.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention can be applied to a display device using an element for controlling the transmittance of a backlight and a liquid crystal, for example, an electronic device such as a television, a personal computer, or a mobile phone using the liquid crystal display device.

It is a conceptual diagram for demonstrating the pixel expansion coefficient and threshold determination value in this invention. It is a conceptual diagram for demonstrating the lower limit of the pixel expansion coefficient in this invention. 1 is a block diagram of a display device drive circuit according to a first embodiment of the present invention. It is a figure which shows the example of the histogram in connection with this invention. It is a graph showing the response | compatibility of the operation | movement of the backlight controller in connection with the 1st Embodiment of this invention, and the gradation luminance characteristic of a liquid crystal screen. It is a conceptual diagram about the pixel expansion | extension regarding the 1st Embodiment of this invention. It is a detailed block diagram of a histogram cumulative value calculation circuit and a coefficient calculation circuit according to the first embodiment of the present invention. It is an example of a setting of the histogram boundary setting register concerning the 1st Embodiment of this invention. It is a figure which shows the example of the histogram of the black-and-white binary image in connection with description of the 1st Embodiment of this invention. It is a figure which shows the example of the histogram of the image with a high-intensity but a delicate shadow in connection with description of the 1st Embodiment of this invention. It is a figure which shows the example of the histogram of the image of the characteristic which the gradation-luminance characteristic in connection with description of the 1st Embodiment of this invention has an upward convex characteristic in the vicinity of the highest gradation. It is a block diagram of a histogram cumulative value calculation circuit and a coefficient calculation circuit according to the second embodiment of the present invention. It is a timing chart which shows operation | movement of the coefficient calculating circuit of the 2nd Embodiment of this invention. It is a block diagram of the display apparatus drive circuit of the 3rd Embodiment of this invention. It is a figure which shows the example of the histogram which has the peak which protruded in the maximum gradation regarding description of the premise of this invention. It is an example of the image which a light source enters in the screen in connection with description of the premise of this invention. It is a figure explaining that a peak is biased to the highest gradation at the time of analog-digital conversion related to explanation of the premise of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... Display apparatus, 101 ... Display apparatus drive circuit, 102 ... Central processing unit (CPU),
103: Display memory, 104: Internal bus,
105: I / O interface circuit, 106: Histogram cumulative value calculation circuit,
107: coefficient calculation circuit, 108: backlight controller,
109 ... Pixel expansion circuit, 110 ... Liquid crystal controller,
111 ... Backlight, 112 ... Liquid crystal screen, 113 ... Drive circuit memory,
114 ... Timing control circuit,
501 ... RGB maximum value extraction circuit, 502 ... Histogram boundary setting register,
503 ... selector, 504 ... histogram counter,
521 ... Threshold storage register, 522 ... Selector,
523 ... Threshold determination value storage register, 524 ... Selector,
525-539 ... adders, 540, 542, 544, 546 ... registers,
541, 543, 545 ... adders, 547 ... dividers,
1060 ... Histogram cumulative value calculation circuit, 1070 ... Coefficient calculation circuit,
1101 ... Mode setting register, 1102 ... Selector, 1103 ... Adder,
1104 ... selector, 1105 ... counter,
1106: Threshold determination value storage register, 1107 ... Averaging circuit

Claims (13)

A display device driving circuit for driving a light source capable of controlling the amount of light and a display device that performs display by controlling a transmittance control element that controls the transmittance of light disposed in front of the light source;
Except for the highest gradation of the display image, the display device driving circuit accumulates the number of pixels for each gradation of the display image, and the accumulated value from the highest gradation to be accumulated reaches a certain percentage of the total number of pixels. Display image data is expanded with a threshold gradation as a maximum gradation, and the light source is controlled to have a luminance corresponding to the display luminance of the threshold gradation during the maximum gradation display. . A histogram cumulative value calculation circuit for calculating a histogram of the display image frame;
A coefficient arithmetic circuit for calculating a pixel expansion coefficient;
A display device driving circuit that drives a display device that performs display by controlling a light source capable of controlling the amount of light, including a pixel expansion circuit, and a transmittance control element that controls the transmittance of light disposed in front of the light source. There,
The histogram cumulative value calculation circuit sums and outputs the number of pixels of each gradation for each display image frame, and the pixel expansion coefficient is a pixel that is a gradation value excluding the highest gradation of the display image to be accumulated. Is a gradation corresponding to a predetermined ratio of the total number of pixels included in the display image,
The coefficient calculation circuit derives the pixel expansion coefficient from the total value of each gradation, and outputs an output pixel expansion coefficient,
The pixel expansion circuit expands the gradation of the display image frame so that the output pixel expansion coefficient becomes the highest gradation so that the luminance corresponding to the display luminance of the pixel expansion coefficient at the time of the highest gradation display. A display device driving circuit which controls the light source.   3. The display device driving circuit according to claim 2, wherein the histogram cumulative value calculation circuit includes a threshold storage register, and the highest histogram only when the number of pixels of the highest gradation is larger than a value of the threshold storage register. A display device driving circuit which outputs the number of pixels of gradation.   3. The display device driving circuit according to claim 2, wherein the histogram cumulative value calculation circuit has a mode switching register, and outputs the number of pixels of the highest gradation according to the setting of the mode switching register. Display device driving circuit.   3. The display device driving circuit according to claim 2, wherein the histogram cumulative value calculation circuit outputs the number of pixels of each gradation through different signal lines.   3. The display device driving circuit according to claim 2, wherein the histogram cumulative value calculation circuit sequentially outputs the number of pixels of each gradation through the same signal line.   3. The display device driving circuit according to claim 2, wherein the coefficient calculation circuit includes a threshold determination value storage register for holding a threshold determination value, and the coefficient calculation circuit sequentially changes the pixel of each gradation from the one having the high gradation. A display device driving circuit comprising: adding a number to determine the pixel expansion coefficient for each display image frame in comparison with the threshold determination value.   8. The display device driving circuit according to claim 7, wherein the coefficient calculation circuit derives the pixel expansion coefficient for each of the plurality of display image frames and outputs an average value thereof as the output pixel expansion coefficient. Display device driving circuit.   3. The display device driving circuit according to claim 2, wherein the pixel expansion circuit linearly expands gradations less than or equal to the output pixel expansion coefficient.   8. The display device driving circuit according to claim 7, further comprising a CPU and an illuminance sensor, wherein the CPU rewrites a value of the threshold determination value storage register according to the illuminance acquired by the illuminance sensor. Display device drive circuit.   11. The display device driving circuit according to claim 2, further comprising a backlight and a backlight controller, wherein the backlight controller controls the backlight according to the pixel expansion coefficient. A display device driving circuit.   A display device comprising the display device drive circuit according to claim 2.   An electronic apparatus comprising the display device according to claim 12.

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