JP2010113052A - Display driving device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display driving device capable of mitigating the degree of degradation of image quality visualized when extending image data and dimming backlight. <P>SOLUTION: The display driving device produces an extension coefficient having a relationship obtained by dividing the maximum gradation value which display data possess with a gradation threshold as a gradation value smaller than the maximum gradation value, supplies the display data extended based on the extension coefficient to a display device and performs dimming control of the backlight module based on the reciprocal of the extension coefficient. A part where a gradation difference for an adjacent pixel exists before extension of the image but the gradation difference is removed after the extension of the image is counted. That is, at every prescribed data amount such as display frame unit of the display data, a frequency with which such a state that gradations are equal to each other between adjacent pixels and both gradations exceed the gradation threshold occurs is measured. The gradation threshold is changed in such a direction that the measurement results fall into a prescribed allowable range. Thereby, in accordance with the degree of gradation of the display data, such a control as to dynamically change the degree of extension and the degree of dimming is performed. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to display data gradation expansion control and backlight dimming control in a display driving device that drives a display device such as a liquid crystal display panel according to display data, and relates to a technique effective when applied to, for example, a liquid crystal display driver LSI. Is.

  In recent years, liquid crystal displays are mounted on battery-operated information devices and mobile phones. Most of these displays are transmissive and transflective types that require a backlight. Currently, much of the power consumption of the liquid crystal display is occupied by the backlight, and it is necessary to devise measures to reduce this power. It has become. Especially in mobile phones, it is possible to view moving images on a TV or the like, and it is necessary to drive the battery for a long time while displaying the display.

  As a device for reducing the power consumption of the backlight, there is a method disclosed in Patent Document 1. For example, when the backlight emits 100% and the front liquid crystal cell has 80% transmission, what is visible is 80% light. In this case, the liquid crystal cell is down by 20% even though the backlight emits 100%. On the other hand, when the backlight emits 80% and the liquid crystal cell transmits 100%, what can be seen is 80% of the light, but the backlight can be reduced to 80%. Utilizing these differences, the amount of light emitted from the backlight is suppressed.

  When a pixel value histogram of an image has a maximum luminance of a pixel with 80% luminance, the backlight is reduced to light emission of 80%, which is 4/5 times, and displayed accordingly. By multiplying the values of all the pixels of the image by 5/4, the same image can be displayed with a light emission amount of 80%.

  Furthermore, using the histogram, paying attention to the pixels in the top several percent rank, for example, when this portion has 60% luminance, the amount of light emitted from the backlight is suppressed to 60% of 3/5. A similar image can be obtained by multiplying all the pixel values by 5/3. In this case, display can be performed with a smaller amount of light emission than in a method using the maximum luminance of an image. However, at this time, when the pixel value is multiplied by 5/3, a pixel larger than 3/5 of the maximum value is saturated to the maximum value. For this reason, this pixel becomes darker than the original luminance when the light emission amount of the backlight is suppressed to 3/5. As a result, this method involves a certain degree of image quality degradation.

JP-A-11-65531

  In the method of Patent Document 1, the original image is displayed in a similar manner by reducing the backlight luminance by the amount corresponding to the expansion of the image data. In this method, the original gradation difference is eliminated in the area where the gradation is saturated, the local contrast of the image is deteriorated, and it is visually recognized as gradation collapse. This deterioration in image quality due to gradation loss tends to be more visible as the number of gradation generation gradations, that is, the number of pixels in the saturation area increases, but depending on the image, the gradation in the saturation area tends to be visible. In some cases, the gray level is easily observed even when the number of pixels is not so large. As a result, there is a problem that even if the number of pixels in which the gradation is saturated is the same, the degree of degradation in image quality that can be visually recognized varies.

  An object of the present invention is to provide a display driving device that can reduce the degree of deterioration of image quality that can be visually recognized when image data is expanded and a backlight is dimmed.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  That is, the display device generates an expansion coefficient having a relationship obtained by dividing the maximum gradation value of the display data by the gradation threshold value which is a smaller gradation value, and expands the display data based on the expansion coefficient. And dimming control of the backlight module based on the reciprocal of the expansion coefficient. At this time, a portion where there is no gradation difference after expansion at a portion where there is a gradation difference with the adjacent pixel before expansion of the image is counted. That is, for each predetermined data amount such as a display frame unit of display data, the frequency of occurrence of a state in which gradation is equal between adjacent pixels and both exceed the gradation threshold is measured. The gradation threshold value is changed in a direction in which the measurement result falls within a predetermined allowable range. As a result, control is performed to dynamically change the degree of expansion and dimming according to the gradation level of the display data, so that the original gradation difference is eliminated in the area where gradation is saturated, and the local contrast of the image is deteriorated. Thus, the variation in the degree of deterioration of the image quality that is visually recognized as gradation collapse is alleviated.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, it is possible to realize backlight control in which the degree of degradation of visible image quality does not become uneven depending on the image, and it is possible to save power by backlight dimming according to the visually observable image quality degradation.

1. First, an outline of a typical embodiment of the invention disclosed in the present application will be described. Reference numerals in the drawings referred to in parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

  [1] <Dynamic control of gradation threshold> A display drive device (101) for driving a display device (114) whose pixel luminance is controlled by the transmittance of light from the backlight module (115) according to display data. And a backlight control unit (104) for performing expansion control of the display data and dimming control of the backlight module. The backlight control unit generates an expansion coefficient arithmetic circuit (dy) having a relationship obtained by dividing the maximum gradation value (Dth) of display data by a gradation threshold value which is a smaller gradation value ( 210), an expansion circuit (211) that expands display data based on the expansion coefficient, and a dimming coefficient calculation circuit (212) that determines the dimming rate of the backlight module based on the inverse of the expansion coefficient; Measuring circuits (201, 202C, 202P, 203B, 203A, 204H, 204V, 205H) that measure the frequency of occurrence of a state in which the gradation is equal between adjacent pixels and both exceed the gradation threshold for each predetermined amount of display data , 205V, 206, and a gradation threshold control circuit (207) that changes the gradation threshold in a direction in which the measurement result of the measurement circuit falls within a predetermined allowable range. To.

  As a result, the degree of expansion and dimming are dynamically changed in accordance with the gradation level of the display data, so that the original gradation difference disappears in the gradation saturated area and the local contrast of the image deteriorates. Variation in degree is reduced. Therefore, it is possible to realize backlight control in which the degree of degradation of visible image quality does not become uneven depending on the image, and it is possible to save power by backlight dimming in accordance with the visually observable image quality degradation.

  [2] In the display driving device according to [1], the measurement circuit is configured such that the gradation is equal between both adjacent pixels in the horizontal direction and between adjacent pixels in the vertical direction and the gradation threshold value is set between the adjacent pixels. Measure the frequency at which the exceeding condition occurs.

  [3] In the display driving apparatus according to item 1, the predetermined data amount is an image data amount of one frame.

  [4] In the display driving device according to [1], the gradation threshold control circuit decreases the gradation threshold when the measured value is equal to or lower than the lower limit value of the allowable range, and the measured value is equal to or higher than the upper limit value of the allowable range. Sometimes the gradation threshold is increased.

  [5] The display driving device according to item 4, further comprising a register (208, 209) in which the value of the allowable range is rewritable from the outside of the display driving device, wherein the gradation threshold control circuit is the register Refer to the set value.

  [6] << With Interpolation >> A display driving apparatus according to another aspect of the present invention has a dynamic control of the gradation threshold, a reduction in the degree of expansion from before the gradation threshold, and a variable section (interpolation section). To do. That is, the display driving device (101) that drives the display device (114) whose pixel brightness is controlled by the transmittance of light from the backlight module (115) in accordance with the display data includes the expansion control of the display data and the backlight. A backlight control unit (104) that performs dimming control of the light module is provided. The backlight control unit is a reduction unit that determines a dimming rate of the backlight module based on a value obtained by dividing a gradation threshold value that is a gradation value smaller than the maximum gradation value of display data by the maximum gradation value. An optical coefficient arithmetic circuit (212) and an expansion coefficient (dy) having a relationship obtained by dividing the maximum gradation value of display data by the gradation threshold value in a non-interpolation section having a gradation value (Dth) smaller than the gradation threshold value. In addition, the interpolation section base point coefficient (dx (*)), the interpolation section extension coefficient (dy (*)), and the gradation of the interpolation section base point, which are the base points of the interpolation section, are generated based on the interpolation section width value in the interpolation section. An expansion coefficient arithmetic circuit (608) for generating a certain gradation offset coefficient (ofsy (*)), and display data is expanded based on the expansion coefficient in the non-interpolation section, and the display data is expanded for the interpolation section in the interpolation section. An expansion circuit (603) that expands based on the above, a gradation threshold control circuit (607) that determines the gradation threshold, and between adjacent pixels of the expanded display data in the interpolation interval for each predetermined amount of display data And a first measurement circuit (601A, 601B, 203B, 602A, 602B, 201, 605, 203A, 602A to 602D, 205H, 205V, 206) for measuring the frequency of occurrence of the same gray level, and the first measurement. An interpolation section control circuit (606) that changes the interpolation section width value in a direction that fits the measurement result of the circuit within a predetermined allowable range and applies the result to the expansion coefficient calculation circuit.

  As a result, it is possible to further reduce variations in the degree of deterioration in image quality, in which the original gradation difference is eliminated in the gradation saturation region and the local contrast of the image is deteriorated.

  [7] In the display driving device according to item 6, the predetermined data amount is an image data amount of one frame.

  [8] << Extension control of interpolation section >> In the display driving apparatus according to item 6, the first measurement circuit is arranged between adjacent pixels in the horizontal direction and adjacent pixels in the vertical direction as adjacent pixels of the display data expanded in the interpolation section. The frequency of occurrence of a state where the expanded gradation is the same for both of them is measured.

  [9] In the display drive device described in [8], the interpolation section control circuit changes the interpolation section value so that the interpolation section is expanded when the measurement value by the first measurement circuit is less than or equal to the lower limit value of the allowable range. Then, the interpolation section value is changed so as to reduce the interpolation section when the measurement value by the first measurement circuit is equal to or greater than the upper limit value of the allowable range.

  [10] The display driving device according to [9], further comprising a register (208, 209) in which the value of the allowable range is rewritable from outside the display driving device, and the interpolation section control circuit Refer to the setting value.

  [11] << Extension control of non-interpolation interval >> In the display driving apparatus according to item 6, for each predetermined data amount of display data, the frequency of occurrence of a state in which the gradation is equal between adjacent pixels and both exceed the gradation threshold. The gradation threshold value control circuit further changes the gradation threshold value in a direction in which a measurement result obtained by the second measurement circuit falls within a predetermined allowable range.

  [12] In the display driving apparatus according to item 11, the second measurement circuit has the same gradation between the adjacent pixels and between the adjacent pixels in the horizontal direction and between the adjacent pixels in the vertical direction. The frequency at which a state exceeding the threshold occurs is measured.

  [13] In the display drive device of item 12, the gradation threshold control circuit reduces the gradation threshold when the measurement value by the second measurement circuit is equal to or lower than the lower limit value of the allowable range, and the measurement value is within the allowable range. When the upper limit value is exceeded, the gradation threshold value is increased.

  [14] The display driving device according to [13], further including a register in which the value of the allowable range is rewritable from the outside of the display driving device, and the gradation threshold control circuit refers to the setting value of the register To do.

2. Details of Embodiments Embodiments will be further described in detail.

Embodiment 1
FIG. 1 illustrates a liquid crystal display device including a liquid crystal driver and a periphery according to a first embodiment of the present invention. In the figure, reference numeral 101 denotes a liquid crystal driver body. The liquid crystal driver body 101 is not particularly limited, but is formed on one semiconductor substrate such as a single crystal silicon substrate. Reference numerals 102 to 110 represent internal blocks of the liquid crystal driver. Reference numeral 102 denotes a system interface of the liquid crystal driver, which transfers display data and write data to a control register for controlling various portions of the liquid crystal driver from the outside of the driver to an internal block. Reference numeral 103 denotes a control register which is a set of registers for controlling each part of the liquid crystal driver.

  A backlight control unit 104 is a central block of the present invention, receives display data output from the graphic RAM 105, performs display data expansion processing described later, and transfers the display data to the source line driving circuit 108. In particular, with regard to backlight control, attention is focused on gradations that mean luminance in the display data. Even if there is no particular description, attention is focused on gradation data when simply referred to as display data for backlight control. A graphic RAM 105 serves as a buffer that receives and accumulates display data via the system interface 102 and delivers display data to the source line driver circuit 108 via the backlight control unit 104. The timing generation circuit 106 generates the operation timing of the entire liquid crystal driver based on the contents of the control register 103. A gradation voltage generation circuit 107 generates a gradation voltage used in the source line driver circuit 108. The source line driver circuit 108 uses the display data transmitted from the backlight control unit 104, selects a specific voltage from the gradation voltages created by the gradation voltage generation circuit 107, and externally outputs it as the liquid crystal source signal 110. Is output. The liquid crystal drive level generation circuit 109 generates a gate signal and a common signal 111 used for driving the liquid crystal and outputs them to the outside.

  In addition, there are the following external blocks. The control processor 113 creates display data and transfers it to the liquid crystal driver via the system interface 102. The backlight power supply circuit 116 generates a desired voltage based on the information of the backlight control signal 112 transmitted from the backlight control unit 104 and supplies the desired voltage to the backlight module 115. The liquid crystal panel 114 receives the liquid crystal source signal 110, the liquid crystal gate signal, and the common signal 111 from the liquid crystal driver, and performs display. Further, the backlight module 115 receives power from the liquid crystal driver through the backlight power line 113, lights the backlight with a desired brightness, and illuminates the liquid crystal panel 114. Thereby, the display of the liquid crystal panel can be viewed as visible light.

  Using these blocks, the liquid crystal driver operates as follows. Display data is fetched from outside via the system interface 102 and stored in the graphic RAM 105. The timing generation circuit 106 generates a read timing of the graphic 105 and transfers display data to the backlight control unit 104 at that timing. The backlight control unit 104 performs display data expansion processing, which will be described later, and transfers it to the source line driver circuit 108. In this case, a voltage is selected from the gradation voltage generated by the gradation voltage generation circuit 107 using the above-described display data, and is transmitted to the liquid crystal panel 114 as the liquid crystal source signal 110. In addition, using the timing generated by the timing generation circuit 106, the liquid crystal drive level generation circuit 109 generates a liquid crystal gate signal and a common signal 111, which are also transmitted to the liquid crystal panel 114. In addition, a voltage is generated by the backlight power supply circuit 116 based on information from the backlight control unit 104 and applied to the backlight power supply line. As a result, the backlight module 115 is turned on. The lit backlight module 115 illuminates the liquid crystal panel 114 from the back, and the liquid crystal panel 114 transmits light according to the driving state to form a display.

  Here, the principle of the display data expansion processing by the backlight control unit 104 will be described with reference to FIGS. 4A and 4B.

  FIG. 4A shows a state of presence or absence of local contrast (hereinafter also simply referred to as an edge) in adjacent pixels. Reference numerals 401 and 402 indicate the actual appearance of the pixel when gradation collapse occurs due to edge disappearance. 401 shows the state of the pixel at the time of input. Since the central pixel PXn has a different value from the gradation of pixels near the top, bottom, left, and right, there is a local contrast between these pixels. Therefore, an edge exists between the center and four neighboring pixels. On the other hand, 402 shows how a pixel is seen as a gradation (gradient after expansion) after the gradation is multiplied by n (1 <n <2) with respect to the input image. Here, the central pixel PXn has the same gradation as the four neighboring pixels, and the local contrast is lost. In the present invention, the gradation collapse of an image is measured by counting the number of states having no edge between pixels as a local contrast with respect to the threshold gradation Dth. FIG. 4B illustrates a condition in which actual gradation collapse occurs. A bold line 404 in the drawing represents an extended gradation characteristic line obtained by extending the original gradation characteristic line 403. When the data gradation is expanded, there is no change in the maximum gradation as the display hardware, so no difference in display appears for gradations greater than Dth. For example, consider a case where there are input data D1 and D2 of two pixels, each having a gradation greater than Dth. At this time, it can be visually confirmed on the display that the gradation of the input data D1 and D2 is different gradation data with respect to the gradation characteristic line 403. However, according to the extended gradation characteristic line 404, the gradation difference on the display does not appear between gradations whose input gradations are Dth or more, and gradation collapse occurs. The condition that gradation collapse occurs due to expansion is that both input gradations of adjacent pixel data are not the same gradation, and both are gradations equal to or greater than Dth. Based on this, the determination circuit of FIG. 2 is configured.

  FIG. 2 is an internal detail view of the backlight control unit. In the figure, 201 is a line memory, 202C and 202P are comparators, 203A and 203B are data latches, 204H and 204V are comparators, 205 is an AND circuit, 206 is an extinction edge coefficient counter, and 207 is a threshold gradation (Dth) adjustment controller. , 208 is an erasure edge allowable number register, 209 is an erasure edge allowable number gap register, 210 is an expansion coefficient arithmetic circuit, 211 is an expansion circuit, 212 is a backlight dimming coefficient arithmetic circuit, 213 is display data, and 214 is a threshold gradation. Values (Dth), 215 are horizontal disappearance edge signals, 216 is a vertical disappearance edge signal, 217 is the number of disappearance edges, 218 is display data after expansion, and 219 is a backlight dimming coefficient.

  A line memory 201 is a first-in first-out (FIFO) memory that can hold display data 213 for one line in the horizontal direction, sequentially holds valid display data, and sequentially reads out after one horizontal period. Since the display data of the next line is always written after the display data of the previous line is read out, it is sufficient to have a capacity for one horizontal line of display data. The comparators 202C and 202P compare the value of the input display data with a threshold gradation value (hereinafter referred to as Dth) 214, and when the input display data has a gradation equal to or higher than Dth, the output is true (high level). Otherwise, it is false (low level). The data latch 203B delays the input display data 213 by one dot clock (one pixel shift interval) and outputs it. The comparators 204H and 204V compare the gradations of the input display data, and output true (high level) when the values do not match, and false (low level) when the values match. For example, in FIG. 4A, the comparator 202C determines whether the gradation of the pixel PXn is larger than Dth, and the comparator 202P determines whether the gradation of the pixel PXn is larger than the gradation of the same vertical direction pixel PXi one line before. The comparator 204V determines whether the gray level of the pixel PXn does not match the gray level of the pixel PXi, and the comparator 204V determines whether the gray level of the pixel PXn does not match the gray level of the pixel PXm. .

  The data latch circuit 203A delays the input determination result by one dot clock time and outputs it. The AND circuit 205H takes a logical product with the output of the data latch circuit 203A, the output of the comparator 202C, and the output of the comparator 204H as three inputs. That is, when the input gradations of two pixels adjacent to each other in the horizontal direction (for example, PXm and PXn in FIG. 4) are not the same gradation and both are gradations equal to or higher than Dth, the output 215 of the AND circuit 205H is Become high level. The AND circuit 205V takes a logical product with the outputs of the comparators 202C, 202P, and 204V as three inputs. That is, when the input gradations of two pixels adjacent to each other in the vertical direction (for example, PXi and PXn in FIG. 4) are not the same gradation, and both are gradations equal to or higher than Dth, the output 216 of the AND circuit 205V is Become high level.

  The disappearance edge counter 206 is a counter that increments +1 when the input 215 horizontal direction disappearance edge signals and 216 vertical direction disappearance edge signals become true. When the horizontal direction extinction edge signal and the vertical direction extinction edge signal are each independently true, +1 is performed. When the two signals are simultaneously true, +2 is performed. This is totaled for one frame, and the result is output as 217 extinction edge numbers. The Dth of the adjustment controller 207 receives the number of annihilation edges of 217, and determines and outputs the Dth used in the next frame from the erasure edge allowable number register value 208 and the erasure edge allowable number gap register value 209. The extinction edge allowable number register 208 and the extinction edge allowable number gap register 209 are arranged in the control register 103 and are readable / writable via the system interface 102 from the control processor 113. By holding the written value and outputting it to 207, the operation of the controller 207 is controlled. The expansion coefficient calculation circuit 210 calculates the expansion coefficient dy used by the expansion circuit 211 based on the Dth value output from the controller 207. As a simple example, the expansion coefficient dy can be calculated by dividing the maximum gradation value of the image data by Dth. The expansion circuit 211 uses the expansion coefficient calculated by the arithmetic circuit 210 to expand the display data 213 and outputs it as display data 218 after expansion. The backlight dimming count calculation circuit 212 calculates the backlight dimming coefficient 219 using the Dth value output from the controller 207. As an example of the calculation method, using the result obtained by dividing the value of Dth by the maximum gradation value of the display data, the power of the gamma value of the display panel is calculated to obtain the backlight dimming coefficient.

  Using these blocks, the backlight control unit operates as follows. First, the input display data 213 is input to the comparators 202C and 202P and compared with Dth 214. The data latch 203A temporarily holds the comparison result and delays it by one pixel. Further, the display data 213 is delayed by one dot clock by the data latch 203B, and it is determined by the comparator 204H whether the gradations of the adjacent data in the horizontal direction do not match. Whether the gradation of the adjacent data in the vertical direction does not match is determined by the comparator 204V. As a result, a horizontal disappearance edge signal is output from the AND circuit 205H, and a vertical disappearance edge signal 216 is output from the AND circuit 205V. The horizontal disappearance edge signal 215 and the vertical disappearance edge signal 216 are counted for one frame by the disappearance edge counter 206, and the result is transmitted to the Dth adjustment controller 207. The Dth adjustment controller 207 determines and outputs the Dth of the next frame based on the count result of the erasure edge, the value of the erasure edge allowable number register 208, and the value of the erasure edge allowable number gap register 209. Using the determined Dth, the expansion coefficient calculation circuit 210 determines the expansion coefficient, and based on this, the display data gradation of the next frame is expanded using the expansion circuit 211 and output as the display data 218 after expansion. To do. At the same time, the backlight dimming coefficient calculation circuit 212 determines and outputs the backlight dimming coefficient 219 based on Dth.

  FIG. 3 is an internal detail view of the Dth adjustment controller 207 in FIG. In the figure, 301 is an adder, 302A and 302B are magnitude comparators, 303 is a Dth operation circuit, and 304 and 305 are table data indicating the relationship between the input and output of the Dth operation circuit 303. The adder 301 adds two input numerical values and outputs the result. The comparators 302A and 302B compare the two input numerical values, determine the magnitude, and output the result as two signals having a large determination result and a small determination result. That is, if the number of annihilated edges is smaller, the determination result small signal is “1”, the determination result large signal is “0”, and if the number of erasure edges is larger, the opposite is true, and if the number is the same, both are “0”. "become. The Dth operation circuit 303 operates the value of Dth based on the outputs output from the two comparators 302A and 302B, and outputs the operated Dth from 214. It is logically impossible for both outputs of the comparators 302A and 302B to have “1” for both signals having a large determination result and a small determination result.

  A detailed example of the operation by the operation circuit 303 will be described. If both comparators 302A and 302B determine that the number of annihilation edges 271 is smaller, it means that the generation of annihilation edges can still be allowed, and the value of Dth is decremented by a specified number (decrease). If both comparators 302A and 302B determine that the number of annihilated edges 271 is larger, this means that the number of annihilated edges has reached the number of gaps from the allowable number, and the value of Dth is defined. Increment by a number (rise). Further, the comparator 302A determines that the number of annihilation edges 271 is larger or the number of annihilation edges is equal to the allowable number of annihilation edges, and the comparator 302B determines that the number of annihilation edges 271 is smaller or the number of annihilation edges. If it is determined that the erasure edge tolerance and the number of gaps are equal, Dth is held. This makes it possible to stabilize Dth in the vicinity of the set allowable number of extinction edges.

  As described above, it is possible to realize backlight control in which the degree of degradation of visible image quality does not become uneven depending on the image, and it is possible to perform power saving by backlight dimming according to the degree of image quality degradation that can be visually recognized.

<< Embodiment 2 >>
In the second embodiment, an interpolation process is performed to alleviate gradation collapse when the display data is expanded. FIG. 5 shows an expansion curve by the expansion circuit when an interpolation section is provided. In FIG. 5, reference numeral 50 denotes a gradation characteristic before the expansion process. Reference numeral 501 denotes an expansion curve when no interpolation processing is performed, and is saturated at the maximum gradation with Dth as a boundary. On the other hand, an example of an extension curve provided with an interpolation section in the range 502 is shown in 503. The extension curve 503 in the interpolation section has a slope, and the possibility of the same post-expansion gradation is reduced for the two input gradations in this section. As a result, gradation loss due to expansion processing is reduced.

  FIG. 6 illustrates a configuration in which the determination of the interpolation interval when performing the interpolation process is controlled by the number of extinction edges. In FIG. 6, functional blocks having the same functions as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted. 601A and 601B are interpolation section area determination circuits, 602A to 602D are comparators, 603 is an interpolation processing expansion circuit, 604 is a selector, 605V and 605H are vertical direction comparison value calculation circuits, 606 is an interpolation section adjustment controller, and 607. Is a Dth adjustment controller, 608 is an expansion coefficient arithmetic circuit, 609, 610 and 611 are interpolation coefficients for interpolation processing, and 609 is an interpolation section coefficient (hereinafter referred to as px (*)) as an interpolation section base point coefficient which is a base point of the interpolation section. ), 610 is an expansion coefficient in the interpolation section (hereinafter referred to as dy (*)), 611 is an interpolation section offset (hereinafter referred to as ofsy (*)) as a gradation offset coefficient that is the gradation of the interpolation section base point, and 612 This is an interpolation interval width value indicating the width of the interpolation interval. The display data in the non-interpolated section is subjected to the same expansion process as in the first embodiment using the expansion coefficient dy of 610A. The dimming control in the interpolation section and the non-interpolation section may be the same as in the first embodiment. Since the processing of the non-interpolated section is the same as that in the first embodiment, the detailed hole description is omitted.

  The Dth adjustment controller 607 is a circuit block that calculates a Dth value of 214 based on the display data 213. For example, the Dth adjustment controller 607 generates the Dth by adopting the configuration described in the first embodiment. Alternatively, Dth may be generated using a method described in Patent Document 1. Interpolation section area determination circuits 601A and 601B that determine a supplementary section that complements the generated Dth determine whether the display data 213 falls within the interpolation section, and output the result as a region number. For example, when the interpolation section is composed of four areas, a value of 0 to 4 is assigned as the area number together with the non-interpolation sections, and the determination result is also a signal indicating a range of 0 to 4. The comparator 602A determines whether adjacent horizontal pixels are included in the same interpolation area, and the comparison circuit 602B determines whether adjacent vertical pixels are included in the same interpolation area. The interpolation processing expansion circuit 603 processes the display data 213 with px (*), dy (*), and ofsy (*) of 609, 610, and 611, and generates post-expansion display data 218. At this time, the selector 604 is used to select px (*), dy (*), and ofsy (*) of the corresponding area using the area number output from the area determination circuit 601A. In the non-interpolated section, the selector 604 selects only the expansion coefficient dy according to the determination result of the area determination circuit 601A and expands the image data. First, px (*) is subtracted from the display data in the interpolation section, dy (*) is multiplied, and finally, ofy (*) is added to calculate decompressed data 218. Also, the data after multiplication of dy (*) is output as disappearance edge determination data. The comparison value calculation circuit 605 is a circuit in which the configuration of “ofsy (*) addition” is omitted from the expansion circuit 603, and uses the image data of the previous line to generate comparison edge determination data. . The comparison circuit 602C compares the gradation data for interpolation before the offset is added between adjacent pixels in the horizontal direction. The comparison circuit 602D compares the gradation data for interpolation before the offset is added with the gradation data for interpolation related to the corresponding pixel one line before. The comparison results of the comparison circuits 602C and 602D are ANDed with the outputs of the comparison circuits 601A and 602B and the AND circuits 205H and 205V to form a horizontal direction disappearance edge signal 215 and a vertical method disappearance edge signal 216. The horizontal direction disappearance edge signal 215 and the vertical method disappearance edge signal 216 are significant signals regarding the interpolation interval. The interpolation interval adjustment controller 606 adjusts the interpolation interval width 612 based on the number of annihilation edges 217 output from the erasure edge count counter 206 and sends it to the expansion coefficient calculation circuit 608. The expansion coefficient arithmetic circuit 608 uses the Dth supplied from the Dth adjustment controller 607 and the interpolation section width supplied from the interpolation section adjustment controller 606 to use the expansion processing coefficients (609, 610) used in the expansion circuit 603 and the like. , 611).

  For example, as an interpolation method, there is a linear interpolation method in which the start point of the interpolation section and the maximum gradation are interpolated with a straight line. When the interpolation section is operated in the direction of enlarging, the slope of the interpolation section (expansion coefficient dy (*)) increases, the local contrast in the interpolation section improves in most images, and the number of disappearing edges decreases. On the other hand, when the interpolation interval is reduced, the local contrast in the interpolation interval deteriorates in most images, and the number of disappearing edges increases. Therefore, by adjusting the width of the interpolation section with the interpolation section adjustment controller 606 so that the number of annihilation edges is close to the value of the erasure edge allowable number register 208, it is possible to obtain a display of the intended degree of gradation collapse. Become.

  FIG. 7 shows a specific example of the interpolation interval adjustment controller 606. This circuit performs almost the same operation as the Dth adjustment controller of FIG. 3 in the first embodiment, and there is a difference in output. In FIG. 3, the Dth value 214 is operated and output, but in FIG. 7, the interpolation interval width 612 is obtained. The operation is almost the same as in FIG. 3, and the output is changed as follows. If both comparator outputs 302A and 302B determine that the number of annihilation edges of 271 is smaller, it is determined that the annihilation edges are still acceptable, and the interpolation section width is reduced. If it is determined that the output of both comparators 302A and 302B has a larger number of 271 extinction edges, it is determined that the number of extinction edges exceeds the allowable number, and the width of the interpolation section is expanded. When the number of annihilation edges is smaller than or equal to 208, the annihilation edge allowable number register value is larger than or equal to the sum of the erasure edge allowable number register value and the erasure edge allowable number gap register value, the erasure edge number is almost annihilated. It is determined that the allowable number of edges matches, and the current interpolation section width is held. Note that there is no case where both the output magnitude signals of the comparators 302A and 302B are true at the same time, and therefore the operation of this block may not be guaranteed. Since it is configured as described above, the interpolation interval width is manipulated as follows according to the number of annihilated edges of 217. When the number of annihilation edges (217) input is smaller than the erasure edge allowable number register value (208), the interpolation interval width is reduced, and the erasure edge allowable number register value and the erasure edge allowable number gap register value (209) are operated. If the sum is greater than the sum of the two, the interpolation interval width is increased, and the interpolation interval width is maintained within the range of the disappearance edge allowable number register value and the disappearance edge allowable number gap register value. As a result, it is possible to stabilize the interpolation section width in the vicinity of the set allowable number of disappearing edges.

  FIG. 16 shows a specific example of the expansion coefficient calculation circuit 608. FIG. 16 shows an example in which the interpolation section is divided into four. Among the parameters used in the decompression circuit arithmetic circuit 608, px (*) and ofsy (*) of 609 and 611 are shown in the graph, and px (*) is the beginning of each of the four interpolation sections (input side ) And ofy (*) indicate the value on the output side at the beginning of each. At this time, dy (*) of 610 can be obtained from px (*) and ofsy (*) according to the equation shown in 1601. Further, using these values, the output out can be obtained from the input in by the expression shown in 1602. A circuit obtained by converting the expression 1602 into a circuit is a decompression circuit 603. With these equations, it is possible to obtain the output out in each interpolation section. In addition, various setting methods are conceivable for px (*) and ofsy (*). As an example, in the case of the above-described four divisions, px (1) is externally given to determine the interpolation section width 1603, and px (2), px (3) when this interpolation section width is equally divided into four. ), Px (4). Since px (1) is also the maximum value of the non-interpolated section 1604, by giving Dth of 1605, ofy (1) is determined, and about ofy (2), ofsy (3), and ofsy (4) Can be determined by the ratio with the value of ofy (1). Here, an example is shown in which all parameters can be determined simply by giving px (1) and Dth in the case of four divisions, but px (*), dy (*), ofsy (*) also by other methods. It is possible to determine

  FIG. 8 illustrates the operation of the interpolation section width using a graph of the input gradation and the expanded gradation. The upper graph in the figure shows the case where the interpolation section width is small. In this case, the allocated amount of the expanded gradation is small with respect to the interpolation interval width of the input gradation. That is, it is considered that a lot of gradation collapse occurs. By expanding the interpolation interval width as shown in the graph below, it is considered that the allocated amount of gradation after expansion increases and the number of gradation collapses decreases.

<< Embodiment 3 >>
In the third embodiment, an interpolation process for reducing gradation loss when the display data is expanded is divided into a plurality of areas.

  FIG. 9 exemplifies a configuration for controlling the determination of an interpolation section by the number of extinguished edges when performing an interpolation process in which a plurality of regions are divided. In the figure, circuit blocks having the same functions as those of the other embodiments are denoted by the same reference numerals, and detailed description thereof is omitted. Reference numeral 901 denotes an erasure edge counter, which is different from 206 in that it has one counter for each area for a plurality of areas, and counts the number of annihilation edges for each area using the area determination of the area determination circuit 601. Therefore, the output 903 is the number of disappearing edges for each region. The interpolation interval coefficient adjustment controller 902 generates and outputs an expansion coefficient control signal 904 for each area from the number of erasure edges 903 for each area. Compared with the expansion coefficient calculation circuit 608, the expansion coefficient calculation circuit 908 performs expansion coefficient increase / decrease operations corresponding to the expansion coefficient control signals in a plurality of areas, and calculates the expansion coefficients from 609 to 611.

  The operation of the configuration according to FIG. 9 will be described. Using the number of disappearing edges 903 counted for each interpolation section by the disappearing edge counting counter 901, the interpolation section coefficient adjustment controller 902 determines the operation direction of the expansion coefficient of each interpolation section, and uses this to use the expansion coefficient arithmetic circuit. In 904, the expansion coefficient is increased / decreased to calculate each expansion coefficient from 609 to 611, and the display data is expanded by the expansion circuit 603 using the expansion coefficient to obtain display data 218 after expansion. The interpolation section coefficient adjustment controller 902 determines the operation of the expansion coefficient so as to average the number of collapses in each interpolation section, thereby realizing a display in which the gradation collapse is more inconspicuous by distributing the gradation collapse for each interpolation section. Make it possible. In the third embodiment, the Dth adjustment controller 607 adjusts Dth as in the second embodiment, and the input data used for this is display data 213. As an adjustment method based thereon, the method described in the first embodiment and the method described in Patent Document 1 can be employed.

  FIG. 10 illustrates details of the interpolation interval coefficient adjustment controller 903 of FIG. In FIG. 9, 1001 is a 4-input adder, 1002 is a 1/4 calculator that calculates 1/4 using bit shift, 1003 is an interpolation section operation determination circuit, 1004 is an expansion coefficient adjustment pitch register, and 1005 is expansion. It is a coefficient adjustment range register. Here, the interpolation section is assumed to be four areas. The total number of extinction edges 903 in each region is summed by the adder 1001, and the total number of extinction edges 1006 in the four regions is calculated by making the quarter calculator 1002 1/4. This is compared with the number of extinguished edges in each region, and the size of each average value is determined. This result is input to the interpolation section operation determination circuit 1003. In this interpolation section operation determination circuit 1003, since a region having a relatively large number of edges is known, the expansion coefficient is manipulated so as to reduce the number of edges in this region. By performing this operation, there is a possibility that the edge increases in a region where the number of edges is relatively small. Therefore, it is possible to converge to an optimum value by repeating small unit changes over a plurality of frames. By adjusting the change unit in one frame by the expansion coefficient adjustment speed register 1004, the convergence time and stability can be adjusted. In addition, by providing the expansion coefficient adjustment range register 1005, it is possible to prevent excessive gradient assignment, compensate for the minimum gradient in the interpolation interval, and completely eliminate gradation even in a very small number of gradation collapse intervals. It becomes possible to do. These registers 1004 and 1005 are arranged in the control register 103 in FIG. 1 and can be set and changed from the host processor 113.

  FIG. 17 shows a specific operation of averaging the number of edge disappearances in the interpolation section by the interpolation section count adjustment controller 901 described in FIG. In FIG. 17, number (1) to number (4) of 1701 are the number of disappearing edges of 903. A broken line 1702 is the average number of annihilation edges num_avg of four areas 1006. By comparing the number of annihilation edges with the average number of annihilation edges, the parameters of ofy (1) to ofy (4) that determine the slope of each interval are manipulated, whereby the disappearance of each interpolation interval is determined. The number of edges (1701) is brought close to the average number of extinguished edges (1702). Specifically, when the number of annihilation edges number (n) (1701) is smaller than the average number of annihilation edges num_avg (1702), Δofsy is subtracted from the expression shown in 1703, and when larger, Δofsy is added according to the expression shown in 1704. Perform the operation. The slope dy (n) of each interpolation section is obtained from the equation 1601 in FIG. According to the above addition and subtraction and 1601 expression, an operation is performed so that a larger slope dy (n) is given to a section where num (n) is larger than num_avg, and a smaller slope dy (n) is given to a smaller section. As a result, it is possible to perform a desired operation of bringing the number of extinction edges (1701) of each interpolation section close to the average number of extinction edges (1702).

<< Embodiment 4 >>
FIG. 11 shows the configuration of the fourth embodiment of the present invention. The fourth embodiment is an example in which both methods of the second embodiment and the third embodiment are combined. Circuit blocks having the same functions as those of the other embodiments are denoted by the same reference numerals, and detailed description thereof is omitted. The extinction edge counting counter 901 has a counter for each region, and uses this count result to determine the expansion coefficient in each interpolation section by the interpolation section coefficient adjustment controller 902, and at the same time by the interpolation section coefficient adjustment controller 902. The total sum of the annihilation edge counters thus obtained is supplied to the interpolation interval adjustment controller 606. The interpolation interval adjustment controller 606 uses the total value of the disappearance edge counter 901 to adjust the interpolation interval. Since the interpolation interval coefficient adjustment controller 902 uses a counter value for each interval, and the interpolation interval adjustment controller 606 uses the total value of the counters, there is no mutual interference and it can operate independently. As a result, it is possible to adjust the interpolation interval width and the expansion coefficient of each interpolation interval by counting the number of disappearing edges, and obtain a display with optimized gradation collapse. As in the second embodiment, the fourth embodiment also adjusts the Dth by the Dth adjustment controller 607, and the input data used for this is the display data 213. The adjustment method is shown in the first embodiment. Other methods described in Patent Document 1 may be adopted.

<< Embodiment 5 >>
FIG. 12 illustrates a fifth embodiment according to the present invention. In the fifth embodiment, the determination for Dth adjustment is simplified compared to the first embodiment, and the same effect is obtained by counting only the number of disappearing edges in the horizontal direction. Since the determination in the vertical direction is not performed, the line memory 201 that is considered to have a large circuit scale can be omitted. The processing after the extinction edge counter 206 is the same as that in the first embodiment.

<< Embodiment 6 >>
FIG. 13 illustrates a sixth embodiment according to the present invention. In the sixth embodiment, the control for adjusting the interpolation interval is simplified compared to the second embodiment, and the same effect is obtained by counting only the number of disappearing edges in the horizontal direction as in the fifth embodiment. Get. Since determination in the vertical direction is not performed, the line memory 201 and the comparison value calculation circuit 604, which are considered to have a large circuit scale, can be omitted. The processing after the disappearing edge counting counter 206 is the same as that in the second embodiment.

<< Embodiment 7 >>
FIG. 14 shows a seventh embodiment according to the present invention. In the seventh embodiment, the control for adjusting the interpolation interval is simplified compared to the third embodiment, and the same effect is obtained by counting only the number of disappearing edges in the horizontal direction as in the fifth embodiment. Get. Since determination in the vertical direction is not performed, the line memory 201 and the comparison value calculation circuit 604, which are considered to have a large circuit scale, can be omitted. The processing after the extinction edge counter 901 is the same as that in the third embodiment.

<< Embodiment 8 >>
FIG. 15 shows an eighth embodiment according to the present invention. In the eighth embodiment, the control for adjusting the interpolation interval is simplified compared to the fourth embodiment, and the same effect is obtained by counting only the number of disappearing edges in the horizontal direction as in the fifth embodiment. Get. Since determination in the vertical direction is not performed, the line memory 201 and the comparison value calculation circuit 604, which are considered to have a large circuit scale, can be omitted. The processing after the extinction edge counter 901 is the same as that in the fourth embodiment.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, in the present invention, the display data does not mean only RGB data, but when luminance information is obtained by combining or decoding RGB components and used for display driving, the luminance information is targeted for expansion. When the luminance information is not acquired, the value of each component may be multiplied by RGB and expanded by RGB.

  The present invention can implement a method for controlling the backlight and saving power, and can be used not only for liquid crystal displays for mobile phones, but also for other portable terminal devices, small media players such as DVDs using liquid crystal displays, etc. It is also applicable to.

FIG. 1 is a system block diagram of a display system having a liquid crystal driver having a backlight power saving function for determining an expansion coefficient based on the number of edge disappearances. FIG. 2 is a block diagram showing an example of a backlight control unit provided in the liquid crystal driver of FIG. FIG. 3 is a block diagram showing details of the Dth adjustment controller according to the first embodiment of the backlight power saving function for determining the expansion coefficient based on the number of edge disappearances. FIG. 4A is an explanatory diagram showing the presence or absence of local contrast (edge) in adjacent pixels. FIG. 4B is an explanatory diagram illustrating conditions under which actual gradation collapse occurs. FIG. 5 is an explanatory diagram of an interpolation section in the second embodiment regarding the backlight power saving function for determining the expansion coefficient based on the number of edge disappearances. FIG. 6 is a block diagram illustrating an example of a backlight control unit according to the second embodiment. FIG. 7 is a block diagram illustrating an example of the interpolation interval adjustment controller according to the second embodiment. FIG. 8 is an explanatory diagram showing the effect of interpolation interval adjustment in the second embodiment. FIG. 9 is a block diagram illustrating an example of a backlight control unit according to the third embodiment relating to the backlight power saving function that determines the expansion coefficient based on the number of edge disappearances. FIG. 10 is a block diagram illustrating an example of the interpolation interval coefficient adjustment controller according to the third embodiment. FIG. 11 is a block diagram illustrating an example of a backlight control unit according to the fourth embodiment related to the backlight power saving function that determines the expansion coefficient based on the number of edge disappearances. FIG. 12 is a block diagram illustrating an example of a backlight control unit according to the fifth embodiment relating to the backlight power saving function that determines the expansion coefficient based on the number of edge disappearances. FIG. 13 is a block diagram illustrating an example of a backlight control unit according to the sixth embodiment related to the backlight power saving function that determines the expansion coefficient based on the number of edge disappearances. FIG. 14 is a block diagram illustrating an example of a backlight control unit according to the seventh embodiment relating to the backlight power saving function for determining the expansion coefficient based on the number of edge disappearances. FIG. 15 is a block diagram illustrating an example of a backlight control unit according to the eighth embodiment relating to the backlight power saving function for determining the expansion coefficient based on the number of edge disappearances. FIG. 16 is an explanatory diagram showing details of an example of interpolation section control in the second embodiment. FIG. 17 is an explanatory diagram showing details of an example of interpolation interval coefficient adjustment control in the third embodiment.

Explanation of symbols

101 LCD Driver 102 System Interface 103 Control Register 104 Backlight Control Unit 105 Graphic RAM
106 timing generation circuit 107 grayscale voltage generation circuit 108 source line drive circuit 109 liquid crystal drive level generation circuit 110 liquid crystal source signal 111 liquid crystal gate signal, common signal 112 backlight power supply line 113 control processor 114 liquid crystal panel 115 backlight module 116 backlight Power circuit 201 Line memory 202C, 202P Comparator 203, 203A, 203B Data latch 204V, 204H Comparator 205V, 205H AND circuit 206 Disappearing edge coefficient counter 207 Threshold gradation (Dth) adjustment controller 208 Disappearing edge allowable number register 209 Disappearing edge Allowable number gap register 210 Expansion coefficient arithmetic circuit 211 Expansion circuit 212 Backlight dimming coefficient arithmetic circuit 213 Display data 214 Threshold gradation value (Dth)
215 Horizontal disappearance edge signal 216 Vertical disappearance edge signal 217 Number of disappearance edges 218 Display data after expansion 219 Backlight dimming coefficient 301 Adder 302A, 302B Size comparator 303 Dth operation table 304 Dth operation table input section 305 Dth operation Table output unit 401 Appearance of pixels when input 402 Appearance of pixels as decompressed gradation 403 Graph of input gradation and decompressed gradation 404 Expansion curve 501 Expansion curve without interpolation processing 502 Interpolation section 503 An example of an expansion curve provided with an interpolation section 601 Interpolation section area determination circuit 602A, 602B, 602C, 602D Comparator 603 Interpolation expansion circuit 604 Selector 605 Vertical comparison value calculation circuit 606 Interpolation section adjustment controller 607 Dth adjustment controller The interpolation section coefficient as expansion factor 609 interpolation intervals origin coefficient of the roller 608 expansion coefficient calculating circuit dy non interpolation interval (px (*))
610 Expansion coefficient in interpolation interval (dy (*))
611 Interpolation section offset (ofsy (*)) as a gradation offset coefficient
612 Interpolation section width value 701 Interpolation section operation table 702 Interpolation section operation table input section 703 Interpolation section operation table output section 901 Vanishing edge count counter 902 Interpolation section coefficient adjustment controller 903 Number of vanishing edges for each area 904 Expansion of each area Coefficient control signal 905 Expansion coefficient arithmetic circuit 1001 4-input adder 1002 1/4 calculator 1003 Interpolation section operation determination circuit 1004 Expansion coefficient adjustment speed register 1005 Expansion coefficient adjustment range register 1601 Interpolation section inclination dy (n) calculation formula 1602 Interpolation section Formula for calculating output value out 1603 Interpolation interval range 1604 Non-interpolation interval range 1701 Number of interpolation interval elimination edges ofy (n)
1702 Average number of annihilation edges in 4 regions num_avg
1703 Number of extinction edges ofsy (n) correction formula 1
1704 Fading edge number ofsy (n) correction formula 2

Claims (14)

A display driving device that drives a display device in which the luminance of a pixel is controlled by the transmittance of light from a backlight module according to display data,
A backlight control unit for performing expansion control of the display data and dimming control of the backlight module;
The backlight control unit
An expansion coefficient arithmetic circuit that generates an expansion coefficient having a relationship obtained by dividing the maximum gradation value of display data by a gradation threshold value that is a smaller gradation value;
An expansion circuit that expands display data based on the expansion coefficient;
A dimming coefficient calculation circuit for determining a dimming rate of the backlight module based on the reciprocal of the expansion coefficient;
A measurement circuit that measures the frequency of occurrence of a state where the gradation is equal between adjacent pixels and exceeds both of the gradation threshold values for each predetermined amount of display data;
And a gradation threshold control circuit that changes the gradation threshold in a direction in which a measurement result obtained by the measurement circuit falls within a predetermined allowable range.   The measurement circuit measures the frequency of occurrence of a state in which gradation is equal between both adjacent pixels in the horizontal direction and between adjacent pixels in the vertical direction and exceeds the gradation threshold value between the adjacent pixels. The display driving apparatus according to 1.   The display driving apparatus according to claim 1, wherein the predetermined data amount is an image data amount of one frame.   The gradation threshold control circuit decreases the gradation threshold when the measured value is equal to or lower than the lower limit value of the allowable range, and increases the gradation threshold when the measured value is equal to or higher than the upper limit value of the allowable range. Display drive device. A register in which the value of the allowable range is set to be rewritable from the outside of the display driving device;
The display driving device according to claim 4, wherein the gradation threshold control circuit refers to a set value of the register. A display driving device that drives a display device in which the luminance of a pixel is controlled by the transmittance of light from a backlight module according to display data,
A backlight control unit for performing expansion control of the display data and dimming control of the backlight module;
The backlight control unit
A dimming coefficient calculation circuit that determines a dimming rate of the backlight module based on a value obtained by dividing a grayscale threshold value that is smaller than the maximum grayscale value of display data by the maximum grayscale value;
Generates an expansion coefficient having a relationship in which the maximum gradation value of display data is divided by the gradation threshold value in a non-interpolation interval having a gradation value smaller than the gradation threshold value, and interpolates based on the interpolation interval width value in the interpolation interval An expansion coefficient arithmetic circuit that generates an interpolation section base coefficient that is a base point of the section, an expansion coefficient for interpolation section, and a gradation offset coefficient that is a gradation of the interpolation section base point;
A decompression circuit that decompresses display data based on the decompression coefficient in a non-interpolation section, and decompresses display data based on an interpolation section decompression coefficient in the interpolation section;
A gradation threshold control circuit for adjusting the gradation threshold;
A first measurement circuit that measures the frequency of occurrence of a state in which gradations are equal between adjacent pixels of the expanded display data in the interpolation section for each predetermined amount of display data;
A display driving device comprising: an interpolation section control circuit that changes the interpolation section width value in a direction in which a measurement result obtained by the first measurement circuit falls within a predetermined allowable range, and supplies the result to the expansion coefficient calculation circuit.   The display driving apparatus according to claim 6, wherein the predetermined data amount is an image data amount of one frame.   The frequency at which the first measurement circuit generates a state where the expanded gradation is the same for both the adjacent pixels in the horizontal direction and the adjacent pixels in the vertical direction between adjacent pixels of the expanded display data in the interpolation section. The display driving device according to claim 6, wherein   The interpolation interval control circuit changes the interpolation interval value so as to expand the interpolation interval when the measurement value by the first measurement circuit is less than or equal to the lower limit value of the allowable range, and the measurement value by the first measurement circuit is The display driving device according to claim 8, wherein the interpolation section value is changed so as to reduce the interpolation section when the upper limit value of the allowable range is exceeded. A register in which the value of the allowable range is set to be rewritable from the outside of the display driving device;
The display driving device according to claim 9, wherein the interpolation section control circuit refers to a set value of the register. A second measurement circuit that measures the frequency of occurrence of a state in which the gradation is equal between adjacent pixels and both exceed the gradation threshold for each predetermined amount of display data;
The display drive device according to claim 6, wherein the gradation threshold control circuit changes the gradation threshold in a direction in which a measurement result obtained by the second measurement circuit falls within a predetermined allowable range.   The second measurement circuit measures the frequency of occurrence of a state in which the gradation is the same for both the adjacent pixels in the horizontal direction and between the adjacent pixels in the vertical direction as the adjacent pixels, and both exceed the gradation threshold value. The display driving apparatus according to claim 11.   The gradation threshold control circuit decreases the gradation threshold when the measurement value by the second measurement circuit is equal to or lower than the lower limit value of the allowable range, and increases the gradation threshold when the measurement value is equal to or higher than the upper limit value of the allowable range. The display driving device according to claim 12. A register in which the value of the allowable range is set to be rewritable from the outside of the display driving device;
The display driving device according to claim 13, wherein the gradation threshold control circuit refers to a set value of the register.

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