JP5231152B2 - Base unit equipped with transmission input circuit and its control circuit - Google Patents

Description

The present invention relates to a master unit, such as a receiver with a transmission input circuit and its control circuit for detecting a transmission current from the slave device, such as a fire detector which is connected via a transmission line serving also as a power supply line .

  Conventionally, in a monitoring system that monitors fire, gas leakage, and other abnormalities by connecting a sensor such as a fire detector or gas detector to the transmission line from the receiver, control information, etc. can be sent from the receiver in voltage mode. A digital signal as a downstream signal is transmitted to the terminal, and the terminal transmits a digital signal as an upstream signal such as sensor information to the receiver in the current mode.

  FIG. 15 shows a conventional monitoring system. Transmission lines 102a and 102b that also serve as power supply lines are drawn out from a receiver 100 as a master unit, and an analog sensor 104 and a repeater 106 are connected as slave units. doing. A unique address is set for the analog sensor 104 and the repeater 106.

  The analog sensor 104 detects an analog value of smoke density or temperature due to a fire, transmits smoke density data or temperature data to the receiver 100, judges a fire, and issues a fire alarm.

  Sensor lines 108a and 108b are drawn from the repeater 106, and an on / off sensor 110 having no transmission function is connected as a load. When the on / off sensor 110 detects a fire, the sensor lines 108a and 108b are connected to the sensor lines 108a and 108b. An alarm current is supplied, the alarm current is received by the repeater 106, fire alarm data is transmitted to the receiver 100, and a fire alarm is issued.

  In addition, the receiver 100 sequentially designates the slave unit address and sends a polling downlink signal in the voltage mode. When the slave unit determines the self address for this polling, it sends a transmission current as an uplink signal indicating normality. ing.

  FIG. 16 shows an equivalent circuit of the receiver 100, the analog sensor 104, and the repeater 106 in the conventional system of FIG. The repeater 106 supplies a power to an on / off type sensor connected as a load to flow a steady operating current. Therefore, the repeater 106 can be regarded as a load 122 indicated by a resistor. For this reason, the load current Iz due to the load 122 constantly flows through the transmission lines 102a and 102b.

  The analog type sensor 104 has a constant current source 112 and a switch 114, and for example, in response to polling from the receiver 100, the CPU 116 transmits an upstream signal indicating normality by a current pulse signal having a predetermined bit length.

  The current pulse signal transmitted from the analog sensor 104 is input to the transmission input circuit 118 of the receiver 100, and a current detection voltage pulse proportional to the current pulse is generated and read into the CPU 120 to recognize that it is normal. That is, the transmission input circuit 118 detects the presence / absence of a transmission current from the slave unit in a state where the load is carrying a load current through the transmission line that also serves as the power supply line.

  FIG. 17 is a circuit diagram of a conventional transmission input circuit provided in the receiver of FIG. In FIG. 17, the transmission input circuit 118 applies a predetermined power supply voltage Vcc to the transmission line 102a, and connects the signal line 102b side to the current detection resistor R11 via the diode D11.

  As shown in FIG. 15, the repeater 106 and the analog type sensor 104 are connected to the transmission lines 102 a and 102 b, and a load current Iz depending on the load 122 of the repeater 106 flows at an idle timing without a transmission current, When the analog sensor 104 outputs a transmission signal, the transmission current Ia flows on top of the load current Iz.

  A detection voltage corresponding to the line current generated at both ends of the current detection resistor R11 is applied to the negative input terminal of the comparator 122. A capacitor C11 is connected to the positive input terminal of the comparator 122, and the capacitor C11 is further connected to the input side of the diode D11 via the switch SW11.

Switch SW1 1 is switched by the transmission empty time from the handset, such as the analog type sensor 104 by CPU 120, plus the threshold voltage Vf serving as a forward drop voltage of the diode D11 to the load current detection voltage Vz of the current detection resistor R11 Reference voltage Vr, that is, Vr = (Va + Vf)
Is sampled and held in the capacitor C11 as the reference voltage Vr.

Figure 18 is a time chart showing signal waveforms of respective units of FIG. 17, FIG. 18 (A) is the input voltage of the comparator 1 2 2, and FIG. 18 (B) shows the sample timing of the capacitor C11 by the switch SW11 ing.

As shown in FIG. 18 (A), the transmission line 102a is in the absence of transmission current Ia, the load current detection voltage Vz is input by the load current Iz flowing through 102b, also the switching of the switches SW1 1 in free time without transmission current Ia Thus, the capacitor C11 samples and holds the reference voltage Vr obtained by adding the threshold voltage Vf, which is the forward drop voltage of the diode D11, to the load current detection voltage Vz of the current detection resistor R11.

  When the transmission current Ia flows due to transmission of the transmission signal from the slave unit, the transmission current detection voltage Va corresponding to the transmission current Ia is generated in the current detection resistor R11 in addition to the load current detection voltage Vz, and the comparator 122 generates the capacitor C11. The received voltage component (voltage pulse component) exceeding the reference voltage Vr = (Vz + Vf) held in is extracted and input to the CPU 120 as a transmission current detection signal to perform fire alarm processing and the like.

  FIG. 19 is a time chart in which the time axis is reduced with respect to FIG. 18, and a pulse signal is sent out from the slave unit by a transmission current at a constant cycle, and the load current detection voltage Vz is supplied to the load current detection voltage Vz at the idle timing. A reference voltage Vr = (Vz + Vf) to which a threshold voltage Vf that is a forward voltage drop is added is sampled and held in the capacitor C11, and a voltage component exceeding the reference voltage Vr of the transmission current detection voltage Va obtained immediately after that is detected and transmitted. The current detection signal is input to the CPU.

Although the load voltage Vz corresponding to the load current Iz is shown as a constant voltage, the load current actually changes gradually according to the environmental temperature and the like.

JP-A-9-91576 Japanese Patent Laid-Open No. 6-301876

  However, in such a conventional transmission input circuit, since the threshold voltage for detecting the transmission current from the slave unit is determined depending on the forward voltage Vf of the diode, an arbitrary threshold is set. In addition, there is a problem that fluctuation due to temperature is large and sufficient reliability cannot be ensured.

  In addition, the reference voltage Vr obtained by adding the threshold voltage Vf which is a forward drop voltage of the diode D11 as an analog voltage to the capacitor is held. However, the holding voltage of the capacitor changes with the passage of time due to leakage current or the like, and frequently There is a problem in that it must be sampled and held.

The present invention provides a transmission input circuit capable of arbitrarily setting a reference value for detecting a transmission current, accurately detecting whether or not there is a transmission current from a slave unit without fluctuation due to temperature or time, and a transmission input circuit thereof It is an object of the present invention to provide a parent device provided with a control circuit .

The present invention provides a base unit including a transmission input circuit for detecting the presence or absence of a transmission current from a slave unit and a control circuit thereof in a state where a load is carrying a load current through the transmission line also serving as a power supply line. And
The transmission input circuit is
A current detection resistor that inputs a line current from the transmission line and generates a line current detection voltage Vi;
A digital-to-analog converter that generates an arbitrary adjustment voltage Vb according to a digital value;
The line current detection voltage Vi generated in the current detection resistor is input to one of the input terminals, the adjustment voltage Vb generated by the digital-analog converter is input to the other input terminal, and the adjustment voltage Vb is obtained from the line current detection voltage Vi. An amplifier that outputs the subtracted corrected detection voltage Vc;
The correction detection voltage Vc output from the amplifier is input to one of the input terminals, the predetermined reference voltage Vr is input to the other input terminal, and the component of the correction detection voltage Vc exceeding the reference voltage Vr is used as a transmission current detection signal. A comparator to output,
With
The control circuit
A first adjustment processing unit that adjusts the adjustment voltage vb from the digital-analog converter so that the correction detection voltage Vc output from the amplifier coincides with the reference voltage Vr at a vacant timing of the transmission current from the slave unit;
The correction detection voltage Vc adjusted by the first adjustment processing unit is set to a correction detection voltage Vc that is reduced by a constant voltage (Va / 2) that is substantially half of the transmission current detection voltage Va corresponding to the transmission current Ia. A second adjustment processing unit for adjusting the adjustment voltage Vb from the digital-analog converter;
It is provided with.

  Here, the first adjustment processing unit adjusts the digital value for the digital-to-analog converter to a digital value in which the output of the comparator is inverted by a 1-bit change or a digital value immediately before the inversion, and sets the corrected detection voltage Vc to the reference voltage Vr. Match.

More specifically, the first adjustment processing unit
If the output of the adjustment at the start of the comparator is at the H level, a digital value or immediately before the inversion when the digital value in the inversed direction of H level to L level is changed to one-bit unit, inverted from H level to L level Fixed to the digital value of
When the output of the comparator at the start of adjustment is L level, the digital value is changed in 1-bit units in the direction of inverting L level to H level, and the digital value when inverting from L level to H level or immediately before inverting Fixed to a digital value.

In another embodiment of the present invention, a transmission input circuit for detecting the presence or absence of a transmission current from a slave unit and a control circuit for the transmission current in a state where a load is carrying a load current through the transmission line also serving as a power supply line, In the main unit equipped with
The transmission input circuit is
A current detecting resistor that generates a line current detection voltage Vi to input line current from the heat transmission line,
A digital-to-analog converter that generates an arbitrary adjustment voltage Vb according to a digital value;
The line current detection voltage Vi generated in the current detection resistor is input to one of the input terminals, the adjustment voltage Vb generated by the digital-analog converter is input to the other input terminal, and the adjustment voltage Vb is obtained from the line current detection voltage Vi. An amplifier that outputs the subtracted corrected detection voltage Vc;
A voltage dividing circuit that divides a predetermined reference voltage Vr by a series resistor and outputs a predetermined divided voltage Ve;
A switch that is inserted into the ground side of the voltage dividing circuit, forms a voltage dividing circuit when the switch is turned on to output the divided voltage Ve, and switches off the ground side of the voltage dividing circuit to output the reference voltage Vr as it is;
The correction detection voltage Vc output from the amplifier is input to one of the input terminals, and the reference voltage Vr from the voltage dividing circuit is input to the other input terminal, and the component of the correction detection voltage Vc exceeding the reference voltage Vr is transmitted current. A comparator that outputs as a detection signal;
With
The control circuit includes:
The correction detection voltage Vc output from the amplifier is matched with the divided voltage Ve in a state where the switch is turned on and the divided voltage Ve is output from the voltage dividing circuit at the idle timing of the transmission current Ia from the slave unit. A first adjustment processing unit for adjusting the adjustment voltage Vb from the digital-analog converter,
A second adjustment processing unit for turning off the switch and fixing the voltage dividing circuit to the output state of the reference voltage Vr after the adjustment by the first adjustment processing unit;
It is provided with.

Here, the voltage dividing circuit uses a reference voltage Vr output from the voltage dividing circuit when the switch is turned off as a reference voltage Vr output from the voltage dividing circuit when the switch is turned on, and a transmission current detection voltage corresponding to the transmission current Ia. about half to become a constant voltage of Va by (Va / 2) to configure so as to increase.

  The first adjustment processing unit adjusts the digital value for the digital-to-analog converter to a digital value in which the output of the comparator is inverted by a 1-bit change or a digital value immediately before the inversion, and matches the corrected detection voltage Vc with the divided voltage Ve. .

More specifically, the first adjustment processing unit
When the output of the comparator at the start of adjustment is at the H level, the digital value is changed in 1-bit units in the direction of inverting the H level to the L level, and the digital value when the H level is inverted to the L level or immediately before the inversion Fixed to digital values,
When the output of the comparator at the start of adjustment is L level, the digital value is changed in 1-bit units in the direction of inverting L level to H level, and the digital value when inverting from L level to H level or immediately before inverting Fixed to a digital value.

In another embodiment of the present invention, a digital variable resistor may be provided in place of the digital-analog converter.

  According to the present invention, the correction detection voltage output from the amplifier obtained by subtracting the adjustment voltage of the digital-to-analog converter from the load current detection voltage at the adjustment timing when there is no transmission current from the slave unit and only the load current flows. The adjustment voltage from the digital-analog converter is adjusted to match the reference voltage of the comparator (first adjustment process), and then the correction detection voltage is lowered by a constant voltage that is approximately half the transmission current detection voltage. Since the adjustment voltage from the digital-analog converter is adjusted (second adjustment process), if the transmission current detection voltage from the slave unit is included in the correction detection voltage regardless of the load current, the transmission current The reference voltage of the comparator is positioned at approximately half of the change in the corrected detection voltage corresponding to the detection voltage, and the transmission current sent from the slave unit is thereby reduced. It is possible to detect the probability.

In another embodiment of the present invention, a voltage dividing circuit for switching and inputting a divided voltage and a reference voltage by turning on and off the switch to the comparator is provided, and the adjustment voltage of the digital-analog converter from the load current detection voltage is provided. After adjusting the adjustment voltage of the digital-to-analog converter so that the corrected detection voltage output from the amplifier minus the voltage matches the divided voltage set in the comparator when the switch is turned on (first adjustment process), the switch is turned off ( The second adjustment process) switches to a reference voltage that is higher by a constant voltage that is approximately half of the transmission current detection voltage, and the adjustment process of the digital-analog converter can be performed only once. Can do.

  FIG. 1 is a block diagram showing a configuration of a receiver in a monitoring system to which the present invention is applied, together with an analog type sensor and a repeater. In FIG. 1, a monitoring system to which the present invention is applied includes an analog sensor 14 and a repeater 16 as slave units on transmission lines 12a and 12b led out from a receiver 10 as a master unit toward a warning area. Provided.

  The analog type sensor 14 and the repeater 16 have a transmission function using an uplink signal and a downlink signal with the receiver 10, and the analog type sensor 14 and the repeater 16 have, for example, 127 per transmission line. A unique address having a maximum address is assigned in advance.

  The analog sensor 14 detects smoke concentration or temperature due to fire, transmits the detected value to the receiver 10 as analog data, and judges fire from analog data of smoke concentration or temperature received at the receiver 10 side. I am trying to alarm.

  On the other hand, the repeater 16 is provided to connect the on / off type sensor 20 having no transmission function to the transmission lines 12a and 12b. The repeater 16 has a transmission function with the receiver 10, and an on / off type sensor 20 is connected to the sensor lines 18 a and 18 b drawn from the repeater 16. When the on-off sensor 20 detects a fire, it sends an alarm current between the sensor lines 18 a and 18 b, receives the alarm current by the repeater 16, and transmits the alarm alarm data to the receiver 10.

  Here, the downstream signals from the receiver 10 to the analog type sensor 14 and the repeater 16 as slave units are transmitted in the voltage mode. For example, the receiver 10 transmits a polling signal by sequentially specifying the slave unit addresses at a constant polling cycle, and this polling signal is a voltage that changes the voltage of the transmission lines 12a and 12b between 18 volts and 30 volts, for example. Transmitted as pulses.

  On the other hand, upstream signals from the analog type sensor 14 and the repeater 16 are transmitted in the current mode. That is, in the current mode, a signal current is caused to flow between the transmission lines 12a and 12b at the timing of bit 1 of the transmission data, and the upstream signal is transmitted to the receiver 10 as a so-called current pulse train. At this time, the transmission current flows.

  Further, the transmission lines 12a and 12b are used as power supply lines for the analog type sensor 14 and the repeater 16 as slave units. That is, the transmission lines 12a and 12b vary the voltage in the range of 18 to 30 volts even during transmission of the downlink signal in the voltage mode, and the voltage supply of 18 volts is provided at the minimum. As a result, power is continuously supplied to the slave unit.

  Also for the sensor lines 18a and 18b drawn from the repeater 16, power supply from the transmission lines 12a and 12b is simultaneously performed via the repeater 16, and the on / off type sensor 20 is powered. Supply.

  The receiver 10 is provided with a CPU 22, a transmission circuit unit 24 is provided for the CPU 22, and transmission lines 12 a and 12 b are drawn from the transmission circuit unit 24.

The transmission output circuit 26 and the heat transmission input circuit 28 is provided in the transmission circuit unit 24. The transmission output circuit 26 outputs a downstream signal to the transmission lines 12a and 12b in the voltage mode based on a command instruction such as polling from the CPU 22, for example.

Den transmission input circuit 28, an uplink signal by the current mode from the analog type sensor 14 or the relay device 16 serving as slave unit, i.e. receives the transmission current, and outputs a transmission current detection signal to the CPU 22, perform a fire alarm operation Make it.

  For the CPU 22, a display unit 30, an operation unit 32, a storage unit 34, and a transfer unit 36 are provided, and various alarm outputs, alarm display, operation, storage of monitoring information, and transfer signal necessary for fire monitoring are provided. Output is possible.

  The analog sensor 14 is provided with a CPU 38, a sensor unit 40 and a transmission circuit unit 42. The sensor unit 40 detects smoke concentration or temperature due to fire and outputs it to the CPU 38.

  The transmission circuit unit 42 receives the downlink signal of the polling command designating its own address from the receiver 10 and, if normal to the CPU 38, transmits a response uplink signal indicating normality to the receiver 10 in the current mode. When detecting a fire, the CPU 38 transmits a fire alarm signal to the receiver 10 as an upstream signal of a fire interrupt as a response to a polling command specifying its own address.

  The repeater 16 is provided with a CPU 44, a notification receiving unit 46 and a transmission circuit unit 48. Sensor lines 18a and 18b are drawn out from the notification receiving unit 46, and the on / off type sensor 20 is connected thereto as a load.

  When the on-off sensor 20 detects a fire, an alarm current is passed between the sensor lines 18a and 18b. The alarm current is received by the alarm receiver 46 and output to the CPU 44. The CPU 44 transmits the transmission circuit 48. Thus, the fire interrupt upstream signal is transmitted to the receiver 10 as a response to the polling command designating the self address.

  Similarly to the analog sensor 14, the repeater 16 receives a polling command downlink signal designating a self-address from the receiver 10. If there is no abnormality, the repeater 16 sends a normal uplink signal in the current mode. Transmit to.

  Further, the transmission process between the receiver 10 and the slave unit will be described in detail as follows. During normal monitoring, the receiver 10 transmits a normal monitoring polling command in which the slave unit addresses are sequentially specified, and the analog sensor 14 and the repeater 16 are polled to match their own set addresses. When a command is received, a normal monitoring response is made. Therefore, the receiver 10 can detect a failure of the analog type sensor 14 or the repeater 16 that is a slave unit that has not responded to the polling command.

  When the analog sensor 14 receives a batch AD conversion command that is repeatedly output at every polling command transmission period for all sensor addresses of the receiver 10, the smoke concentration and temperature in the built-in fire detection mechanism are detected. Analog detection data is sampled, compared with a predetermined fire level, and a fire is detected when the fire level is exceeded.

  When the analog type sensor 14 determines a fire from the sampling result based on the batch AD conversion command, an interrupt signal is transmitted to the receiver 10 at the timing of the subsequent polling command designating its own sensor address. . The interrupt signal is a signal which is not normally used so that the response bit is all 1.

  The repeater 16 also samples the reception state by the notification receiving unit 46 based on the batch AD conversion command from the receiver 10, and when the notification reception is detected, the timing of the subsequent polling command designating its own sensor address Then, an interrupt signal is transmitted to the receiver 10.

  When the receiver 10 receives the interrupt signal from the analog type sensor 14 or the repeater 16, it issues a group search command, and the interrupt response from the group including the analog type sensor 14 or the repeater 16 that has detected the fire. Is received, and the group is discriminated, and then polling is performed for each analog type sensor or repeater included in the discriminated group by sequentially specifying the address, and fire response (analog data or fire alarm data) As a result, the sensor address of the analog type sensor 14 or the repeater 16 that detects the fire is recognized, and a fire alarm operation is performed.

  For the maximum 127 analog type sensors 14 and repeaters 16 connected to the transmission lines 12a and 12b, for example, group addresses are set for every 8 units, and a fire is detected in response to a group search command from the receiver 10. An interrupt response is made from the group including the detecting sensor so that the group including the analog type sensor 14 or the repeater 16 detecting the fire can be specified.

FIG. 2 is a circuit diagram showing a first embodiment of a transmission input circuit according to the present invention and a CPU functioning as its control circuit . 2, the transmission input circuit 28 provided in the receiver 10 includes a current detection resistor R0, an operational amplifier 48, a DA converter (digital / analog converter) 50, a comparator 52, a reference voltage source 54, and an input resistor R1 of the operational amplifier 48. The feedback resistor R2 and the pull-up resistor R3 output from the comparator 52 are included.

  A predetermined power supply voltage Vcc is applied to the transmission line 12a drawn from the receiver 10, and an analog sensor 14 as a slave unit or the like is connected between the transmission lines 12a and 12b as shown in FIG. The repeater 16 is connected, and the load current Iz accompanying the consumption current of the on / off type sensor 20 connected mainly to the sensor lines 18a and 18b provided in the repeater 16 flows from the transmission line 12b. A transmission current Ia accompanying a normal response from the analog sensor 14 and the repeater 16 due to polling from the machine 10 flows at a constant period.

  The current detection resistor R0 generates a line current detection voltage Vi corresponding to the current flowing from the transmission line 12b. When the slave unit does not output the transmission current Ia, the load current Iz basically flows in. Therefore, the current detection resistor R0 generates the load current detection voltage Vz corresponding to the load current Iz.

In this state, the transmission current Ia from the slave unit is added to the load current Iz, and at this time, the line current detection voltage Vi obtained by adding the transmission current detection voltage Va to the load current detection voltage Vz, that is, the current detection resistor R0, that is, Vi = Vz + Va
Will occur.

The operational amplifier 48 inputs the line current detection voltage Vi generated in the current detection resistor R0 to the positive input terminal, and inputs the adjustment voltage Vb from the DA converter 50 to the negative input terminal. The operational amplifier 48 operates as a buffer amplifier whose amplification factor is set to 1, for example, by the input resistor R1 and the feedback resistor R2, and the correction detection voltage Vc obtained by subtracting the adjustment voltage Vb from the line current detection voltage Vi, that is, Vc = Vi−Vb.
Is output.

  The correction detection voltage Vc output from the operational amplifier 48 is input to the negative input terminal of the comparator 52 and compared with the reference voltage Vr from the reference voltage source 54 input to the positive input terminal. That is, if the corrected detection voltage Vc is less than the reference voltage Vr, the comparator 52 generates an H level output. When the corrected detection voltage Vc becomes equal to or higher than the reference voltage Vr, the comparator 52 is inverted to an L level output.

  The CPU 22 is provided with a first adjustment processing unit 56 and a second adjustment processing unit 58 as functions realized by executing the program. The first adjustment processing unit 56 and the second adjustment processing unit 58 execute the adjustment process at the idle timing when the transmission current Ia from the slave unit does not flow, that is, the timing when only the load current Iz is input.

The first adjustment processing unit 56 subtracts the adjustment voltage Vb from the DA converter 50 from the load current detection voltage Vz because it is only the line current detection voltage Vi output from the operational amplifier 48, that is, the load current Iz in this case. Correction detection voltage Vc, that is, Vc = Vz−Vb
Is adjusted to the reference voltage Vr from the reference voltage source 54 set in the comparator 52, the adjustment voltage Vb from the DA converter 50 is adjusted.

  Specifically, the first adjustment processing unit 56 changes the digital value for the DA converter 50 bit by bit, and adjusts it to the digital value when the output of the comparator 52 is inverted or the digital value immediately before the inversion. The corrected detection voltage Vc (= Vz−Vb) is matched with the reference voltage Vr.

  More specifically, for example, if the adjustment voltage Vb output from the DA converter 50 at the start of adjustment is at an initial value of 0 volts, the corrected detection voltage Vc output from the operational amplifier 48 at this time is the load current detection voltage Vz. The same is larger than the reference voltage Vr, and the output of the comparator 52 is L level.

  Since the adjustment voltage Vb from the DA converter 50 is small when the output of the comparator 52 is at the L level, the first adjustment processing unit 56 increases the digital value for the DA converter 50 in 1-bit units, and the output of the comparator 52 is at the L level. When the signal is inverted from H to H level, the digital value at the time of inversion or the digital value immediately before the inversion is fixed, and the correction detection voltage Vc output from the operational amplifier 48 matches the reference voltage Vr by the adjustment voltage Vb at this time. It becomes.

  On the other hand, when the correction detection voltage Vc is lower than the reference voltage Vr at the start of adjustment, the output of the comparator 52 is at the H level. In this case, the digital value of the DA converter 50 is decreased in units of 1 bit. Then, the adjustment voltage Vb is sequentially decreased and the correction detection voltage Vc is increased.

  When the output of the comparator 52 is inverted from the H level to the L level due to the increase in the correction detection voltage Vc accompanying the decrease in the 1-bit unit of the adjustment voltage Vb by the DA converter 50, the digital value or inversion to the DA converter 50 at this time It is possible to fix the correction detection voltage Vc to the reference voltage Vr by fixing the digital value immediately before.

  The second adjustment processing unit 58 operates when the adjustment by the first adjustment processing unit 56 is completed, and transmits the correction detection voltage Vc adjusted by the first adjustment processing unit 56 so as to match the reference voltage Vr. The adjustment voltage Vb from the DA converter 50 is adjusted so that the correction detection voltage Vc is reduced by a constant voltage (Va / 2) that is ½ of the transmission current detection voltage Va corresponding to the current Ia.

  As a result, the reference voltage Vr is set to a position that is approximately half of the increased line current detection voltage Va with respect to the increase of the transmission current detection voltage Va corresponding to the transmission current Ia from the input slave unit. Thus, the line current Ia can be reliably detected by the comparator 52.

  FIG. 3 is a time chart showing signal waveforms of respective parts in the first embodiment of FIG. That is, FIG. 3A shows the line current detection voltage Vi generated in the line current detection resistor R0, and the load current detection voltage corresponding to the load current Iz that basically flows at the idle timing without the transmission current Ia from the slave unit. Vz is generated. When the transmission current Ia from the slave unit flows in this state, the pulse voltage that is increased by the transmission current detection voltage Va is detected in a form added to the load current detection voltage Vz.

  FIG. 3B shows the adjustment voltage Vb output from the DA converter 50. FIG. 3C shows the corrected detection voltage Vc and the reference voltage Vr output from the operational amplifier 48 input to the comparator 52. Further, FIG. 3D shows the output of the comparator 52.

  In FIG. 3, the adjustment processing by the first adjustment processing unit 56 and the second adjustment processing unit 58 provided in the CPU 22 of FIG. 2 will be described as follows.

  First, the first adjustment processing unit 56 starts the adjustment process at time t1, which is a vacant timing when the transmission current Ia does not flow through the transmission line 12b, and makes the correction detection voltage Vc output from the operational amplifier 48 coincide with the reference voltage Vr. Thus, the adjustment voltage Vb from the DA converter 50 is adjusted.

  It is assumed that the adjustment voltage Vb from the DA converter 50 is at the initial value of 0 volts at the start of adjustment. Further, it is assumed that the load current detection voltage Vz at this time is higher than the reference voltage Vr.

  At the start of adjustment at time t1, since the adjustment voltage Vb = 0 volts, the correction detection voltage Vc output from the operational amplifier 48 is Vc = Vz, which is higher than the reference voltage Vr. The output is L level. Therefore, the first adjustment processing unit 56 sets a digital value to be increased in 1-bit units for the DA converter 50 in order to lower the correction detection voltage Vc, and accordingly, the adjustment voltage Vb for the operational amplifier 48 is set in 1-bit units. The adjustment voltage Vb that is increased and output is sequentially increased.

  When the adjustment voltage Vb increases, the correction detection voltage Vc obtained by subtracting the adjustment voltage Vb from the load current detection voltage Vz at that time is output from the operational amplifier 48. Therefore, the correction detection voltage Vc is shown in FIG. Thus, it decreases toward the reference voltage Vr.

  At time t2, when the adjustment voltage Vb increases due to the 1-bit change in the DA converter 50 and conversely the correction detection voltage Vc decreases and falls below the reference voltage Vr, the output of the comparator 52 changes from the previous L level to the H level. Invert to level. Thus, the first adjustment processing unit 56 determines that the corrected detection voltage Vc matches the reference voltage Vr, and ends the adjustment process.

  Subsequently, at time t3 to t4, the second adjustment processing unit 58 adjusts the digital value for the DA converter 50, so that the correction detection voltage Vc for the comparator 52 is only a constant voltage (Va / 2) that is half the transmission current detection voltage Va. Perform adjustment processing to reduce.

  That is, the second adjustment processing unit 58 increases the digital value for the DA converter 50, and increases the adjustment voltage Vb by (Va / 2) half of the transmission current detection voltage Va as shown in FIG. Accordingly, as shown in FIG. 3C, the correction detection voltage Vc output from the operational amplifier 48 for the comparator 52 is decreased by (Va / 2).

  Next, it is assumed that the transmission current Ia corresponding to, for example, 10-bit data “1011010001” is output from the slave unit and the transmission current detection voltage Va is obtained from time t5 to t6 after the adjustment process is completed. The transmission current detection voltage Va flows on top of the load current Vz, so that the line current detection voltage Vi becomes Vi = (Vz + Va) and is reduced by a constant voltage (Va / 2) by subtraction of the adjustment voltage Vb in the operational amplifier 48. The corrected detection voltage Vc is input to the comparator 52.

  For this reason, as shown in FIG. 3C, the reference voltage Vr is located at the approximate center of the change of the line current detection voltage Va in the correction detection voltage Vc input to the comparator 52, thereby detecting the line current more accurately. The voltage Vi can be detected.

  That is, the comparator 52 generates an L level output if the corrected detection voltage Vc is equal to or higher than the reference voltage Vr, and generates an H level output if it is lower than the reference voltage Vr. Therefore, as shown in FIG. A transmission current detection signal obtained by inverting Va, for example, “0100101110” 10-bit data is input to the CPU 22.

  FIG. 4 is a time chart showing signal waveforms at various parts when the load current in the first embodiment of FIG. 2 is stable. 4A shows the line current detection voltage Vi, FIG. 4B shows the input of the comparator 52, FIG. 4C shows the adjustment timing, and FIG. 4D shows the output of the comparator 52.

  As shown in FIG. 4A, in this example, the load current detection voltage Vz corresponding to the load current Iz flowing from the transmission line 12b is constant, and the transmission current detection voltage Va based on the transmission current Ia is added to the load current detection voltage Va. It occurs periodically.

  When the load current Vz is constant as shown in FIG. 4A, for example, every other period with respect to the response period of the normal response digital current from the slave unit accompanying the polling from the receiver 10, for example. Adjustment processing is performed by setting the adjustment timing as described above.

  The initial adjustment timing in FIG. 4 is the same as that in FIG. 3, and thereafter, the adjustment timing is set every other cycle for the output of the periodic transmission current. By such adjustment, as shown in FIG. 4B, the reference voltage Vr is approximately half of the line current detection voltage Va included in the correction detection voltage Vc input to the comparator 52 from the operational amplifier 48. The transmission current detection voltage Va that is adjusted and reliably corresponds to the transmission current Ia from the slave unit can be detected by the comparator 52.

  Here, when the data transmission speed between the receiver 10 as the master unit and the analog sensor 14 or the repeater 16 as the slave unit is set to 19200 bps, the transmission cycle of the transmission current from the slave unit is 4.3 mm. In contrast to this, the time required for the adjustment process is as short as 0.2 to 0.3 milliseconds, but in FIG. 12, the adjustment time is increased to make the explanation easier to understand. Show.

  FIG. 5 is a time chart showing signal waveforms at various parts when the load current in the first embodiment of FIG. 2 varies. As shown in FIG. 5 (A), in this case, the load current detection voltage Vz fluctuates gradually with the lapse of time as the load current Iz flowing through the transmission line fluctuates. A transmission current detection voltage Va is generated by the transmission current Ia from the slave unit.

  When the load current Iz fluctuates in this way, the adjustment timing shown in FIG. 5C is adjusted for all of the idle time during the transmission current output cycle.

  Even if the load current detection voltage Vz fluctuates as shown in the input to the comparator 52 in FIG. 5B by setting the adjustment timing as described above, the correction detection voltage Vc from the operational amplifier 48 immediately after the adjustment is obtained by the adjustment process. Is always adjusted to a voltage that is lower by (Va / 2) than the reference voltage Vr. Thereafter, the load current detection voltage Vz varies until the next adjustment, but the transmission current detection voltage Va is also the reference voltage Vr during this period. On the other hand, it is located near the center of the change, and the transmission current can be reliably detected against the gradual fluctuation of the load current.

  FIG. 6 is a flowchart showing adjustment processing by the first adjustment processing unit 56 and the second adjustment processing unit 58 provided in the first embodiment of FIG. In FIG. 6, first, in step S1, it is determined whether or not the adjustment timing is such that only the load current Iz flows without flowing the transmission current. If the adjustment timing is determined, the process proceeds to step S2, and the output of the comparator 52 is L level. Check whether or not.

  When the output of the comparator is L level, the correction detection voltage Vc from the operational amplifier 48 is higher than the reference voltage Vr at this time. Therefore, in order to lower the correction detection voltage Vc, it is necessary to increase the adjustment voltage Vb for the operational amplifier 48. Therefore, the process proceeds to step S3, where the DA converter 50 is increased in units of 1 bit and the adjustment voltage Vb is increased.

  Subsequently, in step S4, it is checked whether or not the output of the comparator 52 is inverted. Until the output of the comparator 52 is inverted, the digital value for the DA converter 50 is sequentially increased in units of 1 bit by the processing in steps S2 and S3. The process of increasing the adjustment voltage Vb is repeated.

  If it is determined in step S4 that the output of the comparator is inverted from the L level to the H level, it is determined that the adjustment voltage Vb is adjusted so that the correction detection voltage Vc matches the reference voltage Vr at this time, and the process proceeds to step S6. As a process by the second adjustment processing unit 58, a process of increasing the output of the DA converter 50 by a constant voltage (Va / 2) that is half of the transmission voltage detection voltage Va is performed, and thereby the operational amplifier 48 that matches the reference voltage Vr. The correction detection voltage Vc is reduced by a constant voltage (Va / 2), and the series of adjustment processing is terminated.

  On the other hand, if the output of the comparator is at the H level in step S2, the correction detection voltage Vc output from the operational amplifier 48 at this time is smaller than the reference voltage Vr. Therefore, adjustment is performed to increase the correction detection voltage Vc. The voltage Vb needs to be lowered, and therefore, the process proceeds to step S5, where the digital value of the DA converter 50 is lowered in units of 1 bit, and the adjustment voltage Vb is sequentially reduced.

  Subsequently, in step S4, it is checked whether or not the output of the comparator is inverted from the H level to the L level, and the processes of steps S2 and S5 are repeated until the output is inverted to the L level. When the output inversion of the comparator is determined in step S4, it is determined that the correction detection voltage Vc from the operational amplifier 48 coincides with the reference voltage Vr at this time, and the adjustment voltage Vb from the DA converter 50 is determined as the constant voltage Va / in step S6. Adjustment is made to increase by 2, thereby reducing the correction detection voltage Vc from the operational amplifier 48 that matches the reference voltage Vr by a constant voltage (Va / 2), and a series of adjustment processing is completed.

FIG. 7 is a circuit diagram showing a second embodiment of a CPU functioning as a transmission input circuit and its control circuit according to the present invention. The second embodiment is characterized in that a digital variable resistor 60 is provided instead of the DA converter 50 provided in the first embodiment of FIG.

  The digital variable resistor 60 can adjust the adjustment voltage Vb by the output of a digital value from the CPU 22, specifically, an up count pulse or a down count pulse.

  FIG. 8 is a block diagram showing a circuit configuration of the digital variable resistor provided in the second embodiment of FIG. In FIG. 8, the digital variable resistor 60 includes a series resistor array 62, an up / down counter 66, a nonvolatile memory 68, a control circuit 70, and a decoder 72.

  The series resistor array 62 has a predetermined number of fixed resistors r having a predetermined resistance value connected in series, and a switch 64 using a MOS-FET or the like is connected to both ends of the series connection circuit and between the resistance connections. The ends are connected together.

  A power supply terminal 72 is taken out from one end of the series resistance circuit of the series resistor array 62, a ground terminal 74 is taken out from the other end, and a wiper terminal 76 is taken out from the common side connected via the switch 64. .

  The series resistor array 62 can switch the resistance value in 256 steps, for example, by turning on one of the switches 64 by the output of the decoder 72, and correspondingly, between the power supply terminal 72 and the ground terminal 74. The applied DC voltage can be output as a voltage at any of 256 selected stages.

  An up / down counter 66 is provided for the decoder 72, and the up / down counter 66 counts up or down between a minimum value and a maximum value by a count signal as a control signal for the control terminal 78. The binary data counted by the up / down counter 66 is converted into decimal data of, for example, 1 to 256 stages by the decoder 72. By turning on the switch 64 at a position corresponding to the decimal data from the decoder 72, the decoder 72 A voltage corresponding to the set value (number of stages) can be taken out from the wiper terminal 76.

  The control circuit 70 performs timing control for the up / down counter 66 and the decoder 72. A nonvolatile memory 68 is provided, and the nonvolatile memory 68 stores the value of the up / down counter 66.

  For this reason, even if the power of the digital variable resistor 60 is cut off, since the value of the up / down counter 66 at that time is held in the nonvolatile memory 68, the nonvolatile memory 68 is used as an initial value when the power is turned on next time. Is set in the up / down counter 66, so that the adjustment value at that time can be held even when the power is turned off. If the adjustment value does not need to be retained even when the power is turned off, the nonvolatile memory 68 need not be provided.

  FIG. 9 is a flowchart showing the adjustment process in the second embodiment of FIG. This adjustment process is basically the same as the adjustment process of the first embodiment shown in FIG. 6, but the DA converter 50 in the processes of steps S13 and S15 of FIG. 9 corresponding to steps S3 and S5 of FIG. Instead, the digital variable resistor 60 is up or down in 1-bit units.

  When the digital variable resistor 60 is used, the digital value corresponding to the voltage drop needs to be down-counted as a process of reducing the output of the digital variable resistor 60 by a constant voltage (Va / 2) in step S16. Therefore, the adjustment process takes more time than the process in which the DA converter 50 simply sets a digital value for a predetermined decrease at a time.

FIG. 10 is a circuit diagram showing a third embodiment of a CPU functioning as a transmission input circuit and its control circuit according to the present invention. In the third embodiment, the processing of the second adjustment processing unit 58 after the completion of the processing by the first adjustment processing unit 56 is not a change in the digital value of the DA converter, but a transmission current detection by a switch and a resistor network. The process on the software side is simplified by creating a constant voltage (Va / 2) change that is half of the voltage Va.

  10, the transmission input circuit 28 provided in the receiver 10 includes a current detection resistor R0, an operational amplifier 48, a DA converter 50, a comparator 52, a reference voltage source 54, and a pull-up resistor R3. 2 is basically the same as that of the first embodiment, but in the third embodiment, a voltage dividing circuit in which a switch 80 and resistors R4 and R5 are connected in series with respect to a positive input terminal on the reference voltage side of the comparator 52. A circuit 82 is provided.

  That is, the reference voltage Vr from the reference voltage source 54 is input to the positive input terminal of the comparator 52 from the voltage dividing point of the voltage dividing circuit 82 in which the resistors R4 and R5 are connected in series. In this case, a switch 80 such as a transistor or a MOS-FET is provided between the resistor R5 and the ground side.

  The switch 80 is turned on at the time of adjustment by the first adjustment processing unit 56, enables the voltage dividing circuit 82 by the series connection of the resistors R4 and R5, and a predetermined divided voltage obtained by dividing the reference voltage Vr by the resistors R4 and R5. The voltage Ve is set in the comparator 52.

  When the adjustment by the first adjustment processing unit 56 is completed, the second adjustment processing unit 58 switches off the switch 80 as shown in the figure, thereby disconnecting the voltage dividing circuit 82 from the ground side. The reference voltage Vr is set in the comparator 52 as it is.

Here, the reference voltage Vr of the voltage dividing circuit 82 is a voltage obtained by adding a constant voltage (Va / 2) that is half the transmission current detection voltage Va to the divided voltage Ve, that is, Vr = Ve + Va / 2.
The values of the resistors R4 and R5 are determined so that

  11 is a time chart showing signal waveforms of respective parts in the second embodiment of FIG. 10, FIG. 11A is the line current detection voltage Vi, and FIG. 11B is the adjustment voltage output from the DA converter 50. Vb, FIG. 11C shows the input to the comparator 52, and FIG. 11D shows the output of the comparator 52.

  First, only the load current Iz flows without the transmission current Ia flowing, and the first adjustment processing unit 56 and the second adjustment processing are performed at times t1 to t3 when the load current detection voltage Vz is basically generated. Adjustment processing by the unit 58 is performed.

  Here, at the start of the adjustment at time t1, the first adjustment processing unit 56 turns on the switch 80 to enable the voltage dividing circuit 82 and set the divided voltage Ve to the plus input terminal of the comparator 52.

  Thus, when the divided voltage Ve is set by the comparator 52, the correction detection voltage Vc from the operational amplifier 48 at this time is higher than the divided voltage Ve, and therefore the output of the comparator 52 is inverted to the L level.

  Subsequently, at time t2, the first adjustment processing unit 56 determines that the output of the comparator 52 is at the L level and the correction detection voltage Vc is higher than the divided voltage Ve. In order to decrease and match the divided voltage Ve, the digital value is increased in 1-bit units so that the adjustment voltage Vb from the DA converter 50 is increased.

  As the adjustment voltage Vb from the DA converter 50 increases, when the correction detection voltage Vc decreases and falls below the divided voltage Ve at time t3, the output of the comparator 52 is inverted from the L level to the H level. The one adjustment processing unit 56 can determine that the correction detection voltage Vc matches the divided voltage Ve.

  Subsequently, at time t4, the second adjustment processing unit 58 switches the switch 80 to OFF. When the switch 80 is turned off, the ground side of the voltage dividing circuit 82 is disconnected and the voltage dividing function is lost, and the reference voltage Vr from the reference voltage source 54 is set to the positive input terminal of the comparator 52 as it is through the resistor R4. Is done. That is, when the switch 80 is turned off at time t4, the divided voltage Ve with respect to the positive input terminal of the comparator 52 increases to the reference voltage Vr.

Here, in the third embodiment, the voltage change from the divided voltage Ve to the reference voltage Vr, that is, (Vr−Ve) is half of the transmission current detection voltage Va of the line current Ia, that is, (Vr−Ve). = (Va / 2)
Thus, the reference voltage Vr and the values of the resistors R4 and R5 of the voltage dividing circuit 82 are determined.

  Therefore, when the switch 80 is turned off, the reference voltage Vr that is increased from the divided voltage Ve by a constant voltage (Va / 2) is set in the comparator 52 as shown in FIG.

  When the adjustment process from time t1 to t4 is completed in this way, the transmission current detection voltage Va based on the transmission current Ia from the slave unit is superimposed on the load current detection voltage Vz in a pulse manner as shown at times t5 to t6. The reference voltage Vr for the comparator 52 is positioned approximately in the center of the change of the line current detection voltage Vi in the correction detection voltage Vc. Thus, the line current can be accurately detected.

  FIG. 12 is a time chart showing signal waveforms at various parts when the load current in the third embodiment of FIG. 10 is stable. FIG. 12A shows the line current detection voltage Vi, and FIG. FIG. 12C shows the adjustment timing, and FIG. 12D shows the output of the comparator 52.

  As described above, when the load current detection voltage Vz corresponding to the load current Iz is stable, for example, the transmission current idle timing of the sequential response from the slave unit to the polling from the master unit is shown every other period. Adjustment timing is set as shown in FIG. As is apparent from the input of the comparator 52 in FIG. 12B, the reference voltage Vr is set to approximately half the position of the transmission current detection voltage Va by the adjustment process, and thereby the transmission current that flows in a form added to the load current Iz. Ia can be accurately detected.

  FIG. 13 is a time chart showing signal waveforms at various parts when the load current in the third embodiment of FIG. 10 varies. As shown by the line current detection voltage Vi in FIG. 13A, in this example, the load current detection voltage Vz that flows basically changes gradually with the fluctuation of the load current Iz, and is transmitted in the form of being added thereto. A transmission current detection voltage Va corresponding to the current Ia is generated.

  When the load current detection voltage Vz fluctuates in this way, as shown in FIG. 13C, all the empty timings of the transmission current Ia are set as adjustment timings. In the adjustment process at each adjustment timing, the switch 80 of FIG. 10 is turned on to set the divided voltage Ve to the comparator 52, and the DA converter 50 makes the correction detection voltage Vc from the operational amplifier 48 coincide with the divided voltage Ve. After the adjustment voltage Vb is adjusted, the coincidence is determined by inversion of the comparator 52, and then the switch 80 is turned off to switch the setting of the divided voltage Ve to the setting of the reference voltage Vr for the comparator 52.

  As described above, even if the load current detection voltage Vz fluctuates, the DA converter 50 adjusts the adjustment voltage Vb at each adjustment timing, and the correction detection voltage Vc is corrected so as to cancel the fluctuation amount of the load current detection voltage Vz. As a result, the reference voltage Vr is positioned almost half of the transmission current detection voltage Va generated in a form superimposed on the load current detection voltage Vz, and the transmission current Ia can be detected more accurately.

  FIG. 14 is a flowchart showing the adjustment process in the third embodiment of FIG. In FIG. 14, when it is determined in step S21 that the adjustment timing is such that only the load current flows without flowing the transmission current, the process proceeds to step S22, where the switch 80 is turned on and the divided voltage Ve is applied to the comparator 52. Set.

  Subsequently, in step S23, it is checked whether or not the output of the comparator 52 is at L level. If the correction detection voltage Vc is higher than the divided voltage Ve, the output of the comparator 52 becomes L level, so that the correction detection voltage Vc is decreased. Therefore, the process proceeds to step S24 so as to increase the adjustment voltage Vb from the DA converter 50, and the digital value of the DA converter 50 is increased in 1-bit units.

  Subsequently, in step S25, it is checked whether or not the output of the comparator 52 has been inverted. Until the output of the comparator 52 is inverted from the L level to the H level, the downs in units of 1 bit in steps S23 and S24 are repeated. If it is determined in step S25 that the comparator output has been inverted to the H level, it is determined that the correction detection voltage Vc matches the divided voltage Ve, and the process proceeds to step S27 to turn off the switch 80, thereby turning on the comparator 52. In contrast, the reference voltage Vr higher than the divided voltage Ve by (Va / 2) is set, and the adjustment process is terminated.

  On the other hand, if the output of the comparator is at the H level in step S23, the correction detection voltage Vc is lower than the divided voltage Ve. Therefore, in order to increase the correction detection voltage Vc, the DA converter in step S26. Is reduced to one bit unit to lower the adjustment voltage Vb.

  Subsequently, in step S25, it is checked whether or not the output of the comparator 52 has been inverted from the H level to the L level. When the inversion to the L level is determined, it is determined that the correction detection voltage Vc matches the divided voltage Ve. In step S27, the switch 80 is turned off, and the reference voltage Vr higher than the divided voltage Ve by (Va / 2) is set for the comparator 52.

  In the above embodiment, the adjustment function of the CPU 22 is described separately for the first adjustment processing unit 56 and the second adjustment processing unit 58. However, the present invention is not limited to this, and one adjustment process is performed by combining both. You may make it function as a part.

  In the above embodiment, a repeater in which an on / off type fire sensor is connected as an apparatus for mainly supplying a load current to the transmission line drawn from the receiver is taken as an example. The same applies when a device or a burglar alarm is connected.

The present invention includes appropriate modifications that do not impair the object and advantages thereof, and is not limited by the numerical values shown in the above embodiments.

The block diagram which showed the receiver in the monitoring system with which this invention is applied with the analog type sensor and the repeater The circuit diagram which showed 1st Embodiment of CPU which functions as the transmission input circuit by this invention, and its control circuit The time chart which showed the signal waveform of each part in a 1st embodiment The time chart which showed the signal waveform of each part in case load current in the 1st embodiment is stable The time chart which showed the signal waveform of each part when the load current in the 1st embodiment is fluctuating The flowchart which showed the adjustment process in 1st Embodiment. The circuit diagram which showed 2nd Embodiment of CPU which functions as the transmission input circuit by this invention, and its control circuit The circuit block diagram which showed the circuit structure of the digital variable resistor provided in 2nd Embodiment Flowchart showing adjustment processing in the second embodiment A circuit diagram showing a third embodiment of a CPU functioning as a transmission input circuit and its control circuit according to the present invention. The time chart which showed the signal waveform of each part in a 3rd embodiment The time chart which showed the signal waveform of each part in case load current in the 3rd embodiment is stable The time chart which showed the signal waveform of each part in case the load current in 3rd Embodiment is fluctuating The flowchart which showed the adjustment process in 3rd Embodiment System block diagram showing a conventional monitoring system This block diagram showing the repeater and analog sensor in the conventional monitoring system with an equivalent circuit Circuit diagram showing conventional transmission input circuit FIG. 17 is a time chart showing the comparator input voltage and sample hold timing in the conventional circuit of FIG. Time chart showing conventional received voltage and sample and hold timing when load current is stable

Explanation of symbols

10: Receiver 12a, 12b: Transmission line 14: Analog type sensor 16: Repeater 18a, 18b: Sensor line 20: On-off type sensor 22, 38, 44: CPU
24: Transmission circuit unit 26: Transmission output circuit 28: Transmission input circuit 30: Display unit 32: Operation unit 34: Storage unit 36: Transfer unit 40: Sensor unit 42, 48: Transmission circuit unit 46: Notification receiving unit 48 : Operational amplifier 50: DA converter 52: Comparator 54: Reference voltage source 56: First adjustment processing unit 58: Second adjustment processing unit 60: Digital variable resistor 62: Series resistor array 64, 80: Switch 66: Up / down counter 68 : Nonvolatile memory 70: Control circuit 72: Power supply terminal 74: Ground terminal 76: Wiper terminal 78: Control terminal 76: Second inverter 78: AD converter 82: Voltage divider circuit

Claims (8)

In the master unit equipped with a transmission input circuit for detecting the presence or absence of transmission current from the slave unit and its control circuit in a state where the load current is flowing through the transmission line that also serves as the power supply line,
The transmission input circuit is
A current detection resistor that inputs a line current from the transmission line and generates a line current detection voltage;
A digital-to-analog converter that generates an arbitrary adjustment voltage according to the digital value;
The line current detection voltage generated in the current detection resistor is input to one of the input terminals, and the adjustment voltage generated by the digital-analog converter is input to the other input terminal, and the adjustment voltage is calculated from the line current detection voltage. An amplifier that outputs the subtracted correction detection voltage;
A correction detection voltage output from the amplifier is input to one of the input terminals, a predetermined reference voltage is input to the other input terminal, and a component of the correction detection voltage exceeding the reference voltage is output as a transmission current detection signal. A comparator,
With
The control circuit includes:
A first adjustment processing unit that adjusts the adjustment voltage from the digital-analog converter so that the correction detection voltage output from the amplifier coincides with the reference voltage at a vacant timing of the transmission current from the slave unit;
Adjustment from the digital-analog converter so that the correction detection voltage adjusted by the first adjustment processing unit is a correction detection voltage that is reduced by a constant voltage that is substantially half of the transmission current detection voltage corresponding to the transmission current. A second adjustment processing unit for adjusting the voltage;
A master unit characterized by comprising.
2. The master unit according to claim 1, wherein the first adjustment processing unit adjusts a digital value for the digital-to-analog converter to a digital value in which the output of the comparator is inverted by a 1-bit change or a digital value immediately before the inversion. the master unit, characterized in that to match with the reference voltage the correction detection voltage by.
In claim 1 master machine described in the first adjustment processing unit,
When the output of the comparator at the start of adjustment is at the H level, the digital value is changed in 1-bit units in the direction of inverting the H level to the L level, and the digital value when the H level is inverted to the L level or Fixed to the digital value just before inversion,
When the output of the comparator at the start of adjustment is L level, the digital value is changed in 1-bit units in the direction of inverting the L level to H level, and the digital value when inverting from L level to H level or The master unit is characterized in that it is fixed to the digital value just before inversion.
In the master unit equipped with a transmission input circuit for detecting the presence or absence of transmission current from the slave unit and its control circuit in a state where the load current is flowing through the transmission line that also serves as the power supply line,
The transmission input circuit is
A current detection resistor that inputs a line current from the transmission line and generates a line current detection voltage;
A digital-to-analog converter that generates an arbitrary adjustment voltage according to the digital value;
The line current detection voltage generated in the current detection resistor is input to one of the input terminals, and the adjustment voltage generated by the digital-analog converter is input to the other input terminal, and the adjustment voltage is calculated from the line current detection voltage. An amplifier that outputs the subtracted correction detection voltage;
A voltage dividing circuit that divides a predetermined reference voltage by a series resistor and outputs a predetermined divided voltage;
Inserted into the ground side of the voltage dividing circuit, forms the voltage dividing circuit when the switch is turned on and outputs the divided voltage, and disconnects the ground side of the voltage dividing circuit and outputs the reference voltage as it is when the switch is turned off A switch,
The correction detection voltage output from the amplifier is input to one of the input terminals, the reference voltage from the voltage dividing circuit is input to the other input terminal, and the component of the correction detection voltage that exceeds the reference voltage is detected as a transmission current. A comparator that outputs as a signal;
With
The control circuit includes:
At a timing when the transmission current from the slave unit is idle, the correction detection voltage output from the amplifier is changed to the divided voltage while the switch is turned on and the divided voltage is output from the voltage dividing circuit. A first adjustment processing unit that adjusts the adjustment voltage from the digital-analog converter so as to match;
A second adjustment processing unit for turning off the switch and fixing the voltage dividing circuit to an output state of the reference voltage after adjustment by the first adjustment processing unit;
A master unit characterized by comprising.
5. The master unit according to claim 4, wherein the voltage dividing circuit generates a reference voltage output from the voltage dividing circuit when the switch is turned off, with respect to a voltage divided voltage output from the voltage dividing circuit when the switch is turned on. , the master unit, characterized in that have configured to increase by a predetermined voltage as a half approximately transmission current detection voltage corresponding to the transmission current.
5. The master unit according to claim 4, wherein the first adjustment processing unit adjusts a digital value for the digital-to-analog converter to a digital value in which the output of the comparator is inverted by a 1-bit change or a digital value immediately before the inversion. the master unit, characterized in that to match the divided voltage to the correction detection voltage by.
5. The master unit according to claim 4, wherein the first adjustment processing unit is
When the output of the comparator at the start of adjustment is at the H level, the digital value is changed in 1-bit units in the direction of inverting the H level to the L level, and the digital value when the H level is inverted to the L level or Fixed to the digital value just before inversion,
When the output of the comparator at the start of adjustment is L level, the digital value is changed in 1-bit units in the direction of inverting the L level to H level, and the digital value when inverting from L level to H level or The master unit is characterized in that it is fixed to the digital value just before inversion.
In claim 1 or 4 master machine described in the parent device, characterized in that a digital variable resistor in place of the digital-to-analog converter.

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