JP5230992B2 - Manufacturing method of substrate with through electrode - Google Patents

Description

  The present invention relates to a method for manufacturing a substrate with a through electrode, and more specifically, a method for manufacturing a substrate with a through electrode applicable to a method for manufacturing a wiring substrate (such as an interposer) having a through electrode or a semiconductor device having a through electrode. About.

  2. Description of the Related Art Conventionally, there is a silicon interposer for matching or grid-converting a semiconductor chip terminal and a printed wiring board terminal. The silicon interposer has a structure in which a through electrode is provided on a silicon substrate, and wiring layers formed on both sides of the silicon substrate are interconnected through the through electrode.

  As shown in FIG. 1A, a conventional silicon interposer manufacturing method first prepares a silicon wafer 100 having a thickness of 500 to 600 μm. Next, as shown in FIG. 1B, the silicon wafer 100 is polished to a required thickness by polishing the silicon wafer 100 with a grinder.

  Subsequently, as shown in FIG. 1C, a resist 200 having an opening 200a is formed in a portion of the silicon wafer 100 where a through hole is to be formed. Further, the through hole TH penetrating the silicon wafer 100 is formed by etching the silicon wafer 100 in the thickness direction through the opening 200a of the resist 200 by anisotropic dry etching (RIE or the like). Thereafter, the resist 200 is removed.

  Next, as shown in FIG. 1D, the silicon wafer 100 is thermally oxidized to form an insulating layer 300 made of a silicon oxide layer on both surfaces of the silicon wafer 100 and the inner surface of the through hole TH.

  Subsequently, as shown in FIG. 1E, a plating power supply material (not shown) such as a copper foil is disposed under the silicon wafer 100, and copper plating is performed from the lower part to the upper part of the through hole TH by electrolytic plating. Thus, the through electrode 400 is formed in the through hole TH. Alternatively, there is a method of forming the through electrode 400 by filling the through hole TH with a conductive paste by screen printing or the like.

  Further, as shown in FIG. 2A, the through electrodes 400 protruding outward from the insulating layers 300 on both sides of the silicon wafer 100 are each flattened by polishing.

  Thereafter, as shown in FIG. 2B, wiring layers 500 are respectively formed on both sides of the silicon wafer 100 by a semi-additive method or the like. The wiring layers 500 on both sides of the silicon wafer 100 are interconnected through the through electrode 400. Furthermore, if necessary, a required multilayer wiring is formed on the wiring layer 500 via an insulating layer. Then, by cutting the silicon wafer 100 in the thickness direction, individual silicon interposers provided with the through electrodes 400 are obtained.

  In Patent Documents 1 and 2, a conductive pin composed of a head flange portion and a shaft portion is inserted into a through hole of a chip substrate, and individual chip substrates on which the conductive pins are mounted are stacked to each other via the conductive pins. It is described that a multi-chip package is configured by connecting.

Further, in Patent Document 3, a plurality of semiconductor chips having electrodes are stacked, vias penetrating each electrode are formed, brazed plugs are inserted into the vias, and a coupling pillar member is provided by plating. It is described that interconnected semiconductor chips are interconnected.
JP 2001-127242 A JP 2001-77296 A JP 2002-26240 A

  However, in the above-described conventional silicon interposer manufacturing method, silicon wafers are processed one by one and through electrodes are formed in the through holes. Therefore, there is a problem in that productivity is low and costs are increased. In particular, when the through electrode is formed by electrolytic plating, since the copper plating is performed from the lower part to the upper part of the through hole, the processing time is long and the productivity is considerably lowered.

  The present invention was created in view of the above problems, and in a method for manufacturing a substrate with a through electrode such as a wiring board or a semiconductor device provided with a through electrode, a method that can be manufactured with high productivity and at low cost. The purpose is to provide.

  In order to solve the above-mentioned problems, the present invention relates to a method for manufacturing a substrate with a through electrode, wherein a conductive post penetrates in a thickness direction of a member disposed on a support plate in a state of being electrically insulated from the member. A step of preparing a structure to be erected and a step of obtaining a plurality of substrates provided with through electrodes obtained by cutting the conductive posts by cutting the structure horizontally from its side surface and separating it. It is characterized by having.

  In one preferred embodiment of the present invention, first, a support plate on which conductive posts are erected and a plurality of substrates (such as silicon wafers) provided with through holes are prepared, and the conductive posts are inserted into the through holes. In this state, the substrate is placed on the support plate. Thereafter, an insulating layer is formed on the substrate and between the inner surface of the through hole and the conductive post. Further, by repeating these series of steps, the substrate and the insulating layer are alternately laminated on the support plate.

  In this way, there can be obtained a structure in which the conductive post penetrates and stands in a state of being electrically insulated from the member in the thickness direction of the member of the present invention. In this aspect, the conductive posts functioning as through electrodes common to the through holes of the plurality of stacked substrates are inserted and arranged.

  Thereafter, a plurality of substrates provided with through electrodes obtained by cutting the conductive posts are obtained by horizontally cutting and separating between the support plate and the substrate and between the plurality of substrates.

  By adopting such a method, a plurality of substrates provided with through electrodes can be obtained more efficiently than a method of providing through electrodes one by one in the through holes of each substrate. Therefore, productivity in manufacturing the substrate with through electrodes can be improved, and cost reduction can be achieved.

  In another aspect of the present invention, a plurality of substrates are similarly stacked on a support plate in a state where a plurality of substrates are in contact without providing an insulating layer between the substrates, and then cut between the plurality of substrates. Thus, individual substrates provided with through electrodes may be obtained. In this case, the through hole of the substrate may be inserted into the conductive post standing on the support plate, or a plurality of through holes may be connected to the support plate not provided with the conductive post. After the substrates are stacked, the conductive posts may be inserted through the through holes and erected.

  In one preferred embodiment of the present invention, the substrate stacked on the support plate may be a silicon wafer with a built-in element in which a semiconductor element or the like is formed and a connection pad is provided on the upper surface side. In this embodiment, a through-hole penetrating from the part (center portion) of the connection pad to the lower surface is provided in the silicon wafer with a built-in element, and the connection pad is disposed around the through-hole.

  Similarly, the element built-in silicon wafer is laminated on the support plate in a state where the conductive post is inserted through the through hole through the insulating portion.

  Thereafter, the silicon wafer is cut in the horizontal direction between the laminated silicon wafers with built-in elements, and individual silicon wafers with built-in elements having through electrodes are obtained. Furthermore, the through electrode and the connection pad are electrically connected at the local wiring portion. Then, a silicon wafer with a built-in element or a chip (semiconductor memory chip or the like) obtained by dividing it into individual pieces are stacked and interconnected by through electrodes.

  As described above, in the present invention, the substrate with through electrodes is manufactured with high productivity and at low cost.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

(First embodiment)
3-8 is sectional drawing which shows the manufacturing method of the board | substrate with a penetration electrode of 1st Embodiment of this invention. In the first embodiment, a silicon interposer (wiring substrate) is taken as an example of a substrate with a through electrode, and a manufacturing method thereof will be described.

  In the method for manufacturing a substrate with a through electrode according to the first embodiment, as shown in FIG. 3A, first, a support plate 5 with posts in which conductive posts 12 are erected on the upper surface side of the support plate 10 is prepared. There are various methods for forming the post supporting plate 5.

  As a first method of forming the support plate 5 with posts, as shown in FIG. 9A, a copper plate 10a is prepared, and a resist 13 in which an opening 13a is provided in a portion where a conductive post is disposed is formed by using a copper plate. Form on top of 10a. Further, as shown in FIG. 9B, the copper post 12a is formed by performing copper plating on the opening 13a of the resist 13 by electrolytic plating using the copper plate 10a as a plating power feeding path.

  Thereafter, as shown in FIG. 9C, the resist 13 is removed to obtain a structure in which the copper posts 12a are erected on the copper plate 10a. For example, the diameter of the copper post 12a is 50 to 200 μm, and the height is set to 300 to 750 μm.

  As a second method of forming the support plate 5 with posts, as shown in FIG. 10A, a silicon wafer 10b is prepared, and a resist 23 is patterned on a portion on the silicon wafer 10b where the conductive posts are arranged. Form. Further, as shown in FIG. 10B, the resist 23 is masked and the silicon wafer 10b is etched to a predetermined depth by anisotropic dry etching (RIE or the like).

  Thereafter, as shown in FIG. 10C, the resist 23 is removed to obtain a structure in which the silicon post 12b is erected on the silicon wafer 10b. The silicon wafer 10b is doped with conductive impurities such as phosphorus (P) and boron (B) so that sufficient conductivity is obtained. For example, the diameter of the silicon post 12b is 50 to 200 μm, and the height is set to 300 to 750 μm.

  As shown in FIG. 11, a third forming method of the support plate 5 with posts is formed by forming an aluminum layer 15 on a silicon wafer 10c by a sputtering method, and then forming gold bumps 12c (gold) by a wire bonding method thereon. Post). For example, the gold bump 12c has a diameter of 50 to 150 [mu] m and a height of 100 to 200 [mu] m.

  Further, as a fourth method of forming the support plate 5 with posts, as shown in FIG. 12, an adhesive layer 17 is formed on the support plate 10, and the conduction pins 12 d are fixed to the support plate 10 by the adhesive layer 17. May be. For example, the diameter of the conduction pin 12d is 100 to 300 μm, and the height is set to 1 to 2 mm.

  Next, referring back to FIG. 3B, a first silicon wafer 20a (substrate) provided with a through hole TH penetrating in the thickness direction is prepared. Since the conductive posts 12 of the support plate 5 with posts described above are inserted through the through holes TH of the first silicon wafer 20a, the diameter of the through holes TH is set to be slightly larger than the diameter of the conductive posts 12. The thickness of the first silicon wafer 20a is set to 50 to 300 μm.

  Such a first silicon wafer 20a is formed by photolithography and anisotropic dry etching (such as RIE) after a silicon wafer having a thickness of 500 to 600 μm is polished by a grinder and thinned to a required thickness. The through hole TH is formed by processing.

  As shown in FIGS. 3B and 4A, the first silicon wafer 20a is inserted with the conductive posts 12 of the support plate 5 with posts inserted through the through holes TH of the first silicon wafer 20a. Is placed on the support plate 10. At this time, the diameters of the through hole TH and the conductive post 12 are adjusted so that a gap C of about 20 μm is generated between the inner surface of the through hole TH of the first silicon wafer 20 a and the conductive post 12.

  Next, as shown in FIG. 4B, a resin layer 22 (insulating layer) is formed on the upper surface of the first silicon wafer 20a and in the gap C between the through hole TH and the conductive post 12 (FIG. 4A). . The first silicon wafer 20a and the conductive post 12 are electrically insulated by the resin layer 22 filled in the gap C. The resin layer 22 has a thickness of 50 to 200 μm, and a method of spraying a liquid resin on the first silicon wafer 20a or a B-stage (uncured) resin film is pasted on the first silicon wafer 20a. It is formed by the method of wearing. At this time, the resin layer 22 is in an uncured state.

  Next, as shown in FIG. 5A, a second silicon wafer 20b provided with the same through hole TH as the first silicon wafer 20a is prepared, and the conductive post 12 is placed in the through hole TH of the second silicon wafer 20b. The second silicon wafer 20b is disposed on the resin layer 22 in a state in which is inserted.

  Subsequently, as shown in FIG. 5B, similarly, a resin layer 22 is formed in the gap between the upper surface of the second silicon wafer 20 b and the inner surface of the through hole TH and the conductive post 12.

  Thus, after the silicon wafer 20a is placed on the support plate 10 with the conductive post 12 inserted through the through hole TH, a series of steps for forming the resin layer 22 is performed n times (where n is 2 or more). Integer) Repeat. FIG. 6 shows an example in which the series of steps is repeated six times.

  That is, the first to sixth silicon wafers 20a to 20f are laminated on the support plate 10 via the resin layer 22 in a state where the conductive posts 12 are collectively inserted into the respective through holes TH. The first to sixth silicon wafers 20 a to 20 f are electrically insulated from the conductive post 12 by the resin layer 22 filled in the gap between the inner surface of the through hole TH and the conductive post 12.

  As described above, the conductive posts 12 common to the through holes TH of the plurality of laminated silicon wafers 20a to 20f are inserted and arranged, and when attention is paid to the silicon wafers 20a to 20f, the through electrodes are arranged respectively. It becomes a state.

  Thereafter, the uncured resin layer 22 is cured by heat-treating the structure of FIG. 6 at a temperature of 150 to 200 ° C., for example.

  In 1st Embodiment, the 1st-6th silicon wafer 20a-20f shown by FIG. 6 and the resin layer 22 between them are examples of the member arrange | positioned on a support plate, and this member is the thickness direction. The electrically conductive post 12 is erected while being electrically insulated.

  Subsequently, as shown in FIG. 6 as well, each resin layer 22 between the first to sixth silicon wafers 20a to 20f is cut in the horizontal direction (the same direction as the wafer substrate direction) from the center of the side surface. That is, the resin layers 22 and the conductive posts 12 between the first to sixth silicon wafers 20a to 20f are cut.

  At the same time, the boundary between the support plate 10 and the first silicon wafer 20a is cut in the horizontal direction. As the cutting method, a wire saw method in which a diamond wire or the like is wound and moved at high speed, a water jet method in which ultra-high pressure water is sprayed from a small-diameter nozzle and cut, or a dicing method in which a blade is rotated is used. The

  As a result, as shown in FIG. 7, the first to sixth silicon wafers 20 a to 20 f are separated from the support plate 10, and they are separated from each other so that the individual first to sixth silicon wafers 20 a to 20 f are separated. can get. By cutting the conductive posts 12 between the silicon wafers 20a to 20f, the conductive posts 12 left in the through holes TH of the first to sixth silicon wafers 20a to 20f become the through electrodes 32. .

  The through electrode 32 is electrically insulated from the silicon wafer 20a by the resin layer 22 filled between the through hole TH. The first silicon wafer 20a is separated from each other with the resin layer 22 left on the front side and the second to sixth silicon wafers 20b to 20f left with the resin layer 22 left on their front and back surfaces. Thus, the board | substrate 1 with a penetration electrode of this embodiment is obtained.

  As described above, in the present embodiment, the plurality of silicon wafers 20a to 20f are attached to the support plate 10 in a state where the conductive posts 12 of the support plate 5 with posts are inserted into the through holes TH of the silicon wafers 20a to 20f. Laminate on top. At this time, the conductive post 12 functions as a common through electrode that is inserted through the through holes TH of the plurality of silicon wafers 20a to 20f. Then, by cutting between the plurality of silicon wafers 20a to 20f, the conductive posts 12 are separated to form the through electrodes 32 of the individual silicon wafers 20a to 20f.

  By adopting such a method, it is possible to manufacture a plurality of silicon wafers provided with through electrodes extremely efficiently compared to the method of providing through electrodes one by one in the through holes of the silicon wafer. . Therefore, high productivity can be obtained and the cost can be reduced in the manufacture of the substrate with through electrodes.

  Since the lowermost first silicon wafer 20a is directly disposed on the support plate 10, the resin layer 22 is not provided on the lower surface thereof. Therefore, a resin layer having an opening provided on the lower surface of the through electrode 32 is separately formed on the lower surface of the first silicon wafer 20a. Alternatively, a resin layer may be provided in advance so as to expose the conductive posts 12 on the support plate 10 in FIG. 3A, and the resin layer may be cut in the horizontal direction.

  Next, a method for forming a wiring layer on the silicon wafer 20 (20a to 20f) with the through electrode 32 obtained by the above method will be described. As shown in FIG. 8A, first wiring layers 34 that are interconnected via through electrodes 32 are formed on both sides of the silicon wafer 20. The first wiring layer 34 is formed by, for example, a semi-additive method.

  More specifically, first, after forming a seed layer (not shown) on the upper surface side of the silicon wafer 20, a plating resist (not shown) provided with an opening in a portion where the first wiring layer 34 is disposed is formed. . Subsequently, a metal pattern layer (not shown) is formed in the opening portion of the plating resist by electrolytic plating using the seed layer as a plating power feeding path. Furthermore, after removing the plating resist, the first wiring layer 34 constituted by the seed layer and the metal pattern layer is obtained by etching the seed layer using the metal pattern layer as a mask. A first wiring layer 34 is also formed on the lower surface side of the silicon wafer by a similar method.

  Next, as shown in FIG. 8B, interlayer insulating layers 36 that cover the first wiring layer 34 are formed on both sides of the silicon wafer 20. Subsequently, via holes VH having a depth reaching the first wiring layer 34 are formed by processing the interlayer insulating layers 36 on both sides of the silicon wafer 20 by dry etching or laser.

  Subsequently, as shown in FIG. 8B, second wiring layers 34a connected to the first wiring layers 34 via the via holes VH are respectively formed on the interlayer insulating layers 36 on both sides of the silicon wafer 20. To do. Further, as shown in FIG. 8C, solder resists 38 each having an opening are formed on the connection portions of the second wiring layer 34 a on both sides of the silicon wafer 20.

  Thereafter, the silicon interposer 2 (wiring substrate) is obtained by cutting the first silicon wafer 20 in the thickness direction for each chip region. In the example of FIG. 8C, two wiring layers 34 and 34a are respectively laminated on both sides of the silicon wafer 20 provided with the through electrode 32. The n layers (n is an integer of 1 or more) A wiring layer can be arbitrarily formed.

  Next, as shown in FIG. 8D, the bump 40a of the semiconductor chip (LSI chip) 40 is flip-chip connected to the connection portion of the second wiring layer 34a on the upper surface side of the silicon interposer 2. Further, external connection terminals 39 are provided by mounting solder balls on the connection portions of the first wiring layer 34 on the lower surface side of the silicon interposer 2.

  The semiconductor chip 40 may be mounted after obtaining each silicon interposer 2, or the silicon wafer 20 may be cut after mounting the semiconductor chip in each interposer region of the silicon wafer 20.

  In the first embodiment, a silicon interposer has been described as an example of a substrate with a through electrode, but instead of a silicon wafer, a glass substrate, a ceramic substrate, a metal substrate (such as copper, 42 alloy or Kovar), or a carbon substrate is used. A substrate with a through electrode having a core substrate made of various materials can be manufactured by the same manufacturing method by forming a similar through hole.

(Second Embodiment)
13-16 is sectional drawing which shows the manufacturing method of the board | substrate with a penetration electrode of 2nd Embodiment of this invention. In the second embodiment, since the resin layer provided between the silicon wafers in the first embodiment is omitted, detailed description of the same steps as those in the first embodiment is omitted.

  In the second embodiment, as shown in FIG. 13A, first, similarly to the first embodiment, the conductive posts 12 of the support plate 5 with posts are inserted through the through holes TH of the first silicon wafer 20a. In this state, the first silicon wafer 20a is placed on the support plate 10. Next, as shown in FIG. 13B, in the second embodiment, the first silicon wafer 20b is formed with the conductive posts 12 inserted through the through holes TH without forming the resin layer. Place directly on top.

  In this way, by repeating the step of placing the silicon wafer on the support plate 10 n times (n is an integer of 2 or more), a plurality of conductive posts 12 are inserted in the through holes TH that communicate with each other. The silicon wafer is laminated on the support plate 10. FIG. 14A shows an example in which six first to sixth silicon wafers 20 a to 20 f are stacked on the support plate 10. In the second embodiment, the first to sixth silicon wafers 20a to 20f are directly laminated in a state where they are in contact with each other. As a result, the conductive post 12 functioning as a common through electrode is inserted into the center of each through hole TH of the first to sixth silicon wafers 20a to 20f.

  As another method for obtaining the structure of FIG. 14A, as shown in FIG. 16, the first to sixth silicon wafers described above are formed on a support plate 10 such as a tape having an adhesive layer on the surface. 20a to 20f are stacked so that their through holes TH communicate with each other. Thereafter, the conductive post 12 such as a conductive pin may be inserted into the through hole TH that is in communication and fixed to the adhesive layer on the support plate 10.

  That is, the support plate 10 and the conductive post 12 may be prepared separately, and after the silicon wafer is laminated on the support plate 10, the conductive post 12 may be inserted into the through hole TH. As a result, the same structure as that shown in FIG. 14A is obtained.

  Subsequently, as shown in FIG. 14B, a resin portion 22a (insulating portion) is filled in a gap between the inner surface of the through hole TH and the conductive post 12 communicating with each other in the first to sixth silicon wafers 20a to 20f. . Thereafter, the uncured resin portion 22a is cured by heat treatment.

  In the second embodiment, the first to sixth silicon wafers 20a to 20f shown in FIG. 14B are examples of members arranged on the support plate 10, and are electrically insulated from the members in the thickness direction. In this state, the conductive post 12 penetrates and stands.

  Further, as shown in FIG. 14B, the boundaries between the first to sixth first silicon wafers 20a to 20f are cut in the horizontal direction (the same direction as the substrate direction of the wafer). At the same time, the support plate 10 and the first silicon wafer 20a are cut in the horizontal direction.

  As a result, as shown in FIG. 15A, the first to sixth first silicon wafers 20a to 20f are separated from the support plate 10, and are separated from each other so that the first to sixth sixth wafers are separated from each other. 1 silicon wafers 20a to 20f are obtained. At this time, as in the first embodiment, the common conductive post 12 is cut to form the individual through electrodes 32 of the first to sixth first silicon wafers 20a to 20f. The through electrode 32 is electrically insulated from the silicon wafers 20a to 20f by the resin portion 22a filled between the through hole TH and the inner surface of the through hole TH.

  In 2nd Embodiment, since the 1st-6th 1st silicon wafer 20a-20f mutually contacts and is laminated | stacked directly, a resin layer is not formed in those both sides. Therefore, as shown in FIG. 15B, a resin layer provided with openings 24a that expose the upper and lower surfaces of the through-electrode 32 on both sides of the silicon wafer 20 (20a to 20f) obtained by the above-described method. 24 are formed. As a method for forming the opening 24a in the resin layer 24, for example, the opening may be formed in the photosensitive polyimide by photolithography, or the opening may be formed in the non-photosensitive polyimide by a laser. .

  Further, as in the first embodiment, required wiring layers interconnected via the through electrodes 32 are formed on both sides of the silicon wafer 20, respectively, and a semiconductor chip is mounted on the upper surface side wiring layer. External connection terminals are formed in the wiring layer.

  The method for manufacturing a wiring board according to the second embodiment has the same effects as those of the first embodiment.

(Third embodiment)
17 and 18 are cross-sectional views illustrating a method for manufacturing a wiring substrate with through electrodes according to a third embodiment of the present invention. In the third embodiment, detailed description of the same steps as those in the first embodiment is omitted.

  In the third embodiment, as shown in FIG. 17A, a silicon wafer 20x having a thickness capable of obtaining a plurality of silicon wafers from the thickness direction is used, and a through hole TH is provided in the silicon wafer 20x. For example, when 10 silicon wafers having a thickness of 50 μm are finally obtained, the through hole TH is formed in the silicon wafer 20x having a thickness of 500 μm.

  Then, as shown in FIGS. 17A and 17B, the silicon wafer 20x is disposed on the support plate 10 with the conductive posts 12 inserted through the through holes TH of the silicon wafer 20x having such a thickness. To do. At this time, the height of the conductive post 12 is set to be equal to the thickness of the silicon wafer 20x, and the upper surface of the conductive post 12 is substantially the same as the upper surface of the silicon wafer 20, so that the through hole TH is formed. Located in the center.

  As in the second embodiment described above, a support plate without a conductive post is used, and after the silicon wafer 20x is disposed on the support plate, the conductive post 12 is inserted into the through hole TH. It may be allowed to stand.

  Next, as shown in 18 (a), after filling the gap between the conductive post 12 and the inner surface of the through hole TH with the resin portion 22 a, the resin portion 22 a is cured by heat treatment. In the third embodiment, one silicon wafer 20x shown in FIG. 18 (a) is an example of a member disposed on the support plate 10, and the conductive material is electrically insulated from the member in the thickness direction. The post 12 is erected and penetrates.

  Further, as shown in FIG. 18A, the space between the support plate 10 and the silicon wafer 20x and the silicon wafer 20x itself are cut horizontally from the side surfaces. As a result, as shown in FIG. 8B, a plurality of silicon wafers 20y are obtained from the thickness direction of the silicon wafer 20x. At this time, as in the first embodiment, the common conductive post 12 is cut to form the through electrode 32 of each silicon wafer 20y. The through electrode 32 is electrically insulated from the silicon wafer 20y by the resin portion 22a filled between the through hole TH and the inner surface.

  Thereafter, as shown in FIG. 18C, as in the second embodiment, the resin layers 24 provided with openings 24x that expose the upper and lower surfaces of the through electrodes 32 are formed on both sides of the silicon wafer 20y, respectively. Form.

  Further, similar to the first embodiment, required wiring layers interconnected via the through electrodes 32 are formed on both sides of the silicon wafer 20y, respectively, and a semiconductor chip is mounted on the upper surface side wiring layer. External connection terminals are formed in the wiring layer.

  The method for manufacturing a wiring board according to the third embodiment has the same effects as those of the first embodiment. In the third embodiment, since the silicon wafer is not laminated, the process is simplified and the cost can be further reduced.

(Fourth embodiment)
FIGS. 19-21 is a figure which shows the manufacturing method of the board | substrate with a penetration electrode of 4th Embodiment of this invention. In the fourth embodiment, a semiconductor device including a through electrode will be described as an example of a substrate with a through electrode.

  As shown in FIG. 19A, the first silicon wafer 50a used in the fourth embodiment is an element built-in silicon wafer for obtaining a semiconductor chip (LSI chip) such as a memory chip. The first silicon wafer 50a is provided with an element region 52 in which semiconductor elements such as transistors and diodes are formed.

  Further, a multilayer wiring (not shown) for wiring transistors and the like is formed above the element region 52. The connection pads 54 connected to the multilayer wiring are exposed on the upper surface side of the first silicon wafer 50a. A plurality of chip regions are formed in the first silicon wafer 50a. FIG. 19A schematically shows one chip region in the wafer.

  Next, as shown in FIG. 19B, after forming a mask (not shown) having an opening at the center of the connection pad 54 on the upper surface side of the first silicon wafer 50a, the silicon wafer is passed through the opening. Etching is performed by anisotropic dry etching (RIE or the like) from the upper surface side to the lower surface side. Thereby, a through hole TH penetrating from the center of the upper surface of the connection pad 54 of the first silicon wafer 50a to the lower surface side of the silicon wafer 20 is formed. As a result, the connection pad 54 is left in a ring shape around the through hole TH.

  Next, as shown in FIG. 9C, as in the first embodiment, the post supporting plate 5 is prepared, and the conductive post 12 is inserted through the through hole TH of the first silicon wafer 50a. One silicon wafer 50 a is placed on the support plate 10. Subsequently, as in the first embodiment, the resin layer 22 is formed on the first silicon wafer 50 a and in the gap between the inner surface of the through hole TH and the conductive post 12. Furthermore, this series of steps is repeated as in the first embodiment.

  FIG. 19 (d) shows an example in which six first to sixth silicon wafers 50 a to 50 f are stacked on the support plate 10 via the resin layer 22. Further, the resin layer 22 is cured by heat treatment. Thereby, like the first embodiment, the common conductive post 12 is inserted into the through holes TH of the plurality of silicon wafers 20a to 20f. Similarly, as shown in FIG. 19D, the resin layers 22 between the support plate 10 and the first silicon wafer 50a and between the first to sixth silicon wafers 50a to 50f are horizontally arranged from the side surfaces. Cut each one.

  As a result, as shown in FIG. 20, the first to sixth silicon wafers 50a to 50f are separated from the support plate 10 and separated from each other, as in the first embodiment. Sixth silicon wafers 50a to 50f are obtained. At this time, as in the first embodiment, the conductive posts 12 are cut to form the through electrodes 32 of the individual silicon wafers 20. Each through electrode 32 is electrically insulated from the silicon wafers 50a to 50f by the resin layer 22 filled between the through holes TH.

  As in the first embodiment, since the resin layer 22 is not formed on the lower surface of the first silicon wafer 50a, a resin layer provided with an opening for exposing the lower surface of the through electrode 32 is separately formed.

  Next, as shown in FIG. 21 (a), by opening the portions of the resin layer 22 on the connection pads 54 in the individual silicon wafers 50 (50a to 50f) with the through electrodes 32 obtained in FIG. A via hole VH is formed. Further, as shown in FIG. 21B, a local wiring portion 56 that electrically connects the connection pad 54 and the through electrode 32 is formed on the resin layer 22.

  Subsequently, as shown in FIG. 21C, external connection terminals 58 are provided by mounting solder balls on the lower surface side of the through electrodes 32 of the silicon wafer 50. Furthermore, each semiconductor chip 60 provided with the through electrode 32 is obtained by cutting the silicon wafer 50 in the thickness direction.

  Thereafter, as shown in FIG. 21 (d), a plurality of semiconductor chips 60 are stacked by connecting the external connection terminals 58 of the upper semiconductor chip to the local wiring portion 56 of the lower semiconductor chip 60. As a result, a semiconductor device 3 in which a plurality of semiconductor chips 60 are stacked and interconnected via the through electrode 32 is obtained. Alternatively, it is also possible to obtain the semiconductor device 3 having a laminated structure by laminating the silicon wafer 50 provided with the external connection terminals 58 and then cutting it. Although the three semiconductor chips 60 are stacked in the example of FIG. 21D, they can be stacked with an arbitrary number of stacks.

  In the present embodiment, since a plurality of stacked semiconductor chips 60 are connected via the through electrodes 32, the electrical path is shortened and the electrical characteristics are improved as compared with the case where the semiconductor chips are stacked and connected by wires. In addition, the size can be reduced.

  In the fourth embodiment, the form in which the element built-in silicon wafer is used in the manufacturing method of the first embodiment has been described. However, as in the second embodiment, the element built-in silicon wafer is brought into contact without an insulating layer. You may laminate. In that case, like the modification of 2nd Embodiment, after laminating | stacking an element built-in silicon wafer on a support plate, you may insert a conductive post in the through-hole which communicates with them.

  In the present embodiment, an example in which memory chips are stacked is illustrated, but various electronic devices can be stacked. For example, a CPU (logic chip) and a memory chip may be stacked, or an imaging element such as a CMOS sensor and its image processing device may be stacked.

1A to 1E are sectional views (No. 1) showing a conventional method for manufacturing a silicon interposer. 2 (a) and 2 (b) are cross-sectional views (part 2) showing a conventional method for manufacturing a silicon interposer. 3A and 3B are cross-sectional views (part 1) showing the method for manufacturing the wiring substrate with through electrodes according to the first embodiment of the present invention. 4A and 4B are cross-sectional views (part 2) showing the method for manufacturing the wiring substrate with through electrodes according to the first embodiment of the present invention. 5A and 5B are sectional views (No. 3) showing the method for manufacturing the wiring substrate with through electrodes according to the first embodiment of the present invention. FIG. 6 is a sectional view (No. 4) showing the method for manufacturing the wiring substrate with through electrodes according to the first embodiment of the present invention. FIG. 7: is sectional drawing (the 5) which shows the manufacturing method of the wiring board with a penetration electrode of 1st Embodiment of this invention. 8A to 8D are cross-sectional views (No. 6) showing the method for manufacturing the wiring substrate with through electrodes according to the first embodiment of the present invention. FIGS. 9A to 9C are cross-sectional views showing a first method of forming the post-attached support plate of FIG. FIGS. 10A to 10C are cross-sectional views showing a second method of forming the post-attached support plate of FIG. FIG. 11 is a cross-sectional view showing a third method of forming the post-supported plate in FIG. FIG. 12 is a cross-sectional view showing a fourth method of forming the support plate with posts in FIG. 13A and 13B are cross-sectional views (part 1) showing the method for manufacturing the wiring substrate with through electrodes according to the second embodiment of the present invention. 14A and 14B are sectional views (No. 2) showing the method for manufacturing the wiring substrate with through electrodes according to the second embodiment of the present invention. FIGS. 15A and 15B are sectional views (No. 3) showing the method for manufacturing the wiring substrate with through electrodes according to the second embodiment of the present invention. FIG. 16 is a cross-sectional view showing another method for obtaining the structure of FIG. 17A and 17B are sectional views (No. 1) showing the method for manufacturing the wiring substrate with through electrodes according to the third embodiment of the present invention. 18A to 18C are cross-sectional views (part 2) illustrating the method for manufacturing the wiring substrate with through electrodes according to the third embodiment of the present invention. 19A to 19D are cross-sectional views (part 1) illustrating the method for manufacturing the semiconductor device with through electrodes according to the fourth embodiment of the present invention. FIG. 20 is a sectional view (No. 2) showing the method for manufacturing the semiconductor device with through electrodes according to the fourth embodiment of the invention. 21A to 21D are cross-sectional views (part 3) illustrating the method for manufacturing the semiconductor device with through electrodes according to the fourth embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Substrate with a penetration electrode, 2 ... Silicon interposer, 3 ... Semiconductor device, 5 ... Support plate with post, 10 ... Support plate, 10a ... Copper plate, 10b, 10c, 20, 20a-20f, 50, 50a-50f ... Silicon Wafer, 12 ... conductive post, 12a ... copper post, 12b ... silicon post, 12c ... gold bump, 12d ... conductive pin, 13, 23 ... resist, 13a, 24a ... opening, 15 ... aluminum layer, 17 ... adhesive layer 22, 24 ... resin layer, 22a ... resin portion, 32 ... penetrating electrode, 34 ... first wiring layer, 34a ... second wiring layer, 36 ... interlayer insulating layer, 38 ... solder resist, 39, 58 ... external connection terminals , 40, 60 ... semiconductor chip, 40a ... bump, 52 ... element region, 54 ... connection pad, 56 ... local wiring part, C ... gap, TH ... through hole, VH ... via hole .

Claims (8)

Preparing a support plate on which a conductive post is erected and a substrate provided with a through hole;
An insulating layer is formed between the upper surface of the substrate and the inner surface of the through hole and the conductive post after the substrate is disposed on the support plate in a state where the conductive post is inserted into the through hole. Repeating the series of steps to n times (n is an integer of 2 or more), and alternately stacking the substrate and the insulating layer on the support plate;
Obtaining a plurality of substrates provided with through electrodes obtained by cutting the conductive posts by horizontally cutting from between the support plate and the substrate and from the side surface of the insulating layer between the substrates; A method for producing a substrate with a through electrode, comprising: Preparing a support plate on which a conductive post is erected and a substrate provided with a through hole;
By repeating the step of placing the substrate on the support plate with the conductive post inserted through the through hole n times (n is an integer of 2 or more), the substrate is placed on the support plate. Laminating steps;
Filling an insulating portion between the inner surface of the through hole and the conductive post;
A plurality of substrates having through electrodes obtained by cutting the conductive posts by cutting between the support plate and the substrates and between the substrates. A method for manufacturing a substrate with electrodes. Preparing a support plate on which the conductive post is erected and a single substrate set to a thickness in which through holes are provided and a plurality of substrates are obtained from the thickness direction;
Placing the one substrate on the support plate in a state where the conductive posts are inserted through the through holes;
Filling an insulating portion between the inner surface of the through hole and the conductive post;
Cutting between the support plate and the substrate and horizontally cutting the substrate from the side surface to obtain a plurality of substrates provided with through electrodes obtained by cutting the conductive posts. A method for producing a substrate with a through electrode, comprising: Preparing a support plate and one substrate set to a thickness in which through holes are provided and a plurality of substrates are obtained from the thickness direction;
Disposing the one substrate on the support plate;
A step of standing by inserting a conductive post into the through hole;
Filling an insulating portion between the inner surface of the through hole and the conductive post;
Cutting between the support plate and the substrate and horizontally cutting the substrate from the side surface to obtain a plurality of substrates provided with through electrodes obtained by cutting the conductive posts. A method for producing a substrate with a through electrode, comprising: The substrate is an element-embedded silicon wafer in which a semiconductor element is formed and has a connection pad on the upper surface side, and the element-embedded silicon wafer is provided with the through hole penetrating from a part of the connection pad to the lower surface The connection pad is arranged around the through hole,
In the step of obtaining the plurality of substrates, a plurality of the element built-in silicon wafers provided with the through electrodes are obtained,
3. The through electrode according to claim 1, further comprising a step of forming a local wiring portion for connecting the through electrode and the connection pad after the step of obtaining the plurality of element built-in silicon wafers. A method for manufacturing a substrate. After the step of obtaining the individual said element built silicon wafer, and wherein the interconnecting through the through electrode by laminating elements incorporated silicon chips obtained by cutting the element built silicon wafer or the thickness direction The manufacturing method of the board | substrate with a penetration electrode of Claim 5.   The method for producing a substrate with a through electrode according to any one of claims 1 to 6, wherein in the step of obtaining the plurality of substrates, the substrate is cut by a wire saw method, a water jet method, or a dicing method.   5. The method for manufacturing a substrate with a through electrode according to claim 1, wherein the substrate is any one of a silicon wafer, a glass substrate, a ceramic substrate, a metal substrate, and a carbon substrate.

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