JP5220176B2 - Driving circuit - Google Patents

Description

  The present invention relates to a drive circuit, and more particularly to a drive circuit that outputs a potential corresponding to an input potential to an output node.

  2. Description of the Related Art Conventionally, a semiconductor integrated circuit device is provided with a drive circuit for transmitting a potential generated by a potential generation circuit having a small drive capability to a load. FIG. 80 is a circuit diagram showing the configuration of such a drive circuit 300. As shown in FIG. In FIG. 80, this drive circuit 300 includes P-type field effect transistors (hereinafter referred to as P-type transistors) 301 and 302, N-type field effect transistors (hereinafter referred to as N-type transistors) 303 and 304, and a constant current source 305. including.

  P-type transistors 301 and 302 are connected between a node of power supply potential VCC and nodes N301 and N302, respectively, and their gates are both connected to node N301. P-type transistors 301 and 302 constitute a current mirror circuit. N-type transistor 303 is connected between nodes N301 and N305, and its gate is connected to input node N303. N-type transistor 304 is connected between nodes N302 and N305, and has its gate connected to output node N304 and node N302. Constant current source 305 is connected between node N305 and a node of ground potential GND, and allows a constant current to flow.

  A current having a value corresponding to the potential VI of the input node N303 flows through the N-type transistor 303. Since the N-type transistor 303 and the P-type transistor 301 are connected in series, and the P-type transistors 301 and 302 constitute a current mirror circuit, currents of the same value flow through the transistors 301 to 303. When the potential VO of the output node N304 is lower than the input potential VI, the current flowing through the N-type transistor 304 is smaller than the current flowing through the transistors 301 to 303, and the output potential VO increases. When the potential VO of the output node N304 is higher than the input potential VI, the current flowing through the N-type transistor 304 becomes larger than the current flowing through the transistors 301 to 303, and the output potential VO decreases. Therefore, the output potential VO is equal to the input potential VI.

  However, in the conventional drive circuit 300, a constant through current always flows from the node of the power supply potential VCC to the node of the ground potential GND via the transistors 301 to 304 and the constant current source 305, so that the current consumption is large. was there.

  Therefore, a main object of the present invention is to provide a drive circuit with low current consumption.

  A drive circuit according to the present invention is a drive circuit that outputs a potential corresponding to an input potential to an output node, and outputs a potential obtained by shifting the level of the input potential in a certain potential direction by a predetermined first voltage. A first level shift circuit, and a second level shifter configured to output a potential obtained by level shifting the output potential of the first level shift circuit by a predetermined second voltage in a potential direction opposite to a certain potential direction to an output node. And a level shift circuit. The first level shift circuit includes a first current limiting element whose one electrode receives a first power supply potential, a first current receiving a second power supply potential, and an input electrode receiving an input potential. A first transistor of one conductivity type, its first electrode and input electrode are connected to the other electrode of the first current limiting element, and its second electrode is connected to the second electrode of the first transistor And a second transistor of the second conductivity type. The second level shift circuit includes a third transistor of the second conductivity type, the first electrode of which receives the third power supply potential, and the input electrode of which is connected to the other electrode of the first current limiting element. , A fourth transistor of the first conductivity type having its first electrode connected to the second electrode of the third transistor and its second electrode and input electrode connected to the output node. The driving circuit further changes the potential of the first node connected to the input electrode of the third transistor in a certain potential direction in a pulsed manner in response to the input potential being changed in a certain potential direction. 1 pulse generation circuit.

  In the drive circuit according to the present invention, the first level shift circuit that outputs a potential obtained by level shifting the input potential in a certain potential direction by a predetermined first voltage, and the output potential of the first level shift circuit. A second level shift circuit for outputting to the output node a potential level-shifted by a predetermined second voltage in a potential direction opposite to a certain potential direction, and in response to the input potential being changed in a certain potential direction There is provided a first pulse generating circuit for changing the potential of the first node between the first and second level shift circuits in a certain potential direction in a pulse manner. Therefore, by reducing the through current of the first and second level shift circuits, the current consumption can be reduced. Further, since the first pulse generation circuit is provided, the response speed can be increased.

1 is a block diagram showing an overall configuration of a color liquid crystal display device according to Embodiment 1 of the present invention. FIG. 2 is a circuit diagram illustrating a configuration of a liquid crystal driving circuit provided corresponding to each liquid crystal cell illustrated in FIG. 1. FIG. 2 is a circuit block diagram showing a main part of the horizontal scanning circuit shown in FIG. 1. FIG. 4 is a circuit diagram showing a configuration of a drive circuit shown in FIG. 3. FIG. 5 is a circuit diagram for explaining the operation of the drive circuit shown in FIG. 4. 6 is a time chart for explaining the operation of the drive circuit shown in FIG. FIG. 6 is a circuit diagram showing a modification of the first embodiment. FIG. 10 is a circuit diagram showing another modification of the first embodiment. FIG. 12 is a circuit diagram showing still another modification of the first embodiment. It is a circuit diagram which shows the structure of the level shift circuit of the drive circuit by Embodiment 2 of this invention. It is a circuit diagram which shows the structure of the level shift of the drive circuit by Embodiment 3 of this invention. It is a circuit diagram which shows the structure of the level shift circuit of the drive circuit by Embodiment 4 of this invention. It is a circuit diagram which shows the structure of the level shift circuit of the drive circuit by Embodiment 5 of this invention. FIG. 4 is a diagram for explaining a problem of the first embodiment. FIG. 3 is a circuit diagram for explaining a problem of the first embodiment. FIG. 10 is a circuit diagram for illustrating the principle of a sixth embodiment. It is a circuit diagram which shows the structure of the drive circuit by Embodiment 6 of this invention. FIG. 18 is a circuit diagram showing the configuration of the drive circuit shown in FIG. 17 in more detail. FIG. 22 is a circuit diagram showing a modification of the sixth embodiment. FIG. 34 is a circuit diagram showing another modification of the sixth embodiment. FIG. 22 is a circuit diagram showing still another modification example of the sixth embodiment. It is a circuit diagram which shows the structure of the drive circuit by Embodiment 7 of this invention. 23 is a time chart illustrating an operation of the drive circuit illustrated in FIG. 22. FIG. 25 is a circuit diagram showing a modification of the seventh embodiment. It is a circuit diagram which shows the structure of the drive circuit by Embodiment 8 of this invention. FIG. 22 is a circuit diagram showing a modification of the eighth embodiment. FIG. 38 is a circuit diagram showing another modification example of the eighth embodiment. FIG. 22 is a circuit diagram showing still another modification example of the eighth embodiment. FIG. 22 is a circuit diagram showing still another modification example of the eighth embodiment. FIG. 22 is a circuit diagram showing still another modification example of the eighth embodiment. It is a circuit diagram which shows the structure of the drive circuit by Embodiment 9 of this invention. 32 is a time chart showing an operation of the drive circuit shown in FIG. 31. FIG. 32 is a circuit diagram showing a modification of the ninth embodiment. It is a circuit diagram which shows the structure of the drive circuit by Embodiment 10 of this invention. FIG. 38 is a circuit diagram showing a modification of the tenth embodiment. It is a circuit diagram which shows the structure of the drive circuit by Embodiment 11 of this invention. FIG. 37 is a circuit diagram showing a configuration of a drive circuit shown in FIG. 36. It is a circuit block diagram which shows the structure of the drive circuit with an offset compensation function by Embodiment 12 of this invention. FIG. 39 is a time chart showing an operation of the drive circuit with an offset compensation function shown in FIG. 38. FIG. It is a circuit block diagram which shows the structure of the drive circuit with an offset compensation function by Embodiment 13 of this invention. 41 is a time chart illustrating an operation of the drive circuit with an offset compensation function illustrated in FIG. 40. 41 is another time chart showing the operation of the drive circuit with an offset compensation function shown in FIG. 40. FIG. 38 is a circuit diagram showing a modification of the thirteenth embodiment. FIG. 38 is a circuit diagram showing another modification of the thirteenth embodiment. FIG. 38 is a circuit diagram showing still another modification of the thirteenth embodiment. FIG. 38 is a circuit diagram showing still another modification of the thirteenth embodiment. FIG. 38 is a circuit diagram showing still another modification of the thirteenth embodiment. FIG. 38 is a circuit diagram showing still another modification of the thirteenth embodiment. FIG. 38 is a circuit diagram showing still another modification of the thirteenth embodiment. FIG. 38 is a circuit diagram showing still another modification of the thirteenth embodiment. FIG. 38 is a circuit diagram showing still another modification of the thirteenth embodiment. FIG. 38 is a circuit diagram showing still another modification of the thirteenth embodiment. FIG. 38 is a circuit diagram showing still another modification of the thirteenth embodiment. FIG. 38 is a circuit diagram showing still another modification of the thirteenth embodiment. It is a circuit block diagram which shows the structure of the drive circuit with an offset compensation function by Embodiment 14 of this invention. 56 is a time chart showing an operation of the drive circuit with an offset compensation function shown in FIG. 55. 56 is another time chart showing the operation of the drive circuit with an offset compensation function shown in FIG. 55. It is a circuit block diagram which shows the structure of the drive circuit with an offset compensation function by Embodiment 15 of this invention. FIG. 59 is a time chart showing the operation of the drive circuit with an offset compensation function shown in FIG. 58. FIG. It is a circuit diagram which shows the principal part of the color liquid crystal display device by Embodiment 16 of this invention. FIG. 61 is a circuit diagram showing a configuration of a push-type drive circuit included in the color liquid crystal display device shown in FIG. 60. FIG. 61 is a circuit diagram showing in more detail the configuration of the push-type drive circuit shown in FIG. 60. FIG. 38 is a circuit diagram showing a modification of the sixteenth embodiment. FIG. 38 is a circuit diagram showing another modification of the sixteenth embodiment. It is a circuit diagram which shows the structure of the pull type drive circuit by Embodiment 17 of this invention. FIG. 38 is a circuit diagram showing a modification of the seventeenth embodiment. It is a circuit block diagram which shows the structure of the drive circuit by Embodiment 18 of this invention. FIG. 38 is a circuit diagram showing a modification of the eighteenth embodiment. FIG. 38 is a circuit diagram showing another modification of the eighteenth embodiment. FIG. 38 is a circuit diagram showing still another modification of the eighteenth embodiment. FIG. 71 is a circuit diagram showing in more detail the configuration of the drive circuit shown in FIG. 70. It is a circuit block diagram which shows the structure of the push type drive circuit with an offset compensation function by Embodiment 19 of this invention. FIG. 38 is a circuit diagram showing a modification of the twentieth embodiment. It is a circuit block diagram which shows the structure of the drive circuit with an offset compensation function by Embodiment 20 of this invention. FIG. 38 is a circuit diagram showing a modification of the twentieth embodiment. FIG. 38 is a circuit diagram showing another modification of the twentieth embodiment. FIG. 38 is a circuit diagram showing still another modification of the twentieth embodiment. It is a circuit block diagram which shows the structure of the drive circuit with an offset compensation function by Embodiment 21 of this invention. It is a circuit block diagram which shows the structure of the drive circuit with an offset compensation function by Embodiment 22 of this invention. It is a circuit diagram which shows the structure of the conventional drive circuit.

[Embodiment 1]
FIG. 1 is a block diagram showing a configuration of a color liquid crystal display device according to Embodiment 1 of the present invention. In FIG. 1, the color liquid crystal display device includes a liquid crystal panel 1, a vertical scanning circuit 7, and a horizontal scanning circuit 8, and is provided, for example, in a mobile phone.

  The liquid crystal panel 1 includes a plurality of liquid crystal cells 2 arranged in a plurality of rows and columns, a scanning line 4 and a common potential line 5 provided corresponding to each row, and a data line 6 provided corresponding to each column. Including.

  Three liquid crystal cells 2 are grouped in advance in each row. The three liquid crystal cells 2 in each group are provided with R, G, and B color filters, respectively. The three liquid crystal cells 2 in each group constitute one pixel 3.

  Each liquid crystal cell 2 is provided with a liquid crystal driving circuit 10 as shown in FIG. The liquid crystal driving circuit 10 includes an N-type transistor 11 and a capacitor 12. The N-type transistor 11 is connected between the data line 6 and the one electrode 2 a of the liquid crystal cell 2, and its gate is connected to the scanning line 4. The capacitor 12 is connected between the one electrode 2 a of the liquid crystal cell 2 and the common potential line 5. A drive potential VDD is applied to the other electrode of the liquid crystal cell 2, and a common potential VSS is applied to the common potential line 5.

  Returning to FIG. 1, the vertical scanning circuit 7 sequentially selects the plurality of scanning lines 4 for each predetermined time according to the image signal, and sets the selected scanning lines 4 to the “H” level of the selection level. When the scanning line 4 is set to the selection level “H” level, the N-type transistor 11 of FIG. 2 is turned on, and corresponds to the one electrode 2 a of each liquid crystal cell 2 corresponding to the scanning line 4 and the liquid crystal cell 2. Data line 6 is coupled.

  In accordance with the image signal, the horizontal scanning circuit 8 sequentially selects, for example, twelve data lines 6 while the single scanning line 4 is selected by the vertical scanning circuit 7. A regulated potential VG is applied. The light transmittance of the liquid crystal cell 2 changes according to the level of the gradation potential VG.

  When all the liquid crystal cells 2 of the liquid crystal panel 1 are scanned by the vertical scanning circuit 7 and the horizontal scanning circuit 8, one image is displayed on the liquid crystal panel 1.

  FIG. 3 is a circuit block diagram showing a main part of the horizontal scanning circuit 8 shown in FIG. In FIG. 3, the horizontal scanning circuit 8 includes a gradation potential generation circuit 15 and a drive circuit 20. The gradation potential generation circuit 15 and the drive circuit 20 are provided by the number of data lines 6 (12 in this case) simultaneously selected by the horizontal scanning circuit 8.

  The gradation potential generation circuit 15 includes n + 1 (where n is a natural number) resistors connected in series between the node of the first power supply potential V1 (5V) and the node of the second power supply potential V2 (0V). Element 16.1-16. n + 1 and n + 1 resistance elements 16.1 to 16. n switches 17.1 to 17.n connected respectively between the n nodes between n + 1 and the output node 15a. n.

  n + 1 resistance elements 16.1 to 16. n stages of potentials appear at n nodes between n + 1. Switches 17.1-17. n is controlled by the image density signal φP, and only one of them is made conductive. Any one of the n-stage potentials is output to the output node 15a as the gradation potential VG. The drive circuit 20 supplies a current to the data line 6 so that the selected data line 6 becomes the gradation potential VG.

  FIG. 4 is a circuit diagram showing a configuration of the drive circuit 20. In FIG. 4, drive circuit 20 includes level shift circuits 21 and 25, a capacitor 29, a pull-up circuit 30, and a pull-down circuit 33.

  Level shift circuit 21 includes a resistance element 22, an N-type transistor 23, and a P-type transistor 24 connected in series between a node of third power supply potential V3 (15V) and a node of ground potential GND. The gate of the N-type transistor 23 is connected to its drain (node N22). N-type transistor 23 constitutes a diode element. The gate of P-type transistor 24 is connected to input node N20. The resistance value of the resistance element 22 is set to a value sufficiently larger than the conduction resistance values of the transistors 23 and 24.

When the potential (gradation potential) of the input node N20 is VI, the threshold voltage of the P-type transistor is VTP, and the threshold voltage of the N-type transistor is VTN, the source of the P-type transistor 24 (node N23) The potential V23 and the potential V22 of the drain (node N22) of the N-type transistor 23 are expressed by the following equations (1) and (2), respectively.
V23 = VI + | VTP | (1)
V22 = VI + | VTP | + VTN (2)
Therefore, the level shift circuit 21 outputs a potential V22 obtained by shifting the level of the input potential VI by | VTP | + VTN.

  Level shift circuit 25 includes an N-type transistor 26, a P-type transistor 27, and a resistance element 28 connected in series between the node of fourth power supply potential V4 (5V) and fifth power supply potential V5 (-10V). The gate of N-type transistor 26 is connected to input node N20. The gate of P-type transistor 27 is connected to its drain (node N27). The P-type transistor 27 constitutes a diode element. The resistance value of the resistance element 28 is set to a value sufficiently larger than the conduction resistance values of the transistors 26 and 27.

The potential V26 of the source (node N26) of the N-type transistor 26 and the potential V27 of the drain (node N27) of the P-type transistor 27 are represented by the following equations (3) and (4), respectively.
V26 = VI-VTN (3)
V27 = VI−VTN− | VTP | (4)
Therefore, the level shift circuit 25 outputs a potential V27 obtained by shifting the level of the input potential VI by −VTN− | VTP |.

  Capacitor 29 is connected between output node N22 of level shift circuit 21 and output node N27 of level shift circuit 25. Capacitor 29 transmits the potential change of node N22 to node N27 and transmits the potential change of node N27 to node N22.

  Pull-up circuit 30 includes an N-type transistor 31 and a P-type transistor 32 connected in series between the node of sixth power supply potential V6 (15V) and output node N30. A load capacitance (parasitic capacitance of the data line 6) 36 is connected to the output node N30. The gate of N-type transistor 31 receives output potential V22 of level shift circuit 21. The gate of the P-type transistor 32 is connected to its drain. P-type transistor 30 constitutes a diode element. Since the sixth power supply potential V6 is set so that the N-type transistor 31 operates in the saturation region, the N-type transistor 31 performs a so-called source follower operation.

For convenience of explanation, it is assumed that the drain (node N30 ′) of the P-type transistor 32 and the output node N30 are non-conductive as shown in FIG. The potential V31 of the source (node N31) of the N-type transistor 31 and the potential V30 ′ of the drain (node N30 ′) of the P-type transistor 32 are represented by the following equations (5) and (6), respectively.
V31 = V22−VTN = VI + | VTP | (5)
V30 ′ = V31− | VTP | = VI (6)
Returning to FIG. 4, the pull-down circuit 33 includes a P-type transistor 35 and an N-type transistor 34 connected in series between the node of the seventh power supply potential V7 (−10 V) and the output node N30. The gate of P-type transistor 35 receives output potential V27 of level shift circuit 25. The gate of the N-type transistor 34 is connected to its drain. N-type transistor 34 constitutes a diode element. Since the seventh power supply potential V7 is set so that the P-type transistor 35 operates in the saturation region, the P-type transistor 35 performs a so-called source follower operation.

For convenience of explanation, it is assumed that the drain (node N30 ″) of the N-type transistor 34 and the output node N30 are in a non-conductive state as shown in FIG. The potential V34 of N34) and the potential V30 ″ of the drain (node N30 ″) of the N-type transistor 34 are expressed by the following equations (7) and (8), respectively.
V34 = V27 + | VTP | = VI−VTN (7)
V30 ″ = V34 + VTN = VI (8)
Equations (7) and (8) indicate that the node of the sixth power supply potential V6 and the seventh power supply potential even when the drain of the P-type transistor 32 (node N30 ′) and the drain of the N-type transistor 34 (node N30 ″) are connected. This indicates that no current flows between the node V7 and the potential VO of the output node N30 is the same as the potential VI of the input node N20, so that the resistance values of the resistance elements 22 and 28 are made sufficiently large. If so, the through current becomes extremely small in the steady state where VO = VI.

FIG. 6 is a time chart for explaining the AC operation (operation in the transition state) of the drive circuit 20. In FIG. 6, it is assumed that VI = VL in the initial state. As a result, V22, V27, and VO are as follows.
V22 = VL + | VTP | + VTN
V27 = VL- | VTP | -VTN
VO = VL
When VI rises from VL to VH at time t1, V22, V27, and VO are as follows after a predetermined time has elapsed.
V22 = VH + | VTP | + VTN
V27 = VH− | VTP | −VTN
VO = VH
In the process of this level change, the following operations are performed. In the level shift circuit 25, when the input potential VI rises from VL to VH at time t1, the driving capability of the N-type transistor 26 increases and the potential V26 of the node N26 rises rapidly. As a result, the source-gate voltage of the P-type transistor 27 increases, the drive capability of the P-type transistor 27 also increases, and the potential V27 of the node N27 rises rapidly.

  When the potential V27 of the node N27 rises rapidly, the potential V22 of the node N22 rises rapidly by VH−VL via the capacitor 29 due to capacitive coupling. In response to this, the potential VO of the output node N30 is also rapidly raised from VL to VH.

  Further, when the input potential VI falls from VH to VL at time t2, the driving capability of the P-type transistor 24 increases and the potential V23 of the node N23 rapidly decreases. As a result, the gate-source voltage of the N-type transistor 23 increases, the drive capability of the N-type transistor 23 also increases, and the potential V22 of the node N22 rapidly decreases.

  When the potential V22 of the node N22 rapidly decreases, the potential V27 of the node N27 rapidly decreases by VH−VL through the capacitor 29 due to capacitive coupling. In response to this, the potential VO of the output node N30 is also rapidly lowered from VH to VL.

  In the first embodiment, no through current flows through the pull-up circuit 30 and the pull-down circuit 33 in the steady state, and the resistance values of the resistance elements 22 and 28 are sufficiently higher than the conduction resistance values of the transistors 23, 24, 26, and 27. By doing so, the through current of the level shift circuits 21 and 25 can also be reduced, so that the direct current can be reduced. In addition, since the capacitor 29 is provided, it is possible to respond quickly to changes in the input potential VI.

  Hereinafter, various modified examples will be described. The drive circuit 36 of FIG. 7 is obtained by removing the capacitor 29 from the drive circuit 20 of FIG. When the capacitance value of the load capacitor 36 is relatively small, the dimensions of the transistors 23, 24, 26, 27, 31, 32, 34, and 35 can be reduced. When the dimensions of the transistors 23, 27, 31, and 35 are reduced, the gate capacitances of the transistors 23, 27, 31, and 35 are reduced, and the parasitic capacitances of the nodes N22 and N27 are reduced. Therefore, even if the capacitor 29 is not provided, the potentials V22 and V27 of the nodes N22 and N27 can be raised and lowered by charging and discharging performed through the resistance elements 22 and 28. In this modified example, since the capacitor 29 is removed, the area occupied by the circuit can be reduced.

  The drive circuit 37 of FIG. 8 is obtained by removing the diode-connected transistors 23, 27, 32, and 34 from the drive circuit 20 of FIG. The output potential VO is VO = VI + | VTP | −VTN. However, if | VTP | ≈VTN, VO≈VI. Alternatively, if the value of | VTP | −VTN is taken into consideration as an offset value, it can be used similarly to the drive circuit 20 of FIG. In this modification, the transistors 23, 27, 32, and 34 are removed, so that the area occupied by the circuit can be reduced.

  The drive circuit 38 of FIG. 9 is obtained by removing the capacitor 29 from the drive circuit 37 of FIG. When the capacitance value of the load capacitor 36 is relatively small, the dimensions of the transistors 24, 26, 31, and 35 can be reduced, and the parasitic capacitances of the nodes N22 and N27 can be reduced. Therefore, even if the capacitor 29 is not provided, the potentials V22 and V27 of the nodes N22 and N27 can be raised and lowered by charging and discharging performed through the resistance elements 22 and 28. In this modified example, since the capacitor 29 is removed, the area occupied by the circuit can be further reduced.

[Embodiment 2]
In the first embodiment, it is assumed that the threshold voltages of the transistors having the same polarity are all the same, but in reality, the threshold voltages of the transistors may vary due to variations in manufacturing conditions. . When the threshold voltage of the transistor varies, VI = VO is not satisfied. In the second embodiment, this problem is solved.

  FIG. 10 is a circuit diagram showing the configuration of the level shift circuit 40 of the drive circuit according to the second embodiment of the present invention, and is compared with the level shift circuit 21 of FIG. Referring to FIG. 10, level shift circuit 40 is different from level shift circuit 21 in FIG. 4 in that N-type transistor 23 and P-type transistor 24 have fuses 41.1 to 41. m (where m is a natural number), N-type transistors 42.0 to 42. m and P-type transistors 43.0-43. It is a point that is replaced by m.

  Each of fuses 41.1 to 41m is formed of an aluminum wiring or the like used to connect transistors. Fuses 41.1 to 41. One electrode of m is both connected to the node N22.

  N-type transistors 42.0 to 42. The sum of the gate widths of m is set to be the same as the gate width of the N-type transistor 23 in FIG. N-type transistor 42.0 has its gate and drain connected to node N22. N-type transistors 42.1 to 42. m gate and drain are respectively connected to fuses 41.1 to 41. It is connected to the other electrode of m. N-type transistors 42.0 to 42. Each of m constitutes a diode element.

  P-type transistors 43.0 to 43. The sum of the gate widths of m is set to be the same as the gate width of the P-type transistor 24 of FIG. P-type transistors 43.0 to 43. m represents N-type transistors 42.0 to 42. Connected between the source of m and the node of ground potential GND, both gates receive input potential VI.

  As described in the first embodiment, the potential V22 of the node N22 is almost the same as that of the transistors 42.0 to 42. m, 43.0-43. It is determined by the threshold voltage of m. However, when the resistance value between the node N22 and the node of the ground potential GND is increased with respect to the resistance value of the resistance element 22, the potential V22 of the node N22 slightly increases accordingly. Therefore, the fuses 41.1 to 41. By cutting an appropriate number of fuses of m, the potential V22 of the node N22 can be slightly increased, and the transistors 42.0 to 42. m, 43.0-43. Even when the absolute value of the threshold voltage of m is smaller than the design value, the potential V22 of the node N22 can be corrected.

  In the second embodiment, both the N-type transistor 23 and the P-type transistor 24 are divided into m + 1 pieces. However, only one of the N-type transistor 23 and the P-type transistor 24 may be divided into m + 1 pieces. One of the N-type transistor 23 and the P-type transistor 24 may be divided into m + 1 pieces, and the other may be divided into two pieces, for example. Specifically, the P-type transistors 43.1 to 43. m source is short-circuited, and P-type transistors 43.1 to 43. m may be one P-type transistor. In addition, fuses 41.1 to 41. m are N-type transistors 42.1 to 42.m, respectively. m source and P-type transistors 43.1 to 43. and n-type transistors 42.1 to 42.n. The source of m is short-circuited and N-type transistors 42.1 to 42.42. m may be one N-type transistor.

[Embodiment 3]
FIG. 11 is a circuit diagram showing the configuration of the level shift circuit 45 of the drive circuit according to the third embodiment of the present invention, and is a diagram compared with the level shift circuit 25 of FIG. Referring to FIG. 11, level shift circuit 45 is different from level shift circuit 25 of FIG. 4 in that N-type transistor 26 and P-type transistor 27 have fuses 46.1 to 46. m, N-type transistor 47.0 to 47. m and P-type transistors 48.0-48. It is a point that is replaced by m.

  Fuses 46.1 to 46. Each m is formed of an aluminum wiring or the like used to connect the transistors. Fuses 46.1 to 46. One electrode of m is both connected to the node of the fourth power supply potential V4.

  N-type transistor 47.0 to 47. The sum of the gate widths of m is set to be the same as the gate width of the N-type transistor 26 of FIG. The drain of N-type transistor 47.0 is connected to the node of fourth power supply voltage V4, and the gate thereof receives input potential VI. N-type transistors 47.1 to 47. m drains are fuses 46.1 to 46, respectively. Both are connected to the other electrode of m, and their gates receive the input potential VI.

  P-type transistor 48.0-48. The sum of the gate widths of m is set to be the same as the gate width of the P-type transistor 27 of FIG. P-type transistor 48.0-48. m represents N-type transistors 47.0 to 47. The source of m is connected between the node N27 and their gates are connected to the node N27. P-type transistor 48.0-48. Each of m constitutes a diode element.

  As described in the first embodiment, the potential V27 of the node N27 is almost the same as that of the transistors 47.0 to 47. m, 48.0-48. It is determined by the threshold voltage of m. However, when the resistance value between the node of the fourth power supply potential V4 and the node N27 is increased with respect to the resistance value of the resistance element 28, the potential V27 of the node N27 slightly decreases accordingly. Accordingly, the fuses 46.1 to 46. By cutting an appropriate number of fuses of m, the potential V27 of the node N27 can be slightly decreased, and the transistors 47.0 to 47. m, 48.0-48. Even when the absolute value of the threshold voltage of m is smaller than the design value, the potential V27 of the node N27 can be corrected.

  In the third embodiment, both the N-type transistor 26 and the P-type transistor 27 are divided into m + 1 pieces. However, only one of the N-type transistor 26 and the P-type transistor 27 may be divided into m + 1 pieces. One of the N-type transistor 26 and the P-type transistor 27 may be divided into m + 1 pieces, and the other may be divided into two pieces, for example. Specifically, the P-type transistors 48.1 to 48. of FIG. m source is short-circuited and P-type transistors 48.1 to 48. m may be one P-type transistor. In addition, fuses 41.1 to 41. m is an N-type transistor 47.1 to 47. m source and P-type transistors 48.1 to 48. m, and N-type transistors 47.1 to 47. m source is short-circuited and N-type transistors 47.1 to 47. m may be one N-type transistor.

  Needless to say, the level shift circuits 21 and 25 in FIG. 4 may be replaced with the level shift circuits 40 and 45, respectively, by combining the second and third embodiments.

[Embodiment 4]
FIG. 12 is a circuit diagram showing the configuration of the level shift circuit 50 of the drive circuit according to the fourth embodiment of the present invention, and is a diagram compared with the level shift circuit 21 of FIG. Referring to FIG. 12, level shift circuit 50 is different from level shift circuit 21 in FIG. 4 in that resistance element 22 has resistance elements 51.0 to 51. i (where i is a natural number) and fuses 52.1-52. It is a point that is replaced by i.

  Resistance element 51.0-51. The sum of the resistance values of i is set to be almost the same as the resistance value of the resistance element 22 of FIG. Resistance element 51.0-51. i is connected in series between the node of the third power supply potential V3 and the node N22.

  Fuses 52.1 to 52. i is formed of an aluminum wiring or the like used to connect the transistors. Fuses 52.1 to 52. i represents resistance elements 51.1 to 51. i connected in parallel.

  As described in the first embodiment, the potential V22 of the node N22 is almost determined by the threshold voltages of the transistors 23 and 24. However, when the resistance value between the node of the third power supply potential V3 and the node N22 is increased with respect to the conduction resistance values of the transistors 23 and 24, the potential V22 of the node N22 slightly decreases accordingly. Therefore, the fuses 52.1 to 52. By cutting an appropriate number of fuses of i, the potential V22 of the node N22 can be slightly lowered, and even when the absolute value of the threshold voltage of the transistors 23 and 24 is higher than the design value, the node N22 Can be corrected.

[Embodiment 5]
FIG. 13 is a circuit diagram showing a configuration of a level shift circuit 55 of the drive circuit according to the fifth embodiment of the present invention, and is compared with the level shift circuit 25 of FIG. Referring to FIG. 13, level shift circuit 55 is different from level shift circuit 25 in FIG. 4 in that resistance element 28 has resistance elements 56.0 to 56. i and fuses 57.1-57. It is a point that is replaced by i.

  Resistance element 56.0-56. The sum of the resistance values of i is set to be almost the same as the resistance value of the resistance element 28 of FIG. Resistance element 56.0-56. i is connected in series between the node N27 and the node of the fifth power supply potential V5.

  Fuses 57.1 to 57. i is formed of an aluminum wiring or the like used to connect the transistors. Fuses 57.1 to 57. i represents resistance elements 56.1 to 56, respectively. i connected in parallel.

  As described in the first embodiment, the potential V27 of the node N27 is almost determined by the threshold voltages of the transistors 26 and 27. However, when the resistance value between the node N27 and the node of the fifth power supply potential V5 is increased with respect to the conduction resistance values of the transistors 26 and 27, the potential V22 of the node N22 slightly increases accordingly. Therefore, the fuses 57.1 to 57. By cutting an appropriate number of fuses of i, the potential V27 of the node N27 can be slightly increased, and even if the absolute value of the threshold voltage of the transistors 26 and 27 is higher than the design value, the node The potential V22 of N22 can be corrected.

  Needless to say, the level shift circuits 21 and 25 in FIG. 4 may be replaced with the level shift circuits 50 and 55, respectively, by combining the fourth and fifth embodiments.

  In the above first to fifth embodiments, the field effect transistor may be a MOS transistor or a TFT (thin film transistor). The resistance element may be formed of a refractory metal, an impurity diffusion layer, or a field effect transistor for reducing the occupied area. Further, the above driving circuit serves as an analog buffer for controlling the potential of the output node so as to be the same potential as the input analog potential as well as transmitting the gradation potential in the liquid crystal display device and other devices. Needless to say, it can be used.

[Embodiment 6]
As the characteristics of the drive circuit, it is ideal that the input potential VI and the output potential VO are equal as shown by the characteristic line A in FIG. However, the characteristics of the drive circuits shown in the first to fifth embodiments are as shown by the characteristic line B in FIG. 14, and the difference ΔV between the ideal value and the actual value of VO increases as VI increases.

The reason for this is as follows. In the level shift circuit 21 ′ shown in FIG. 15, when the resistance value of the resistance element 22 is R, the value of the current flowing through the resistance element 22 and the P-type transistor 24 is i, and the current amplification factor of the P-type transistor 24 is β, Expressions (9) and (10) hold.
V22 = VDD-Ri (9)
i = (VI−VTP−V22) ² β / 2 (10)
Here, assuming that Rβ / 2 = K, V22 is expressed by the following equation (11).

  From this equation (11), it can be seen that the difference between the ideal value VI-VTP of V22 and the actual value increases as VI increases. For this reason, the difference ΔV between the ideal value of V4 and the actual value also increases as VI increases.

In order to solve this problem, in the sixth embodiment, the resistance element 22 is replaced with a constant current source 62 as shown in FIG. In the level shift circuit of FIG. 16, the following equation (12) is established.
i = (VI−VTB−V22) ² β / 2 (12)
The following equation (13) is derived from this equation (12).

  Therefore, in the level shift circuit of FIG. 16, the difference between the ideal value VI-VTP of V22 and the actual value is constant regardless of VI. Also, by making the value of β sufficiently larger than the constant current value i, VO can be made substantially equal to the ideal value VI-VTP. Hereinafter, the drive circuit 60 of the sixth embodiment will be specifically described.

  FIG. 17 is a circuit diagram showing a configuration of drive circuit 60 according to the sixth embodiment of the present invention. Referring to FIG. 17, drive circuit 60 is different from drive circuit 20 in FIG. 4 in that level shift circuits 21 and 25 are replaced with level shift circuits 61 and 63, respectively. The level shift circuit 61 replaces the resistance element 22 of the level shift circuit 21 with a constant current source 62, and the level shift circuit 63 replaces the resistance element 28 of the level shift circuit 25 with a constant current source 64.

  As shown in FIG. 18, constant current source 62 includes P-type transistors 65 and 66 and a resistance element 67. P-type transistor 65 is connected between a line of third power supply voltage V3 and node N22, and P-type transistor 66 and resistance element 67 are connected in series between a line of third power supply potential 3 and a line of ground potential GND. Is done. The gates of P-type transistors 65 and 66 are both connected to the drain of P-type transistor 66. P-type transistors 65 and 66 constitute a current mirror circuit. A constant current having a value corresponding to the resistance value of the resistance element 67 flows through the P-type transistor 66 and the resistance element 67, and a constant current having a value corresponding to the value of the constant current flowing through the P-type transistor 66 is supplied to the P-type transistor 65. Flowing. One electrode of the resistance element 67 is connected to the ground potential GND line, but is lower than the potential obtained by subtracting the absolute value | VTP | of the threshold voltage of the P-type transistor 66 from the third power supply potential V3. One electrode of the resistance element 67 may be connected to the power supply potential line. Instead of the transistors 65 and 66 and the resistance element 67 as a constant current source, a depletion type transistor having a gate and a source connected to each other may be provided between the line of the third power supply potential V3 and the node N22.

  Constant current source 64 includes a resistance element 68 and N-type transistors 69 and 70. Resistance element 68 and N-type transistor 69 are connected in series between a line of fourth power supply potential V4 and a line of fifth power supply potential V5, and N-type transistor 70 is connected between node N27 and a line of fifth power supply potential V5. Connected to. The gates of N-type transistors 69 and 74 are both connected to the drain of N-type transistor 69. N-type transistors 69 and 70 constitute a current mirror circuit. A constant current having a value corresponding to the resistance value of the resistance element 68 flows through the resistance element 68 and the N-type transistor 69, and a constant current having a value corresponding to the value of the constant current flowing through the N-type transistor 69 is supplied to the N-type transistor 70. Flowing. One electrode of the resistance element 68 is connected to the fourth power supply potential V4. However, a line of another power supply potential higher than the potential obtained by adding the threshold voltage VTN of the N-type transistor 69 to the fifth power supply potential V5. One electrode of the resistance element 68 may be connected to the first electrode. Instead of the transistors 69 and 70 and the resistance element 68 as a constant current source, a depletion type transistor having a gate and a source connected to each other may be provided between the line of the fifth power supply potential V5 and the node N27. Since other configurations and operations are the same as those of drive circuit 20 in FIG. 4, description thereof will not be repeated.

  In the sixth embodiment, since the resistance elements 22 and 28 of the drive circuit 20 of FIG. 4 are replaced by the constant current sources 62 and 64, respectively, an output potential VO equal to the input potential VI is obtained regardless of the value of the input potential VI. be able to.

  Hereinafter, various modifications of the sixth embodiment will be described. The drive circuit 71 in FIG. 19 is obtained by removing the capacitor 29 from the drive circuit 60 in FIG. This modified example is effective when the capacity value of the load capacity 36 is relatively small. In this modified example, since the capacitor 29 is removed, the area occupied by the circuit can be reduced.

  The drive circuit 72 in FIG. 20 is obtained by removing the N-type transistors 23 and 34 and the P-type transistors 27 and 32 from the drive circuit 60 in FIG. In this modification, the transistors 23, 27, 32, and 34 are removed, so that the area occupied by the circuit can be reduced. However, the output potential VO is VO = VI + | VTP | −VTN.

  The drive circuit 73 of FIG. 21 is obtained by removing the capacitor 29 from the drive circuit 72 of FIG. This modified example is effective when the capacity value of the load capacity 36 is relatively small. In this modified example, since the capacitor 29 is removed, the area occupied by the circuit can be reduced.

[Embodiment 7]
For example, in the drive circuit 20 of FIG. 4, when charging and discharging the load capacitor 36, each of the transistors 31, 32, 34, and 35 performs a so-called source follower operation. At this time, as the output potential VO approaches the input potential VI, the gate-source voltage of each of the transistors 31, 32, 34, and 35 decreases, and the current drive capability of the transistors 31, 32, 34, and 35 decreases. For the transistors 32 and 34, it is possible to prevent the driving capability from being lowered by increasing the gate electrode width. However, if the gate electrode width of the transistors 31 and 35 is increased, the gate capacitance increases, The operating speed will decrease. In the seventh embodiment, this problem can be solved.

  FIG. 22 is a circuit diagram showing a configuration of drive circuit 75 according to the seventh embodiment of the present invention. Referring to FIG. 22, drive circuit 75 is obtained by adding capacitors 76 and 77 to drive circuit 71 in FIG. One electrode of capacitor 76 receives boost signal φB, and the other electrode is connected to node N22. One electrode of capacitor 77 receives complementary signal / φB of boosted signal φB, and the other electrode is connected to node N27.

  FIG. 23 is a time chart showing the operation of the drive circuit 75 shown in FIG. In FIG. 23, for easy understanding, the transition times of the potentials V22 and V27 of the nodes N22 and N27 and the output potential VO are shown to be longer than actual. When input potential VI rises from "L" level VL to "H" level VH at time t1, each of potentials V22, V27, and VO gradually rises. As described above, each of the potentials V22, V27, and VO rises relatively quickly in the period of potential change, but the rising speed becomes slower as it approaches the final level.

  At time t2 after elapse of a predetermined time from time t1, boost signal φB is raised to “H” level and signal / φB is lowered to “L” level. When signal φB is raised to “H” level, potential V22 at node N22 rises by a predetermined voltage ΔV1 due to capacitive coupling via capacitor 76. When signal / φB falls to “L” level, potential V27 of node N27 is lowered by a predetermined potential ΔV2 due to capacitive coupling through capacitor 77. At this time, the operation of outputting the “H” level VH to the output node N30 is performed, and the conduction resistance value of the N-type transistor 31 is lower than the conduction resistance value of the P-type transistor 35. The level raising action works more strongly than the level lowering action by V27, and the output potential VO rises more rapidly from time t2 (when V22 is not boosted, it becomes as shown by a broken line).

  The boosted potential V22 drops to VI + | VTP | + VTN as a current flows from the node N22 to the ground potential GND line through the transistors 23 and 24. Further, the lowered potential V27 rises to VI− | VTP | −VTN as a current flows from the line of the fourth power supply voltage V4 to the node N27 via the transistors 26 and 27.

  At time t3, boost signal φB is lowered to “L” level and signal / φB is raised to “H” level. When signal φB falls to “L” level, potential V22 of node N22 is lowered by a predetermined voltage ΔV1 due to capacitive coupling via capacitor 76. When signal / φB is raised to “H” level, potential V27 of node N27 rises by a predetermined voltage ΔV2 due to capacitive coupling through capacitor 77. Even if V22 decreases by ΔV1, the pull-up circuit 30 does not have the ability to decrease the output potential VO, and even if V27 increases by ΔV2, the pull-down circuit 33 does not have the ability to increase the output potential VO. VO does not change.

  The lowered potential V22 rises to VI + | VTP | + VTN when a current flows from the third power supply potential V3 line into the node N22 via the P-type transistor 65. However, since the current driving capability of the P-type transistor 65 is set to be small for reducing power consumption, the time required for the potential V22 of the node N22 to rise to the original level VI + | VTP | + VTN is V22 It is longer than the time required to drop to that level VI + | VTP | + VTN.

  Further, the boosted potential V27 is reduced to VI−VTN− | VTP | as a current flows from the node N27 to the line of the fifth power supply potential V5 through the N-type transistor. However, since the current drive capability of the N-type transistor is set to be small in order to reduce power consumption, the time required for the potential V27 of the node N27 to drop to the original level VI-VTN- | VTP | Is longer than the time required to rise to its level VI-VTN- | VTP |.

  Next, at time t4, when input potential VI falls from "H" level VH to "L" level VL, each of potentials V22, V27, and V4 gradually decreases. Each of the potentials V22, V27, and V4 falls relatively quickly at the initial stage of the potential change, but the descending speed becomes slower as it approaches the final level.

  At time t5 after elapse of a predetermined time from time t4, boost signal φB is raised to “H” level and signal / φB is lowered to “L” level. When signal φB is raised to “H” level, potential V22 at node N22 rises by a predetermined voltage ΔV1 due to capacitive coupling via capacitor 76. When signal / φB falls to “L” level, potential V27 of node N27 is lowered by a predetermined potential ΔV2 due to capacitive coupling through capacitor 77. At this time, the operation of outputting the “L” level VL to the output node N30 is performed, and the conduction resistance value of the P-type transistor 35 is lower than the conduction resistance value of the N-type transistor 31. The level lowering action works more strongly than the level raising action by V22, and the output potential VO decreases more rapidly from time t5 (when V27 is not stepped down, it becomes as shown by a broken line).

  The boosted potential V22 drops to VI + | VTP | + VTN as a current flows from the node N22 to the ground potential GND line through the transistors 23 and 24. Further, the lowered potential V27 rises to VI− | VTP | −VTN as a current flows from the line of the fourth power supply voltage V4 to the node N27 via the transistors 26 and 27.

  At time t6, boost signal φB is lowered to “L” level and signal / φB is raised to “H” level. When signal φB falls to “L” level, potential V22 of node N22 is lowered by a predetermined voltage ΔV1 due to capacitive coupling via capacitor 76. When signal / φB is raised to “H” level, potential V27 of node N27 rises by a predetermined voltage ΔV2 due to capacitive coupling through capacitor 77. Even if ΔV1 decreases, the pull-up circuit 30 does not have the ability to lower the output potential VO, and even if ΔV2 increases, the pull-down circuit 33 does not have the ability to increase the output potential VO, so the output potential VO does not change. .

  The lowered potential V22 rises to VI + | VTP | + VTN when a current flows from the third power supply potential V3 line into the node N22 via the P-type transistor 65. However, since the current driving capability of the P-type transistor 65 is set to be small in order to reduce power consumption, the time required for the potential V22 of the node N22 to rise to the original level VI + | VTP | + VTN is V22 It is longer than the time required to drop to that level VI + | VTP | + VTN.

  Further, the boosted potential V27 drops to VI−VTN− | VTP | due to current flowing out from the node N27 to the line of the fifth power supply potential VO through the N-type transistor 70. However, since the current drive capability of the N-type transistor 70 is set to be small in order to reduce power consumption, the time required for the potential V27 of the node N27 to drop to the original level VI-VTN- | VTP | It is longer than the time required for V22 to rise to its level VI-VTN- | VTP |.

  In the seventh embodiment, the potential V22 of the node N22 is higher than the potential VI + | VTP | + VTN that should originally be reached in response to the rise of the input potential VI from the “L” level VL to the “H” level VH. Since the voltage is boosted to the potential, the rising speed of the output potential VO can be increased. Further, in response to the fall of the input potential VI from the “H” level VH to the “L” level VL, the potential V27 of the node N27 is stepped down to a potential lower than the potential VI− | VTP | −VTN that should be originally reached. Therefore, the descending speed of the output potential VO can be increased. Therefore, the response speed of the drive circuit 75 can be increased.

  FIG. 24 is a circuit diagram showing a configuration of a drive circuit 78 according to a modification of the seventh embodiment. The drive circuit 78 is obtained by removing the transistors 23, 27, 32, and 34 from the drive circuit 75 of FIG. In this modification, since the transistors 23, 27, 32, and 34 are removed, the output potential VO becomes VO = VI + | VTP | −VTN, but the area occupied by the circuit can be reduced.

[Embodiment 8]
FIG. 25 is a circuit diagram showing a configuration of drive circuit 80 according to the eighth embodiment of the present invention. Referring to FIG. 25, drive circuit 80 is obtained by adding P-type transistor 81 and N-type transistor 82 to drive circuit 71 in FIG. P-type transistor 81 is connected between the line of third power supply potential V3 and node N22, and has its gate receiving pull-up signal / φP. N-type transistor 82 is connected between node N27 and the line of fifth power supply potential V5, and has its gate receiving complementary signal φP of pull-up signal / φP.

  The levels of the signals φP and / φP are changed at the same timing as the signals φB and / φB shown in the seventh embodiment. That is, after a predetermined time has elapsed since input signal VI was raised from "L" level VL to "H" level VH, signals / φP and φP are pulsed to "L" level and "H" level, respectively. The P-type transistor 81 and the N-type transistor 82 are turned on in a pulse manner. As a result, the potential V22 of the node N22 rises to the potential obtained by dividing the third power supply potential V3 by the transistor 81 and the transistors 23 and 24, and then becomes the predetermined value VI + | VTP | + VTN. The potential V27 of the node N27 is lowered to a potential obtained by dividing the voltage V4-V5 between the fourth power supply potential V4 and the fifth power supply potential V5 by the transistors 26, 27 and the transistor 82, and then the predetermined value VI. −VTN− | VTP | At this time, as described in the seventh embodiment, the charging operation by the N-type transistor 31 works more strongly than the discharging operation by the P-type transistor 35, and the output potential VO becomes rapidly equal to the input potential VI. When the input potential VI is lowered from the “H” level VH to the “L” level VL, the discharging action by the P-type transistor 35 works more strongly than the charging action by the N-type transistor 31, and the output potential VO is rapidly increased. Is equal to the input potential VI.

In the eighth embodiment, the same effect as in the seventh embodiment can be obtained.
Hereinafter, various modifications of the eighth embodiment will be described. 26 is obtained by removing N-type transistors 23 and 34 and P-type transistors 27 and 32 from drive circuit 80 in FIG. In this modification, since the transistors 23, 27, 32, and 34 are removed, the output potential VO becomes VO = VI + | VTP | −VTN, but the area occupied by the circuit can be reduced.

  The drive circuit 85 of FIG. 27 is obtained by adding an N-type transistor 86 and a P-type transistor 87 to the drive circuit 80 of FIG. N-type transistor 86 is connected between the source of P-type transistor 24 and the line of ground potential GND, and the gate thereof receives pull-up signal / φP. P-type transistor 87 is connected between the line of fourth power supply potential V4 and the drain of N-type transistor 26, and its gate receives complementary signal φP of pull-up signal / φP. In this modified example, since the N-type transistor 86 is turned off when the P-type transistor 81 is turned on, a through current flows from the third power supply potential V3 line to the ground potential GND line via the transistors 81, 23, 24, 86. Can be prevented from flowing. Further, since the P-type transistor 87 becomes non-conductive when the N-type transistor 82 is turned on, a through current flows from the fourth power supply potential V4 line to the fifth power supply potential V5 line through the transistors 87, 26, 27, and 82. It can be prevented from flowing. Therefore, the current consumption of the circuits 61 and 63 can be reduced.

  The drive circuit 88 in FIG. 28 is obtained by removing the N-type transistors 23 and 34 and the P-type transistors 27 and 32 from the drive circuit 85 in FIG. In this modification, the transistors 23, 27, 32, and 34 are removed, so that the output potential VO becomes VO = VI + | VTP | −VTN, but the area occupied by the circuit can be reduced.

  29 applies a signal φP instead of the ground potential GND to the source of the P-type transistor 24 of the drive circuit 80 of FIG. 25, and supplies a signal / φP instead of the fourth power supply potential VO to the drain of the N-type transistor. Is given. In this modified example, since the drain of the P-type transistor 24 is set to the “H” level when the P-type transistor 81 is turned on, it is possible to prevent a through current from flowing through the transistors 81, 23, and 24. Further, since the drain of the N-type transistor 26 is set to the “L” level when the N-type transistor 82 is turned on, it is possible to prevent a through current from flowing through the transistors 26, 27, and 82. Therefore, current consumption of the circuits 61 and 63 can be reduced.

  30 is obtained by removing N-type transistors 23 and 34 and P-type transistors 27 and 32 from drive circuit 90 of FIG. In this modification, since the transistors 23, 27, 32, and 34 are removed, the output potential VO becomes VO = VI + | VTP | −VTN, but the area occupied by the circuit can be reduced.

[Embodiment 9]
FIG. 31 is a circuit diagram showing a configuration of drive circuit 95 according to the ninth embodiment of the present invention. Referring to FIG. 31, drive circuit 95 is different from drive circuit 75 in FIG. 22 in that level shift circuits 61 and 63 are replaced with level shift circuits 96 and 102, respectively.

  The level shift circuit 96 is obtained by adding P-type transistors 97 and 98 and N-type transistors 99 to 101 to the level shift circuit 61. P-type transistor 97 has N-type transistors 99 and 100 and P-type transistor 98 connected in series between a third power supply potential V3 line and a ground potential GND line, and N-type transistor 101 has third power supply potential V3. Connected between the line and node N22. The gate of the P-type transistor 97 is connected to the gate of the P-type transistor 66. Therefore, a constant current having a value corresponding to the value of the constant current flowing through the P-type transistor 66 flows through the transistors 97, 99, 100, and 98. The gates of N-type transistors 99 and 100 are connected to their drains, respectively. Each of N-type transistors 99 and 100 constitutes a diode. The gate of P-type transistor 98 receives input potential VI. The potential V99 of the node between the transistors 97 and 99 is V99 = VI + | VTP | + 2VTN. V99 is applied to the gate of the N-type transistor 101. The N-type transistor 101 charges the node N22 to V99−VTN = VI + | VTP | + VTN.

  The level shift circuit 102 is obtained by adding N-type transistors 103 and 104 and P-type transistors 105 to 107 to the level shift circuit 63. N-type transistor 103, P-type transistors 105 and 106, and N-type transistor 104 are connected in series between the line of fourth power supply potential V4 and the line of fifth power supply potential V5, and P-type transistor 107 is connected to node N27 and 5 connected to the line of the power supply potential V5. The gate of N-type transistor 103 receives input potential VI. The gates of P-type transistors 105 and 106 are connected to their drains, respectively. Each of P-type transistors 105 and 106 constitutes a diode. The gate of the N-type transistor 104 is connected to the gate of the N-type transistor 69. A constant current having a value corresponding to the value of the constant current flowing through the N-type transistor 69 flows through the N-type transistor 104. The potential V106 at the node between the MOS transistors 106 and 104 is V106 = VI−VTN−2 | VTP |. V106 is applied to the gate of the P-type transistor 107. The P-type transistor 107 discharges the node N27 to V106− | VTP | = VI−VTN− | VTP |. Since other configurations and operations are the same as those of drive circuit 75 in FIG. 22, description thereof will not be repeated.

  FIG. 32 is a time chart showing the operation of the drive circuit 95 shown in FIG. 31, and is a diagram compared with FIG. Referring to FIG. 32, in drive circuit 95, node N22 is charged to VI + | VTP | + VTN by transistors 97-101, so that potential V22 at node N22 falls below a predetermined value VI + | VTP | + VTN ( At times t3 and t6), the potential V22 of the node N22 can be rapidly returned to the predetermined value VI + | VTP | + VTN. Further, since the node N27 is discharged to VI-VTN- | VTP | by the transistors 103 to 107, when the potential V27 of the node N27 rises above the predetermined value VI-VTN- | VTP | (time t3, t6) The potential V27 of N27 can be rapidly returned to the predetermined value VI−VTN− | VTP |. Therefore, the response speed of the circuit can be increased.

  FIG. 33 is a circuit diagram showing a modification of the ninth embodiment. The drive circuit 108 is obtained by removing the N-type transistors 23, 34, 100 and the P-type transistors 27, 32, 105 from the drive circuit 95 of FIG. In this modified example, since the transistors 23, 27, 32, 34, 100, and 105 are removed, the output potential VO becomes VO = VI + | VTP | −VTN, but the area occupied by the circuit can be reduced.

[Embodiment 10]
FIG. 34 is a circuit diagram showing a configuration of drive circuit 110 according to the tenth embodiment of the present invention. 34, the drive circuit 110 is different from the drive circuit 95 of FIG. 31 in that the level shift circuits 96 and 102 are replaced with level shift circuits 111 and 112.

  The level shift circuit 111 is obtained by removing the P-type transistors 97 and 98 and the N-type transistor 100 from the level shift circuit 96 and connecting the N-type transistor 99 between the source of the P-type transistor 65 and the node N22. The gate of N-type transistor 99 is connected to the drain of N-type transistor 99 and the gate of N-type transistor 101. The potential V99 of the gates of the N-type transistors 99 and 101 is V99 = VI + | VTP | + 2VTN. The N-type transistor 101 charges the node N22 to V99−VTN = VO + | VTP | + VTN.

  The level shift circuit 112 is obtained by removing the N-type transistors 103 and 104 and the P-type transistor 105 from the level shift circuit 102 and connecting the P-type transistor 106 between the node N27 and the drain of the N-type transistor 70. The gate of P-type transistor 106 is connected to its drain and the gate of P-type transistor 107. The potential V106 of the gates of the P-type transistors 106 and 107 is V106 = VI−VTN−2 | VTP |. P-type transistor 107 discharges node N27 to V106 + | VTP | = VI−VTN− | VTP |. Since other configurations and operations are the same as those of drive circuit 95 in FIG. 31, description thereof will not be repeated.

  In the tenth embodiment, the same effect as in the ninth embodiment can be obtained, and the current flowing from the third power supply potential V3 line to the ground potential GND line via the transistors 97, 99, 100, and 98, and the fourth Since the current flowing from the power supply potential VO line to the fifth power supply potential V5 line through the transistors 103, 105, 106, 104 can be reduced, current consumption can be reduced. Further, since the transistors 97, 98, 100, and 103 to 105 are removed, the area occupied by the circuit can be reduced.

  FIG. 35 is a circuit diagram showing a modification of the tenth embodiment. The drive circuit 113 is obtained by removing the N-type transistors 23 and 34 and the P-type transistors 27 and 32 from the drive circuit 110 of FIG. In this modification, since the transistors 23, 27, 32, and 34 are removed, the output potential VO becomes VO = VI + | VTP | −VTN, but the area occupied by the circuit can be reduced.

[Embodiment 11]
FIG. 36 is a circuit block diagram showing a main portion of a semiconductor integrated circuit device according to the eleventh embodiment of the present invention. 36, this semiconductor integrated circuit device includes j (where j is an integer of 2 or more) drive circuits 115.1-115. j.

  As shown in FIG. 37, the drive circuit 115.1 is obtained by replacing the level shift circuits 61 and 63 of the drive circuit 60 of FIG. 18 with level shift circuits 116 and 117, respectively. The level shift circuit 116 is obtained by removing the P-type transistor 66 and the resistance element 67 from the level shift circuit 61, and the level shift circuit 117 is obtained by removing the resistance element 68 and the N-type transistor 69 from the level shift circuit 63. The gates of transistors 65 and 70 receive bias potentials VBP and VBN, respectively. Other drive circuits 115.2 to 115. Each of j has the same configuration as the drive circuit 115.1.

  Returning to FIG. 36, in this semiconductor integrated circuit device, a P-type transistor 66 and a resistance element 67 for generating a bias potential VBP and a resistance element 68 and an N-type transistor 69 for generating a bias potential VBN are drive circuits. 115.1-115. j is provided in common.

  P-type transistor 66 and resistance element 67 are connected in series between the third power supply potential V3 line and the ground potential GND line, and the gate of P-type transistor 66 is connected to its drain (node N66). Bias potential VBP appears at node N66. A capacitor 118 for stabilizing the bias potential VBP is connected between the node N66 and the ground potential GND line. Drive circuits 115.1 to 115. A constant current having a value corresponding to the constant current flowing through the P-type transistor 66 flows through each P-type transistor 65 of j.

  Resistance element 68 and N-type transistor 69 are connected between the line of fourth power supply potential V4 and the line of fifth power supply potential V5, and the gate of N-type transistor 69 is connected to its drain (node N68). Bias potential VBN appears at node N68. A capacitor 119 for stabilizing the bias potential VBN is connected between the node N68 and the ground potential GND line. Drive potential 115.1-115. A constant current having a value corresponding to the constant current flowing through the N-type transistor 69 flows through each N-type transistor 70 of j.

  In the eleventh embodiment, the same effect as in the sixth embodiment can be obtained, and a circuit for generating bias potentials VBP and VBN is provided as drive circuits 115.1 to 115. j are provided in common, the drive circuits 115.1 to 115.j. The occupied area per j can be small.

[Embodiment 12]
FIG. 38 is a circuit block diagram showing a configuration of drive circuit 120 with an offset compensation function according to the twelfth embodiment of the present invention. 38, the drive circuit 120 with an offset compensation function includes a drive circuit 121, a capacitor 122, and switches S1 to S4. The drive circuit 121 is any one of the drive circuits shown in the first to eleventh embodiments. The capacitor 122 and the switches S1 to S4 are connected to the offset voltage VOF when a potential difference, that is, an offset voltage VOF is generated between the input potential and the output potential of the drive circuit 121 due to variations in the threshold voltage of the transistors of the drive circuit 121. An offset compensation circuit for compensating for the above is configured.

  That is, the switch S1 is connected between the input node N120 and the input node N20 of the drive circuit 121, and the switch S4 is connected between the output node N121 and the output node N30 of the drive circuit 121. Capacitor 122 and switch S2 are connected in series between input node N20 and output node N30 of drive circuit 121. Switch S3 is connected between input node N120 and node N122 between capacitor 122 and switch S2. Each of the switches S1 to S4 may be a P-type transistor, an N-type transistor, or a P-type transistor and an N-type transistor connected in parallel. Each of the switches S1 to S4 is on / off controlled by a control signal (not shown).

  Now, a case where the output potential of the drive circuit 121 is lower than the input potential by the offset voltage VOF will be described. As shown in FIG. 39, in the initial state, all the switches S1 to S4 are turned off. When the switches S1 and S2 are turned on at a certain time t1, the potential V20 of the input node N20 of the drive circuit 121 becomes V20 = VI, and the output potential V30 of the drive circuit 121 and the potential V122 of the node N122 are V30 = V122. = VI-VOF, and the capacitor 122 is charged to the offset voltage VOF.

  Next, when the switches S1 and S2 are turned off at time t2, the offset voltage VOF is held in the capacitor 122. Next, when the switch S3 is turned on at time t3, the potential V122 of the node N122 becomes V122 = VI, and the input potential V20 of the drive circuit 121 becomes V20 = VI + VOF. As a result, the output potential V30 of the drive circuit 121 becomes V30 = V20−VOF = VI, and the offset voltage VOF of the drive circuit 121 is cancelled. Next, when the switch S4 is turned on at time t4, the output potential VO becomes VO = VI and is supplied to the load.

  In the twelfth embodiment, the offset voltage VOF of the drive circuit 121 can be canceled, and the output potential VO and the input potential VI can be matched.

  The switch S4 is not always necessary. However, if the switch S4 is not provided, when the capacitance value of the load capacitor 36 is large, the time from when the switches S1 and S2 are turned on at time t1 until the voltage VOF between the terminals of the capacitor 122 becomes stable becomes longer.

[Embodiment 13]
FIG. 40 is a circuit block diagram showing a configuration of drive circuit 125 with an offset compensation function according to the thirteenth embodiment of the present invention. 40, the drive circuit 125 with an offset compensation function is obtained by adding capacitors 122a, 122b, 126a, 126b and switches S1a to S4a, S1b to S4b to the drive circuit 60 of FIG.

  Switches S1a and S1b are connected between input node N120 and the gates of transistors 24 and 26 (nodes N20a and N20b), respectively. The switches S4a and S4b are connected between the output node N121 and the drains of the transistors 32 and 34 (nodes N30a and N30b), respectively. Capacitor 122a and switch S2a are connected in series between nodes N20a and N30a. Capacitor 122b and switch S2b are connected in series between nodes N20b and N30b. Switch S3a is connected between input node N120 and node N122a between capacitor 122a and switch S2a. Switch 3b is connected between input node N120 and node N122b between capacitor 122b and switch S2b. Capacitors 126a and 126b have one electrodes connected to nodes N30a and N30b, respectively, and the other electrodes receiving reset signal / φR and its complementary signal φR, respectively.

  41 is a time chart showing the operation of the drive circuit 125 with the offset compensation function shown in FIG. The charging circuit composed of the constant current source 62 and the transistors 23, 24, 31, and 32 and the discharging circuit composed of the constant current source 64 and the transistors 26, 27, 34, and 35 have the same operation although there is a difference between charging and discharging. 41, only the operation of the charging circuit will be described. Now, since the threshold voltage VTN of the N-type transistor 31 is VOFa larger than the threshold voltage VTN of the N-type transistor, there is an offset voltage VOFa on the charging circuit side and no offset voltage VOFb on the discharging circuit side. To do.

  In the initial state, the switches S1a to S3a are turned off and the switch S4a is turned on, and the previous potential VI ′ is held at the nodes N20a, N122a, N30a, and N121. When the switches S1a, S2a are turned on at time t1, the potentials V20a, V122a, V30a, VO of the nodes N20a, N122a, N30a, N121 are all equal to the input potential VI. Further, the potential V22 of the node N22 is V22 = VI + | VTP | + VTN. The reason why V20a, V122a, V30a and VO are all equal to VI even though the threshold voltage VTN 'of the N-type transistor 31 is higher than the threshold voltage VTN of the N-type transistor 23 by VOFa is This is because the node N121 is discharged to the input potential VI by the discharge circuit, but is not discharged below it.

  Next, at time t2, the switch S4a is turned off, and the output node N30a of the charging circuit and the output node N30b of the discharging circuit are electrically disconnected. Next, when reset signal / φR falls from "H" level to "L" level at time t3, potentials V30a and V122a of nodes N30a and N122a are stepped down by a predetermined voltage due to capacitive coupling via capacitor 126a. As a result, transistors 31 and 32 become conductive, and potentials V30a and V122a of nodes N30a and N122a rise to VI-VOFa, and capacitor 122a is charged to VOFa.

  After the potentials V30a and V122a of the nodes N30a and N122a are stabilized, when the switches S1a and S2a are turned off at time t4 and further the switch S3a is turned on at time t5, the offset voltage VOFa is added to the input potential VI. The applied potential VI + VOFa is applied to node N20a. As a result, the potential V22 of the node N22 becomes V22 = VI + | VTP | + VTN + VOFa, and the potentials V30a and V122a of the nodes N30a and N122a become the same level as the input potential VI.

  The output potential V30a of the charging circuit changes from time t1 to V30a = VI, but during the period from time t1 to t2, it is only the potential held by the wiring capacitance or the like, and when there is negative noise, V30a is VI-VOF. Will fall to. On the other hand, after time t5, even if there is a negative noise, the transistors 31 and 32 are charged, so V30a is maintained at VI.

  Next, when the switch S3a is turned off at time t6 and further the switch S4a is turned on at time t7, the load capacitor 36 is driven by the drive circuit. When reset signal / φR is raised to “H” level at time t8, the initial state is restored. At time t8, since the output impedance is sufficiently low, the output potential VO hardly changes even when the reset signal / φR is raised to the “H” level. A similar operation is performed on the discharge circuit side, and the output potential VO is maintained at VI.

  FIG. 42 is another time chart showing the operation of the drive circuit 125 with the offset compensation function shown in FIG. The charging circuit composed of the constant current source 62 and the transistors 23, 24, 31, and 32 and the discharging circuit composed of the constant current source 64 and the transistors 26, 27, 34, and 35 have the same operation although there is a difference between charging and discharging. Therefore, only the operation of the discharge circuit will be described with reference to FIG. Now, since the absolute value | VTP ′ | of the threshold voltage of the P-type transistor 35 is larger than the absolute value | VTP | of the threshold voltage of the P-type transistor 27 by VOFb, there is an offset voltage VOFb on the discharge circuit side. It is assumed that there is no offset voltage VOFa on the charging circuit side.

  In the initial state, the switches S1b to S3b are turned off and the switch S4b is turned on, and the previous potential VI ′ is held at the nodes N20b, N122b, N30b, and N121. When the switches S1b and S2b are turned on at time t1, the potentials V20b, V122b, V30b, and VO of the nodes N20b, N122b, N30b, and N121 are all equal to the input potential VI. Further, the potential V27 of the node N27 is V27 = VI− | VTP | −VTN. Although the absolute value | VTP '| of the threshold voltage of the P-type transistor 35 is higher than the absolute value | VTP | of the threshold voltage of the V-type transistor 27 by VOFb, V20b, V122b, V30b, and VO are all The potential equal to VI is because output node N121 is charged to input potential VI by the charging circuit, but is not charged any more.

  Next, at time t2, the switch S4b is turned off, and the output node N30a of the charging circuit and the output node N30b of the discharging circuit are electrically disconnected. Next, when signal φR rises from “L” level to “H” level at time t3, potentials V30b and V122b of nodes N30b and N122b are boosted by a predetermined voltage by capacitive coupling via capacitor 126b. As a result, transistors 34 and 35 become conductive, potentials V30b and V122b of nodes N30b and N122b drop to VI + VOFb, and capacitor 122b is charged to VOFb.

  After the potentials V30b and V122b of the nodes N30b and N122b are stabilized, when the switches S1b and S2b are turned off at time t4 and further the switch S3b is turned on at time t5, the offset voltage VOFb is subtracted from the input potential VI. The potential VI-VOF is applied to the node N20b. As a result, the potential V27 of the node N27 becomes V27 = VI−VTN− | VTP | −VOFb, and the potentials V30b and V122b of the nodes N30b and V122b become the same level as the input potential VI.

  The output potential V30b of the discharge circuit changes from time t1 to V30b = VI, but during the period from time t1 to time t2, it is only the potential held by the wiring capacitance etc., and when there is positive noise, V30b rises to VI + VOFb Resulting in. On the other hand, after time t5, even if there is a positive noise, it is discharged by the transistors 34 and 35, so V30b is maintained at VI.

  Next, when the switch S3b is turned off at time t6 and the switch S4b is turned on at time t7, the load capacitor 36 is driven by the drive circuit. When signal φR falls to “L” level at time t8, the initial state is restored. At this time t8, since the output impedance is low, the output potential V hardly changes even when the signal φR is raised to the “L” level. A similar operation is performed on the discharge circuit side, and the output potential VO is maintained at VI.

  Hereinafter, various modifications of the thirteenth embodiment will be described. 43 is obtained by removing N-type transistors 23 and 34 and P-type transistors 27 and 32 from drive circuit 125 with an offset compensation function in FIG. In this modified example, the area occupied by the circuit can be small.

  The drive circuit 130 with an offset compensation function in FIG. 44 is obtained by replacing the capacitors 126a and 126b of the drive circuit 125 with an offset compensation function in FIG. 40 with an N-type transistor 131a and a P-type transistor 131b, respectively. N-type transistor 131a is connected between the line of eighth power supply potential V8 and node N30a, and has its gate receiving reset signal φR ′. P-type transistor 131b is connected between node N30b and the line of ninth power supply potential V9, and has its gate receiving complementary signal / φR 'of reset signal φR'.

  Normally, the signals φR ′ and / φR ′ are set to the “L” level and the “H” level, respectively, and both the N-type transistor 131a and the P-type transistor 131b are made non-conductive. At time t3 in FIGS. 41 and 42, signal φR ′ is pulsed to “H” level for a predetermined time and signal / φR ′ is pulsed to “L” level for a predetermined time. As a result, the N-type transistor 131a is pulsed and the potential V30a of the node N30a is lowered to the eighth power supply potential V8, and the P-type transistor 131b is pulsed and the potential V30b of the node N30b is the ninth. The power supply potential is raised to V9. Thereafter, in the case described with reference to FIG. 41, the node N30a is charged to VI-VOF, and in the case described with reference to FIG. 42, the node N30b is discharged to VO + VOF. In this modified example, no noise is generated in the output potential VO even at time t8 in FIGS. The pulse widths of the signals φR ′ and / φR ′ are set to the minimum necessary values.

  45 is obtained by adding an offset compensation circuit including capacitors 122a, 122b, 126a, and 126b and switches S1a to S4a and S1b to S4b to the drive circuit 80 of FIG. 41 and 42, signal / φP is pulsed to “L” level and signal φP is pulsed to “H” level. In this modified example, the potentials V22 and V27 of the nodes N22 and N27 reach the predetermined value quickly, so that the operation speed can be increased.

  46 is obtained by removing N-type transistors 23 and 34 and P-type transistors 27 and 32 from drive circuit 132 with an offset compensation function in FIG. In this modified example, the area occupied by the circuit can be small.

  The drive circuit 135 with an offset compensation function in FIG. 47 is obtained by adding an offset compensation circuit including capacitors 122a, 122b, 126a, 126b and switches S1a to S4a, S1b to S4b to the drive circuit 85 with an offset compensation function in FIG. is there. In this modified example, when the signals / φP and φP become the “L” level and the “H” level, respectively, and the transistors 81 and 82 are turned on, the transistors 86 and 87 are turned off at the same time, so that a through current flows. The current consumption can be reduced.

  The drive circuit 136 with an offset compensation function in FIG. 48 is obtained by removing the N-type transistors 23 and 34 and the P-type transistors 27 and 32 from the drive circuit 135 with an offset compensation function in FIG. In this modification, the area occupied by the circuit can be small.

  The drive circuit 140 with an offset compensation function in FIG. 49 is obtained by adding an offset compensation circuit including capacitors 122a, 122b, 126a, 126b and switches S1 to S4a, S1b to S4b to the drive circuit 90 in FIG. In this modification, when the signal / φP is set to “L” level and the P-type transistor 81 is turned on, the drain of the P-type transistor 24 is set to “H” level, and the signal φP is set to “H” level and N Since the drain of the N-type transistor 26 is set to the “L” level when the type transistor 82 is turned on, it is possible to prevent a through current from flowing, and power consumption can be reduced.

  The drive circuit 141 with an offset compensation function in FIG. 50 is obtained by removing the N-type transistors 23 and 34 and the P-type transistors 27 and 32 from the drive circuit 140 with an offset compensation function in FIG. In this modified example, the area occupied by the circuit can be small.

  The drive circuit 145 with an offset compensation function shown in FIG. 51 is obtained by adding an offset compensation circuit including capacitors 122a, 122b, 126a, 126b and switches S1a to S4a, S1b to S4b to the drive circuit 95 with an offset compensation function shown in FIG. is there. 41 and 42, signal .phi.B is pulsed to "H" level and signal /.phi.B is pulsed to "L" level during time t1-t2. In this modified example, the potentials V22 and V27 of the nodes N22 and N27 reach the predetermined value quickly, so that the operation speed can be increased.

  52 is obtained by removing N-type transistors 23, 34, and 100 and P-type transistors 27, 32, and 105 from drive circuit 145 with an offset compensation function in FIG. In this modified example, the area occupied by the circuit can be small.

  The drive circuit 150 with an offset compensation function in FIG. 53 is obtained by adding an offset compensation circuit including capacitors 122a, 122b, 126a, 126b and switches S1 to S4a, S1b to S4b to the drive circuit 110 in FIG. 41 and 42, signal .phi.B is pulsed to "H" level and signal /.phi.B is pulsed to "L" level during time t1-t2. In this modified example, the potentials V22 and V27 of the nodes N22 and N27 reach the predetermined value quickly, so that the operation speed can be increased.

  54 is obtained by removing N-type transistors 23 and 34 and P-type transistors 27 and 32 from drive circuit 150 with an offset compensation function in FIG. In this modified example, the area occupied by the circuit can be small.

[Embodiment 14]
FIG. 55 is a circuit diagram showing a configuration of a drive circuit 155 with an offset compensation function according to the fourteenth embodiment of the present invention. 55, the drive circuit 155 with an offset compensation function is different from the drive circuit 145 with an offset compensation function in FIG. 51 in that a switch S5 and a capacitor 156 are added, and the boost signals φB and / φB are boosted respectively. This is the point that the signals φB1, / φB1 are replaced.

  Switch S5 is connected between a node between switches S4a and S4b and output node N121. Capacitor 156 is connected between a node between switches S4a and S4b and a line of ground potential GND. The capacitance value of the capacitor 156 is set smaller than the capacitance value of the load capacitor 36.

  FIG. 56 is a time chart showing the operation of drive circuit 155 with an offset compensation function shown in FIG. 55, and is a diagram compared with FIG. Here, only the operation on the charging circuit side will be described. Referring to FIG. 56, switch S5 is in the OFF state until time t9, and load capacitor 36 is electrically disconnected. Therefore, for example, potentials V22, V30a, and V122a are quickly supplied from time t1 to t2. The input potential VI is reached.

  When the switch S5 is turned on at time t9, the potential V156 between the switches S4a and S4b changes according to the potential VO of the data line connected to the output node N121. FIG. 56 shows a case where the potential VO of the data line is lower than V156. After the potential V156 decreases at time t9, current is supplied by the transistors 31 and 32 and the potential V156 gradually increases. Next, at time t10, the signal φB1 rises from the “L” level to the “H” level, the potential V22 of the node N22 rises in a pulse manner, the current flowing through the N-type transistor 31 increases, and the potential V156 = VO rapidly Reaches the input potential VI.

  FIG. 57 is another time chart showing the operation of drive circuit 155 with an offset compensation function shown in FIG. 55, and is compared with FIG. Here, only the operation on the discharge circuit side will be described. Referring to FIG. 57, switch S5 is in the OFF state until time t9, and load capacitor 36 is electrically disconnected. Therefore, for example, potentials V27, V30b, and V122b are quickly supplied from time t1 to t2. The input potential VI is reached.

  When the switch S5 is turned on at time t9, the potential V156 between the switches S4a and S4b changes according to the potential VO of the data line connected to the output node N121. FIG. 57 shows a case where the potential VO of the data line is higher than V156. After the potential V156 rises at time t9, current is discharged by the transistors 34 and 35 and the potential V156 gradually decreases.

  Next, at time t10, the signal / φB1 falls from the “H” level to the “L” level, the potential V27 of the node N27 falls in a pulse manner, the current flowing through the P-type transistor 35 increases, and the potential V156 = VO becomes The input potential VI is rapidly reached.

  In the fourteenth embodiment, a high operating speed can be obtained even when the capacitance value of the load capacitor 36 is large.

[Embodiment 15]
FIG. 58 is a circuit diagram showing a configuration of drive circuit 157 with an offset compensation function according to the fifteenth embodiment of the present invention. Referring to FIG. 58, drive circuit 157 with an offset compensation function is different from drive circuit 155 with an offset compensation function in FIG. 55 in that capacitor 156 is removed, the on / off timing of switch S5, and This is the timing of the level change of the signals φB1, / φB1.

  59 is a time chart showing an operation of drive circuit 157 with an offset compensation function shown in FIG. Here, it is assumed that threshold voltage VTN ′ of N-type transistor 31 is higher than threshold voltage VTN of N-type transistor 23 by VOF. In the initial state, the switches S1a to S3a, S1b to S3b are turned off and the switches S4a, S4b, and S5 are turned on, and the potentials V30a, V30b, and V20a of the nodes N30a, N30b, and N20a are all the previous input potentials. (VH in the figure).

  At time t1, the switch S5 is turned off, and the node between the switches S30a and S30b and the load capacitor 36 are electrically disconnected. At time t2, the switches S1a, S1b, S2a, S2b are turned on, and the input potential VI is set to the current potential (VL in the figure). As described above, the potentials V30a, V30b, and V20b of the nodes N30a, N30b, and N20b are all VI = VL. Although the threshold voltage VTN 'of the N-type transistor 31 is VOF higher than the threshold voltage VTN of the other N-type transistors, V30a and V30b become VI = VL because the discharge circuit is connected to the node N30a, This is because N30b is discharged to VI = VL, but not below that.

  At time t3, the switches S4a and S4b are turned off, and the charging circuit and the discharging circuit are electrically disconnected. At time t4, reset signal / φR falls from “H” level to “L” level and signal φR rises from “L” level to “H” level. As a result, the potential V30a of the node N30a is stepped down from VL to become VL-VOF, and the potential V30b of the node N30b is stepped up from VL to become VL.

  When the switches S1a, S1b, S2a, s2b are turned off at time t5, and then the switches S3a, S3b are turned on at time t6, the potential V20a of the node N20a becomes VL + VOF, and the offset voltage VOF is canceled. The potential V30a of the node N30a is VI = VL.

  When the switches S3a and S3b are turned off at time t7 and then the switches S4a, S4b and S5 are turned on at time t8, the load capacitor 36 is charged to VH which is the previous potential, so that the node N30a , N30b potentials V30a and V30b once increase and then gradually decrease. At time t9, signal φB1 is raised from “L” level to “H” level, and signal / φB1 is lowered from “H” level to “L” level.

  Thus, the potential V22 of the node N22 is boosted through the capacitor 76, and the potential V27 of the node N27 is stepped down through the capacitor 77. At this time, the operation of outputting the “L” level VL to the output node N121 is performed, and the conduction resistance value of the P-type transistor 35 is lower than the conduction resistance value of the N-type transistor 31, so that the level drop due to V27 The action is stronger than the level raising action by V22, and the potentials V30a, V30b, and VO of the nodes N30a, N30b, and N121 are rapidly lowered to reach VL.

In the fifteenth embodiment, the operating speed can be increased.
[Embodiment 16]
FIG. 60 is a circuit diagram showing a main part of a color liquid crystal display device according to Embodiment 16 of the present invention. In FIG. 60, this color liquid crystal display device is provided with an equalizer + precharge circuit 158 for setting the potential of each data line 6 to the precharge potential VPC before giving the gradation potential to each data line 6.

  The equalizer + precharge circuit 158 includes a switch S6 provided corresponding to each data line 6 and a switch S7 provided corresponding to each two adjacent data lines 6. One terminal of the switch S6 receives the precharge potential VPC, and the other terminal is connected to the corresponding data line 6. The switch S6 is turned on in response to the precharge signal φPC being set to the activation level “H” level. When the switch S6 is turned on, each data line 6 is set to the precharge potential VPC. Switch S7 is connected between two data lines 6, and is turned on in response to equalization signal φEQ being set to the activation level “H” level. When the switch S7 is turned on, the potentials of all the data lines 6 are averaged. After the switches S6 and S7 are turned off, a gradation potential is applied to each data line 6.

  Here, the precharge potential VCP is set to 0V. Since the gradation potential is 0 V to 5 V (see FIG. 3), the drive circuit only needs to charge the data line 6 and does not need to discharge. Therefore, in this color liquid crystal display device, a push type drive circuit is used.

  FIG. 61 is a circuit diagram showing a configuration of the push-type drive circuit 160. In FIG. 61, this push type drive circuit 160 includes a level shift circuit 61, a pull-up circuit 30, and a constant current source 161. The level shift circuit 61 and the pull-up circuit 30 are the same as those shown in FIG.

  That is, level shift circuit 61 includes a constant current source 62, an N-type transistor 23, and a P-type transistor 24 connected in series between a node of third power supply potential V3 (15V) and a node of ground potential GND. The constant current source 62 includes P-type transistors 65 and 66 and a resistance element 67 as shown in FIG. P-type transistor 65 is connected between the node of third power supply potential V3 and the drain (node N22) of N-type transistor 23, and P-type transistor 66 and resistance element 67 are connected to the node of third power supply potential V3 and ground potential GND. Connected in series with other nodes. The gates of P-type transistors 65 and 66 are both connected to the drain of P-type transistor 66. P-type transistors 65 and 66 constitute a current mirror circuit. A constant current having a value corresponding to the resistance value of the resistance element 67 flows through the P-type transistor 66 and the resistance element 67, and a constant current having a value corresponding to the value of the constant current flowing through the P-type transistor 66 is supplied to the P-type transistor 65. Flowing. The gate of the N-type transistor 23 is connected to its drain (node N22). N-type transistor 23 constitutes a diode element. The gate of P-type transistor 24 is connected to input node N20. The current value of the constant current source 62 is set to a minimum value necessary for generating a predetermined threshold voltage in each of the transistors 23 and 24.

  When the potential (gradation potential) of the input node N20 is VI, the threshold voltage of the P-type transistor is VTP, and the threshold voltage of the N-type transistor is VTN, the source of the P-type transistor 24 (node N23) The potential V23 and the potential V22 of the drain (node N22) of the N-type transistor 23 are V23 = VI + | VTP | and V22 = VI + | VTP | + VTN, respectively. Therefore, the level shift circuit 61 outputs a potential V22 obtained by shifting the level of the input potential VI by | VTP | + VTN.

  Pull-up circuit 30 includes an N-type transistor 31 and a P-type transistor 32 connected in series between the node of sixth power supply potential V6 (15V) and output node N30. The gate of N-type transistor 31 receives output potential V22 of level shift circuit 61. The gate of the P-type transistor 32 is connected to its drain. The P-type transistor 32 constitutes a diode element. Since the sixth power supply potential V6 is set so that the N-type transistor 31 operates in the saturation region, the N-type transistor 31 performs a so-called source follower operation.

  Constant current source 161 is connected between output node N30 and the node of ground potential GND. As shown in FIG. 62, constant current source 161 includes N-type transistors 162 and 163 and a resistance element 164. N-type transistor 162 is connected between output node N30 and a node of ground potential GND, and resistance element 164 and N-type transistor 163 are connected in series between a node of sixth power supply potential V6 and a node of ground potential GND. The The gates of N-type transistors 162 and 163 are both connected to the drain of N-type transistor 163. N-type transistors 162 and 163 form a current mirror circuit. A constant current having a value corresponding to the resistance value of the resistance element 164 flows through the resistance element 164 and the N-type transistor 163, and a constant current having a value corresponding to the value of the constant current flowing through the N-type transistor 163 is passed through the N-type transistor 162. Flowing. The current value of the constant current source 161 is set to a minimum value necessary for causing each of the transistors 31 and 32 to generate a predetermined threshold voltage.

  The potential V31 of the source (node N31) of the N-type transistor 31 is V31 = V22−VTN = VI + | VTP |, and the potential VO of the output node N30 is VO = V31− | VTP | = VI.

  In the sixteenth embodiment, it is sufficient to pass a through current having a minimum value necessary for generating a predetermined threshold voltage in each of the transistors 23, 24, 31, and 32. Therefore, the current consumption can be reduced. .

  FIG. 63 is a circuit diagram showing a configuration of push-type drive circuit 165 according to a modification of the sixteenth embodiment. Referring to FIG. 63, drive circuit 165 differs from drive circuit 160 in FIG. 62 in that resistance element 164 is removed and resistance element 67 is shared by two constant current sources 62 and 161. . Resistance element 67 and N-type transistor 163 are connected in series between the source of P-type transistor 66 and the node of ground potential GND. The gate of N-type transistor 163 is connected to its drain. In this modification, it is possible to prevent an offset voltage from being generated due to variations in resistance values of the resistance elements 67 and 164.

  Also, the push-type drive circuit 166 in FIG. 64 is obtained by removing the diode-connected transistors 23 and 32 from the push-type drive circuit 160 in FIG. The output potential VO is VO = VI + | VTP | −VTN. However, if | VTP | ≈VTN, VO≈VI. Alternatively, if the value of | VTP | −VTN is taken into consideration as an offset value, it can be used similarly to the drive circuit 160 of FIG. In this modified example, since the transistors 23 and 32 are removed, the area occupied by the circuit can be reduced.

[Embodiment 17]
In the color liquid crystal display device shown in FIG. 60, if the precharge potential VCP is 5 V, the gradation potential is 0 V to 5 V (see FIG. 3), so the drive circuit only needs to discharge the data line 6 and charge the data. There is no need to do it. Therefore, in this color liquid crystal display device, a pull type driving circuit is used.

  FIG. 65 is a circuit diagram showing a structure of pull-type drive circuit 170 according to the seventeenth embodiment of the present invention. In FIG. 65, the drive circuit 170 includes a level shift circuit 63, a constant current source 171 and a pull-down circuit 33. The level shift circuit 63 and the pull-down circuit 33 are the same as those shown in FIG.

  That is, the level shift circuit 63 includes the N-type transistor 26, the P-type transistor 27, and the constant current connected in series between the node of the fourth power supply potential V4 (5V) and the node of the fifth power supply potential V5 (-10V). Source 64 is included. N-type transistor 26 has its gate receiving potential VI of input node N20. The gate of P-type transistor 27 is connected to its drain (node N27). The P-type transistor 27 constitutes a diode element. The current value of the constant current source 64 is set to a minimum value necessary for generating a predetermined threshold voltage in each of the transistors 26 and 27.

  The potential V26 of the source (node N26) of the N-type transistor 26 is V26 = VI−VTN. The potential V127 of the drain (node N27) of the P-type transistor 27 is V27 = VI−VTN− | VTP |. Therefore, the level shift circuit 63 outputs a potential V27 obtained by shifting the level of the input potential VI by −VTN− | VTP |.

  Constant current source 171 is connected between the node of fourth power supply potential V4 and output node N30. Pull-down circuit 33 includes a P-type transistor 35 and an N-type transistor 34 connected in series between a node of seventh power supply potential V7 (−10 V) and output node N30. The gate of P-type transistor 35 receives output potential V27 of level shift circuit 63. The gate of the N-type transistor 34 is connected to its drain. N-type transistor 34 constitutes a diode element. Since the seventh power supply potential V7 is set so that the P-type transistor 35 operates in the saturation region, the P-type transistor 35 performs a so-called source follower operation. The current value of the constant current source 71 is set to a minimum value necessary for generating a predetermined threshold voltage in each of the transistors 34 and 35.

  The potential V34 of the source (node N34) of the P-type transistor 35 is V34 = V27 + | VTP | = VI−VTN. The potential VO of the output node N30 is VO = V34 + VTN = VI.

  In the seventeenth embodiment, it is sufficient to pass a through current having a minimum value necessary for generating a predetermined threshold voltage in each of the transistors 26, 27, 34, and 35, so that the current consumption can be reduced. .

  FIG. 66 is a circuit diagram showing a configuration of pull-type drive circuit 172 according to a modification of the seventeenth embodiment. Referring to FIG. 66, pull-type drive circuit 172 is obtained by removing diode-connected transistors 27 and 34 from pull-type drive circuit 170 of FIG. The output potential VO is VO = VI + | VTP | −VTN. However, if | VTP | ≈VTN, VO≈VI. Alternatively, if the value of | VTP | −VTN is taken into consideration as an offset value, it can be used in the same manner as the drive circuit 170 of FIG. In this modified example, since the transistors 27 and 34 are removed, the area occupied by the circuit can be reduced.

[Embodiment 18]
FIG. 67 is a circuit diagram showing a configuration of drive circuit 175 according to the eighteenth embodiment of the present invention. 67, the drive circuit 175 is a combination of the push type drive circuit 160 of FIG. 61 and the pull type drive circuit 170 of FIG. The gate of P-type transistor 24 of level shift circuit 61 and the gate of N-type transistor 26 of level shift circuit 63 receive potential VI of input node N20. The drain of the P-type transistor 32 of the pull-up circuit 30 and the drain of the N-type transistor 34 of the pull-down circuit 33 are both connected to the output node N30.

  When the output potential VO is higher than the input potential VI, the transistors 31 and 32 of the pull-up circuit 30 are turned off, and the transistors 34 and 35 of the pull-down circuit 33 are turned on, so that the output potential VO is lowered. When the output potential VO is lower than the input potential VI, the transistors 34 and 35 of the pull-down circuit 33 are turned off, the transistors 31 and 32 of the pull-up circuit 30 are turned on, and the output potential VO rises. Therefore, VO = VI.

  The drive circuit 175 is used as a push-type drive circuit, a pull-type drive circuit, or a push-pull type drive circuit. When the drive circuit 175 is used as a push-type drive circuit, the current drive capability of the transistors 34 and 35 of the pull-down circuit 33 is set to a level sufficiently smaller than the current drive capability of the transistors 31 and 32 of the pull-up circuit 30. The When the drive circuit 175 is used as a pull-type drive circuit, the current drive capability of the transistors 31 and 32 of the pull-up circuit 30 is set to a level sufficiently smaller than the current drive capability of the transistors 34 and 35 of the pull-down circuit 33. The When the drive circuit 175 is used as a push-pull type drive circuit, the current drive capability of the transistors 31 and 32 of the pull-up circuit 30 and the current drive capability of the transistors 34 and 35 of the pull-down circuit 33 are set to the same level.

  Also in the eighteenth embodiment, it is possible to obtain the drive circuit 175 having a small through current and to reduce the power consumption.

  FIG. 68 is a circuit diagram showing a configuration of drive circuit 176 according to a modification of the eighteenth embodiment. Referring to FIG. 68, drive circuit 176 is obtained by removing diode-connected transistors 23, 27, 32, and 34 from drive circuit 170 in FIG. The output potential VO is VO = VI + | VTP | −VTN. However, if | VTP | ≈VTN, VO≈VI. Alternatively, if the value of | VTP | −VTN is taken into consideration as an offset value, it can be used in the same manner as the drive circuit 175 of FIG. In this modification, the transistors 23, 27, 32, and 34 are removed, so that the area occupied by the circuit can be reduced.

  FIG. 69 is a circuit diagram showing a configuration of drive circuit 180 according to another modification of the eighteenth embodiment. 69, the drive circuit 180 is obtained by replacing the level shift circuits 61 and 63 of the drive circuit 175 of FIG. 67 with level shift circuits 181 and 183, respectively. The level shift circuit 181 is obtained by replacing the constant current source 62 of the level shift circuit 61 with a resistance element 182. The level shift circuit 183 is obtained by replacing the constant current source 64 of the level shift circuit 63 with a resistance element 184. The resistance values of the resistance elements 182 and 184 are set to values at which the resistance elements 182 and 184 pass the same current as the constant current sources 62 and 64. In this modified example, the same effect as that of the drive circuit 175 of FIG. 67 can be obtained.

  FIG. 70 is a circuit diagram showing a configuration of drive circuit 185 according to still another modification of the eighteenth embodiment. Referring to FIG. 70, drive circuit 185 differs from drive circuit 175 in FIG. 67 in that constant current source 161 is connected between output node N30 and the node of fifth power supply potential V5, and constant current source 171 is connected. Is connected between the node of the third power supply potential V3 and the output node N30.

  As shown in FIG. 71, the constant current sources 62, 64, 161, and 171 include a resistance element 67, P-type transistors 65, 66, and 189, and N-type transistors 186 to 188. P-type transistor 66, resistance element 67, and N-type transistor 186 are connected in series between the node of third power supply potential V3 and the node of fifth power supply potential V5. The gate of P-type transistor 66 is connected to its drain, and the gate of N-type transistor 186 is connected to its drain. Each of transistors 66 and 186 constitutes a diode element.

  P-type transistor 65 is connected between the node of third power supply potential V 3 and node N 22, and its gate is connected to the gate of P-type transistor 66. P-type transistor 189 is connected between the node of third power supply potential V 3 and output node N 30, and its gate is connected to the gate of P-type transistor 66. P-type transistors 66, 65, and 189 constitute a current mirror circuit. A current having a value corresponding to the current flowing through the P-type transistor 66 flows through each of the P-type transistors 65 and 189. P-type transistors 65 and 189 constitute constant current sources 62 and 171, respectively.

  N-type transistor 187 is connected between the node of fifth power supply potential V 5 and node N 27, and its gate is connected to the gate of N-type transistor 186. N-type transistor 188 is connected between the node of fifth power supply potential V 5 and output node N 30, and its gate is connected to the gate of N-type transistor 186. N-type transistors 186 to 188 constitute a current mirror circuit. A current having a value corresponding to the current flowing through the N-type transistor 186 flows through each of the N-type transistors 187 and 188. N-type transistors 187 and 188 constitute constant current sources 64 and 161, respectively. Since other configurations and operations are the same as those of drive circuit 175 in FIG. 67, description thereof will not be repeated. In this modified example, the same effect as that of the drive circuit 175 of FIG. 67 can be obtained.

[Embodiment 19]
FIG. 72 is a circuit block diagram showing a configuration of a drive circuit 190 with an offset compensation function according to the nineteenth embodiment of the present invention. In FIG. 72, the drive circuit 190 with an offset compensation function is obtained by adding a capacitor 122 and switches S1 to S4 to the push type drive circuit 160 of FIG. Capacitor 122 and switches S1 to S4 constitute an offset compensation circuit for compensating for offset voltage VOF of push-type drive circuit 160.

  That is, the switch S1 is connected between the input node N120 and the input node N20 of the drive circuit 160, and the switch S4 is connected between the output node N121 and the output node N30 of the drive circuit 160. Capacitor 122 and switch S2 are connected in series between input node N20 and output node N30 of drive circuit 160. Switch S3 is connected between input node N120 and node N122 between capacitor 122 and switch S2.

  Next, the operation of the drive circuit 190 with an offset compensation function will be described. In the initial state, all the switches S1 to S4 are turned off. When the switches S1 and S2 are turned on at a certain time, the potential V20 of the input node N20 of the drive circuit 160 becomes V20 = VI, and the output potential V30 of the drive circuit 121 and the potential V122 of the node N122 are V30 = V122 = VI-VOF, and the capacitor 122 is charged to the offset voltage VOF.

  Next, when the switches S1 and S2 are turned off, the offset voltage VOF is held in the capacitor 122. Next, when the switch S3 is turned on, the potential V122 of the node N122 becomes V122 = VI, and the input potential V20 of the drive circuit 160 becomes V20 = VI + VOF. As a result, the output potential V30 of the drive circuit 160 becomes V30 = V20−VOF = VI, and the offset voltage VOF of the drive circuit 160 is cancelled. Next, when the switch S4 is turned on, the output potential VO becomes VO = VI and is supplied to the load.

  In the nineteenth embodiment, the offset voltage VOF of the push type drive circuit 160 can be canceled, and the output potential VO and the input potential VI can be matched.

  The pull type drive circuit 191 with an offset compensation function in FIG. 73 is obtained by adding a capacitor 122 and switches S1 to S4 to the pull type drive circuit 170 in FIG. In this modification, the offset voltage VOF of the pull-type drive circuit 191 can be canceled, and the output potential VO and the input potential VI can be matched. Needless to say, the same effect can be obtained by adding the capacitor 122 and the switches S1 to S4 to each of the drive circuits 165, 166, and 172.

[Embodiment 20]
FIG. 74 is a circuit block diagram showing a configuration of a drive circuit 195 with an offset compensation function according to the twentieth embodiment of the present invention. 74, a drive circuit 195 with an offset compensation function is obtained by adding capacitors 122a and 122b and switches S1a to S4a and S1b to S4b to the drive circuit 175 of FIG.

  Switches S1a and S1b are connected between input node N120 and the gates of transistors 24 and 26 (nodes N20a and N20b), respectively. The switches S4a and S4b are connected between the output node N121 and the drains of the transistors 32 and 34 (nodes N30a and N30b), respectively. Capacitor 122a and switch S2a are connected in series between nodes N20a and N30a. Capacitor 121b and switch S2b are connected in series between nodes N20b and N30b. Switch S3a is connected between input node N120 and node N122a between capacitor 122a and switch S2a. Switch 3b is connected between input node N120 and node N122b between capacitor 122b and switch S2b.

  Next, the operation of the drive circuit 195 will be described. In the initial state, all the switches S1a to S4a, S1b to S4b are turned off. When the switches S1a, S2a, S1b, and S2b are turned on at a certain time, the potentials V30a and V30b of the nodes N30a and N30b become V30a = VI−VOFa and V30b = VI−VOFb, and the capacitors 122a and 122b are offset. The voltages VOFa and VOFb are charged.

  Next, when the switches S1a, S2a, S1b, and S2b are turned off, the offset voltages VOFa and VOFb are held in the capacitors 122a and 122b, respectively. Next, when the switches S3a and S3b are turned on, the gate potentials of the transistors 24 and 26 become VI + VOFa and VI + VOFb, respectively. As a result, the potentials V30a and V30b of the nodes N30a and N30b become V30a = VI + VOFa−VOFa = VI and V30b = VI + VOFb−VOFb = VI, respectively, and the offset voltages VOFa and VOFb of the drive circuit 175 are canceled. Finally, the switches S4a and S4b are turned on so that VO = VI.

  In the twentieth embodiment, a drive circuit 195 having no offset voltage and low power consumption can be obtained.

  Needless to say, the same effect can be obtained by adding capacitors 122a and 122b and switches S1a to S4a and S1b to S4b to each of the drive circuits 176, 180, and 185.

  75 is obtained by adding capacitors 126a and 126b to the drive circuit 195 with an offset compensation function in FIG. Capacitors 126a and 126b have one electrodes connected to nodes N30a and N30b, respectively, and the other electrodes receiving reset signal / φR and its complementary signal φR, respectively. In the initial state, signals / φR and φR are set to “H” level and “L” level, respectively. Since the current value of the constant current source 161 is set small, the potential V30a of the node N30a gradually decreases even if the switches S1a and S2a are turned on when the potential V30a of the node N30a is higher than the input potential VI. To do. Further, since the current value of the constant current source 171 is set small, the potential V30b of the node N30b is moderate even if the switches S1b and S2b are turned on when the potential V30b of the node N30b is lower than the input potential VI. To rise. Therefore, in this modification, immediately after the switches S1a, S2a, S1b, and S2b are turned on, the signal / φR falls from the “H” level to the “L” level and the signal φR is changed from the “L” level to the “L” level. Raise to “H” level. As a result, transistors 31, 32, 34, and 35 are rendered conductive, and each of potentials V30a and V30b of nodes N30a and N30b quickly matches input potential VI. Therefore, in the modified example, the operation speed of the drive circuit can be increased.

  Further, the drive circuit 197 with an offset compensation function in FIG. 76 is obtained by replacing the capacitors 126a and 126b of the drive circuit 196 with an offset compensation function in FIG. 75 with an N-type transistor 131a and a P-type transistor 131b, respectively. N-type transistor 131a is connected between the line of eighth power supply potential V8 and node N30a, and has its gate receiving reset signal φR ′. P-type transistor 131b is connected between node N30b and the line of ninth power supply potential V9, and has its gate receiving complementary signal / φR 'of reset signal φR'. Normally, the signals φR ′ and / φR ′ are set to the “L” level and the “H” level, respectively, and both the N-type transistor 131a and the P-type transistor 131b are made non-conductive. Immediately after the switches S1a, S2a, S1b, and S2b are turned on, the signal φR ′ is pulsed to “H” level for a predetermined time and the signal / φR ′ is pulsed to “L” level for a predetermined time. To be. As a result, the N-type transistor 131a is pulsed and the potential V30a of the node N30a is lowered to the eighth power supply potential V8, and the P-type transistor 131b is pulsed and the potential V30b of the node N30b is the ninth. The power supply potential is raised to V9. Even in this modified example, the operation speed can be increased.

  77 is obtained by adding a P-type transistor 81 and an N-type transistor 82 to the drive circuit 196 in FIG. P-type transistor 81 is connected in parallel to constant current source 62 and has its gate receiving signal / φP. N-type transistor 82 is connected in parallel to constant current source 64 and has its gate receiving signal φP. In the initial state, signals / φP and φP are set to “H” level and “L” level, respectively. Since the current value of the constant current source 62 is set to be small, even if the switches S1a and S2a are turned on when the potential V22 of the node N22 is lower than the input potential VI, the potential V22 of the node N22 is gradually reduced. To rise. Further, since the current value of the constant current source 64 is set small, even if the switches S1b and S2b are turned on when the potential V27 of the node N27 is higher than the input potential VI, the potential V27 of the node N27 is moderate. To descend. Therefore, in this modification, immediately after the switches S1a, S2a, S1b, and S2b are turned on, the signal / φP is pulsed to the “L” level for a predetermined time and the signal φP is pulsed for a predetermined time. To “H” level. As a result, transistors 81 and 82 are turned on in a pulse manner, and potential V22 at node N22 rises rapidly and potential V27 at node N27 falls rapidly. Therefore, in the modified example, the operation speed of the drive circuit can be increased.

[Embodiment 21]
In the push type drive circuit 190 with an offset compensation function in FIG. 72, in order to generate the offset voltage VOF when the switches S1 and S2 are turned on, the transistors 31 and 32 need to be turned on. In order to make the transistors 31 and 32 conductive when the switches S1 and S2 are turned on, the potential V30 of the node N30 is offset from the minimum value VImin of the input potential VI before the switches S1 and S2 are turned on. It is necessary to reset to the constant potential VImin−ΔVmax obtained by subtracting the maximum value ΔVmax of the voltage VOF. Further, it is necessary to prevent a large current from flowing through the transistors 31 and 32 when the constant potential VImin−ΔVmax is applied to the node N30. In the twenty-first embodiment, this problem is solved.

  FIG. 78 is a circuit block diagram showing a configuration of a push type drive circuit 200 with an offset compensation function according to the twenty-first embodiment of the present invention. In FIG. 78, this push type drive circuit 200 with an offset compensation function is obtained by adding N type transistors 201, 202, 204 and a P type transistor 203 to the drive circuit 190 of FIG. Transistors 201 to 204 form a reset circuit for initializing potential V30 of node N30.

  That is, transistors 201-203 are connected in series between node N22 and the node of ground potential GND. The gate of N-type transistor 201 receives clock signal CLK. The gate of N-type transistor 202 is connected to its drain. N-type transistor 202 constitutes a diode element. The gate of P-type transistor 203 receives constant potential VImin−ΔVmax obtained by subtracting maximum value ΔVmax of offset voltage VOF from minimum value VImin of input potential VI. N-type transistor 204 has its drain connected to node N30, its source receiving constant potential VImin-ΔVmax, and its gate receiving clock signal CLK.

  In a period in which the switches S1 and S2 are in the ON state, the clock signal CLK is pulsed to the “H” level for a predetermined time. As a result, N-type transistor 204 is turned on to set potential V30 at node N30 to constant potential VImin−ΔVmax, and transistors 31 and 32 are turned on to generate offset voltage VOF. Further, the N-type transistor 201 becomes conductive, and the potential V22 of the node N22 adds the absolute value | VTP | of the threshold voltage of the P-type transistor 203 and the threshold voltage VTN of the N-type transistor 201 to the constant potential VImin−ΔVmax. Potential VImin−ΔVmax + | VTP | + VTN. At this time, since the potential difference between the nodes N22 and N30 is | VTP | + VTN, only a minute current flows through the transistors 31 and 32. Since other configurations and operations are the same as those of drive circuit 190 in FIG. 72, description thereof will not be repeated.

  In the twenty-first embodiment, the drive circuit 200 with the output potential VO and the input potential VI accurately matching and low power consumption is obtained.

  Note that the N-type transistors 201 and 204 may be controlled by different signals. Each of the N-type transistors 201 and 204 may be replaced with a P-type transistor. However, it is necessary to supply the complementary signal / CLK of the signal CLK to the gate of the P-type transistor. If a predetermined potential appears at the node N22, the drain of the P-type transistor 203 may be connected to a node having a potential other than the ground potential GND. If a predetermined current flows, the low potential side terminal of the constant current source 161 may be connected to a node having a potential other than the ground potential GND.

[Embodiment 22]
In the pull drive circuit 191 with an offset compensation function in FIG. 73, in order to generate the offset voltage VOF when the switches S1 and S2 are turned on, the transistors 34 and 35 need to be turned on. In order to make the transistors 34 and 35 conductive when the switches S1 and S2 are turned on, the potential V30 of the node N30 is offset to the maximum value VImax of the input potential VI before the switches S1 and S2 are turned on. It is necessary to reset to the constant potential VImax + ΔVmax obtained by adding the maximum value ΔVmax of the voltage VOF. Further, it is necessary to prevent a large current from flowing through the transistors 34 and 35 when the constant potential VImax + ΔVmax is applied to the node N30. In the twenty-second embodiment, this problem is solved.

  FIG. 79 is a circuit block diagram showing a configuration of pull type drive circuit 210 with an offset compensation function according to the twenty-second embodiment of the present invention. In FIG. 79, this pull-type drive circuit 210 with an offset compensation function is obtained by adding an N-type transistor 211 and P-type transistors 212 to 214 to the drive circuit 191 of FIG. Transistors 211 to 214 form a reset circuit for initializing potential V30 of node N30.

  That is, the transistors 211 to 213 are connected in series between the node of the fourth power supply potential V4 and the node N27. The gate of P-type transistor 211 receives constant potential VImax + ΔVmax obtained by adding maximum value ΔVmax of offset voltage VOF to maximum value VImax of input potential VI. The gate of the P-type transistor 212 is connected to its drain. The P-type transistor 212 constitutes a diode element. The gate of P-type transistor 213 receives complementary clock signal / CLK. P-type transistor 214 has its drain connected to node N30, its source receiving constant potential VImax + ΔVmax, and its gate receiving complementary clock signal / CLK.

  In a period in which switches S1 and S2 are on, complementary clock signal / CLK is pulsed to "L" level for a predetermined time. As a result, P-type transistor 214 is turned on and potential V30 at node N30 is set to constant potential VImax + ΔVmax, and transistors 34 and 35 are turned on to generate offset voltage VOF. Further, the P-type transistor 213 becomes conductive, and the potential V27 of the node N27 is a potential obtained by subtracting the threshold voltage VTN of the N-type transistor 211 and the absolute value | VTP | of the threshold voltage of the P-type transistor 212 from the constant potential VImax + ΔVmax. VImax + ΔVmax−VTN− | VTP | At this time, since the potential difference between the nodes N30 and N27 is VTN + | VTP |, only a very small current flows through the transistors 34 and 35. Since other configurations and operations are the same as those of drive circuit 191 in FIG. 73, description thereof will not be repeated.

  In the twenty-second embodiment, the drive circuit 210 with the output potential VO and the input potential VI accurately matching and low power consumption is obtained.

  Note that the P-type transistors 213 and 214 may be controlled by different signals. Further, each of the N-type transistors 213 and 214 may be replaced with an N-type transistor. However, it is necessary to supply a complementary signal CLK of the signal / CLK to the gate of the N-type transistor. If a predetermined potential appears at the node N27, the drain of the N-type transistor 211 may be connected to a node having a potential other than the fourth power supply potential V4. If a predetermined current flows, the terminal on the high potential side of the constant current source 165 may be connected to a node having a potential other than the fourth power supply potential V4. Furthermore, it goes without saying that a good push-pull drive circuit with an offset compensation function can be obtained by connecting the drive circuit 200 of FIG. 78 and the drive circuit 210 of FIG. 79 in parallel.

  In Embodiments 1 to 22 above, the field effect transistor may be a MOS transistor or a thin film transistor (TFT). The thin film transistor may be formed of any semiconductor thin film such as a polysilicon thin film or an amorphous silicon thin film, or may be formed on any insulating substrate such as a resin substrate or a glass substrate.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  1 liquid crystal panel, 2 liquid crystal cells, 3 pixels, 4 scanning lines, 5 common potential lines, 6 data lines, 7 vertical scanning circuit, 8 horizontal scanning circuit, 10 liquid crystal driving circuit, 11, 23, 26, 31, 34, 42 .0 to 42. m, 47.0-47. m, 69, 70, 82, 86, 99 to 101, 103, 104, 131a, 162, 163, 186 to 188, 201, 202, 204, 211, 303, 304 N-type field effect transistor, 12, 29, 76 , 77, 118, 119, 122, 122a, 122b, 126a, 126b, 156 capacitor, 15 gradation potential generating circuit, 16.1-16. n + 1, 22, 28, 51.0-51. i, 56.1-56. i, 67, 68, 164 resistance elements, 17.1-17. n, S1, S1a, S1b, S2, S2a, S2b, S3, S3a, S3b, S4, S4a, S4b, S5 to S7 switches, 20, 36, 37, 38, 60, 71, 72, 73, 75, 78 , 80, 83, 85, 88, 90, 91, 95, 108, 110, 113, 115.1 to 115. j, 121, 160, 165, 166, 170, 172, 175, 176, 180, 185, 190, 191, 195 to 198, 200, 210, 300 drive circuit, 21, 21 ', 25, 25', 40, 45, 50, 55, 61, 61 ', 63, 63', 96, 96 ', 102, 102', 111, 111 ', 112, 112', 116, 117 Level shift circuit, 24, 27, 32, 35 43.0-43. m, 48.0-48. m, 65, 66, 81, 87, 97, 98, 105-107, 131b, 189, 203, 212-214, 301, 302 P-type field effect transistor, 30, 30 'pull-up circuit, 33, 33' pull-down Circuit, 36 load capacity, 41.1-41. m, 46.1-46. m, 52.1-52. i, 57.1-57. i fuse, 120, 125, 127, 130, 132, 133, 135, 136, 140, 141, 145, 146, 150, 151, 155, 157 drive circuit with offset compensation function, 62, 64, 161, 171, 305 Constant current source.

Claims (17)

A drive circuit that outputs a potential corresponding to an input potential to an output node,
A first level shift circuit for outputting a potential obtained by level-shifting the input potential in a certain potential direction by a predetermined first voltage; and an output potential of the first level shift circuit opposite to the certain potential direction. A second level shift circuit that outputs a potential level-shifted by a predetermined second voltage in the potential direction to the output node,
The first level shift circuit includes:
A first current limiting element whose one electrode receives a first power supply potential;
A first transistor of a first conductivity type whose first electrode receives a second power supply potential and whose input electrode receives said input potential, and whose first electrode and input electrode are said first current limiting A second transistor of the second conductivity type connected to the other electrode of the element, the second electrode of which is connected to the second electrode of the first transistor;
The second level shift circuit includes:
A third transistor of the second conductivity type, the first electrode receiving a third power supply potential, the input electrode connected to the other electrode of the first current limiting element, and the first electrode comprising: A fourth transistor of a first conductivity type connected to a second electrode of the third transistor, the second electrode and an input electrode of which are connected to the output node;
Further, in response to the change in the input potential in the certain potential direction, the first node connected to the input electrode of the third transistor changes in pulse in the certain potential direction. equipped with a pulse generating circuit,
The first pulse generation circuit includes:
A switching element whose one electrode receives a fifth power supply potential and whose other electrode is connected to the first node, and which conducts in a pulse manner in response to the input potential being changed in the certain potential direction;
A drive circuit comprising: a current cutoff circuit that prevents a current from flowing between the first node and the node of the second power supply potential when the switching element is conductive.   The drive circuit according to claim 1, wherein the second level shift circuit further includes a second current limiting element connected between the output node and a fourth power supply potential line. The first and third power supply potentials are the same potential;
The drive circuit according to claim 2, wherein the second and fourth power supply potentials are the same potential.   4. The drive circuit according to claim 2, wherein the first and second current limiting elements are first and second resistance elements, respectively. 5. The first current limiting element is a fifth transistor of the first conductivity type whose input electrode receives a first constant voltage;
The second current limiting element, the input electrode is sixth transistor of the second conductivity type for receiving the second constant voltage drive according to any one of claims 2 to claim 4 circuit.   The drive circuit according to claim 5, further comprising a constant voltage generation circuit that generates the first and second constant voltages. A plurality of drive circuits are provided,
The drive circuit according to claim 6, wherein the constant voltage generation circuit is provided in common to the plurality of drive circuits. A third level shift circuit for outputting a potential obtained by level-shifting the input potential by the second voltage in a potential direction opposite to the certain potential direction;
The fourth level shift circuit, and the potential direction in which the input potential is said for outputting the first potential is level-shifted voltage output potential in the potential direction the of the third level shift circuit to the output node In response to the change, the second pulse for changing the potential of the second node connected to the output node of the third level shift circuit in a potential direction opposite to the certain potential direction. comprising a generator, a drive circuit according to any one of claims 1 to 7. A drive circuit that outputs a potential corresponding to an input potential to an output node,
A first level shift circuit for outputting a potential obtained by shifting the input potential in a potential direction by a predetermined first voltage; and
A second level shift circuit for outputting to the output node a potential obtained by shifting the output potential of the first level shift circuit by a predetermined second voltage in a potential direction opposite to the certain potential direction; ,
The first level shift circuit includes:
A first current limiting element whose one electrode receives a first power supply potential;
A first transistor of a first conductivity type whose first electrode receives a second power supply potential and whose input electrode receives said input potential; and
The second conductivity type second electrode is connected to the other electrode of the first current limiting element and the second electrode is connected to the second electrode of the first transistor. Including two transistors,
The second level shift circuit includes:
A third transistor of the second conductivity type, the first electrode receiving a third power supply potential and the input electrode connected to the other electrode of the first current limiting element;
Including a fourth transistor of the first conductivity type having a first electrode connected to a second electrode of the third transistor, the second electrode and an input electrode connected to the output node;
Further, in response to the change in the input potential in the certain potential direction, the first node connected to the input electrode of the third transistor changes in pulse in the certain potential direction. Equipped with a pulse generation circuit
The first pulse generating circuit has one electrode connected to the first node, and the potential of the other electrode is pulsed in the certain potential direction in response to the input potential being changed in the certain potential direction. Including capacitors that are subject to change,
The drive circuit is
A fifth transistor of the second conductivity type, the first electrode receiving the first power supply potential and the second electrode connected to the first node;
A potential generated by level-shifting the input potential in the direction of the certain potential by the sum of the first voltage and the threshold voltage of the fifth transistor is applied to the input electrode of the fifth transistor. A drive circuit comprising three level shift circuits. The drive circuit according to claim 9, wherein the second level shift circuit further includes a second current limiting element connected between the output node and a fourth power supply potential line. The first and third power supply potentials are the same potential;
The drive circuit according to claim 10, wherein the second and fourth power supply potentials are the same potential. 12. The drive circuit according to claim 10, wherein the first and second current limiting elements are first and second resistance elements, respectively. The first current limiting element is a sixth transistor of a first conductivity type whose input electrode receives a first constant voltage;
The drive according to any one of claims 10 to 12, wherein the second current limiting element is a seventh transistor of a second conductivity type whose input electrode receives a second constant voltage. circuit. The drive circuit according to claim 13, further comprising a constant voltage generation circuit that generates the first and second constant voltages. A plurality of drive circuits are provided,
The drive circuit according to claim 14, wherein the constant voltage generation circuit is provided in common to the plurality of drive circuits. A fourth level shift circuit for outputting a potential obtained by level-shifting the input potential by the second voltage in a potential direction opposite to the certain potential direction;
A fifth level shift circuit for outputting to the output node a potential obtained by level shifting the output potential of the fourth level shift circuit by the first voltage in the certain potential direction;
In response to the change of the input potential in the certain potential direction, the potential of the second node connected to the output node of the fourth level shift circuit is pulsed in the potential direction opposite to the certain potential direction. The drive circuit according to any one of claims 10 to 15, further comprising a second pulse generation circuit that changes in a moving manner. Wherein each of the first to fourth transistors are thin film transistors, the driving circuit according to any one of claims 1 to 1 6.

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