JP5212943B2 - Slot synchronous transmission system and receiving apparatus - Google Patents

Description

  The present invention relates to a slot synchronous transmission system and a receiving apparatus that transmit data using a transmission channel having a non-stationary transmission failure.

2. Description of the Related Art In recent years, PLC (Power Line Communication) that connects a broadband router and a personal computer using a power line of a commercial power source and a short-wave transmission channel has been put into practical use in homes and offices.
In this PLC, a data transmission device (PLC terminal) is arranged at an arbitrary position on the indoor wiring, and data transmission is performed via a coupling circuit in the PLC terminal, and between PLC terminals or between the PLC terminal and an external device. Data communication is performed with PLC terminals connected to the network.

Prior to this, a PLC using a 10 to 450 kHz band was also standardized. However, in this band, a transmission system with high reliability was not widespread due to a large transmission failure. However, I would like to use this band for remote measurement of home appliances control and electric energy.
Unlike wireless transmission media, PLCs have severe and unsteady transmission failures. That is, large swell noise and sharp impulse noise generated from home appliances are added at a level equal to or higher than the signal power. In addition, signal power is absorbed by home appliances, and reception signals are attenuated by branching of a distribution board.
The transmission failure described above fluctuates with a half of the power supply frequency as a period, but the fluctuation pattern fluctuates for each period.

FIG. 12 is an explanatory diagram illustrating an example of a failure in a home appliance. The horizontal axis represents time, and the vertical axis represents the indoor wiring voltage measured by extracting a frequency range of 100 kHz to 500 kHz through an analog bandpass filter.
FIG. 12A shows a failure of the inverter fluorescent lamp. The transmitted signal is not visible because it is buried in a cluster of noises. This noise is additive noise superimposed on the transmission signal.
FIG. 12B shows a failure of the air conditioner. The transmission signal is a portion that appears thick along the horizontal axis, and is an additive noise in which a sharp impulse is superimposed on the transmission signal.
FIG. 12 (c) shows a failure of the quick charger. The transmission signal is a portion that appears thick along the horizontal axis. Since the transmission signal is absorbed during the charging period, the amplitude of the transmission signal varies between the charging period and the discharging period. As the charging of the rechargeable battery proceeds, the time period of the charging period becomes narrower. In the transition period in which the amplitude changes discontinuously, the transmission failure becomes large.
FIG. 12D shows a failure when a large number of home appliances are connected. Fifteen types of home appliances were connected to a wiring board simulating a detached two-story house. This figure shows a received waveform for one cycle of 100 Hz, but the waveform within the cycle changes from moment to moment. The top and bottom of the measured values are cut off. The indoor wiring is branched by a distribution board or outlet. The line length and termination impedance change by connecting or disconnecting a new load to / from an outlet, or by turning on / off any home appliance with a power switch.

In general, a spread spectrum transmission method and an error correction code having a large redundant bit are employed as a conventional method for a poor transmission environment. This method is optimal reception when it is assumed that the transmission failure is random additive Gaussian noise (stationary noise).
However, PLC transmission faults are extremely artificial and are non-stationary transmission faults that cannot assume continuity or strict periodicity. Since transmission failures are concentrated in time, there is a large difference in the reliability of the determination result of transmission data depending on the time zone.
There is a limit to applying the well-known “Shannon theory” to such an unsteady situation. The reason is that if there is a bit having a very large error rate in the transmission bit string, the error rate is governed by the bit error rate. In a realistic example, if the time zone in which data judgment is almost certainly wrong approaches 50%, the average bit rate reaches 0.5, and according to the Shannon limit, it becomes an infinite length encoding, Error correction is impossible.

In Shannon's theory based on the premise of stationarity, there is a water injection theorem that “it is optimal to concentrate and transmit power in a frequency band with good SNR”. For the non-stationary transmission failure as shown in FIG. 12, this optimality principle may be applied to the time axis.
However, in practice, it is difficult to predict in advance a time zone with a good signal-to-noise ratio (SNR). Even if it can be predicted, a time zone with a good SNR must be predicted by implementing a new meeting protocol between the transmitter and the receiver. However, since this meeting protocol itself cannot refer to evaluation of a time zone with a good SNR, there is no guarantee that the meeting protocol will be executed reliably.
As a practical measure for avoiding this dilemma, ARQ (retransmission control) is conceivable in which transmission data in a time zone with a good SNR is determined and adopted, and transmission data in a time zone with a bad SNR is retransmitted. In order to realize this method, it is necessary to know the position of the adopted transmission data and the position of the abandoned transmission data.

Generally, transmission data is assembled into a frame and transmitted, and ARQ is executed on a frame basis. Error detection and error correction are often performed on a frame basis.
Therefore, a frame synchronization signal using an M-sequence or the like is inserted at the head of the frame, or the frame synchronization signal is distributed and transmitted in transmission data in the frame to execute frame synchronization (see Patent Document 1). .
However, when the time at which a large transmission failure occurs coincides with the position of the frame synchronization signal, the frame synchronization signal cannot be detected, so that frame synchronization is not established. However, the time zone during which no transmission failure occurs is very limited and is not constant in time.
In the following specification, “frame” in the above-described prior art has a corresponding relationship with “slot”, and the term “frame” is used as “data frame” composed of a plurality of “slots”. doing.

  In addition, the frequency spectrum of the PLC is not uniform, and the PLC frequently changes depending on the load state and the like. Therefore, an equalizer is used. However, there is a problem that there is no guarantee that the reference signal can be transmitted in a time zone with a good SNR. However, this problem can be solved by adopting a blind equalizer (see Patent Document 2) that does not need to transmit a reference signal.

Japanese Patent No. 3511520 JP 2001-36436 A

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a slot synchronous transmission system and a receiving apparatus capable of slot synchronization even in a transmission channel having a non-stationary transmission failure. It is.

According to the first aspect of the present invention, one slot is composed of J (J is an integer of 2 or more) symbols, and one data frame is composed of k (k is an integer of 2 or more) slots. Is a slot synchronous transmission system that transmits a position information code sequence that has a length of J × k bits or more and a sequence of all consecutive N bits (N is an integer of 2 or more). A position information code sequence generator, a transmission data sequence, a position information code sequence output from the position information code sequence generator, a multiplexing means for multiplexing in symbol timing units, and a multiplexing means A digital modulation means for modulating the multiplexed symbol to obtain a transmission signal; and receiving the reception signal demodulated by receiving the transmission signal transmitted by the transmission apparatus at the reception apparatus; The position information code sequence is separated, and the N-bit arrangement of the separated position information code sequence and the N-bit arrangement of the same reference code sequence as the position information code sequence are set in units of the symbol timing. Slot synchronization means for detecting the position of each slot in the one data frame by comparing, one slot is constituted by N (N is an integer of 2 or more) symbols, and k (k is an integer of 2 or more) slot 1 is a slot synchronous transmission system for transmitting data by constituting one data frame, and in a transmission apparatus, a position information code sequence having a length of N × k bits or more and all of the consecutive N bit arrangements being different A position information code sequence generator, a transmission data sequence, and a position information code sequence output from the position information code sequence generator. And a digital modulation means for modulating a symbol multiplexed by the multiplexing means to be a transmission signal, and receiving the transmission signal transmitted by the transmission apparatus at the reception apparatus. And receiving the demodulated received signal, separating the position information code sequence from the received signal, and arranging the N-bit array of the separated position information code sequence and the same reference code sequence as the position information code sequence. Slot synchronization means for detecting the position of each slot in the one data frame by comparing the N bit arrangement with the symbol timing as a unit.
Therefore, even if there is a transmission failure, if a part of the transmission signal can be received, the position information code sequence multiplexed on the transmission data can detect the bit position in one data frame, so each slot in one data frame can be detected. The position of Further, the transmission data of the transmission data sequence multiplexed with the position information code sequence can also be known in one data frame. As a result, slot synchronization is possible even in a transmission channel having a non-stationary transmission failure.
In particular, if the slot length J is set to J = N, the position and slot number of each slot are immediately known from the identified N bit array.

According to a second aspect of the present invention, in the slot synchronous transmission system according to the first aspect, the transmission data sequence in each slot includes redundant bits for error detection with respect to transmission data in the slot, and the reception When the slot synchronization means cannot detect the position of the transmission data in each slot, the apparatus uses synchronization determination means for outputting a synchronization error in each slot, and reception in each slot using the redundant bit. Data error detection means for detecting a data error, synchronization error output from the synchronization determination means, and data error output from the data error detection means, and determination of reliability of received data in each slot Transmission control processing means for performing the processing.
Therefore, it is possible to determine the reliability of received data in units of slots.

In the invention according to claim 3, in the slot synchronous transmission system according to claim 1 or 2, as the position information code sequence, one period L is 2 ^N −1 bits, and J × k ≦ L. M series is used.
Therefore, the position information code sequence can be easily generated by the linear shift register.
In particular, the slot length J may be J = N.

According to a fourth aspect of the present invention, in the slot synchronous transmission system according to any one of the first to third aspects, the reception device receives and demodulates a transmission signal transmitted by the transmission device. A blind equalizer for blind equalizing a signal is provided, and the slot synchronization means inputs a reception signal blind-equalized by the blind equalizer as the reception signal.
Therefore, transmission channels can be equalized without transmitting a reference signal.

According to a fifth aspect of the present invention, in the slot synchronous transmission system according to any one of the first to fourth aspects, the digital modulation means is an 8PSK modulation means, and a 2-bit value of the transmission data is set. On the other hand, while assigning a 4QAM signal point arrangement, the signal point arrangement assigned to the 2-bit value of the transmission data is left as it is in accordance with the 1-bit value of the position information code sequence, or the signal The point arrangement is a signal point arrangement with a phase shift of 135 degrees.
According to a sixth aspect of the present invention, in the slot synchronous transmission system according to any one of the first to fourth aspects, the digital modulation means is an 8PSK modulation means, and two bits of the transmission data are transmitted. Assign a 4QAM signal point arrangement to the value and leave the signal point arrangement assigned to the 2-bit value of the transmission data as it is, depending on the 1-bit value of the position information code sequence, or The signal point arrangement is a signal point arrangement having a phase shift of -135 degrees.
Therefore, in any of the inventions described in the claims, the transmission data sequence and the position information code sequence can be easily multiplexed. The spectrum of the transmission data sequence can be flattened by the position information code sequence.

According to a seventh aspect of the present invention, in the slot synchronous transmission system according to any one of the first to fourth aspects, the digital modulation means is a 4QAM modulation means, and a value of 1 bit of the transmission data is set. Accordingly, one of the two signal points forming an angle of 90 degrees is assigned, and the signal point assigned according to the 1-bit value of the transmission data is directly used according to the 1-bit value of the position information code sequence. Or a signal point obtained by phase-shifting the signal point by 180 degrees.
Therefore, the transmission data sequence and the position information code sequence can be easily multiplexed. The spectrum of the transmission data sequence can be flattened by the position information code sequence. Also, there is no phase uncertainty in the received signal.

According to an eighth aspect of the present invention, there is provided a receiving apparatus used in the slot synchronous transmission system according to any one of the first to seventh aspects, wherein the slot synchronizing means receives the reception of the symbol of the transmission signal. Assuming a plurality of signal point constellations of signals, and for each of a plurality of assumed signal point constellations, the determination sequence of the position information code sequence is separated from the received signal, and the separated position information code sequence As a result of comparing the N-bit arrangement of the determination sequence and the N-bit arrangement of the same reference code sequence as the position information code sequence in units of the symbol timing, based on the number of times that coincident detection continues. The position information obtained by selecting the most probable signal point arrangement from a plurality of cases of the assumed signal point arrangement and separating the signal points on the basis of the selected signal point arrangement. Based on the decision sequence of No. sequence, and detects the position of each slot in the one data frame.
Therefore, the position information code sequence can be easily separated from the received signal.

According to a ninth aspect of the present invention, in the receiving device according to the eighth aspect, the slot synchronization means has a free-run counter for counting symbol timing in the receiving device, and the selected signal point arrangement is When a sequence number indicating the position of the transmission data in the one data frame is detected based on the determination sequence of the position information code sequence separated as a premise, the detected sequence number is set in the free-run counter. Thus, the count value of the free-run counter is synchronized with the sequence number representing the position of the transmission data.
Therefore, even when the transmitted position information code sequence is not continuously detected from the received signal, the sequence number representing the position of the transmission data is obtained from the count value of the free-run counter, and the one data The order number of each slot in the frame can also be detected.

According to the present invention, there is an effect that slot synchronization is possible even for a transmission channel having a transmission failure such as non-stationary noise or non-stationary signal power change.
As a result, the present invention is effective when applied to slot synchronization of robust transmission aimed at so-called fault-resistant transmission.

It is a whole block diagram which shows one Embodiment of the slot synchronous transmission system of this invention. It is explanatory drawing which shows the property of the positional infomation code sequence (M series) used in embodiment of FIG. It is explanatory drawing of the correspondence of the M series used for embodiment of FIG. 1, a data frame, a slot, and a transmission data series. It is explanatory drawing which shows 8PSK as an example of the digital modulation employ | adopted in embodiment shown in FIG. It is explanatory drawing which shows 1st 4QAM (example 1) as an example of the digital modulation employ | adopted in embodiment shown in FIG. It is explanatory drawing which shows 2nd 4QAM (example 2) as an example of the digital modulation employ | adopted in embodiment shown in FIG. It is a flowchart which shows the 1st specific example about the reception operation | movement in the block following the blind equalizer shown in FIG. It is explanatory drawing of the process of the flowchart shown in FIG. A specific example in the case where the equalized received signal matches the transmitted 8PSK with the even / odd phase will be described. 12 is a flowchart showing a second specific example of the reception operation in the block subsequent to the blind equalizer shown in FIG. 1. It is explanatory drawing of the process of the flowchart shown in FIG. It is a graph which shows the simulation result of the 1st specific example which employ | adopted 8PSK demonstrated with reference to FIG. 7, FIG. It is explanatory drawing which shows the example of a failure of household appliances.

FIG. 1 is an overall configuration diagram showing an embodiment to which a slot synchronous transmission system of the present invention is applied.
The illustrated example is a PLC, in which indoor electric wiring of a power line is used as the transmission path 2, and a data transmission apparatus (PLC terminal) is connected to the transmission path 2.
As described in the background art, a PLC is required to have a strong data transmission capability. In this embodiment, this robustness is achieved by a blind equalizer that does not require transmission of a training signal (reference signal), slot synchronization by multiplexing a position information code sequence with transmission data, and a slot synchronization state. And selective retransmission correction (Selective-ARQ: Automatic Repeat reQuest) based on reliability determination by error detection.

One PLC terminal A is shown in the upper part of FIG. 1, and the other PLC terminal B is shown in the lower part.
The PLC terminal A and the PLC terminal B have the same configuration, in which the transmission unit 1 and the reception unit 3 are connected to the transmission line 2 via the hybrid circuit 4. Details of the transmitter 1 are shown for the upper PLC terminal A, and details of the receiver 3 are shown for the lower PLC terminal B.

In the transmission unit 1, transmission data is temporarily stored in the data buffer 11 and then output to the serial-parallel conversion / encoder 13. The error detection redundant bit generator 12 generates redundant bits based on the transmission data read from the data buffer 11 and outputs the redundant bits to the serial-parallel conversion / encoder 13.
The position information code sequence generator 14 generates a bit string within one period of an M sequence (Maximum length code) as a position information code sequence, and outputs it to the serial-parallel conversion / encoder 13.

The transmission control processing unit 15 assembles a plurality of slots as one data frame with the transmission data as a unit, and adds a redundant bit (one or more bits to be a redundant symbol C) to the end of each slot. To do. As will be described later, a slot synchronization bit (one or a plurality of bits to be a reference phase symbol S) for determining a reference phase may be added at the beginning of each slot.
The transmission control processing unit 15 also starts the position information code sequence generator 14 from a predetermined initial value at the start timing of one data frame.

The serial-parallel conversion / encoder 13 sets a transmission data sequence by inserting redundant bits into the transmission data output from the data buffer 11 and, if necessary, slot synchronization bits.
This transmission data sequence is further multiplexed with a position information code sequence (M sequence) output from the position information code sequence generator 14 in units of symbol timing, and the multiplexed transmission data sequence is converted into a digital modulation scheme. Convert to parallel data of 2 series I phase (in-phase) and Q phase (orthogonal) according to the rules.

  With respect to one symbol timing, I phase (in-phase) by one or more bits (the number of bits determined by the digital modulation system) of the transmission data sequence before multiplexing, and 1 bit of the position information code sequence (M sequence), Converted to Q-phase (orthogonal) parallel data. The converted data represents a transmission data symbol after multiplexing. On the other hand, one or a plurality of bits of the transmission data sequence before being multiplexed can also be called a transmission data symbol before being multiplexed. At the next symbol timing, the next bit or bits of the transmission data sequence before multiplexing and the next bit of the position information code sequence (M sequence) are converted into multiplexed transmission data symbols. Is done.

Here, the position information code sequence is a code sequence in which a predetermined continuous plurality of N-bit arrangements are all different, and in the receiving unit 3, a predetermined continuous plurality of N-bits that are part of the position information code sequence. It is a code sequence that can specify a bit position (bit time position) in symbol timing units by detecting a pattern. Details will be described later with reference to FIGS.
In the following description, 8PSK (8 Phse Shift Keying) described later with reference to FIG. 4 and 4QAM (Quadrature Amplitude Modulation) described later with reference to FIG. Example 1) 4QAM (Example 2) described later with reference to FIG. 6 is illustrated.

Multiplexing of the transmission data sequence and the position information code sequence is performed by independently separating the transmission data sequence and the position information code sequence at each symbol timing from the demodulated baseband received symbols on the receiving side. In order to be able to do so, it means that the transmitting side converts into symbols based on both sequences.
The scramble technique is well known. In the scramble technique, in order to flatten the spectrum of the transmission signal, the transmission data sequence and the M sequence are converted by multiplying each 1 and 0 into 1 and -1 as they are in baseband, or Further digitally modulate and transmit. In this scramble technique, the transmission data sequence and the M sequence are integrated and transmitted. For this reason, the transmission data sequence cannot be separated unless phase synchronization is established between the M sequence on the transmission side and the reference M sequence on the reception side.

The I-phase (in-phase) data and Q-phase (orthogonal) data output from the serial / parallel converter / encoder 13 are limited to frequency bands corresponding to a predetermined symbol rate in the roll-off filters 16I and 16Q, respectively. Is formed so as not to cause intersymbol interference, and is output to the modulator 17.
The modulator 17 includes multipliers 18 and 19, a phase shifter 20, and an adder 21. The I-phase data and the Q-phase data are quadrature-modulated by multiplying the carrier signal output from the carrier signal generator 22 by the modulator 17.
The output signal of the modulator 17 is converted into an analog signal by the D / A converter 23, amplified by the amplifier 24, and sent to the transmission line 2 via the hybrid circuit 4.

In the PLC terminal B, a signal received from the transmission line 2 via the hybrid circuit 4 passes through a BPF (band pass filter) 31 in the receiving unit 3 and is converted into a digital value by an A / D converter 32 and demodulator. 33 is output.
The demodulator 33 includes multipliers 34 and 35 and a phase shifter 36. The demodulator 33 performs quadrature demodulation by multiplying the received signal by the carrier signal 37, and outputs the I-phase component and the Q-phase component to the blind equalizer 38.

The equalizer generally controls the tap gain of the equalizer by transmitting a training signal (reference signal) that is a target of forced equalization.
In contrast, the blind equalizer 38 uses the square of the difference between the absolute value of the symbol output from the blind equalizer 38 and a predetermined radius value as an evaluation function, and tap gain so that this evaluation function is minimized. (See Yoichi Sato, "Linear Equalization Theory-Adaptive Digital Signal Processing", Maruzen Co., Ltd., issued May 31, 1990, p.187 etc.).
Therefore, this blind equalizer 38 does not require the above-described training signal (reference signal), and automatically converges when AGC (automatic gain control) is established. In both cases of 8PSK and 4QAM on the same radius, they converge rapidly. As a result, the eye pattern of the equalizer output signal opens in this time zone, even when the time zone with few transmission failures is small, enabling accurate level judgment and obtaining the same received data as the transmission data can do.

The phase shift / level determination unit 39 compares the equalizer output signals of the I-phase component and Q-phase component output from the blind equalizer 38 individually with the threshold at the symbol timing, thereby obtaining an equalizer. It is determined whether or not the output signal is within a predetermined range of signal points.
In addition, when the phase of the equalizer output signal based on the carrier signal 37 does not match the phase of the transmission signal based on the carrier signal 22 on the transmission side, the phase shift / level determination unit 39 The output signal of the equalizer is phase shifted, in other words, phase rotated.

The slot synchronization unit 40 includes, for example, a position information code sequence detector 41, a free-run counter 42, and a synchronization determination unit 43.
The position information code sequence detector 41 receives the baseband received signal output from the blind equalizer 38 and separates and detects the position information code sequence.
The position information code sequence detector 41 uses the same position information code sequence as the position information code sequence output from the position information code sequence generator 14 on the transmission side as a reference code sequence, and detects the position information code sequence.
The specific operation of the position information code sequence detector 41 will be described later with reference to FIGS. 7 to 10, and the outline of the function will be described here.

  Position information code sequence detector 41 assumes a plurality of cases of signal point arrangement of received signals (arrangement of signal points of each symbol that has become a baseband signal), and each of a plurality of cases of assumed signal point arrangements. , Separating the determination sequence of the position information code sequence from the received signal, an array (pattern) of a part (N bits) of the determination sequence of the separated position information code sequence, and the same reference code as the position information code sequence As a result of comparing the arrangement of a part of the sequence with the symbol timing as a unit, based on the number of consecutive detections of matching, in other words, based on the continuous length of matching symbol periods, The most probable signal point arrangement is selected, and the position information code sequence is constructed based on the determination sequence of the position information code sequence separated on the assumption of the selected signal point arrangement. The sequence number of the bit to be transmitted, in other words, the sequence number of the multiplexed transmission data symbol is detected. As a result, the position of each slot in one data frame is known. Further, the transmission data of the transmission data sequence multiplexed with the position information code sequence can also be known in one data frame.

  In the transmission path 2 having an unsteady transmission failure, it is difficult to detect all the bits of the position information code sequence without error. However, as described in the explanation of the position information code sequence generator 14 on the transmitting side, the position information code sequence can be obtained by detecting the bits of the bits constituting the position information code sequence as long as a predetermined continuous bit pattern can be detected. Since the position (temporal position) can be specified, the position information code sequence can be partially detected.

The partially detected position information code sequence is output to the phase shift / level determination unit 39, and the transmission data sequence is separated from the equalized received signal.
The position information code sequence detector 41 also detects the sequence number continuously over a predetermined number of symbols when the number of consecutive detections of the match (the continuous length of the matching symbol period) is a predetermined value or more. The sequence number is output to the free-run counter 42 and the synchronization determination unit 43.
The free-run counter 42 counts and outputs the symbol timing on the receiving side, and forcibly sets the sequence number output by the position information code sequence detector 41 to represent the position of transmission data on the transmitting side. Synchronize with the sequence number.
The first number in the sequence number represents the first symbol timing of one data frame.
On the other hand, when the position information code sequence detector 41 does not output the sequence number, the sequence number is output by continuing counting at the symbol timing.
The free-run counter 42 also outputs a synchronization timing (symbol timing) and a slot number.
The synchronization determination unit 43 compares the output (sequence number on the transmission side) of the position information code sequence detector 41 and the sequence number output from the free-run counter 42. If they do not match, the slot is used as a unit. The synchronization error signal is output to the transmission control processing unit 15.

  The decoder / parallel serial converter 44 converts the I-phase data and Q-phase data after the level determination into serial data according to the rules of the digital modulation method. Out of the serial data, transmission data is output to the data buffer 45, and transmission data and redundant bits are output to the error detection unit 46. When the slot synchronization symbol S is added, this is output to the phase shift / level determination unit 39, and the phase mismatch between the carrier signal of the carrier signal generation unit 37 and the carrier signal of the carrier signal generation unit 22 on the transmission side is detected. In order to eliminate this, the phase shift / level determination unit 39 phase shifts (phase rotation) the signal point arrangement of the received signal output from the blind equalizer 38.

The error detection unit 46 performs error detection in units of slots using transmission data and redundant bits. When an error is detected, the error detection unit 46 outputs a data error signal to the transmission control processing unit 15 in units of slots.
The transmission control processing unit 15 of the PLC terminal A and the transmission control processing unit 15 of the PLC terminal B perform selective ARQ control on the transmission data in the unreliable slot, and finally assemble the reliable transmission data. Then, the data is output from the data buffer 45 to a utilization device (not shown).

This selective ARQ control is a technology of the MAC (Media Access Control) layer in the data link layer of the OSI (Open Systems Interconnection) model.
The data received in a time zone with few transmission failures should be as accurate as possible. If the reliability of the received data is low, error correction is required and the significance of the present invention is lost. In the present invention, transmission data is transmitted in a short slot unit (eg, 24 bits) transmission data sequence. Assess the reliability of this slot and classify it as almost 100% correct (accept), seems correct, but is suspended (suspend), error (reject).
In communication control command transmission and transmission that requires high reliability, only accept data is raised to the MAC layer, and the MAC layer is caused to execute selective ARQ on reject and suspend data. In other cases, for example, in the case of an audio signal or an image signal, the accept and suspend data are raised to the MAC layer, and selective ARQ is executed on the reject data.

  The transmission control processing unit 15 of the PLC terminal B receives the synchronization error signal output from the synchronization determination unit 43, the slot number output from the free-run counter 42, and the data error signal output from the error detection unit 46. Then, the reliability of the transmission data is determined, and when there is no reliability, a transmission control signal (NACK) for requesting retransmission of the transmission data of the unreliable slot is sent to the transmission unit 1 of the PLC terminal B, Insert into the transmission data sequence and transmit to PLC terminal A.

When the PLC terminal A receives a retransmission request from the transmission unit 1 of the PLC terminal B, the transmission data of the slot determined to be unreliable is extracted from the data buffer 11 in the transmission unit 1 and is combined with the slot number. Then, it transmits it again to the PLC terminal B.
If the retransmitted received data is reliable when retransmitted from the PLC terminal A, the same slot number in the data buffer 45 is assigned with reference to the slot number of the retransmitted received data. Replace the received data in the unreliable slot.

  In the slot synchronous transmission system with reference to FIG. 1, the start timing of each slot in one data frame can be estimated by multiplexing and transmitting the position information code sequence and detecting the position information code sequence partially. . Further, since it is possible to know which slot and which symbol position of the transmission data is in one data frame, the position of the unreliable received data can be determined by the slot number or the like, so that selective retransmission correction can be performed.

FIG. 2 is an explanatory diagram showing the nature of the position information code sequence (M sequence) used in the embodiment of FIG. In order to simplify the description, a short-cycle M sequence will be described as the position information code sequence.
FIG. 2A is a specific example of the M sequence generator.
The M-sequence generator is an LFSR (Linear Feedback Shift Register), and when the number of stages of the shift register is a predetermined number of stages, an M-sequence (Maximum length code) becomes a PN (pseudo-random number) sequence with the maximum period. ).
In the example shown in the figure, in the linear feedback shift register (LFSR) with N = 4 stages (N is a positive integer), when the tap of the output terminal is 0, tap 0 and tap 3 are feedback taps, and the output of the feedback tap Are added to each other and input to the tap 4 as an input terminal.

FIG. 2B is a specific example of the M sequence generated by the M sequence generation unit of FIG. The period of the M sequence is L = 2 ^N −1 = 2 ⁴ −1 = 15.
As one of the properties of the M-sequence, it is known that consecutive N = 4 bit arrays are all different everywhere. That is, the M sequence is shifted one bit at a time over its period = 15 to identify consecutive N = 4 bits (in other words, identified through a window of N = 4 bits) (across the second period) Identify) all different patterns are identified.
This all different pattern is a combination of binary 4 digits excluding all 0s.
Therefore, if the pattern identified in the N = 4-bit window described above can be identified in a part of one period of the M sequence, the position of the identified window, that is, the bit position from the beginning of one period of the M sequence. It is decided whether there is.

A finite-length binary code sequence that has such a characteristic that all consecutive N-bit patterns are different from each other has conventionally been used in a measuring instrument (absolute encoder) that optically detects the absolute position of a length or an angle. It is used as.
A typical example of the finite-length binary code sequence having the characteristics that all the consecutive N-bit patterns are different from each other is an M sequence. A code sequence having such a property can be searched from all binary code sequences of finite length. The inventors of the present invention call a code sequence having the above-described properties as a “position information code sequence”.
Here, the position information is a position of a symbol or data bit, and can also be referred to as a time position (time).

FIG. 2C is an explanatory diagram of a correspondence relationship between the M sequence, the data frame, the slot, and the transmission data sequence.
In the embodiment described with reference to FIG. 1, the length of one slot is N = 4, and a plurality of k = 3 slots constitute one data frame. The illustrated M sequence has a length of one period L = 2 ^N −1 = 15 bits.
Therefore, the length of one data frame = 12 = N × k <L = 15. In general, N × k ≦ L. That is, when the length of the data frame is designed, an M sequence having a period L equal to or longer than the length of the data frame is employed.
Here, the slot length N is a numerical value indicating that all consecutive N = 4 bit arrays (patterns) are different in the M series, as shown in FIG. Therefore, the slot number can be immediately identified by identifying the array of consecutive N = 4 bits.
In FIG. 2 (b), 15 types of patterns identified by N = 4-bit windows are associated with sequence numbers 1 to 15, and slot numbers 1, 2, and 3 are associated with sequence numbers 1, 5, and 9. Yes.

  In order to identify consecutive N = 4 bits of the M sequence, a delay of 3 symbol timing occurs. Therefore, as shown in the lower part of FIG. 2C, the position information code sequence detector detects sequence numbers 1 to 9 and slot numbers 1 to 3 with a delay of 3 symbol timings. In the illustrated example, the sequence numbers 10 to 15 are not detected in the N = 4 bit window. However, it can be seen that, in the symbol timing at which the sequence number 9 is detected, the bit positions up to the preceding 3 symbol timings correspond to the sequence numbers 10 to 12 in the third slot.

In the illustrated example, slot numbers 1, 2, and 3 can be immediately identified by identifying “0001”, [1110], and “1011” as a continuous N = 4-bit pattern.
However, the length of the slot (denoted as J) does not necessarily have to be equal to J (J = N), which is the length of successive different patterns. As described in FIG. 2 (b), if an N = 4 bit pattern is identified, it is possible to know where the identified pattern is in one period of the M sequence. The number of bits from the start bit can be identified.
On the other hand, the head position and length J of each slot in one data frame are fixed in advance. Therefore, since the head position of the slot is known, the slot can be cut out accurately and in synchronization. This clipping can be performed without contradiction even if J ≠ N.

In the slot synchronous transmission system shown in FIG. 1, the above-described M sequence and transmission data sequence are multiplexed in symbol units and assigned with digital modulation symbols. Therefore, by identifying the above-described M-sequence N = 4 patterns, it is possible to determine the number of symbols (bits) from the beginning of one data frame for transmission data before multiplexing.
Since this is not related to the value of J, J = 1 (1 symbol = 1 slot), and a system that transmits a pair of 1 symbol (bit) and 1 bit of a position information code sequence representing its position. It can also be said.

A specific example using a practical long-period M-sequence will be described on the premise of the properties of the position information code sequence described above.
FIG. 3 is an explanatory diagram of the correspondence relationship between the M sequence used in the embodiment of FIG. 1 and the data frame, slot, and transmission data sequence.
The PLC shown in FIG. 1 transmits data in a burst mode. Due to standard restrictions, the maximum allowable time is determined for one burst, and the next one burst must be transmitted after a transmission pause period.
One data frame is transmitted in one burst. The length of one data frame may be a fixed length or a variable length as long as it is within the maximum allowable time. Therefore, the number of slots included in one data frame may be a fixed number or a variable number.

Since the position information code sequence may be longer than the length of one data frame, it may be longer than the maximum allowable data frame.
In the illustrated example, an M sequence of N = 12 is adopted as the position information code sequence, and the slot length is set to N (the number of consecutive bits in which a different arrangement is detected) = 12 described above. This M-sequence has a period L = 2 ^N −1 = 4095. As a result, the number k of slots in the data frame having the maximum length is L ÷ N = (2 ^N −1) ÷ integer part of N = 341, and includes a maximum of 341 slots from Slot1 to Slot341. Yes. At this time, N × k = 4092 bits are allocated to one data frame from the head of the M sequence.

In the transmission data sequence multiplexed with the position information code sequence (M sequence) described above, in this embodiment, a bit serving as the reference phase symbol S is inserted at the beginning of each segment, and error detection redundancy is provided at the end of each segment. Inserts a bit that becomes symbol C. The remaining 10 symbols in one slot are transmission symbols based on transmission data.
In 8PSK, which will be described later, 1-symbol transmission data is created based on 2-bit transmission data. In 4QAM, 1-symbol transmission data is created based on 1-bit transmission data.
The reference phase symbol S described above is used to match the reference phase between the transmission side and the reception side in the case of 8PSK described later.
The error detection redundant symbol C is used when error detection is performed on transmission data in one slot.

FIG. 4 is an explanatory diagram showing 8PSK as an example of digital modulation employed in the embodiment shown in FIG.
FIG. 4A is an arrangement diagram of signal points, and FIG. 4B is a symbol map showing the correspondence between the position information code sequence (M sequence) bits and transmission data and the signal symbol arrangement of transmission symbols.
As shown in FIG. 4A, there are eight signal points (0) to (7), and their absolute values are equal. When the M sequence bit = 0, it corresponds to one of the black circle signal points, and when the M sequence bit = 1, it corresponds to one of the white circle signal points.
As shown in FIG. 4C, when the M-sequence bit = 0, it corresponds to an odd-numbered signal point. As shown in FIG. 4D, when the M-sequence bit = 1, it corresponds to an even-numbered signal point. Any signal point arrangement is 4QAM signal point arrangement. In the figure, what is described as [0, 0] at each signal point indicates corresponding 2-bit transmission data.

If the signal point arrangement at M = 0 bit = 0 shown in the left of FIG. 4C is phase shifted by +135 degrees, the signal point arrangement at M = 1 bit = 1 shown in the right of FIG. 4C is obtained. As a result, for each signal point, the signal point when the M sequence bit = 1 is shifted by 135 degrees from the signal point when the M sequence bit = 0.
The phase shift angle may be an arbitrary angle, for example, +45 degrees or −45 degrees as long as the phase shift does not overlap the original signal point arrangement. However, the closer to ± 180 degrees, the less the spectrum of the transmission signal after multiplexing depends on the spectrum of the transmission data sequence (the spectrum is concentrated when the transmission data has the same continuity). That is, since the spectrum of the transmission data sequence is flattened due to the randomness of the position information code sequence, it is less susceptible to the influence of non-uniform frequency characteristics of the transmission channel. Therefore, a phase shift of −135 degrees may be performed instead of 135 degrees.

In the case of 8PSK described above, a 4QAM signal point arrangement is assigned to a 2-bit value of transmission data, and the signal point arrangement described above is left as it is or a signal point is assigned to a 1-bit value of a position information code sequence. The phase shift does not overlap.
Digital modulation is not limited to the 8PSK described above. The signal point arrangement assigned to one or a plurality of bits of the transmission data is left as it is for the 1-bit value of the position information code sequence, or the phase relative to this signal point arrangement A shifted signal point arrangement is used. The phase shift is preferably set to a value close to 180 degrees.
Note that the signal point arrangement of the transmission symbol is a signal point arrangement in which the entire signal point arrangement shown in the figure is phase-shifted (phase rotation, eg, 22.5 degrees) if the phase is fixed with respect to the carrier signal. Also good.

  In known digital modulation signal point arrangements, such as 4QAM, 16QAM, etc., the signal points are divided into two equal groups, and each of the first and second groups is a position information code sequence. When the first and second signal point arrangements corresponding to the values of the first and second signal point arrangements are configured and the first signal point arrangements are phase-shifted, the second signal point arrangements may be matched.

FIG. 5 is an explanatory diagram showing a first 4QAM (Example 1) as an example of digital modulation employed in the embodiment shown in FIG.
FIG. 5A is an arrangement diagram of signal points, and FIG. 5B is a symbol map showing the correspondence between the position information code sequence (M sequence) bits and transmission data and the signal symbol arrangement of transmission symbols. The overall signal point arrangement (0) to (3) is 4QAM.
As shown in FIG. 5 (c), depending on the value of the M-sequence, the 2PSK signal point arrangement (0), (2) is left as it is, or the signal point arrangement is shifted by +90 degrees with respect to this arrangement. To do.
Also in this specific example, the signal point arrangement of the transmission symbol is a signal point obtained by phase-shifting (phase rotation, for example, 45 degrees) the entire signal point arrangement shown in the figure if the phase is fixed with respect to the carrier signal. It may be an arrangement.

FIG. 6 is an explanatory diagram showing a second 4QAM (example 2) as an example of digital modulation employed in the embodiment shown in FIG.
FIG. 6A is an arrangement diagram of signal points, and FIG. 6B is a symbol map showing the correspondence between the position information code sequence (M sequence) bits and transmission data and the signal symbol arrangement of transmission symbols. The overall signal point arrangement (0) to (3) is 4QAM.
As shown in FIG. 6 (c), the irregular 2PSK signal point arrangement (3), (2) having a phase difference of 90 degrees is left as it is or 180 degrees depending on the value of the M sequence. The signal points are shifted in phase.

In the example shown in the figure, the signal point arrangement is symmetric with respect to the Q-axis according to the M-sequence bit value, but the signal point arrangement is symmetric with respect to the I-axis according to the M-sequence bit value. It may be a point arrangement.
This 4QAM (example 2) assigns one of two signal points forming an angle of 90 degrees according to the 1-bit value of the transmission data, and 1 of the transmission data according to the 1-bit value of the M sequence. This is a typical example in the case where a signal point assigned according to the value of the bit is left as it is, or a signal point obtained by performing a phase shift of 180 degrees on this signal point.

The second 4QAM (example 2) shown in FIG. 6 has a phase shift of 180 degrees in accordance with the value of the M sequence as compared to the first 4QAM (example 1) shown in FIG. As described with respect to 8PSK, the spectrum is flat.
Also, since it is asymmetric PSK modulation, the so-called “90 degree arbitraryness” problem of 4QAM symbols can be avoided. Therefore, as will be described later with reference to FIGS. 9 and 10, the slot synchronization symbol S need not be added to the head of the slot. As a result, the number of transmission symbols can be increased by one symbol.

FIG. 7 is a flowchart showing a first specific example of the receiving operation in the block subsequent to the blind equalizer 38 shown in FIG. The operations described above can be executed by a computer incorporated in a terminal using hardware logic or a program.
The first specific example employs the data frame configuration and M series of FIG. 3 and the 8PSK digital modulation system of FIG.

FIG. 8 is an explanatory diagram of the processing steps of the flowchart shown in FIG. A specific example in the case where the equalized received signal matches the transmitted 8PSK with the even / odd phase will be described.
FIG. 8A is a signal point arrangement diagram showing signal point positions of the equalized reception signal.
FIG. 8B is an explanatory diagram of a process of converting an 8PSK signal point arrangement into a 4QAM signal point arrangement when the M-sequence bit = 1.
FIG. 8C is a signal point arrangement diagram after the absolute phase of the equalized received signal is determined by the reference phase symbol S added to the head of the slot.

In FIG. 7, steps S101 to S110 correspond to the function of the position information code sequence detector 41 shown in FIG.
The baseband signals of the I-phase component and the Q-phase component that are digitally demodulated by the demodulator 33 shown in FIG. 1 are received signals that are equalized by the blind equalizer 38.
In S101, the level of the equalized I-phase component and Q-phase component of the received signal is determined (symbol signal point determination). If the blind equalization eye pattern is open, it can be identified whether the signal point is an even number or an odd number of the 8PSK signal. When neither the even-phase signal point nor the odd-phase signal point can be determined, neither the determination series 1 nor the determination series 2 described later is acquired, and therefore the following processes of S102 to S110 are not performed.

Here, with respect to the phase of the received signal with respect to the transmitted 8PSK signal, possible first signal point arrangement and second signal point arrangement are assumed.
The first signal point constellation is a signal point constellation in which the even and odd phases of the received signal equalized with the transmitted 8PSK match. On the other hand, the second signal point arrangement is a signal point arrangement in which the even and odd phases of the received signal equalized to the transmitted 8PSK are reversed.
In the case where the first signal point arrangement is assumed, the position information code sequence (M series) is detected in S102 to S105, and in the case where the second signal point arrangement is assumed, the position information code sequence in S106 to S109. (M series) detection processing is performed. S102 to S105 and S106 to S109 are simultaneously executed by time division multiplexing processing or the like.

In S102, the determination sequence 1 of the position information code sequence assuming the first signal point arrangement is acquired from the level determination result in S101.
As shown in the left figure of FIG. 8 (a), when the phase is an even phase (0 degree, 90 degree, 180 degree, 270 degree) with a double circle, “1”, odd phase ( If any of 45 degrees, 135 degrees, 225 degrees, and 315 degrees), the determination sequence 1 that is “0” is output.
On the other hand, in S106, the determination sequence 2 of the positional information code sequence assuming the second signal point arrangement is acquired from the level determination result in S101. As shown in the right diagram of FIG. 8A, “1” is set for any odd phase (45 °, 135 °, 225 °, 315 °) with a double circle, and the even phase (0 In the case of any one of degrees, 90 degrees, 180 degrees, and 270 degrees, a determination series 2 that is “0” is output.
Note that the determination sequence 1 and the determination sequence 2 are complementary, so that the other determination sequence can be obtained by reversing “0” and “1” of one determination sequence.

The specific example shown in FIG. 8 is a specific example in the case where the equalized reception signal matches the transmitted 8PSK with the phase even / odd.
In this specific example, when determination sequence 1 is acquired in the left diagram of FIG. 8A, an M-sequence bit pattern is detected. That is, the position information code sequence (M sequence) multiplexed in the transmission signal sequence is separated from the equalized reception signal.
On the other hand, even if the determination sequence 2 is acquired in the right diagram of FIG. 8B, the M-sequence bit pattern is not detected.

In S103, 12 consecutive bits are extracted from the judgment sequence 1. That is, the judgment sequence 1 is identified sequentially from the 12-bit window.
In S104, referring to the code table, a sequence number (also referred to as a serial number) corresponding to consecutive 12 bits is read.
Here, the code table is a table in which position information code sequences (M sequences) are arranged in sequence (bit patterns) when the sequence information is identified by a 12-bit window and their sequence numbers. The sequence number is a number indicating the sequence from the first bit in one cycle of the position information code sequence (M sequence). If there is an array (bit pattern) not included in the code table (for example, an array included in an unused sequence when an unused sequence is known in advance during one period of the M sequence), sequence number = 0 Is output.
The process of S104 is equivalent to comparing the consecutive N-bit arrangement of the position information code sequence with the consecutive N-bit arrangement of the reference code sequence of the position information code in units of symbol timing.
The M-sequence 4-bit pattern shown in FIG. 2B is given a sequence number.

In S105, whether or not the number of consecutive detections of the sequence number exceeds n (n is a positive integer, for example, n = 8), in other words, an N-bit array of the position information code sequence and the position information code The number of times that a match of the sequence with the reference code sequence is continuously detected (the length of the period of continuous match) is determined. If yes, output yes, otherwise output no.
S107 to S109 are the same processes as S103 to S105.
In S110, the determination sequence 1 or the determination sequence 2 that first output yes is selected from S105 and S109. The sequence number (output in S104 or S108) output by the selected yes determination sequence is acquired.
In other words, based on the number of consecutive coincidence detections, the decision sequence separated on the assumption of the most probable signal point arrangement is selected from the assumed signal point arrangements, and the sequence number is detected based on the selected decision series To do. This continuity of the N-bit continuous pattern match is a very strong error detection.

In S111, the value of the free-run counter 42 in FIG. 1 is matched with the sequence number output by the selected determination sequence. As a result, the sequence number output by the position information code sequence (M sequence) detection unit 41 is set to synchronize with the sequence number on the transmission side.
In S112, when the selected decision sequence bit (that is, M sequence bit) is 1, as shown in FIG. 8B, the equalized received signal is phase-shifted by −135 °.
This process is a process for converting the 8PSK signal arrangement into the 4QAM signal arrangement so that the subsequent decoder / parallel serial converter 44 can be realized by the 4QAM decoder.

If the M sequence is only separated, the signal phase of the digital modulation signal does not always match between the transmission side and the reception side. There are four possibilities with a 90 degree angle difference. Therefore, as shown in FIG. 8C, the first symbol of the slot is transmitted as the reference phase symbol S on the transmission side. Since the position of the first symbol in the slot can be identified from the above-described sequence number, the symbol signal point at this time is phase-shifted so as to be (1) in the first quadrant.
In S113, the above-described processing is executed. The entire received signal in the slot is phase-shifted (phase rotated) so that the position of the slot cut-out timing becomes the reference phase symbol S, and a received data sequence (received data and redundant bits) is acquired.

The processes of S112 and S113 described above are part of the function of the phase shift / level determination unit 39 in FIG.
The −135 ° phase shift in S112 described above corresponds to a phase shift of 135 degrees on the transmission side, but may be an odd multiple of 45 degrees. This is because the phase shift is also performed in S113 based on the reference phase symbol S.
The phase shift / level determination unit 39 does not perform phase shift, and the decoder / parallel serial conversion unit 44 selects the value of the selected determination sequence bit (M sequence bit) and the reference phase of the position of the first symbol in the slot. The transmission data may be decoded with reference to the 8PSK symbol map shown in FIG.

  The specific example described with reference to FIG. 8 is a case where the equalized received signal matches the transmitted 8PSK with the even / odd phase. On the other hand, when the transmitted 8PSK does not match the even-odd phase, the M-sequence bit pattern in the determination sequence 2 is assumed when the second signal point arrangement shown on the right side of FIG. In step S110, the determination sequence 2 is selected through the processing in steps S106 to S109 in FIG.

In S114, error detection is performed using a redundant symbol C (two redundant bits) for each slot (12 symbols). This processing corresponds to the error detection unit 46 in FIG.
In S115, the value of the free-run counter 42 is compared with the sequence number output from the position information code sequence detector 41 and output from the selected determination sequence. This process corresponds to the synchronization determination unit 43 in FIG.

S116 is one of the functions executed by the transmission control processing unit 15 in FIG. 1, and determines the reliability of received data in units of slots.
If the error detection is OK (no data error) & the value of the free-run counter = “sequence number” (no synchronization error) output by the selected determination sequence, it is determined as “accept (true)”. In this case, the slot number output from the free-run counter 42 is added to the received data of the slot determined as described above, and the data is output to the data buffer 45 of FIG.

  Error detection OK (no data error) & free-run counter value ≠ “sequence number” (with synchronization error) output by the selected determination sequence is determined to be “suspend”. In this case, the slot number output from the free-run counter 42 is added to the received data of the slot determined as described above, and the data is output to the data buffer 45.

In the case of “error detection NG (with data error)”, it is determined as “reject (false)”. In this case, the slot number output from the free-run counter 42 is added to the received data of the slot determined as described above, and the data is output to the data buffer 45.
The transmission control processing unit 15 in FIG. 1 executes the selective ARQ communication control procedure using the received data and the slot number temporarily stored in the data buffer 45 in slot units.

Although the above-described flowchart employs 8PSK as a digital modulation signal, the case where 4QAM (Example 1) shown in FIG. 5 is employed has also been described with reference to FIGS. Similar to the first specific example, the processing on the receiving side can be executed.
In this case, the first signal point constellation is a signal point constellation when it is assumed that the phase matches that of the transmitted 4QAM, and the second signal point constellation is the phase of the transmitted 4QAM and the phase. This is a signal point arrangement when it is assumed that they are orthogonal (shifted by 90 degrees).

  Assuming the first signal point constellation, if the equalized received signal is 45 degrees or 225 degrees, it is “0”, and if it is either 135 degrees or 315 degrees, it is “1”. The determination sequence 1 is acquired. On the other hand, in the case of assuming the second signal point arrangement, the determination sequence 2 is “0” at any of 135 degrees and 315 degrees, and “1” at any of 45 degrees and 225 degrees. get. When the selected judgment sequence is “1”, shift the phase by −45 degrees to convert 4QAM to 2PSK, or obtain transmission data by referring to the 4QAM symbol map shown in FIG. To do.

FIG. 9 is a flowchart showing a second specific example of the receiving operation in the block subsequent to the blind equalizer 38 shown in FIG. The above-described operation can also be executed by a computer incorporated in a terminal using hardware logic or a program.
The second specific example employs the data frame configuration and M series of FIG. 3 and 4QAM (example 2) of FIG.
Using the asymmetry of the signal point arrangement of 4QAM (example 2), the absolute phase is determined without adding the reference phase symbol S to the head of the slot.

FIG. 10 is an explanatory diagram of the processing steps of the flowchart shown in FIG.
FIG. 10A is an explanatory diagram of the phase shift process assuming the first to fourth signal point arrangements.
The illustrated specific example shows a specific example in the case where the phase of the transmitted 4QAM (example 2) and the equalized received signal match.
FIG. 10B is a signal point arrangement diagram of 4QAM (example 2) in the selected determination sequence.
FIG. 10C is a symbol map of 4QAM (example 2).

9, steps S121 to S142 include not only the function of the position information code sequence detector 41 shown in FIG. 1, but also the function of combining the phase shift / level determination unit 39 and the decoder / parallel serial conversion unit 44. ing. That is, the position information code sequence detection function and the transmission data sequence detection function are integrated.
In S121, the I-phase component and Q-phase component of the equalized received signal are subjected to level determination (symbol signal point determination).
Next, a possible first to fourth signal point arrangement is assumed for the phase of the received signal with respect to the 4QAM signal on the transmitting side.

The first signal point arrangement is a signal point shown in the upper left of FIG. 10A assuming that the phase of the transmitted 4QAM (example 2) and the equalized received signal are in phase. Arrangement. In S122, assuming the first signal point arrangement, the process immediately proceeds to S123.
The second signal point arrangement is a signal point arrangement on the assumption that the phase of the equalized received signal is shifted by 90 degrees with respect to the transmitted 4QAM (example 2). In this case, in S127, as shown in the upper right of FIG. 10A, the equalized reception signal is phase-shifted (phase rotated) by −90 degrees.

The third signal point constellation is a signal point constellation that assumes that the phase of the equalized received signal is shifted by 180 degrees with respect to the transmitted 4QAM (example 2). In this case, in S132, the equalized received signal is phase-shifted by −180 degrees as shown in the lower left of FIG.
The fourth signal point arrangement is a signal point arrangement on the assumption that the phase of the equalized received signal is shifted by 270 degrees with respect to the transmitted 4QAM (example 2). In this case, in S137, the equalized received signal is phase-shifted by −270 degrees as shown in the lower right of FIG.

In S123 assuming the first signal point arrangement, the determination sequence 1 is obtained by determining the I-phase component. As shown in the upper left of FIG. 10A, when the M sequence is “1”, the signal point is at a position of ± 45 degrees, and therefore the M sequence is acquired from the determination sequence 1.
In S124, 12 consecutive bits are extracted from the judgment sequence 1.
S125, S126, S142, and S143 are the same processes as S104, S105, S110, and S111 in FIG.
In S144, the Q phase data of the selected determination sequence in the selected determination sequence shown in FIG. 10B (in the illustrated example, the determination sequence 1 based on the upper left diagram in FIG. 10A). The received data sequence (received data and redundant bits) is obtained by multiplying the value of (± 1) by the value of I-phase data (± 1). This calculation is based on the symbol map conversion rule of FIG. The function of S144 corresponds to the function of the decoder / parallel converter 44 of FIG.
S145 to S147 are the same as S114 to S116 in FIG.

The specific example described with reference to FIG. 10 is a case where the equalized received signal matches the transmitted 4QAM and the signal point arrangement (phase). On the other hand, if the transmitted 4QAM does not match the signal point arrangement (phase), the second to fourth signal point arrangements shown in the upper right, lower left, and lower right of FIG. When one of them is assumed, an M-sequence bit pattern is detected in the determination sequence obtained from the in-phase component. As a result, S141 selects one of the determination sequence 2 to the determination sequence 4 through the processing of S127 to S131, S132 to S136, and S137 to S141 in FIG.
As a result, the absolute phase is determined even if the reference phase symbol is not added to the head position of the slot.

  In the flowcharts of FIG. 7 and FIG. 9 described above, once one determination sequence of the position information code sequence is determined after the start of burst transmission in one burst (one data frame) period shown in FIG. Thereafter, the judgment sequence is not switched during the burst period unless the non-stationary disturbance is severe. Therefore, after the determination sequence is selected in S110 of FIG. 7 and S142 of FIG. 9, the processing for the determination sequence that is not selected is not required in the same burst period.

The multiplexing of the position information code sequence using the digital modulation scheme shown in FIGS. 4 to 6 constitutes the first and second signal point arrangements corresponding to the values of the position information code sequence, and the first signal point When the arrangement is phase-shifted, the relationship coincides with the second signal point arrangement.
On the other hand, the method of performing reception processing for selecting all signal point arrangements as shown in FIG. 9 and FIG. 10 matches the second signal point arrangement when the first signal point arrangement is phase-shifted. Applicable regardless of whether or not.

FIG. 11 is a graph showing a simulation result of the first specific example employing 8PSK described with reference to FIGS. 7 and 8.
In the figure, the horizontal axis represents the symbol number, and the reliability for each slot determined by the transmission control processing unit 15 is represented by a rectangular pattern. For reference, the vertical axis represents the I-phase component of the equalized received signal.

In the above description, in the case of one-to-one transmission between PLC terminal A and PLC terminal B, the case where one type of position information code sequence (M sequence) is used has been described.
However, even in the case of one-to-one transmission, depending on the contents of transmission data, different position information code sequences (M Series) may be used.
In addition, when data transmission is performed between three or more PLC terminals or between one PLC parent terminal and a plurality of PLC child terminals, each PLC terminal has a length of a different N bit pattern ( Different position information code sequences (M sequences) may be used with the same identification window bits and slot lengths.
In the case of M sequences, a plurality of types of M sequences can be obtained even if the period L = 2 ^N −1 is the same. For example, when the cycle L = 4095 using a 12-stage shift register, about 70 types of M sequences are obtained.

In the above description, as shown in FIG. 3, the case where one data frame is transmitted in one burst has been described.
However, a combination of a plurality of data frames described above may be transmitted in one burst, or continuous transmission may be performed in units of data frames.
In this case, the position information code sequence assigned to one data frame may not have the property that the lengths of successive N bit patterns are different at the boundary of one data frame. However, even in this case, the serial number cannot be obtained temporarily. When one M-sequence period is assigned to one data frame, the property that the lengths of consecutive N-bit patterns are different at the boundary of one data frame is maintained.

  By applying the present invention not only to the PLC but also to data transmission using a subscriber telephone line or a transmission channel of a local area network, reliable data transmission is possible.

DESCRIPTION OF SYMBOLS 1 ... Transmission part, 2 ... Transmission path, 3 ... Reception part, 4 ... Hybrid circuit,
DESCRIPTION OF SYMBOLS 11 ... Data buffer, 12 ... Error detection redundant bit generation part, 13 ... Serial-parallel conversion / encoder, 14 ... Position information code sequence generator, 15 ... Transmission control processing part, _16I , _16Q ... Roll-off filter, 17 ... Modulator, 18, 19 ... Multiplier, 20 ... Phase shifter, 21 ... Adder, 22 ... Carrier signal generator, 23 ... D / A converter, 24 ... Amplifier 31 ... BPF, 32 ... A / D conversion 33, demodulator, 34, 35, multiplier, 36, phase shifter, 37 ... carrier signal generator, 38 ... blind equalizer, 39 ... phase shift / level determination unit, 40 ... slot synchronization unit, 41 ... Position information code sequence detector, 42 ... Free-run counter, 43 ... Synchronization determination unit, 44 ... Decoder / parallel serial conversion unit, 45 ... Data buffer, 46 error detection unit

Claims (9)

A slot synchronous transmission system in which one slot is composed of J (J is an integer of 2 or more) symbols and one data frame is composed of k (k is an integer of 2 or more) slots to transmit data,
In the transmission device,
A positional information code sequence generator that generates a positional information code sequence that has a length of J × k bits or more and in which all consecutive N bits (N is an integer of 2 or more) have different arrays;
Multiplexing means for multiplexing the transmission data sequence and the positional information code sequence output from the positional information code sequence generator in units of symbol timing;
Digital modulation means for modulating a symbol multiplexed by the multiplexing means to be a transmission signal;
In the receiving device,
A received signal demodulated by receiving a transmission signal transmitted by the transmission device is input, and the position information code sequence is separated from the received signal, and the N-bit array of the separated position information code sequence and the position Slot synchronization means for detecting the position of each slot in the one data frame by comparing the N-bit array of the same reference code sequence with the information code sequence in units of the symbol timing;
A slot synchronous transmission system comprising: The transmission data sequence in each slot includes redundant bits for error detection for transmission data in the slot,
The receiving device is:
Synchronization determination means for outputting a synchronization error of each slot when the slot synchronization means cannot detect the position of the transmission data in each slot;
Data error detection means for detecting an error in received data in each slot using the redundant bits;
Transmission control processing means for determining the reliability of the received data in each slot based on the synchronization error output by the synchronization determination means and the data error output by the data error detection means;
It is characterized by having
The slot synchronous transmission system according to claim 1. As the position information code sequence, an M sequence in which 1 period L is 2 ^N −1 bits and J × k ≦ L is used.
The slot synchronous transmission system according to claim 1 or 2, characterized in that. The receiving device has a blind equalizer that blindly equalizes a received signal demodulated by receiving a transmission signal transmitted by the transmitting device;
The slot synchronization means inputs a reception signal blind-equalized by the blind equalizer as the reception signal.
The slot synchronous transmission system according to any one of claims 1 to 3, wherein the slot synchronous transmission system is provided. The digital modulation means is 8PSK modulation means,
4QAM signal point allocation is assigned to the 2-bit value of the transmission data,
Depending on the 1-bit value of the position information code sequence, the signal point arrangement assigned to the 2-bit value of the transmission data is left as it is, or the signal point arrangement is a signal having a phase shift of 135 degrees Point placement,
The slot synchronous transmission system according to any one of claims 1 to 4, wherein the slot synchronous transmission system is provided. The digital modulation means is 8PSK modulation means,
4QAM signal point allocation is assigned to the 2-bit value of the transmission data,
Depending on the 1-bit value of the position information code sequence, the signal point arrangement assigned to the 2-bit value of the transmission data is left as it is, or the signal point arrangement is shifted by -135 degrees. Signal point arrangement,
The slot synchronous transmission system according to any one of claims 1 to 4, wherein the slot synchronous transmission system is provided. The digital modulation means is 4QAM modulation means,
One of two signal points forming an angle of 90 degrees is assigned according to the value of 1 bit of the transmission data, and the value of 1 bit of the transmission data is determined according to the value of 1 bit of the position information code sequence. The signal point assigned according to is left as it is, or it is a signal point with a phase shift of 180 degrees to the signal point,
The slot synchronous transmission system according to any one of claims 1 to 4, wherein the slot synchronous transmission system is provided. A receiving device used in the slot synchronous transmission system according to any one of claims 1 to 7,
The slot synchronization means includes
A plurality of cases of signal point arrangement of the received signal with respect to the symbol of the transmission signal are assumed, and the determination sequence of the position information code sequence is separated from the received signal for each of a plurality of cases of the assumed signal point arrangement. As a result of comparing the N-bit arrangement of the determination sequence of the separated position information code sequence with the N-bit arrangement of the same reference code sequence as the position information code sequence in units of the symbol timing Based on the number of consecutive detections, the most probable signal point arrangement is selected from a plurality of cases of the assumed signal point arrangement, and the determination sequence of the position information code sequence is separated based on the selected signal point arrangement. On the basis of the position of each slot in the one data frame,
A receiving apparatus. The slot synchronization means has a free-run counter that counts symbol timing in the receiving device,
When a sequence number representing the position of the transmission data in the one data frame is detected based on the determination sequence of the position information code sequence separated on the basis of the selected signal point arrangement, the detected sequence number is By setting the run counter, the count value of the free run counter is synchronized with a sequence number representing the position of the transmission data.
The receiving device according to claim 8.

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