JP5211537B2 - Interface circuit - Google Patents

Description

  The present invention relates to an interface circuit, and more particularly to an interface circuit that mediates data exchange between a processor and a device.

  In recent years, the processing speed of a processor such as a CPU (Central Processing Unit) has been increased, but the interface speed of various devices controlled thereby has not sufficiently followed. Depending on the device, there are devices that take time to start up after power-on and devices that take time to stabilize characteristics.

  FIG. 9 is a diagram for explaining electronic device control by the processor. The circuit block shown in the figure is, for example, a circuit block of an optical transmission apparatus, and includes a processor 101, an EEPROM (Electrically Erasable Programmable Read-only Memory) 102, LSIs (Large Scale Integration) 103 and 107, optical modules 104 and 109, and an amplifier. 105 and 108, and electronic devices of ASSP LSI (Application Specific Standard Product LSI) 106 are shown.

  The processor 101 is a processor such as a CPU or a DSP (Digital Signal Processor). The bus 111 is a bus that directly exchanges data with the processor 101, and is, for example, a PCI (Peripheral Component Interconnect) bus.

  The electronic device is connected to the bus 111 via I / F (InterFace) circuits 121 to 128 such as a bus bridge circuit and a controller. The buses 112 and 117 are, for example, I2C buses, and the buses 113 and 116 are RS-232C. The bus 114 is a low-speed bus whose bus cycle is slower than that of the bus 111, and the bus 115 is a narrow-band bus whose bus width is narrower than that of the bus 111.

  The I / F circuits 121 to 128 convert data such that the bus 111 connected to the processor 101 is compatible with another bus, and mediate exchange of data between the processor 101 and the electronic device. The processor 101 performs data read / write access to each electronic device via the I / F circuits 121 to 128.

  FIG. 10 is a diagram illustrating an example of the write operation timing of the processor. When writing data to the electronic device, the processor 101 outputs a write address and write data of the electronic device to which the data is written. Further, a chip select for selecting an electronic device to which data is written and a write enable signal for writing data to the electronic device are output.

  As a result, the write data output from the processor 101 is written to the selected electronic device, and the electronic device to which the data has been written returns an acknowledge to the processor 101. When the processor 101 receives an acknowledge from the electronic device, the processor 101 can start the next access.

  When the interface clock of the electronic device is slower than the operation clock of the bus 111 or when the response time of the electronic device is long, the time until the acknowledgment is returned becomes longer as shown by the arrow A101 in FIG. . In addition, when the bit width of the bus of the electronic device is smaller than that of the processor 101, the I / F circuit must repeat multiple accesses to the electronic device for one access of the processor 101. First, the time until the acknowledge is returned becomes longer. In this case, the processor 101 cannot immediately start the next access.

  FIG. 11 is a diagram illustrating an example of the read operation timing of the processor. When reading data from the electronic device, the processor 101 outputs a read address of the electronic device from which the data is read. Further, a chip select for selecting an electronic device from which data is read and a read enable for reading data are output.

Thereby, the read data and the acknowledge are output from the electronic device, and the processor 101 can read the read data.
Similar to the write operation described above, when the interface clock of the electronic device is slower than the operation clock of the bus 111 or when the response time of the electronic device is long, as shown by the arrow A102, until the acknowledge is returned. The time will be longer. In addition, when the bit width of the bus of the electronic device is smaller than that of the processor 101, the I / F circuit must repeat multiple accesses to the electronic device for one access of the processor 101. First, the time until the acknowledge is returned becomes longer. In this case, the processor 101 cannot immediately start the next access.

  FIG. 12 is a sequence diagram showing an access control operation. The processor in the figure corresponds to the processor 101 in FIG. The I / F circuits # 1 to # 3 correspond to three I / F circuits among the I / F circuits 121 to 128. Electronic devices # 1 to # 3 correspond to three electronic devices of the electronic devices in FIG. Steps S101 to S103 indicate a data write operation, and steps S104 to S106 indicate a data read operation.

  In step S101, the processor writes the write data # 1 to the electronic device # 1 via the I / F circuit # 1. When writing the write data # 1, the electronic device # 1 notifies the processor of Ack (acknowledge) # 1 via the I / F circuit # 1.

  In step S102, the processor writes the write data # 2 to the electronic device # 2 via the I / F circuit # 2. When writing the write data # 2, the electronic device # 2 notifies the processor of Ack # 2 via the I / F circuit # 2.

  In step S103, the processor writes the write data # 3 to the electronic device # 3 via the I / F circuit # 3. When the electronic device # 3 writes the write data # 3, the electronic device # 3 notifies the processor of Ack # 3 via the I / F circuit # 3.

  In step S104, the processor makes a data read request # 1 to the electronic device # 1 via the I / F circuit # 1. Upon receiving the read request # 1, the electronic device # 1 outputs Ack # 1 and the read Data # 1 to the processor via the I / F circuit # 1.

  In step S105, the processor makes a data read request # 2 to the electronic device # 2 via the I / F circuit # 2. When the electronic device # 2 receives the read request # 2, the electronic device # 2 outputs Ack # 2 and the read Data # 2 to the processor via the I / F circuit # 2.

  In step S106, the processor makes a data read request # 3 to the electronic device # 3 via the I / F circuit # 3. Upon receiving the read request # 3, the electronic device # 3 outputs Ack # 3 and the read Data # 3 to the processor via the I / F circuit # 1.

  When the processor writes or reads data, the processor occupies the operation of writing or reading data until an acknowledgment is returned from the electronic device. For example, when the processor outputs write data # 1 to the I / F circuit # 1 in step S101, it cannot perform the operation of write data # 2 in the next step S102 until Ack # 1 is returned. In particular, when the speed of the electronic device is low, the occupation time of the processor becomes long.

  Depending on the architecture of the processor, a busy signal may be asserted until processing is completed, or a ready signal may be asserted when processing is possible. The point that the access cycle becomes longer when the device is slow is the same.

Conventionally, there has been proposed a file access control apparatus that executes read processing at the maximum speed without waiting for the data file read / write requests from a plurality of users in the order in which the requests are generated (for example, Patent Document 1). reference).
JP-A-6-250792

  As described above, when the processor accesses a low-speed device, it takes a long time to receive a response signal from the device, and the processor and its bus are occupied by the access operation of the device during that time. .

  The present invention has been made in view of these points, and an object of the present invention is to provide an interface circuit that can operate without occupying the access operation of the processor even with a low-speed device.

  In an embodiment of the present invention, in order to solve the above problem, in the interface circuit 1 that mediates the exchange of data between the processor 2 and the device 3 as shown in FIG. The access information is received, a response signal to the access information is autonomously output to the processor 2, and the processor side interface means 1a for outputting the data from the device 3 to the processor 2, and the access information received by the processor side interface means 1a Access information storage means 1b for storing, device side interface means 1c for accessing the device 3 based on the access information stored in the access information storage means 1b and receiving data output from the device 3, and device side interface means 1c received The interface circuit 1 is provided, characterized in that it comprises a data storage unit 1d for storing over data, the.

  According to such an interface circuit 1, a response signal for access information from the processor 2 is autonomously output to the processor 2. Further, the access information from the processor 2 is stored in the access information storage unit 1b, and the data from the device 3 is stored in the data storage unit 1d.

  Thereby, the access information and data exchanged between the processor 2 and the device 3 are temporarily stored in the access information storage means 1b and the data storage means 1d, and the processor 2 responds autonomously from the interface circuit 1. Therefore, other control can be performed.

  In the interface circuit of the present invention, access information and data exchanged between the processor and the device are temporarily stored in the access information storage means and the data storage means, and a response signal is output autonomously to the processor. did. As a result, the processor can perform other control and is not occupied by the access operation of the device.

Hereinafter, the principle of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a diagram for explaining the outline of the interface circuit. The interface circuit 1 includes a processor side interface unit 1a, an access information storage unit 1b, a device side interface unit 1c, and a data storage unit 1d. The interface circuit 1 is connected to the processor 2 and the device 3 through a bus, and mediates data exchange between the processor 2 and the device 3.

  The processor-side interface unit 1 a receives access information for accessing the device 3 from the processor 2. The access information is, for example, a write address, write data, or read address of the device 3. The processor-side interface unit 1a autonomously outputs a response signal to the access information to the processor 2. The processor-side interface unit 1a outputs the data stored in the data storage unit 1d to the processor 2.

The access information storage unit 1b stores the access information received by the processor side interface unit 1a.
The device-side interface unit 1c accesses the device 3 based on the access information stored in the access information storage unit 1b. For example, the device 3 is write-accessed or read-accessed based on the access information stored in the access information storage means 1b. The device-side interface unit 1 c receives data output from the device 3. For example, read data for read access is received.

The data storage unit 1d stores the data received by the device side interface unit 1c.
The operation will be described below. When accessing the device 3, the processor 2 outputs access information to the interface circuit 1. The processor side interface unit 1 a of the interface circuit 1 autonomously outputs a response signal to the processor 2 regardless of the response of the device 3.

  On the other hand, the access information of the processor 2 is stored in the access information storage means 1b. Thus, the device-side interface unit 1c can access the device 3 based on the access information stored in the access information storage unit 1b regardless of the processor 2. The data of the device 3 corresponding to the access information is stored in the data storage unit 1d. As a result, the processor 2 can read the data stored in the data storage unit 1d at any time.

  Thus, since the interface circuit 1 mediates between the processor 2 and the device 3, the processor 2 can perform other control and is not occupied by the access operation of the device 3.

Next, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 2 is a block diagram of the I / F circuit. As shown in the figure, the I / F circuit 10 includes a CPU bus I / F unit 11, a CPU side memory control unit 12, a memory unit 20, a device side memory control unit 31, a device I / F unit 32, an access monitoring unit 41, And selectors 42 and 43. The I / F circuit 10 is a circuit that mediates exchange between the CPU and a low-speed electronic device, and is applied to, for example, the I / F circuits 121 to 128 shown in FIG. The CPU bus I / F unit 11 is connected to a bus (for example, the bus 111 in FIG. 9) connected to the CPU, and the device I / F unit 32 is a bus (for example, the bus in FIG. 9) connected to an electronic device. 112-119).

  Note that the functions of the I / F circuit 10 are a memory unit 20 that stores data exchanged between the CPU and the electronic device, and a CPU bus I / F unit 11 that controls the exchange between the memory unit 20 and the CPU. And the CPU side memory control unit 12, the device side memory control unit 31 and the device I / F unit 32 that control the exchange between the memory unit 20 and the electronic device, and the exchange between the CPU and the electronic device. It can be divided into an access monitoring unit 41 and selectors 42 and 43 which are controlled so that they can be performed directly without going through.

  When the CPU bus I / F unit 11 receives a write access from the CPU, the CPU bus I / F unit 11 notifies the CPU side memory control unit 12 of that fact and autonomously acknowledges the CPU regardless of the acknowledgment of the electronic device. return. At that time, the CPU bus I / F unit 11 outputs access information including a write address and write data from the CPU to the memory unit 20.

  When the CPU bus I / F unit 11 receives a read access from the CPU, the CPU bus I / F unit 11 notifies the CPU side memory control unit 12 of that fact and autonomously acknowledges the CPU regardless of the acknowledgment of the electronic device. return. At that time, the CPU bus I / F unit 11 outputs the read data stored in the memory unit 20 to the CPU. Further, the CPU bus I / F unit 11 sends access information including a read address from the CPU to the memory unit 20.

  As will be described in detail later, the CPU 20 obtains read data that was previously read-accessed because the CPU 20 stores read data that was previously read-accessed by the CPU.

  The CPU side memory control unit 12 controls the writing of access information to the memory unit 20. For example, access information including a write address and write data transmitted from the CPU is stored in the memory unit 20, and access information including a read address transmitted from the CPU is stored in the memory unit 20. The CPU-side memory control unit 12 reads the read data corresponding to the read address sent from the CPU from the memory unit 20 and outputs the read data to the CPU bus I / F unit 11.

  The memory unit 20 includes a first in first out (FIFO) memory 21 and a read data storage memory 22. In the FIFO memory 21, access information from the CPU is stored in a FIFO manner.

  The read data storage memory 22 stores read data read from the electronic device. The address of the read data storage memory 22 corresponds to the read address of the electronic device. When a predetermined address of the read data storage memory 22 is read, the read address of the corresponding electronic device can be read.

  The device-side memory control unit 31 controls access information reading when the access information is stored in the FIFO memory 21 and the device I / F unit 32 is not accessing the electronic device. The access information read from the FIFO memory 21 is output to the device I / F unit 32. The device-side memory control unit 31 reads the access information until there is no access information in the FIFO memory 21.

  The device I / F unit 32 converts the access information output from the FIFO memory 21 into a format and timing compatible with the electronic device and outputs the converted information. In addition, a necessary control signal for accessing the electronic device is output to the electronic device.

  For example, when the access information output from the FIFO memory 21 is a write address and write data, the device I / F unit 32 outputs the write address and write data to the electronic device, and also provides a chip select signal and a write enable. The signal control signal is output. Thereby, the write data from the CPU is written to the electronic device.

  When the access information output from the FIFO memory 21 is a read address, the device I / F unit 32 outputs the read address to the electronic device and also outputs a control signal for a chip select signal and a read enable signal. To do. Further, the device I / F unit 32 receives read data corresponding to the read address from the electronic device, and stores it in the corresponding address of the read data storage memory 22.

  When an acknowledgment is returned from the electronic device, the device I / F unit 32 notifies the device-side memory control unit 31 that the access to the device is completed. As a result, the device-side memory control unit 31 can recognize whether or not the device I / F unit 32 is accessing the electronic device.

  The access monitoring unit 41 monitors whether the CPU has accessed a specific address of the electronic device. The specific address is, for example, an address that requires real-time property for data writing / reading. The access monitoring unit 41 enables direct write access and read access to the electronic device without going through the memory unit 20 when the CPU accesses a specific address of the electronic device.

  For example, when the CPU performs read access to a specific address, the access monitoring unit 41 selects the address information of the read address output from the CPU bus I / F unit 11 so as to be output directly to the device I / F unit 32. 42 is controlled. Then, the selector 43 is controlled so that the read data of the electronic device output from the device I / F unit 32 is directly output to the CPU bus I / F unit 11. As a result, the CPU can obtain the currently requested read data, not the read data of the read access performed once before, for the read data that requires real-time performance.

  The specific address can be fixedly set in the access monitoring unit 41 at the design stage, or can be set in the access monitoring unit 41 when the I / F circuit 10 is initialized at power-on or the like. .

  The CPU bus I / F unit 11 autonomously returns an acknowledge, but when the CPU accesses a specific address, it returns an acknowledge to the CPU according to the acknowledge of the electronic device.

  FIG. 3 is a sequence diagram showing the write access control operation. The CPU in the figure corresponds to, for example, the processor 101 in FIG. The I / F circuits # 1 to # 3 correspond to three I / F circuits among the I / F circuits 121 to 128 shown in FIG. However, the I / F circuits # 1 to # 3 have the block configuration shown in FIG. Electronic devices # 1 to # 3 correspond to three electronic devices of the electronic devices in FIG.

  As shown in the figure, the CPU outputs write data including write addresses and write data of the electronic devices # 1 to # 3 to the I / F circuits # 1 to # 3. When each CPU bus I / F unit 11 of the I / F circuits # 1 to # 3 receives write data from the CPU, it autonomously returns an acknowledge.

  Each CPU bus I / F unit 11 of the I / F circuits # 1 to # 3 outputs write data from the CPU to the FIFO memory 21. The device I / F units 32 of the I / F circuits # 1 to # 3 output the write data stored in the FIFO memory 21 to the electronic devices # 1 to # 3 independently of the operation of the CPU.

  As described above, the I / F circuits # 1 to # 3 store the write data from the CPU in the memory unit 20 and autonomously return an acknowledge to the CPU. Thereafter, the I / F circuits # 1 to # 3 write the write data from the CPU into the electronic devices # 1 to # 3 independently of the CPU. Thus, data writing to the electronic device is performed in parallel in each of the I / F circuits # 1 to # 3 as shown in the figure, and the CPU can perform other control at the arrow A1.

FIG. 4 is a sequence diagram showing the read access control operation. The CPU, the I / F circuits # 1 to # 3, and the electronic devices # 1 to # 3 in the figure are the same as those in FIG.
As shown in the figure, the CPU issues a read request including the read addresses of the electronic devices # 1 to # 3 to the I / F circuits # 1 to # 3. When each CPU bus I / F unit 11 of the I / F circuits # 1 to # 3 receives a read request from the CPU, it autonomously returns an acknowledge.

  No read data is stored in the read address of the read data storage memory 22 that the CPU has read-accessed for the first time. Therefore, when the CPU makes a read access to the electronic devices # 1 to # 3 for the first time, the dummy data is received from the I / F circuits # 1 to # 3 as shown in the figure. Therefore, the CPU needs to discard the read data that has been read-accessed for the first time.

  When the CPU bus I / F unit 11 of each of the I / F circuits # 1 to # 3 receives a read request from the CPU, the read address included in the read request is stored in the FIFO memory 21. The device I / F units 32 of the I / F circuits # 1 to # 3 read from the electronic devices # 1 to # 3 based on the read address stored in the FIFO memory 21 independently of the operation of the CPU. Read data. The device I / F units 32 of the I / F circuits # 1 to # 3 store the read data read from the electronic device in the read data storage memory 22.

  Next, when the CPU performs a read access with the same read address, the read data stored in the read data storage memory 22 is stored. Therefore, the CPU acquires the read data when the previous read access was made.

For example, as indicated by arrows A <b> 11 and A <b> 12, Data # 1-1 of the read request # 1-1 performed for the first time by the CPU is stored in the read data storage memory 22.
When the CPU next issues a read request # 1-1 as indicated by an arrow A13, Data # 1-1 indicated by an arrow A12 is stored in the read data storage memory 22; As shown, Data # 1-1 is output to the CPU.

  Thus, the I / F circuits # 1 to # 3 store the read request from the CPU in the memory unit 20 and autonomously return an acknowledge to the CPU. Also, the read data stored in the read data storage memory 22 is returned to the CPU. The I / F circuits # 1 to # 3 perform read access to the electronic devices # 1 to # 3 independently of the CPU. As a result, reading of the read data to the electronic device is performed in parallel in each of the I / F circuits # 1 to # 3 as shown in the figure, and the CPU can perform other controls at the arrows A15 and A16. it can.

  As described above, the read data acquired by the CPU is read data that was previously read-accessed with the same read address. When read access is performed periodically, data one cycle before is read out. However, in a low-speed electronic device, since real-time reading is inherently difficult, there are few cases of problems. Even when real time is required, the access monitoring unit 41 and the selectors 42 and 43 can directly access the electronic device without going through the memory unit 20, and can acquire read data.

Hereinafter, an operation flow on the CPU side (CPU bus I / F unit 11 and CPU side memory control unit 12) of the I / F circuit 10 will be described.
5 and 6 are flowcharts showing the operation on the CPU side of the I / F circuit.

  In step S1, the CPU bus I / F unit 11 of the I / F circuit 10 determines whether there is an access from the CPU bus (CPU). If there is no access from the CPU, the process of step S1 is repeated. If there is an access from the CPU, the process proceeds to step S2.

  In step S2, the access monitoring unit 41 determines whether or not a direct response of the electronic device is necessary. For example, it is determined whether or not the CPU has accessed a write address or read address that requires real-time performance. If the access monitoring unit 41 determines that a direct response is necessary, the process proceeds to step S11. If it is determined that no direct response is required, the process proceeds to step S3. That is, the access monitoring unit 41 proceeds to step S11 when not exchanging data via the memory unit 20, and proceeds to step S3 when exchanging data via the memory unit 20.

  The CPU-side memory control unit 12 determines the access type of the CPU. If the access type of the CPU is write access, the process proceeds to step S4. If the access type of the CPU is read access, the process proceeds to step S6.

In step S <b> 4, the CPU-side memory control unit 12 stores write access access information in the FIFO memory 21.
In step S5, the CPU bus I / F unit 11 returns an acknowledge to the CPU. By receiving the acknowledge from the CPU bus I / F unit 11, the CPU is released from data writing to the electronic device and can perform other controls.

In step S <b> 6, the CPU-side memory control unit 12 stores read access access information in the FIFO memory 21.
In step S7, the CPU side memory control unit 12 reads the read data from the read data storage memory 22 of the read address.

  In step S8, the CPU bus I / F unit 11 returns the read data read from the read data storage memory 22 to the CPU together with an acknowledge. The read data storage memory 22 stores the read data of the read address at the previous read access.

In step S <b> 11, the access monitoring unit 41 notifies the device I / F unit 32 of an access request to the electronic device.
In step S12, the access monitoring unit 41 determines whether or not the device I / F unit 32 can access the electronic device. That is, it is determined whether the device I / F unit 32 is accessing the electronic device. If the device I / F unit 32 can access the electronic device, the process proceeds to step S13. If the device I / F unit 32 cannot access the electronic device, the process of step S12 is repeated.

  In step S13, the access monitoring unit 41 determines whether the access type is write access or read access. In the case of write access, the process proceeds to step S14. In the case of read access, the process proceeds to step S16.

  In step S14, the access monitoring unit 41 sets the selectors 42 and 43 so that the write access access information output from the CPU bus I / F unit 11 is output to the device I / F unit 32 without passing through the memory unit 20. Control.

  In step S15, the CPU bus I / F unit 11 returns an acknowledge to the CPU. The acknowledge response is not performed autonomously by the CPU bus I / F unit 11 but according to the acknowledge of the electronic device.

  In step S <b> 16, the access monitoring unit 41 sets the selectors 42 and 43 to output the read access access information output from the CPU bus I / F unit 11 to the device I / F unit 32 without passing through the memory unit 20. Control.

  In step S <b> 17, the access monitoring unit 41 determines whether the device I / F unit 32 has completed access to read data. That is, it is determined whether the device I / F unit 32 has acquired read data from the electronic device. If the device I / F unit 32 determines that the access to the read data has been completed, the process proceeds to step S18. When the device I / F unit 32 determines that the access to the read data has not been completed, the process of step S17 is repeated.

In step S <b> 18, the CPU bus I / F unit 11 receives read data from the device I / F unit 32 without going through the memory unit 20.
In step S19, the CPU bus I / F unit 11 returns read data and an acknowledge to the CPU. The acknowledge response is not performed autonomously by the CPU bus I / F unit 11 but according to the acknowledge of the electronic device.

Next, an operation flow on the electronic device side (device-side memory control unit 31 and device I / F unit 32) of the I / F circuit 10 will be described.
7 and 8 are flowcharts showing operations on the electronic device side of the I / F circuit.

  In step S21, the access monitoring unit 41 determines whether or not there is a direct access request from the CPU. If there is no direct access request from the CPU side, the process proceeds to step S22. If there is an access request from the CPU side, the process proceeds to step S31.

  In step S <b> 22, the device-side memory control unit 31 determines whether access information is stored in the FIFO memory 21. If the access information is stored in the FIFO memory 21, the process proceeds to step S23. If the access information is not stored in the FIFO memory 21, the process proceeds to step S21.

In step S <b> 23, the device-side memory control unit 31 reads access information from the FIFO memory 21.
In step S24, the device-side memory control unit 31 determines from the read access information whether the access type accessed by the CPU is read access or write access. In the case of read access, the process proceeds to step S27. In the case of write access, the process proceeds to step S25.

In step S <b> 25, the device I / F unit 32 performs write access to the electronic device based on the access information read from the FIFO memory 21.
In step S26, the device I / F unit 32 determines whether or not an acknowledge signal from the electronic device has been received. If no acknowledgment is received from the electronic device, the process of step S26 is repeated. If an acknowledge is received from the electronic device, the process proceeds to step S21.

In step S <b> 27, the device I / F unit 32 performs read access to the electronic device based on the access information read from the FIFO memory 21.
In step S28, the device I / F unit 32 determines whether or not an acknowledge and read data are received from the electronic device. If the acknowledge and read data are not received from the electronic device, the process of step S28 is repeated. When the acknowledge and read data are received from the electronic device, the process proceeds to step S29.

In step S29, the device I / F unit 32 writes the read data of the electronic device to the address of the read data storage memory 22 corresponding to the read address of the CPU.
In step S31, the device I / F unit 32 notifies the access monitoring unit 41 that access to the electronic device is possible.

In step S <b> 32, the device I / F unit 32 receives access information via the selector 42.
In step S33, the device-side memory control unit 31 determines whether the access type of the access information output from the selector 42 is a read access or a write access. If the access type is read access, the process proceeds to step S36. If the access type is write access, the process proceeds to step S34.

In step S34, the device I / F unit 32 performs write access to the electronic device based on the access information.
In step S35, the device I / F unit 32 determines whether there is an acknowledge from the electronic device. If there is an acknowledge from the electronic device, the process proceeds to step S21. If there is no acknowledge from the electronic device, the process of step S35 is repeated.

In step S36, the device I / F unit 32 performs read access to the electronic device based on the access information.
In step S37, the device I / F unit 32 determines whether an acknowledge and read data are received from the electronic device. When the acknowledge and read data are received from the electronic device, the process proceeds to step S38. When the acknowledge and read data are not received from the electronic device, the process of step S37 is repeated.

In step S <b> 38, the device I / F unit 32 sends the read data to the CPU bus I / F unit 11 without going through the memory unit 20.
As described above, the I / F circuit 10 temporarily stores access information and read / write data exchanged between the CPU and the electronic device in the FIFO memory 21 and the read data storage memory 22, and stores the electronic information in the CPU. The device responds autonomously with an acknowledge. As a result, the CPU can perform other control and is not occupied by the access operation of the electronic device.

Further, in the system using the I / F circuit 10, the system start-up time such as when the power is turned on can be shortened.
Further, in the system using the I / F circuit 10, the processing capacity of the entire system can be improved.

  Further, the CPU can directly access the electronic device by the access monitoring unit 41 without going through the memory unit 20, and can cope with processing that requires real-time performance.

(Supplementary note 1) In an interface circuit that mediates the exchange of data between a processor and a device,
Processor-side interface means for receiving access information for accessing the device from the processor, autonomously outputting a response signal to the access information to the processor, and outputting the data from the device to the processor; ,
Access information storage means for storing the access information received by the processor side interface means;
Device-side interface means for accessing the device based on the access information stored in the access information storage means and receiving the data output from the device;
Data storage means for storing the data received by the device-side interface means;
An interface circuit comprising:

(Additional remark 2) It has an access information output means which outputs the access information to the device side interface means without going through the access information storage means based on the contents of the access information received by the processor side interface means ,
The interface circuit according to claim 1, wherein the device-side interface unit accesses the device based on the access information output from the access information output unit.

(Supplementary Note 3) Data output for outputting the data received by the device side interface means to the processor side interface means without going through the data storage means based on the contents of the access information received by the processor side interface means Further comprising means,
2. The interface circuit according to claim 1, wherein the processor-side interface means outputs the data output from the data output means to the processor.

  (Supplementary Note 4) The interface circuit according to claim 1, wherein the processor-side interface means outputs an acknowledge signal to the processor when the access information is received from the processor.

(Supplementary Note 5) The interface circuit according to claim 1, wherein the access information storage means is a FIFO memory.
(Supplementary note 6) The interface circuit according to claim 1, wherein the processor-side interface means outputs the data stored in the data storage means to the processor together with the response signal.

It is a figure explaining the outline | summary of an interface circuit. It is a block block diagram of an I / F circuit. FIG. 10 is a sequence diagram showing a write access control operation. FIG. 5 is a sequence diagram showing a read access control operation. It is the flowchart which showed the operation | movement by the side of CPU of an I / F circuit. It is the flowchart which showed the operation | movement by the side of CPU of an I / F circuit. It is the flowchart which showed the operation | movement by the side of the electronic device of an I / F circuit. It is the flowchart which showed the operation | movement by the side of the electronic device of an I / F circuit. It is a figure explaining electronic device control by a processor. It is the figure which showed the example of the write operation timing of the processor. It is the figure which showed the example of the read operation timing of the processor. It is the sequence diagram which showed the access control operation.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Interface circuit 1a Processor side interface means 1b Access information storage means 1c Device side interface means 1d Data storage means 2 Processor 3 Device

Claims (5)

In the interface circuit that mediates the exchange of data between the processor and the device,
Receives access information including a write address, write data, and a read address for accessing the device from the processor, autonomously outputs a response signal to the access information to the processor, and reads data from the device Processor side interface means for outputting to the processor;
Access information storage means for storing the access information received by the processor side interface means;
When the access information output from the access information storage means in a first-in first-out manner is the write address and write data, the device accesses the device based on the write address and writes the write data, and the access information storage means When the access information output in a first-in first-out method is the read address, device side interface means for accessing the device with the read address and receiving the read data output from the device;
Data storage means for storing the read data received by the device-side interface means;
I have a,
The processor-side interface means outputs dummy data to the processor when the data storage means does not store the read data received from the device-side interface means, and the data storage means is the device-side interface means An interface circuit which outputs the read data to the processor when the read data received from the memory is stored . Based on the content of the access information received by the processor side interface means, further comprising access information output means for outputting the access information to the device side interface means without going through the access information storage means;
The interface circuit according to claim 1, wherein the device-side interface unit accesses the device based on the access information output from the access information output unit. Based on the content of the access information received by the processor-side interface means, the apparatus further comprises data output means for outputting the data received by the device-side interface means to the processor-side interface means without going through the data storage means. And
2. The interface circuit according to claim 1, wherein the processor-side interface means outputs the data output from the data output means to the processor.   2. The interface circuit according to claim 1, wherein said processor side interface means outputs an acknowledge signal to said processor when receiving said access information from said processor. 2. The interface circuit according to claim 1, wherein the access information storage means is a FIFO memory.

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