JP5173310B2 - Semiconductor integrated circuit - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit in which a regulator for stepping down an external power supply voltage is arranged. In particular, the present invention relates to the arrangement of the regulator and is applied to, for example, a semiconductor integrated circuit for data processing of a microcomputer requiring high integration. And effective technology.

  In a semiconductor integrated circuit or the like that operates at a low voltage like a microcomputer, for example, a regulator that steps down an external power supply voltage to form an internal power supply voltage is used. In Patent Document 1, an external connection region in which external terminals used for connection to the outside are arranged on a semiconductor chip, and a buffer and a protection element related to input / output of signals and power supplies are arranged next to the external connection region. A semiconductor integrated circuit having an output circuit region and a core region having a core circuit that operates with an internal power supply voltage output from the input / output circuit region is described. In this semiconductor integrated circuit, a regulator that steps down the external power supply voltage in the external connection region to an internal power supply voltage lower than the external power supply voltage is disposed in the input / output circuit region.

JP 2002-038772 A

  If a regulator is simply added to the semiconductor chip, the area of the semiconductor chip is increased accordingly. Therefore, in order to suppress the expansion of the area of the semiconductor chip, as shown in Patent Document 1, a regulator can be arranged in an empty area where no buffer in the input / output circuit area is arranged.

  In addition, a regulator having an output transistor and a start-up circuit that outputs a predetermined output current to the output transistor has been proposed in a previous application by the present applicant, though not yet known. In this regulator, the inrush current can be suppressed by controlling the start-up circuit so that the output current from the output transistor is gradually increased with respect to the time change in the initial period when the external power supply is turned on. As the circuit for gradually increasing the output current, a charge pump circuit or the like that gradually increases the input voltage from the external power supply voltage terminal immediately after turning on the external power supply voltage is used. The charge pump circuit has a circuit form in which a voltage is sequentially accumulated in a capacitor to perform a boosting operation, and requires a plurality of relatively large capacitive elements.

  However, since the capacitive element for forming the charge pump circuit occupies a relatively large area, such a regulator does not fit in the empty area of the input / output circuit area in Patent Document 1, and eventually the area of the semiconductor chip is reduced. It leads to the factor to spread.

  An object of the present invention is to provide a semiconductor integrated circuit that suppresses an increase in the area of a semiconductor chip and prevents an inrush current in a regulator that steps down an external power supply voltage.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  That is, the regulator of the present invention includes an output transistor that outputs an internal power supply voltage from an external power supply voltage by negative feedback control, and an output current of the output transistor before the negative feedback control is activated when the external power supply voltage is turned on. And a charge pump circuit for forming a voltage for gradually increasing the voltage. The regulator of the present invention is arranged in an external input / output circuit area assigned to a semiconductor chip, and one charge pump circuit is assigned to a plurality of output transistors. As a result, it is not necessary to provide a specific charge pump circuit for each of the plurality of output transistors. Therefore, it is possible to prevent an inrush current from occurring while suppressing an increase in the area of the semiconductor chip.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, in the regulator that steps down the external power supply voltage, it is possible to prevent the occurrence of an inrush current while suppressing an increase in the area of the semiconductor chip.

1. First, an outline of a typical embodiment of the invention disclosed in the present application will be described. Reference numerals in the drawings referred to in parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

  [1] A semiconductor integrated circuit according to a typical embodiment of the present invention has an internal power supply voltage (VCC) supplied from the outside to an external input / output circuit area (2) assigned to a semiconductor chip (1). A regulator (20) for generating a power supply voltage (VDD) is included. The regulator includes an output transistor that outputs the internal power supply voltage from the external power supply voltage by negative feedback control, and an output current of the output transistor before the negative feedback control is activated when the external power supply voltage is turned on And a charge pump circuit for forming a voltage for gradually increasing the voltage. In the regulator, one charge pump circuit is assigned to the plurality of output transistors. Therefore, it is possible to prevent the inrush current from occurring while suppressing the area of the semiconductor chip.

  A semiconductor integrated circuit according to another aspect of the present invention has an input / output circuit region in which a circuit connected to the external connection electrode (10) of the semiconductor chip is formed. The external input / output circuit area includes a regulator that generates an internal power supply voltage based on an external power supply voltage supplied from the outside. The regulator includes a drive circuit (20D_1 to 20D_4) and a start circuit (20A or 20B), and the drive circuit includes an output transistor that outputs the internal power supply voltage from the external power supply voltage by negative feedback control. The startup circuit has a charge pump circuit that forms a voltage for gradually increasing the output current of the output transistor before the negative feedback control is activated when the external power supply voltage is applied. A plurality of the drive circuits are commonly connected to one starter circuit.

  A semiconductor integrated circuit according to still another aspect of the present invention includes a plurality of external connection electrodes provided on an outer periphery of a semiconductor chip, an input / output circuit region in which a circuit connected to the external connection electrodes is formed, And a core circuit region (3) disposed inside the entry output circuit region. The input / output circuit region includes a regulator that forms an internal power supply voltage for operating the core circuit based on an external power supply voltage supplied from the external power supply terminal. The regulator includes a drive circuit and a start-up circuit, and the drive circuit includes an output transistor that outputs the internal power supply voltage from the external power supply voltage when the mutual conductance is controlled by negative feedback control. The start-up circuit forms a voltage for gradually increasing the output current of the output transistor based on the external power supply voltage instead of the negative feedback control for a predetermined time when the external power supply voltage is turned on It has a circuit. A plurality of the drive circuits are commonly connected to one starter circuit.

  As one specific form, the drive circuit is disposed in the vicinity of the external connection electrode (10_S) assigned to the connection of the stabilization capacitor of the internal power supply voltage. According to this, an undesired voltage drop due to the wiring connecting the external connection electrode and the drive circuit can be reduced. This undesired voltage drop leads to a decrease in the charge level of the stabilizing capacitor. In this case, when the control by the starting circuit is finished and the circuit operation is started by supplying power from the output transistor exclusively, the internal power supply voltage may be lowered and an inrush current may be generated.

  As another specific form, the activation circuit is arranged in a region located at the four corners of the semiconductor chip in the input / output circuit region. Therefore, the expansion of the area of the semiconductor chip can be efficiently suppressed by disposing the startup circuit at the four corners of the semiconductor chip, which is normally the ineffective region (2B) where no transistor or the like is disposed. In addition, since the operation of the core circuit is before starting, there is no problem even if the wiring connecting the driving circuit and the starting circuit is long or intersects with the power supply wiring in the input / output circuit region.

  As yet another specific form, the activation circuit is arranged in the vicinity of the drive circuit. Therefore, when it is necessary to insert a MOS transistor for electrostatic breakdown protection in the invalid area, it can be arranged in an area excluding the portions corresponding to the four corners in the input / output circuit area. However, the area of the semiconductor chip is larger than the area of the semiconductor chip.

2. Details of Embodiments Embodiments will be further described in detail.

  FIG. 1 shows a configuration diagram of a data processor which is an example of a semiconductor integrated circuit according to the present invention. The data processor according to the present invention includes, for example, an external connection terminal region 1_a on the outermost side, an input / output circuit region 2 and a core circuit region 3 in the central portion on the inner side thereof.

  A plurality of external connection terminals 10 connected to the outside are disposed in the external connection terminal region 1_a. In the input / output circuit area 2, an input buffer connected to an external terminal, an output buffer, an input / output buffer (hereinafter simply referred to as a buffer) and the like are arranged. The core circuit area 3 includes various processing circuits for outputting processing based on information input via a buffer and outputting the processing result to the outside. Here, a central processing unit (CPU) 30 that decodes and executes a fetched instruction, a random access memory (RAM) 31 used for a work area of the central processing unit 30, and an operation program for the central processing unit 30 A read only memory (ROM) 32 for storing the above and a system controller (SYSCONT) 33 are representatively shown in the core circuit area 3. The system controller 33 is supplied with a reset signal / RES (symbol / means a low enable signal), a mode signal, and the like from the outside, and performs a reset control, a mode control, and the like in the data processor according to the signal.

  The data processor steps down the external power supply voltage VCC supplied from the external power supply terminal 10_V assigned to a part of the external connection terminal 10, and the central processing unit 30, the random access memory 31, the read It has a regulator that generates an internal power supply voltage VDD that is used as an operating power supply for various processing circuits such as the only memory 32. In FIG. 1, the regulator is not particularly limited, and includes a starter circuit (ACT) 20A and four drive circuits (DRV) 20D_1 to 20D_4. Before describing the arrangement relationship between the activation circuit 20A and the drive circuits 20D_1 to 20D_4 on the data processor, the circuit configuration of the regulator will be described based on FIG.

  In FIG. 2, one starter circuit 20A and four drive circuits 20D_1 to 20D_4 are collectively referred to as a regulator 20. The drive circuit 20D_1 includes a drive PMOS transistor M1 composed of a p-channel MOS transistor (hereinafter also referred to as a PMOS transistor) capable of supplying a current from the terminal of the external power supply voltage VCC to the terminal of the internal power supply voltage VDD. The gate of the driving PMOS transistor M1 is connected to the output of the differential amplifier 21 or the activation circuit 20A via a selection switch DSW1. In the differential amplifier 21, for example, a reference voltage SV of 1.5 V, which is the target voltage of the internal power supply voltage VDD, is supplied to the inverting input terminal (−), and the internal power supply voltage VDD is supplied to the non-inverting input terminal (+). Supplied. The signal A output by the differential amplifier 21 has a voltage value for adjusting the load current so that the internal power supply voltage VDD and the reference voltage SV are equal. When the output of the differential amplifier 21 is connected to the gate of the drive PMOS transistor M1 by the selection switch DSW1, the drive PMOS transistor M1 is subjected to negative feedback control by the output of the differential amplifier 21, and the internal power supply voltage VDD Tries to be made equal to the reference voltage SV. The selection switch DSW1 is switch-controlled by a control circuit DCONT.

  The control circuit DCONT detects that the reset signal / RES is set to a low level and the internal power supply voltage VDD is lower than the potential of the reference voltage SV, and connects the gate of the driving PMOS transistor M1 to the start circuit 20A. Connect to output. Thereafter, when the control circuit DCONT once detects that the internal power supply voltage VDD is equal to or higher than the reference voltage SV, the control circuit DCONT always connects the output of the differential amplifier 21 to the gate of the drive PMOS transistor M1. The selection switch DSW1 is controlled. The drive circuits 20D_2 to 20D_4 also perform the same operation as the drive circuit 20D_1.

  The starting circuit 20A has a series circuit of a PMOS transistor M2 and a resistor R between the external power supply voltage VCC and the ground GND. The gate of the start PMOS transistor M2 is connected to the output of the differential amplifier 22. The output voltage N1 of the charge pump circuit is supplied to the inverting input terminal (−) of the differential amplifier 22, and the voltage at the coupling node of the start PMOS transistor M2 and the resistor R is fed back to the non-inverting input terminal (+). Entered. In the charge pump circuit, a plurality of pairs of switch circuits ASW1 and ASW2 that are switched in a complementary manner are arranged in series, and storage capacitors C1 to Cn are connected between the connection point of each switch circuit and the ground potential GND. . One end of the series path of the switch circuit is coupled to the external power supply voltage VCC, and the other end is coupled to the inverting input / output terminal (−) of the differential amplifier 22. In the figure, a pair of the switch circuits ASW1 and ASW2 are illustrated, but a plurality of sets are actually arranged. The switches of each pair are complementarily controlled by clock signals CKP and / CKP that are 180 ° out of phase. The clock signal CKP is generated by inverting the output of the oscillator OSC. The clock signal / CKP is generated by inverting the clock signal CKP. The oscillation operation of the oscillator OSC is controlled by the control circuit ACONT.

  The control circuit ACONT detects that the reset signal / RES is set to the low level and the internal power supply voltage VDD is lower than the potential of the reference voltage SV (the low level of the signal A), and sends it to the oscillator OSC. Starts oscillating operation. Thereafter, when the control circuit ACONT once detects that the voltage level of the internal power supply voltage VDD has become equal to or higher than the potential of the reference voltage SV, the control circuit ACONT ends the oscillation operation by the oscillator OSC. When the oscillation operation by the oscillator OSC is started, the charge pump circuit supplies the charge from the previous-stage switch in the on state to the storage capacitor of the next stage and stores it in synchronization with the clock signals CKP and / CKP. The transferred charge is further transferred to the subsequent stage through the subsequent switch in the ON state. As a result, when the charge is transferred to the final stage, a voltage corresponding to the charge accumulated at the final stage is applied to the inverting input terminal (−) of the differential amplifier 22. As the voltage at the inverting input terminal (−) of the differential amplifier 22 increases, the mutual conductance of the startup PMOS transistor M2 increases and the current I1 gradually increases. In a state where the gate of the start PMOS transistor M2 and the gate of the drive PMOS transistor M1 are connected, the drive PMOS transistor M1 flows a current I2 proportional to the current I1 flowing through the start PMOS transistor M2. As a result, the current I2 flowing through the drive PMOS transistor M1 increases due to the boosting operation of the charge pump circuit, and the internal power supply voltage VDD approaches the reference voltage SV. When the internal power supply voltage VDD becomes the reference voltage SV, the control circuit ACONT stops the oscillation operation by the oscillator OSC.

  As described above, when the reset state is instructed by the reset signal / RES, the generation operation of the internal power supply voltage VDD is started. When the control circuits DCONT and ACONT detect that the internal power supply voltage VDD has reached a potential equal to or higher than the reference voltage SV, the gate of the drive PMOS transistor M1 is connected to the output of the start circuit 20A, and the start The current I1 increases according to the boosting operation of the circuit 20A. Accordingly, when the internal power supply voltage VDD reaches the reference voltage SV, the driving PMOS transistor M1 is switched to negative feedback control by the differential amplifier 21. Therefore, it is possible to prevent an inrush current from occurring when the external power supply voltage VCC is turned on.

  FIG. 3 illustrates an operation timing chart of the regulator 20. Between time 0 and X (μs), the current I2 is gradually increased by the control of the activation circuit 20A, and the internal power supply voltage VDD is gradually increased accordingly. When the internal power supply voltage VDD reaches the reference voltage SV (time X (μs)), the connection to the gate of the drive PMOS transistor M1 is switched from the output from the activation circuit 20A to the output of the differential amplifier 21. The internal power supply voltage VDD is controlled to be a constant voltage by negative feedback control using the differential amplifier 21. Thereafter, when the reset signal / RES is set to a high level and a reset release is instructed, an instruction execution operation by the central processing unit 30 is started. At this stage, since the internal power supply voltage VDD is controlled to be constant at the reference pressure SV, the occurrence of an inrush current when the power is turned on is prevented.

  Next, the arrangement of the activation circuit 20A and the drive circuits 20D_1 to 20D_4 will be described. The drive circuits 20D_1 to 20D_4 shown in FIG. 1 are arranged at positions excluding portions corresponding to the four corners of the semiconductor chip 1 in the input / output circuit region 2 (hereinafter, this region is simply referred to as an effective region 2A). ). The activation circuit 20A is arranged at a position corresponding to the four corners of the semiconductor chip 1 in the input / output circuit area 2 (hereinafter, this area is simply referred to as an invalid area 2B). One starter circuit 20A including a charge pump circuit having a large capacity is commonly connected to the four drive circuits 20D_1 to 20D_4. Therefore, the area occupied by the regulator in the effective area 2A can be reduced as compared with the case where a total of four sets of regulators each including the starter circuit and the drive circuit are arranged on each side of the input / output circuit area 2. . The drive circuits 20D_1 to 20D_4 are arranged in the effective area 2A, in the vicinity of the external connection terminal 10_S assigned to the connection of the stabilization capacitor, in the area not assigned to the arrangement of the buffer or the like. Accordingly, each wiring for connecting the external connection terminal 10_S and the driving circuits 20D_1 to 20D_4 can be shortened, so that an undesired voltage drop due to the wiring can be reduced. That is, when the wiring becomes longer, the charging level of the stabilization capacitor is lowered. Therefore, when the output of the activation circuit 20A is terminated and the circuit operation is started by the output of the differential amplifier 21, the internal power supply voltage VDD An inrush current is generated due to a decrease in. The activation circuit 20A is disposed in the invalid area 2B and is commonly connected to the drive circuits 20D_1 to 20D_4. Therefore, by utilizing the invalid region 2B of the semiconductor chip 1 that is not originally used, it is possible to minimize the expansion of the area occupied by the regulator in the effective region 2A.

  In the input / output circuit region 2, wirings for connecting the activation circuit 20 </ b> A and the driving circuits 20 </ b> D_ <b> 1 to 20 </ b> __ <b> 4 and power supply wirings 23 are installed. Although not shown in the figure, the input / output circuit region 2 includes signal wirings for connecting the external connection terminal region 1-a and the core circuit region 3 through the buffers and the like. It is installed crossing. An output of the differential amplifier 22 of the activation circuit 20A is connected to the drive circuits 20D_1 to 20D_4 via a signal wiring 23_S (see FIG. 2) assigned to a part of the wiring 23. Such signal wiring 23_S is installed so as to intersect with other signal wirings and the like in the same manner as described above. The activation circuit 20A operates during a period in which the reset signal / RES is at a low level, and the operation after the reset is released by the high level of the reset signal / RES is stopped. Therefore, the signal wiring 23_S during the reset period is not affected by other signal wirings, and the signal wiring 23_S after the reset is released does not affect the signal wiring such as the buffer.

  FIG. 4 shows a configuration diagram of a data processor which is another example of the semiconductor integrated circuit according to the present invention. The activation circuit 20B is disposed in the effective area 2A, for example, adjacent to the drive circuit 20D_1. Other configurations are the same as in FIG. Accordingly, it is possible to suppress an increase in the area occupied by the regulator in the effective region 2A. However, the area occupied by the regulator is larger than in the case of FIG. 1 in which the activation circuit 20A is arranged in the invalid region 2B.

  FIG. 5 illustrates regulator occupancy in the effective area 2A. In the figure, the occupancy ratio RG_P of a semiconductor chip by a regulator in which one set of regulators each including a starter circuit and a drive circuit is arranged on each side, and four drive circuits 20D_1 in one starter circuit 20B. -20D_4 is commonly connected, and the semiconductor chip occupation ratio RG_J by the regulator 20 arranged in the effective area 2A of the input / output circuit area 2 is shown. Further, four drive circuits 20D_1 to 20D_4 are commonly connected to one starter circuit 20A, and four drive circuits 20D_1 to 20D_4 are arranged in the effective area 2A of the input / output circuit area 2. The occupancy ratio RG_C of the semiconductor chip by the regulator 20 in which the activation circuit 20A is arranged in the invalid area 2B is shown. The area occupied by each regulator in the semiconductor chip 1 can be reduced to 55% for the occupation ratio RG_J and to 73% for the occupation ratio RG_C as compared to the occupation ratio RG_P. Accordingly, four drive circuits are commonly connected to one activation circuit and each is arranged in the effective area 2A. Further, one activation circuit is arranged in the invalid area 2B, and the effective area 2A is arranged. By commonly connecting to the four drive circuits arranged in the semiconductor chip, it is possible to minimize the expansion of the area of the semiconductor chip.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  The regulator in which four drive circuits are commonly connected to one starter circuit has been described above, but the number of common drive circuits is not particularly limited and can be changed as appropriate. When two sets of regulators in which two drive circuits are connected in common are used, activation circuits may be installed in two invalid areas. The activation circuit may be arranged at any position in the four corners of the semiconductor chip. The detailed circuit configuration of the regulator is not limited to the above description, and can be changed as appropriate.

  The operation control of the regulator is not limited to the case where only the reset signal is used, and a standby signal may be used. For example, if the standby signal is set to the standby state at the low level, the ring oscillator is started to oscillate when the standby signal is set to the high level thereafter to start the regulator. The reset instruction state by the reset signal may be canceled at a timing after the internal power supply voltage VDD generated by the regulator reaches a specified voltage. The semiconductor integrated circuit of the present invention is not limited to the semiconductor integrated circuit having the external connection electrode on the outer peripheral portion of the semiconductor chip and having the input / output circuit region on the inner side as described above. For example, a semiconductor integrated circuit having an external connection electrode at the center of the semiconductor chip and an input / output circuit region around it may be used.

It is a block diagram which shows the structure of the data processor which is an example of the semiconductor integrated circuit which concerns on this invention. It is a circuit diagram of the regulator which concerns on this invention. 3 is an operation timing chart of the regulator 20. It is a block diagram which shows the structure of the data processor which is another example of the semiconductor integrated circuit which concerns on this invention. It is a comparative explanatory view showing the occupation rate of the area of the regulator in the effective area of the semiconductor chip.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Input / output circuit area 3 Core circuit area 10 External connection terminal 20 Regulator 21 Drive circuit differential amplifier 22 Start-up circuit differential amplifier 23 Wiring 30 Central processing unit 31 Random access memory 32 Read only memory 33 System Controller 1_a External Connection Terminal Area 2A Effective Area 2B Invalid Area 10_S External Connection Terminal Assigned to Stabilizing Capacitance 10_V External Power Supply Voltage 20A Start Circuit 20B Start Circuit 20D_1 to 20D_4 Drive Circuit 23_S Signal Wiring

Claims (6)

A semiconductor integrated circuit having a regulator that generates an internal power supply voltage based on an external power supply voltage supplied from the outside to an external input / output circuit area assigned to the semiconductor chip,
The regulator includes an output transistor that outputs the internal power supply voltage from the external power supply voltage by negative feedback control, and an output of the output transistor before the negative feedback control is activated when the external power supply voltage is turned on. A charge pump circuit for forming a voltage for gradually increasing the current;
A semiconductor integrated circuit in which one charge pump circuit is assigned to a plurality of output transistors. A semiconductor integrated circuit having an input / output circuit region in which a circuit connected to an external connection electrode of a semiconductor chip is formed,
The input / output circuit region includes a regulator that forms an internal power supply voltage based on an external power supply voltage supplied from the outside,
The regulator has a drive circuit and a startup circuit,
The drive circuit has an output transistor that outputs the internal power supply voltage from the external power supply voltage by negative feedback control,
The startup circuit has a charge pump circuit that forms a voltage for gradually increasing the output current of the output transistor before the negative feedback control is activated when the external power supply voltage is turned on,
A semiconductor integrated circuit in which a plurality of driving circuits are commonly connected to one starting circuit. A plurality of external connection electrodes provided on the outer periphery of the semiconductor chip;
An input / output circuit region in which a circuit connected to the external connection electrode is formed;
A semiconductor integrated circuit having a core circuit region disposed inside the input / output circuit region,
A regulator for forming an internal power supply voltage for operating the core circuit based on an external power supply voltage supplied from an external power supply terminal assigned to the external connection electrode in the input / output circuit region;
The regulator has a drive circuit and a startup circuit,
The drive circuit has an output transistor that outputs the internal power supply voltage from the external power supply voltage by controlling the mutual conductance by negative feedback control,
The start-up circuit forms a voltage for gradually increasing the output current of the output transistor based on the external power supply voltage instead of the negative feedback control for a predetermined period when the external power supply voltage is turned on Have a circuit,
A semiconductor integrated circuit in which a plurality of driving circuits are commonly connected to one starting circuit.   4. The semiconductor integrated circuit according to claim 3, wherein the drive circuit is disposed in the vicinity of the external connection electrode assigned to the connection of the stabilization capacitor of the internal power supply voltage.   5. The semiconductor integrated circuit according to claim 3, wherein the activation circuit is arranged in a region located at four corners of the semiconductor chip in the input / output circuit region.   The semiconductor integrated circuit according to claim 3, wherein the starting circuit is disposed in the vicinity of the driving circuit.

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