JP5166716B2 - Semiconductor chip laminate and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor chip laminate in which a part of an end of an upper layer semiconductor chip protrudes toward a side beyond an end of a lower layer semiconductor chip and the deformation of the upper layer semiconductor chip is suppressed to prevent inclination of the upper layer semiconductor chip. <P>SOLUTION: The semiconductor chip laminate 1 is provided with a substrate or a first semiconductor chip 2 and second and third semiconductor chips 3, 4. At least a part of an end 4a of the third semiconductor chip 4 protrudes in the side beyond the end 3a of the second semiconductor chip 3. A supporting layer 9 is formed between the bottom surface of a protruding portion 4A of the third semiconductor chip 4 and the top surface of the substrate or the top surface of the first semiconductor chip 2. The supporting layer 9 includes particles 10 for regulating a gap between the first and third semiconductor chips 2 and 4. <P>COPYRIGHT: (C)2008,JPO&amp;INPIT

Description

  The present invention relates to a semiconductor chip stacked body formed by stacking a plurality of semiconductor chips, and more specifically, a semiconductor in which an end portion of an upper layer semiconductor chip projects laterally from an end portion of a lower layer semiconductor chip. The present invention relates to a chip stack and a method for manufacturing the semiconductor chip stack.

  A semiconductor chip laminated body in which a plurality of semiconductor chips having electrodes are laminated via an adhesive layer is known. The electrodes of the semiconductor chip stacked body are electrically connected to connected parts such as other semiconductor chips and substrates by wire bonding.

  Conventionally, by stacking a dummy semiconductor chip on the upper surface of a semiconductor chip having electrodes, a space is provided on the electrode of the lower semiconductor chip, the connection height of the wire is secured, and the electrodes are connected.

  In recent years, there has been a strong demand for high-density mounted semiconductor chip stacks, and semiconductor chip stacks having an overhang structure have been used. In a semiconductor chip stacked body having an overhang structure, semiconductor chips are stacked such that the end of the upper semiconductor chip protrudes to the side of the end of the lower semiconductor chip. Thereby, a space for connecting a wire is provided above the electrode of the semiconductor chip. Therefore, in the semiconductor chip stacked body having the overhang structure, since the dummy semiconductor chips do not have to be stacked in order to ensure the connection height of the wires, the stacked thickness can be reduced.

As an example of the semiconductor chip stacked body having the overhang structure, Patent Document 1 below discloses a semiconductor device in which first to third semiconductor chips having a rectangular planar shape are stacked on a substrate. In Patent Document 1, the first to third semiconductor chips are stacked so that the length directions of the upper and lower semiconductor chips facing each other are orthogonal to each other. Spacers are provided between the second and third semiconductor chips stacked on the first semiconductor chip. Due to the spacer, the length of the overhanging portion of the upper third semiconductor chip, that is, the length of the overhang portion is set to 200 μm or more. Below the overhang portion of the third semiconductor chip, the first bonding pad at the edge of the first semiconductor chip is connected to the bonding pad of the substrate. A synthetic resin is filled between the upper surface of the first semiconductor chip and the lower surface of the overhang portion of the third semiconductor chip.
JP 2006-66816 A

  In Patent Document 1, since the synthetic resin is filled between the upper surface of the first semiconductor chip and the lower surface of the overhang portion of the third semiconductor chip, the weight when connecting the bonding wires is the third. The third semiconductor chip is prevented from being broken or deformed when it is added to the edge of the semiconductor chip.

  However, in Patent Document 1, a synthetic resin is filled between the upper surface of the first semiconductor chip and the lower surface of the overhang portion of the third semiconductor chip. If the filling amount of the synthetic resin is too small, the thickness of the synthetic resin may not be uniform, the edge of the third semiconductor chip may be bent toward the second semiconductor chip, and the third semiconductor chip may be inclined. was there. Even if the filling amount of the synthetic resin is controlled with high accuracy, the synthetic resin may be pushed out or deformed depending on the pressure applied when the third semiconductor chips are stacked. There was a tilt. Furthermore, the synthetic resin is easily contracted, and the thickness of the synthetic resin is reduced by the contraction of the synthetic resin, and the third semiconductor chip may be deformed.

  Therefore, there has been a strong demand for further suppressing the cracking and deformation of the third semiconductor chip.

  An object of the present invention is a semiconductor chip stacked body in which at least a part of an end portion of an upper semiconductor chip protrudes laterally from an end portion of a lower semiconductor chip in view of the above-described state of the prior art. An object of the present invention is to provide a semiconductor chip stacked body in which deformation of the upper semiconductor chip is suppressed and the upper semiconductor chip is prevented from tilting, and a method for manufacturing the semiconductor chip stacked body.

The present invention includes a substrate or first semiconductor chip having an electrical connection terminal on the top surface, a second semiconductor chip stacked in a region where the electrical connection terminal on the top surface of the substrate or the first semiconductor chip is not provided, And a third semiconductor chip stacked on the upper surface of the second semiconductor chip, wherein at least a part of the end of the third semiconductor chip is more than the end of the second semiconductor chip. An electrical connection terminal provided on the upper surface of the substrate or the first semiconductor chip is located below the projecting portion of the third semiconductor chip. The electrical connection terminal is located on the substrate or the first semiconductor chip. Bonding wires are connected to electrical connection terminals provided on the upper surface of the chip, and the lower surface of the protruding portion of the third semiconductor chip and the upper surface of the substrate or the first semiconductor A support layer is filled between the top surface of the semiconductor chip and the end of the second semiconductor chip, and the support layer is formed using particles and a resin material. regulates the distance between the first semiconductor chip and the third semiconductor chip, and look-containing particles in contact with the upper surface or lower surface of the upper surface of the first semiconductor chip third semiconductor chip substrate, the support layer, the substrate Alternatively, between the electrical connection terminal provided on the upper surface of the first semiconductor chip and the end of the second semiconductor chip, the electrical connection terminal is filled so that the particles do not reach the electrical connection terminal. It is characterized by being arranged between the electrical connection terminal provided on the upper surface of the semiconductor chip and the end of the second semiconductor chip so as not to reach the electrical connection terminal .

In a specific aspect of the semiconductor chip laminated body according to the present invention, the elastic modulus at 175 ° C. Tree fat material is in the range of 50MPa～1GPa.

A method for manufacturing a semiconductor chip laminate according to the present invention is a method for manufacturing a semiconductor chip laminate according to the present invention, wherein a substrate having an electrical connection terminal on an upper surface or an electrical connection terminal on an upper surface of a first semiconductor chip is provided. A step of laminating the second semiconductor chip in a region that is not, a step of connecting a bonding wire to an electrical connection terminal provided on the upper surface of the substrate or the first semiconductor chip, and a step of connecting the substrate or the first semiconductor chip. A step of disposing a material constituting a support layer including particles and a resin material on the upper surface; and at least a part of an end portion of the third semiconductor chip projects laterally from the end portion of the second semiconductor chip. And the second semiconductor so that the electrical connection terminal provided on the upper surface of the substrate or the first semiconductor chip is located below the projecting portion of the third semiconductor chip. A third semiconductor chip is stacked on the upper surface of the substrate and a support layer is formed between the lower surface of the protruding portion of the third semiconductor chip and the upper surface of the substrate or the upper surface of the first semiconductor chip. The support layer is filled in contact with the end of the second semiconductor chip, and the support layer regulates the distance between the substrate or the first semiconductor chip and the third semiconductor chip, and the upper surface of the substrate or look-containing particles in contact with the lower surface of the upper surface of the first semiconductor chip third semiconductor chip, the support layer, an electrical connection is provided on the upper surface of the substrate or the first semiconductor chip terminals and the second semiconductor chip It is filled so as not to reach the electrical connection terminal between the end portions, and the particles are formed between the electrical connection terminal provided on the upper surface of the substrate or the first semiconductor chip and the end portion of the second semiconductor chip. In between, lead to the electrical connection terminal Characterized in that it comprises the step of obtaining a semiconductor chip stack being arranged odd.

  In a specific aspect of the method for manufacturing a semiconductor chip stacked body according to the present invention, the substrate or the first portion between the electrical connection terminal provided on the upper surface of the substrate or the first semiconductor chip and the end portion of the second semiconductor chip. The material constituting the support layer is disposed on the upper surface of one semiconductor chip.

  In the semiconductor chip stacked body according to the present invention, at least a part of the end portion of the third semiconductor chip projects laterally from the end portion of the second semiconductor chip, and the projecting portion of the third semiconductor chip. A support layer is filled between the lower surface of the substrate and the upper surface of the substrate or the upper surface of the first semiconductor chip, and the support layer contains particles that regulate the distance between the first semiconductor chip and the third semiconductor chip. As a result, the third semiconductor chip can be prevented from being deformed or the third semiconductor chip from being tilted.

  When the support layer is composed of particles and a resin material, and the elastic modulus of the resin material at 175 ° C. is in the range of 50 MPa to 1 GPa, the adhesion between the support layer and the substrate or the semiconductor chip is enhanced. The deformation of the third semiconductor chip can be further suppressed. In addition, when the support layer is formed using the resin material, the resin material has an appropriate fluidity, so that the resin material is prevented from reaching the electrical connection terminal provided on the upper surface of the substrate or the first semiconductor chip. be able to.

  When the particles are coated particles having resin particles and a layer covering the resin particles, and the support layer is the coated particles, the particles can be easily arranged at a predetermined position when the particles are arranged. Can do. Further, the third semiconductor chip can be prevented from being tilted by the particles.

  When the particles are arranged so as not to reach the electrical connection terminal between the electrical connection terminal provided on the upper surface of the substrate or the first semiconductor chip and the end of the second semiconductor chip, the substrate Alternatively, in the electrical connection terminal of the first semiconductor chip, it is possible to prevent the wire from being poorly connected due to the particles.

  When the support layer is provided so as not to reach the electrical connection terminal between the electrical connection terminal provided on the upper surface of the substrate or the first semiconductor chip and the end of the second semiconductor chip, In the electrical connection terminals of the substrate or the first semiconductor chip, it is possible to prevent the connection failure of the wires due to the support layer.

  In the method for manufacturing a semiconductor chip stacked body according to the present invention, the step of disposing the material constituting the support layer on the upper surface of the substrate or the first semiconductor chip, and at least a part of the end portion of the third semiconductor chip is the first An electrical connection terminal provided on the upper surface of the substrate or the first semiconductor chip is positioned so as to project laterally from the end of the second semiconductor chip and below the projecting portion of the third semiconductor chip. The third semiconductor chip is stacked on the upper surface of the second semiconductor chip, and the supporting layer is formed. Therefore, the lower surface of the protruding portion of the third semiconductor chip, and the substrate A support layer can be provided between the upper surface and the upper surface of the first semiconductor chip so as not to reach the electrical connection terminal. Therefore, the support layer can prevent the third semiconductor chip from being cracked or deformed, and the third semiconductor chip can be prevented from being tilted.

  When the material constituting the support layer is arranged on the upper surface of the substrate or the first semiconductor chip between the electrical connection terminal provided on the upper surface of the substrate or the first semiconductor chip and the end of the second semiconductor chip The support layer may be configured so as not to reach the electrical connection terminal between the electrical connection terminal provided on the upper surface of the substrate or the first semiconductor chip and the end portion of the second semiconductor chip. Therefore, it is possible to prevent the poor connection of the wires due to the support layer in the electrical connection terminals of the substrate or the first semiconductor chip.

  Hereinafter, the present invention will be clarified by describing specific embodiments of the present invention with reference to the drawings.

  In FIG. 1, the semiconductor chip laminated body which concerns on one Embodiment of this invention is shown with a partial notch front sectional drawing.

  As shown in FIG. 1, the semiconductor chip laminate 1 is a laminate in which second and third semiconductor chips are laminated on a substrate or a first semiconductor chip. In the present embodiment, the first to third semiconductor chips 2 to 4 are stacked to form the semiconductor chip stacked body 1, and the semiconductor chip stacked body 1 is stacked on the substrate 5. On the substrate 5, the first semiconductor chip 2, the second semiconductor chip 3, and the third semiconductor chip 4 are stacked in this order.

  The substrate 5 and the first to third semiconductor chips 2 to 4 are bonded via the adhesive layer 6. Although not shown, the adhesive layer 6 includes spacer particles. Since the thickness of the adhesive layer can be made constant and the upper semiconductor chip can be prevented from tilting, the adhesive layer preferably contains spacer particles. However, the adhesive layer may not contain spacer particles. The particle diameter of the spacer particles is not particularly limited, but is smaller than the thickness of the semiconductor chip, for example, about 10 μm.

  The first to third semiconductor chips 2 to 4 have a rectangular planar shape. As shown in a schematic perspective view of the stacked state of the first and second semiconductor chips in FIG. 2, the first to third semiconductor chips 2 to 4 have the length directions of the upper and lower semiconductor chips facing each other. They are stacked in a cross shape so as to be orthogonal. The size of the semiconductor chip having a rectangular planar shape is not particularly limited, but is, for example, about 5 mm to 10 mm × 7 to 15 mm in width. Although it does not specifically limit as thickness of a semiconductor chip, For example, it is about 50-100 micrometers.

  The third semiconductor chip 4 is positioned on the upper surface of the second semiconductor chip 3 so that at least a part of the end 4a of the third semiconductor chip 4 protrudes to the side of the end 3a of the second semiconductor chip 3. Are stacked. Both side end portions 4a in the length direction of the third semiconductor chip 4 protrude beyond the end portion 3a of the second semiconductor chip 3, and the semiconductor chip stacked body 1 has an overhang structure. The length of the protruding portion 4A of the third semiconductor chip 4, that is, the overhang length is not particularly limited, but is, for example, about 0.5 to 2.5 mm.

  Note that the shapes of the substrate or the first semiconductor chip and the second and third semiconductor chips are not particularly limited. For example, as shown in a schematic perspective view in FIG. 3, the substrate or the first semiconductor chip 11 and the second and third semiconductor chips 12 and 13 may have a square planar shape. In addition, as shown in FIG. 3, the substrate or the first semiconductor chip 11 and the second and third semiconductor chips 12 and 13 are stacked at different positions so that at least one of the end portions of the third semiconductor chip is stacked. The semiconductor chip stacked body may be configured such that the portion protrudes laterally from the end of the second semiconductor chip. The size of the semiconductor chip having a square planar shape is not particularly limited, but is about 5 to 25 mm in length and width.

  The first semiconductor chip 2 has an electrical connection terminal 2a on the upper surface. The electrical connection terminal 2 a is located below the protruding portion 4 A of the third semiconductor chip 4. The electrical connection terminals 2 a are provided on both side edges in the length direction of the first semiconductor chip 2.

  The end of the electrical connection terminal 2a and the end 3a of the second semiconductor chip 3 are spaced apart from each other, and the second surface of the upper surface of the first semiconductor chip 2 is not provided with the electrical connection terminal 2a. The semiconductor chips 3 are stacked. The second semiconductor chip 3 is stacked between the electrical connection terminals 2 a provided at both side edges in the length direction of the first semiconductor chip 2. The electrical connection terminal 2 a and the electrode pad 5 a on the substrate 5 are connected by a bonding wire 7.

  In the protruding portion 4A of the third semiconductor chip 4, the third semiconductor chip 4 has an electrical connection terminal 4b on the upper surface. The electrical connection terminals 4 b are provided at both side edges in the length direction of the third semiconductor chip 4. The electrical connection terminal 4 b and the electrode pad 5 b on the substrate 5 are connected by a bonding wire 8. Although not shown, electrical connection terminals are also provided on both side edges in the length direction of the second semiconductor chip 3, and the electrical connection terminals and electrode pads on the substrate 5 are connected by bonding wires. Has been.

  In the semiconductor chip stacked body 1, the support layer 9 is filled between the lower surface of the protruding portion 4 </ b> A of the third semiconductor chip 4 and the upper surface of the first semiconductor chip 2. In the present embodiment, the support layer 9 does not reach the electrical connection terminal 2 a between the electrical connection terminal 2 a provided on the upper surface of the first semiconductor chip 2 and the end portion 3 a of the second semiconductor chip 3. Is provided. Thus, the support layer is provided so as not to reach the electrical connection terminal between the electrical connection terminal provided on the upper surface of the substrate or the first semiconductor chip and the end portion of the second semiconductor chip. It is preferable. In this case, in the electrical connection terminal of the substrate or the first semiconductor chip, it is possible to prevent the poor connection of the wires due to the support layer.

  The support layer 9 includes particles 10 and 10. The particles 10 and 10 have a particle diameter that is approximately equal to or slightly larger than the thickness of the second semiconductor chip 3. The distance between the first semiconductor chip 2 and the third semiconductor chip 4 is regulated by the particles 10 and 10. The particles 10 and 10 are provided between the electrical connection terminal 2 a provided on the upper surface of the first semiconductor chip 2 and the end portion 3 a of the second semiconductor chip 3 so as not to reach the electrical connection terminal 2 a. Yes. As described above, the particles are provided so as not to reach the electrical connection terminal between the electrical connection terminal provided on the upper surface of the substrate or the first semiconductor chip and the end of the second semiconductor chip. Is preferred. In this case, it is possible to prevent the connection failure of the wire due to the particles in the electrical connection terminal of the substrate or the first semiconductor chip.

  In the semiconductor device disclosed in Patent Document 1 described above, the synthetic resin is filled between the upper surface of the first semiconductor chip and the lower surface of the overhang portion of the third semiconductor chip. If the filling amount of the synthetic resin is too small, the thickness of the synthetic resin may not be uniform, the edge of the third semiconductor chip may be bent toward the second semiconductor chip, and the third semiconductor chip may be inclined. was there. Even if the filling amount of the synthetic resin is controlled with high accuracy, the synthetic resin may be pushed out or deformed depending on the pressure applied when the third semiconductor chips are stacked. There was a tilt. Furthermore, the synthetic resin is easily contracted, and the thickness of the synthetic resin is reduced by the contraction of the synthetic resin, and the third semiconductor chip may be deformed.

  On the other hand, in the present invention, the support layer is filled between the lower surface of the protruding portion of the third semiconductor chip and the upper surface of the substrate or the upper surface of the first semiconductor chip, and the support layer contains particles. Thus, the third semiconductor chip can be prevented from being deformed, and the third semiconductor chip can be prevented from being inclined.

  Next, taking the semiconductor chip laminate 1 described above as an example, a method for manufacturing the semiconductor chip laminate will be described.

  First, as shown in FIG. 4A, the first semiconductor chip 2 is laminated on the substrate 5 via the adhesive layer 6 and bonded. Further, the second semiconductor chip 3 is laminated and bonded to the region where the electrical connection terminal 2 a is not provided on the upper surface of the first semiconductor chip 2 via the adhesive layer 6.

  Next, as shown in FIG. 4B, the electrical connection terminal 2 a and the electrode pad 5 a on the substrate 5 are connected by the bonding wire 7.

  Next, as shown in FIG. 4C, the material 9 </ b> A constituting the support layer is disposed on the upper surface of the first semiconductor chip 2. The material 9A includes particles 10 and 10.

  Next, as shown in FIG. 4D, the third semiconductor chip 4 is laminated on the upper surface of the second semiconductor chip 3 via the adhesive layer 6 and bonded. At this time, at least a part of the end portion 4 a of the third semiconductor chip 4 protrudes to the side of the end portion 3 a of the second semiconductor chip 3. Specifically, both side end portions 4 a in the length direction of the third semiconductor chip 4 protrude beyond the end portions 3 a of the second semiconductor chip 3. Further, the electrical connection terminal 2 a is positioned below the protruding portion 4 A of the third semiconductor chip 4.

  Further, when the third semiconductor chip 4 is laminated on the upper surface of the second semiconductor chip 3, the material 9A is expanded while the lower surface of the protruding portion 4A of the third semiconductor chip 4 and the first semiconductor A support layer 9 including particles 10 and 10 is formed between the top surface of the chip 2. Here, the support layer 9 is configured so as not to reach the electrical connection terminal 2 a between the electrical connection terminal 2 a provided on the upper surface of the first semiconductor chip 2 and the end 3 a of the second semiconductor chip 3. ing.

  Furthermore, the electrode pads on the substrate 5 and the electrical connection terminals of the second semiconductor chip 3 and the electrode pads on the substrate 5 and the electrical connection terminals 4b of the third semiconductor chip 4 are connected using bonding wires. Thereby, the semiconductor chip laminated body 1 mentioned above can be obtained.

  Although it does not specifically limit as a material which comprises the said support layer, The resin material containing particle | grains and resin is mentioned. The support layer is composed of particles and a resin material, and the elastic modulus of the resin material at 175 ° C. is preferably in the range of 50 MPa to 1 GPa. If the elastic modulus of the resin material is less than 50 MPa, the fluidity may be too high and the resin material may expand too much. If it exceeds 1 GPa, the fluidity may be too low and the resin material may not expand sufficiently. is there. Further, when the elastic modulus of the resin material is in the range of 50 MPa to 1 GPa, the adhesion between the support layer and the substrate or the semiconductor chip is enhanced, and the deformation of the third semiconductor chip can be further suppressed.

  Although it does not specifically limit as said resin, A curable compound can be mentioned. As a material constituting the support layer, a resin material containing a curable compound and a curing agent can be preferably used.

  The curable compound is not particularly limited, and a compound that is cured by addition polymerization, polycondensation, polyaddition, addition condensation, or ring-opening polymerization reaction can be used. Specifically, for example, urea resin, melamine resin, phenol resin, resorcinol resin, epoxy resin, acrylic resin, polyester resin, polyamide resin, polybenzimidazole resin, diallyl phthalate resin, xylene resin, alkyl-benzene resin, epoxy acrylate resin Thermosetting compounds such as silicon resin and urethane resin can be used. Among these, an epoxy resin and an acrylic resin are preferable, and an epoxy resin having an imide skeleton is more preferable because bonding reliability and bonding strength between the support layer and the substrate or the semiconductor chip are increased.

  The epoxy resin is not particularly limited, and examples thereof include bisphenol type epoxy resins such as bisphenol A type, bisphenol F type, bisphenol AD type, and bisphenol S type, novolac type epoxy resins such as phenol novolak type and cresol novolak type, and trisphenolmethane. Examples thereof include aromatic epoxy resins such as triglycidyl ether, naphthalene type epoxy resins, fluorene type epoxy resins, dicyclopentadiene type epoxy resins, and water additives thereof. Among these, naphthalene type epoxy resin and fluorene type epoxy resin are preferable because heat resistance is improved.

  As a commercial item of the said naphthalene type epoxy resin, HP-4032, HP-4032D, HP-4700, HP-4701, etc. by Dainippon Ink & Chemicals, Inc. are mentioned, for example. As a commercial item of the said fluorene type epoxy resin, Nagase ChemteX company make EX-1010, EX-1011, EX-1012, EX-1020, EX-1030, EX-1040, EX-1050, EX-1051, EX-1060 etc. are mentioned.

  As the naphthalene type epoxy resin or fluorene type epoxy resin, those having a softening point of 60 ° C. or less are preferably used. By using the one having a softening point of 60 ° C. or less, it is not necessary to add a large amount of liquid components such as a diluent to the resin material in order to lower the viscosity, and the content of volatile components is reduced during and after curing. can do. As the naphthalene type epoxy resin or fluorene type epoxy resin, those having a softening point of 40 ° C. or lower are more preferably used, and those having a softening point of 20 ° C. or lower are more preferably used. Among the commercially available products, HP-4032, HP-4032D, and EX-1020 are preferably used.

  When using the said naphthalene type epoxy resin and / or a fluorene type epoxy resin, it is preferable that the compounding quantity is 40 weight% or more in 100 weight% of resin materials. When the naphthalene type epoxy resin and / or the fluorene type epoxy resin is less than 40% by weight, the heat resistance may be inferior. The more preferable lower limit of the naphthalene type epoxy resin and / or the fluorene type epoxy resin is 60% by weight, and the preferable upper limit is 90% by weight.

  As the epoxy resin, a rubber-modified epoxy resin having a rubber component such as NBR, CTBN, polybutadiene, or acrylic rubber, or an epoxy compound such as a flexible epoxy compound is preferably used. When these epoxy compounds are used, the flexibility after curing can be increased.

  The preferable lower limit of the moisture absorption rate of the curable compound is 1.1%, and the preferable upper limit is 1.5%. Examples of the curable compound having a moisture absorption rate in the range of 1.1 to 1.5% include naphthalene type epoxy resins, fluorene type epoxy resins, dicyclopentadiene type epoxy resins, phenol novolac type epoxy resins, and cresol novolac type epoxy resins. Etc.

  It does not specifically limit as said hardening | curing agent, A conventionally well-known hardening | curing agent can be selected suitably and used together with a sclerosing | hardenable compound. Examples of the curing agent include heat curing acid anhydride curing agents such as trialkyltetrahydrophthalic anhydride, phenolic curing agents, amine curing agents, latent curing agents such as dicyandiamide, and cationic catalyst curing agents. Is mentioned. These curing agents are preferably used when an epoxy resin is used as the curable compound. These curing agents may be used alone or in combination of two or more.

  Although it does not specifically limit as a compounding quantity of the said hardening | curing agent, When using the hardening | curing agent which carries out an equivalent reaction with the functional group of a curable compound, it is preferable that it is 90-110 equivalent with respect to the functional group amount of a curable compound. Moreover, when using the hardening | curing agent which functions as a catalyst, with respect to 100 weight part of sclerosing | hardenable compounds, the preferable minimum of a hardening | curing agent is 1 weight part and a preferable upper limit is 20 weight part.

  Since the curing speed and the physical properties of the cured product can be adjusted, the resin material may contain a curing accelerator in addition to the curable compound and the curing agent.

  It does not specifically limit as said hardening accelerator, For example, an imidazole type hardening accelerator and a tertiary amine type hardening accelerator are mentioned. Among these, an imidazole-based curing accelerator is preferably used because the reaction system is easily controlled in order to adjust the curing rate and the physical properties of the cured product. These hardening accelerators may be used independently and 2 or more types may be used together.

  The imidazole curing accelerator is not particularly limited. For example, 1-cyanoethyl-2-phenylimidazole in which the 1-position of imidazole is protected with a cyanoethyl group, or a basic group protected with isocyanuric acid (Shikoku Chemical Industry) Product name "2MA-OK") and the like. These imidazole type hardening accelerators may be used independently and may use 2 or more types together.

  The blending amount of the curing accelerator is not particularly limited, and is preferably 1 to 10 parts by weight with respect to 100 parts by weight of the curable compound.

  The melting point of the curing agent and / or curing accelerator is preferably 120 ° C. or higher. When the melting point is 120 ° C. or higher, gelation can be suppressed when the resin material is heated. Either one of the curing agent and the curing accelerator is preferably a powder.

  Examples of the curing agent having a melting point of 120 ° C. or higher include 5- (2,5-dioxotetrahydro-3-feranyl) -3-methyl-3-cyclohexene-1,2-dicarboxylic acid anhydride, TD- Phenol novolac resins such as 2090, bisphenol A novolac resins such as KH-6021, orthocresol novolac resins such as KA-1165, EH-3636AS, EH-3842, EH-3780, EH-4339S, EH-4346S (above, Asahi Dicyandiamide such as Denka Kogyo Co., Ltd.). Further, a microcapsule type curing agent coated with a material having a melting point of 120 ° C. or higher can also be suitably used.

  Examples of the curing accelerator having a melting point of 120 ° C. or higher include 2MZ, 2MZ-P, 2PZ, 2PZ-PW, 2P4MZ, C11Z-CNS, 2PZ-CNS, 2PZCNS-PW, 2MZ-A, 2MZA-PW, C11Z-A, 2E4MZ-A, 2MA-OK, 2MAOK-PW, 2PZ-OK, 2MZ-OK, 2PHZ, 2PHZ-PW, 2P4MHZ, 2P4MHZ-PW, 2E4MZ · BIS, VT, VT-OK, MAVT, MAVT- OK (above, manufactured by Shikoku Kasei Kogyo Co., Ltd.). In particular, a curing accelerator that is stable up to 130 ° C. and activated at 135 to 200 ° C. is preferable. Among those described above, 2MA-OK and 2MAOK-PW are preferable. When these curing accelerators are used, the storage stability is enhanced, and both heat stability and fast curability can be achieved.

  When an epoxy resin is used as the curable compound and the curing agent and the curing accelerator are used in combination, the blending amount of the curing agent is preferably equal to or less than an equivalent theoretically required for the epoxy group. If the compounding amount of the curing agent exceeds the theoretically required equivalent, chlorine ions may be easily eluted by moisture after curing. That is, when the curing agent is excessive, for example, when the elution component is extracted from the cured resin material with hot water, the pH of the extracted water becomes about 4 to 5, so that a large amount of chlorine ions are generated from the epoxy resin. May elute. Accordingly, it is preferable that the pH of pure water after 1 g of cured resin material is immersed in 10 g of pure water at 100 ° C. for 2 hours is 6 to 8, and the pH is 6.5 to 7.5. More preferred.

  Since the viscosity can be lowered, the resin material may contain a diluent. As a diluent, what has an epoxy group is preferable, and the preferable minimum of the number of epoxy groups in 1 molecule is 2, and a preferable upper limit is 4. If the number of epoxy groups is less than 2, the heat resistance may be inferior after curing. If the number of epoxy groups exceeds 4, distortion due to curing may occur or uncured epoxy groups may remain. In some cases, poor strength and poor bonding due to repeated thermal stress may occur. A preferable upper limit of the number of epoxy groups is 3.

  As the diluent, a compound having an aromatic ring and / or a dicyclopentadiene structure is preferably used.

  The diluent preferably has a weight loss at 120 ° C. and a weight loss at 150 ° C. of 1% or less. If the weight loss exceeds 1%, the unreacted material volatilizes during or after curing, which may deteriorate the productivity of the semiconductor chip laminate or adversely affect the semiconductor chip or the like.

  In addition, the diluent preferably has a lower curing start temperature and a higher curing rate than the curable compound.

  As a compounding quantity of the said diluent, a preferable minimum is 1 weight% with respect to 100 weight% of resin materials, and a preferable upper limit is 20 weight%. When the blending amount of the diluent is outside the range of 1 to 20% by weight, the viscosity of the resin material may not be sufficiently reduced.

  The resin material preferably contains a polymer compound having a functional group capable of reacting with the curable compound. By containing the polymer compound, it is possible to improve the bonding reliability when distortion is caused by heat.

  Examples of the polymer compound having a functional group capable of reacting with the curable compound include polymer compounds having an amino group, a urethane group, an imide group, a hydroxyl group, a carboxyl group, an epoxy group, and the like. It is preferably used when using an epoxy resin. Among these, a polymer compound having an epoxy group is preferable. By using a polymer compound having an epoxy group, a cured product of the resin material exhibits excellent flexibility, and the bonding reliability between the support layer and the substrate or the semiconductor chip can be improved.

  The polymer compound having an epoxy group is not particularly limited as long as it is a polymer compound having an epoxy group at a terminal and / or side chain (pendant position). For example, an epoxy group-containing acrylic rubber, an epoxy group-containing compound Examples thereof include butadiene rubber, bisphenol type high molecular weight epoxy resin, epoxy group-containing phenoxy resin, epoxy group-containing acrylic resin, epoxy group-containing urethane resin, and epoxy group-containing polyester resin. Especially, since the high molecular compound containing many epoxy groups can be obtained and the mechanical strength and heat resistance of hardened | cured material are improved, an epoxy-group-containing acrylic resin is used suitably. These polymer compounds having an epoxy group may be used alone or in combination of two or more.

  As the polymer compound having a functional group capable of reacting with the curable compound, when a polymer compound having the epoxy group, particularly an epoxy group-containing acrylic resin, is used, the preferred lower limit of the weight average molecular weight of the polymer compound is 10,000. is there. If the weight average molecular weight is less than 10,000, the flexibility of the cured product may not be sufficiently improved.

  When a polymer compound having an epoxy group, particularly an epoxy group-containing acrylic resin, is used as the polymer compound having a functional group capable of reacting with the curable compound, the preferable lower limit of the epoxy equivalent is 200, and the preferable upper limit is 1000. . If the epoxy equivalent is less than 200, the flexibility may not be sufficiently improved. Conversely, if it exceeds 1000, the mechanical strength and heat resistance of the cured resin material may be inferior.

  As a compounding quantity of the high molecular compound which has a functional group which can react with the said curable compound, a preferable minimum is 1 weight part and a preferable upper limit is 20 weight part with respect to 100 weight part of curable compounds. When the amount of the polymer compound is less than 1 part by weight, the reliability against thermal strain may not be sufficiently obtained, and when it exceeds 20 parts by weight, the heat resistance may decrease.

  In order to express appropriate thixotropy, the resin material preferably contains a thixotropic agent. The thixotropy imparting agent is not particularly limited, and for example, metal fine particles, calcium carbonate, fumed silica, aluminum oxide, boron nitride, aluminum nitride, aluminum borate, and other inorganic fine particles can be used. Of these, fumed silica is preferable.

  As the thixotropy-imparting agent, those subjected to surface treatment as necessary can be used, and it is particularly preferable to use particles having a hydrophobic group on the surface. Specifically, for example, fumed silica having a hydrophobic surface is preferably used.

  As the thixotropy imparting agent, when a particulate material is used, the preferable upper limit of the average particle diameter is 1 μm. When the particle diameter exceeds 1 μm, appropriate thixotropy may not be expressed.

  The amount of the thixotropy-imparting agent is not particularly limited, but a preferable lower limit is 0.5% by weight and a preferable upper limit is 20% by weight in 100% by weight of the resin material. In particular, when using a thixotropy-imparting agent other than the surface-treated particles, the thixotropy-imparting agent is preferably blended in the range of 0.5 to 20% by weight. If the thixotropy-imparting agent is less than 0.5% by weight, moderate thixotropy cannot be obtained, and if it exceeds 20% by weight, the bonding reliability between the support layer and the substrate or semiconductor chip may be lowered. The more preferable lower limit of the amount of the thixotropy-imparting agent is 0.1% by weight, and the more preferable upper limit is 10% by weight.

  Although it does not specifically limit as said particle | grains contained in a support layer, The resin particle which consists of resin is used preferably.

  The resin constituting the resin particles is not particularly limited. For example, polyethylene, polypropylene, polymethylpentene, polyvinyl chloride, polytetrafluoroethylene, polystyrene, polymethyl methacrylate, polyethylene terephthalate, polybutylene terephthalate, polyamide, polyimide , Polysulfone, polyphenylene oxide, polyacetal and the like.

  As the resin constituting the resin particles, it is preferable to use a crosslinked resin because the hardness and recovery rate of the particles can be easily adjusted and the heat resistance can be improved.

  The cross-linked resin is not particularly limited. For example, epoxy resin, phenol resin, melamine resin, unsaturated polyester resin, divinylbenzene polymer, divinylbenzene-styrene copolymer, divinylbenzene-acrylate copolymer, diallyl Examples thereof include a resin having a network structure such as a phthalate polymer, a triallyl isocyanurate polymer, and a benzoguanamine polymer. Of these, divinylbenzene polymer, divinylbenzene-styrene copolymer, divinylbenzene- (meth) acrylate copolymer, and diallyl phthalate polymer are preferable. When these cross-linked resins are used, the heat resistance is improved.

  FIG. 5 is a front sectional view showing a semiconductor chip stacked body according to another embodiment of the present invention. The same components as those of the semiconductor chip stacked body 1 are denoted by the same reference numerals, and the description thereof is omitted.

  In the semiconductor chip stacked body 31 shown in FIG. 5, the semiconductor chip stacked body 1 except that the support layer is coated particles 32 and 32 having a particle diameter substantially equal to or slightly larger than the thickness of the second semiconductor chip 4. It is configured in the same way.

  The coated particle 32 has a core-shell structure in which the resin particle 32a is coated with the layer 32b, that is, the resin particle 32a is a core and the layer 32b is a shell. In the semiconductor chip laminated body 31, the distance between the first semiconductor chip 2 and the third semiconductor chip 4 is regulated by the covering particles 32, 32, and the third semiconductor chip 4 is prevented from being inclined. Yes. Thus, the support layer may be coated particles having resin particles and a layer covering the resin particles.

  The resin particles described above can be used as the resin particles 32a.

  As a material constituting the layer 32b, by having a coating layer, the resin particles can be easily fixed to the substrate or chip, and as a result, a stable support layer can be obtained when interposed between the substrate and the chip or between the chips. It is preferable that the material gives the coated particles that can be formed. The layer 32b is preferably a layer made of a conventionally known adhesive material or a coating layer made of fine particles having a particle diameter smaller than that of the core particles. Although it does not specifically limit as a particle diameter of a microparticle, It is preferable that it is 1/10 or less of the particle diameter of a resin particle. If it exceeds 1/10, the physical properties of the coated particles may be governed by the physical properties of the fine particles.

  The fine particles are preferably hollow particles. Since the hollow particles are easily softened and deformed to act as a fixing agent between the resin particles as the base material and the chip or the substrate, the coated particles can be more suitably used as the support layer.

  The method for coating the resin particles with the fine particles is not particularly limited, but for example, the resin particles can be suitably coated by a heteroaggregation method.

  The material for the fine particles is not particularly limited, and may be the same as or different from the resin particles.

  FIG. 6 is a front sectional view showing a semiconductor chip stacked body according to another embodiment of the present invention.

  In the semiconductor chip stacked body 51 shown in FIG. 6, a plurality of semiconductor chips 52 to 56 are stacked, and the semiconductor chip stacked body 51 is stacked on a substrate 57. The semiconductor chips 52 to 56 have a rectangular planar shape, and are stacked in a cross shape so that the length directions of the upper and lower semiconductor chips facing each other are orthogonal to each other. The substrate 57 and the plurality of semiconductor chips 52 to 56 are bonded via an adhesive layer 58.

  Both end portions in the length direction of the semiconductor chips 53 to 56 protrude laterally from end portions of the lower semiconductor chips 52 to 55.

  Electrical connection terminals are provided on both side edges in the length direction of the semiconductor chips 52 to 56. In FIG. 6, electrical connection terminals 52a, 54a, and 56a provided on the upper surfaces of the semiconductor chips 52, 54, and 56 are illustrated.

  The electrical connection terminals on the upper surfaces of the semiconductor chips 52 to 55 are respectively located below the protruding portions of the upper semiconductor chips 53 to 56. For example, as shown in FIG. 6, the electrical connection terminal 54 a is positioned below the protruding portion 56 A of the semiconductor chip 56, and the electrical connection terminal 52 a is positioned below the protruding portion 54 A of the semiconductor chip 54. positioned.

  Electrical connection terminals on the upper surfaces of the semiconductor chips 52 to 56 and electrode pads 57 a and 57 a on the substrate 57 are connected by bonding wires 59 and 59.

  Support layers 60 and 60 are filled between the lower surface of the protruding portion of the semiconductor chips 53 to 56 and the upper surface of the semiconductor chip. The support layer 60 prevents the upper semiconductor chip from being deformed. The support layer 60 is provided between the electrical connection terminal and the end of the semiconductor chip so as not to reach the electrical connection terminal.

  The support layer 60 includes a plurality of particles 61 and 61 having a particle diameter substantially equal to or slightly larger than the thickness of the second semiconductor chip 4. The distance between the semiconductor chips is regulated by the particles 61 and 61, the curvature of the upper semiconductor chip is effectively prevented, and the third semiconductor chip is prevented from being inclined.

  Hereinafter, the present invention will be clarified by describing specific examples of the present invention. In addition, this invention is not limited to a following example.

  The following were prepared to construct the semiconductor chip stack.

(substrate)
Substrate (FR4 glass epoxy, thickness 0.21mm)

(Semiconductor chip)
(1) Production of Semiconductor Wafer An SiO film (500 nm), a Ti film (70 nm), and an Al film (1 μm) were laminated in this order on an 8-inch bare wafer. A 100 μm square Al pad was formed at a 155 μm pitch on the periphery of the chip by photolithography using an i-line resist and wet etching. On top of that, a SiN film (500 nm) was laminated, and a wafer in which the SiN film on the Al pad was opened at 80 μm square was produced. The Al pads were electrically connected in pairs.

(2) Fabrication of first and second semiconductor chips After the semiconductor wafer obtained in (1) above is back-ground to 80 μm thickness, a dicing tape with a die attach film (epoxy, 40 μm thickness, manufactured by Sekisui Chemical Co., Ltd.) Was diced into a size of 8.6 × 5.4 mm and separated into individual pieces to obtain a semiconductor chip with a die attach film.

(3) Fabrication of third semiconductor chip The semiconductor wafer obtained in (1) above is back-ground to 80 μm thickness, and then diced to a size of 8.6 × 5.4 mm using a dicing tape. The semiconductor chip was obtained by dividing into pieces.

(adhesive)
(1) Preparation of adhesives 1 and 2 (resin material) Each material except the spacer particles shown in Table 1 below is blended in the proportions shown in Table 1 below (units are parts by weight), and stirred and mixed using a homodisper. Thus, an adhesive composition was prepared. Adhesives 1 and 2 (resin materials) were prepared by blending spacer particles in the obtained adhesive composition in the proportions shown in Table 1 below and further stirring and mixing using a homodisper.

  Using DVA-200 (manufactured by IT Measurement & Control Co., Ltd.), the elastic modulus at 175 ° C. of adhesives 1 and 2 (resin material) at a frequency of 10 Hz, a deformation rate of 0.1%, and a heating rate of 5 ° C./min. Was measured. The results are shown in Table 1 below.

  In Table 1 above, the following materials were used.

1. Epoxy resin Resin 1: Dicyclopentadiene type epoxy resin (HP-7200HH, manufactured by Dainippon Ink & Chemicals, Inc.)
Resin 2: Naphthalene type epoxy resin (HP-4032D, manufactured by Dainippon Ink & Chemicals, Inc.)
2. Polymer compound having epoxy group Resin 3: Epoxy group-containing acrylic resin (Blemmer CP-30, manufactured by Japan Epoxy Resin Co., Ltd.)
3. Rubber-modified epoxy resin Resin 4: CTBN-modified epoxy resin (EPR-4023, manufactured by Asahi Denka Kogyo Co., Ltd.)
4). Curing agent Curing agent 1: Acid anhydride (YH-307, manufactured by Japan Epoxy Resin Co., Ltd.)
5. Curing accelerator Curing accelerator 1: Imidazole compound (2MA-OK, manufactured by Shikoku Kasei Kogyo Co., Ltd.)
6). Adhesion imparting agent Adhesion imparting agent 1: Imidazole silane coupling agent (SP-1000, manufactured by Nikko Materials)
7). Thixotropic agent Additive 1: Fumed silica (AEROSIL R202S, manufactured by Nippon Aerosil Co., Ltd.)
8). Spacer particles Particle 1: Resin particles (Micropearl SP, manufactured by Sekisui Chemical Co., Ltd., average particle size: 100 μm, CV value = 4%)

(2) Preparation of particles coated with resin particles (Synthesis 1) 10000 parts by weight of ion exchange water, 30 parts by weight of polyvinyl alcohol (manufactured by Nippon Synthetic Chemical Co., Ltd., “GH-20”), and polyallylamine (Nittobo) "PPA-H-10C"), a mixture of 100 parts by weight of divinylbenzene and 1 part by weight of benzoyl peroxide is dispersed in 10 parts by weight of the solution using an SPG membrane and polymerized at 90 ° C for 10 hours. went. After washing, classification was performed to obtain base particles having an amino group on the surface having an average particle size of 99 μm (CV value 5%).

  (Synthesis 2) 10 parts by weight of dodecyl mercaptan, 95 parts by weight of styrene, 5 parts by weight of dimethylaminopropylacrylamide and 1000 parts by weight of ion-exchanged water were added, and 1 part by weight of AIBA and 1 part by weight of dodecyltrimethylammonium chloride were added thereto. Polymerization was performed at 70 ° C. for 8 hours to obtain a latex dispersion having an average particle size of 90 nm (CV value 10%).

  Using this latex as seed particles, 10 parts by weight of this latex, 2 parts by weight of dodecyltrimethylammonium chloride, and 1 part by weight of AIBA were dispersed in 900 parts by weight of ion-exchanged water. When a mixture of 40 parts by weight of methyl methacrylate, 20 parts by weight of glycidyl methacrylate, 30 parts by weight of styrene and 10 parts by weight of divinylbenzene was added and stirred for 48 hours at room temperature, most of the above substances were absorbed by the seed particles. It was done. Subsequently, when this was polymerized at 60 ° C. for 6 hours, a dispersion of hollow particles (1) having an average particle diameter of 180 nm (CV value 10%) was obtained. When this particle dispersion was dried and observed with a transmission electron microscope, the central portion of the particles was transparent and the inner diameter was 90 nm (hollow rate 12.5%). Moreover, the glass transition temperature (Tg) of this particle | grain was 107 degreeC. The hollow particle (1) dispersion was replaced with acetone by centrifugation to obtain an acetone dispersion (1) of the hollow particles (1).

  10 parts by weight of the base particles obtained in Synthesis 1 were dispersed in acetone, and 10 parts by weight of solid dispersion (1) of the hollow particles (1) obtained in Synthesis 2 was added at room temperature. Stir for 3 hours. After filtration, it was further washed with acetone and dried to obtain coated particles A (particles in which resin particles were coated with a layer) having an average particle size of 100 μm (CV value = 4%).

Example 1
In Example 1, a semiconductor chip stack was formed in which first to third semiconductor chips were stacked in a cross shape so that the length directions of the upper and lower semiconductor chips facing each other were orthogonal to each other on the substrate. .

  The semiconductor chip with the die attach film as the first semiconductor chip was die-bonded from the die attach film side on the substrate by using a die bonder (manufactured by NEC Machinery, BEST-D02). Thereafter, the die attach film was cured at 175 ° C. for 30 minutes.

  Wire bonder: UTC-1000 (manufactured by Shinkawa Co., Ltd.), Au wire (manufactured by Tanaka Electronics, 4N), bonding temperature: 150 ° C., bonding load: 0.3 N, on the top surface of the first semiconductor chip Wire bonding was performed on the provided electrical connection terminals.

  0.5 mg of the adhesive 1 was applied to the center of the upper surface of the first semiconductor chip. After that, the adhesive 1 applied to the upper surface of the first semiconductor chip is spread out, and the first semiconductor chip is cross-shaped so that the length direction of the first semiconductor chip is orthogonal to the first semiconductor chip. The semiconductor chip with the die attach film as the semiconductor chip 2 was die-bonded. Thereafter, the die attach film and the adhesive 1 were cured at 150 ° C. for 30 minutes.

  0.5 mg of the adhesive 1 was applied to the center of the upper surface of the second semiconductor chip. Further, 0.5 mg of the adhesive 2 was applied to the upper surface of the first semiconductor chip between the electrical connection terminal provided on the upper surface of the first semiconductor chip and the second semiconductor chip. Thereafter, the adhesive 1 applied to the upper surfaces of the first and second semiconductor chips is pushed and spread on the second semiconductor chip so that the length direction of the second semiconductor chip is orthogonal to the second semiconductor chip. In addition, the semiconductor chip as the third semiconductor chip was die-bonded. Thereafter, the die attach film, adhesive 1 and adhesive 2 were cured at 150 ° C. for 30 minutes.

  Thereafter, wire bonding is performed on the electrical connection terminal provided on the upper surface of the third semiconductor chip under the same conditions as the connection process of the electrical connection terminal provided on the upper surface of the first semiconductor chip, and the semiconductor chip stack is formed. Obtained.

(Example 2)
Instead of applying the adhesive 2 to the upper surface of the first semiconductor chip between the electrical connection terminals provided on both side edges of the upper surface of the first semiconductor chip and the second semiconductor chip, the coated particles A A semiconductor chip laminated body was obtained in the same manner as in Example 2 except that was placed at a pitch of 300 μm.

(Comparative Example 1)
Instead of applying the adhesive 2 to the upper surface of the first semiconductor chip between the electrical connection terminals provided on both side edges of the upper surface of the first semiconductor chip and the second semiconductor chip, the adhesive 1 A semiconductor chip laminate was obtained in the same manner as in Example 1 except that was applied.

(Comparative Example 2)
Example except that the covering particle A is not arranged on the upper surface of the first semiconductor chip between the electrical connection terminals provided on both side edges of the upper surface of the first semiconductor chip and the second semiconductor chip. In the same manner as in Example 2, a semiconductor chip laminate was obtained.

(Evaluation of semiconductor chip laminate)
(1) Evaluation of the formation state of a support layer The obtained semiconductor chip laminated body was sealed with transparent resin, and cross-section grinding | polishing was performed, and the cross section of the semiconductor chip laminated body was exposed. The obtained cross section was observed with an optical microscope (trade name SMZ1500, manufactured by Nikon Corporation).

  As a result, in the semiconductor chip stacked body according to the first and second embodiments, the lower surface of the third semiconductor chip and the first semiconductor chip are disposed between the electrical connection terminal provided on the upper surface of the first semiconductor chip and the second semiconductor chip. A support layer containing particles that regulate the distance between the first semiconductor chip and the third semiconductor chip is formed between the upper surface of the semiconductor chip. The support layer did not reach the electrical connection terminal provided on the upper surface of the first semiconductor chip.

  That is, in the semiconductor chip stacks of Examples 1 and 2, as shown in FIG. 7, the support layer is formed to a position of about 0.8 mm laterally from the end of the second semiconductor chip. The layer did not reach the electrical connection terminal 2a. Note that the end portions of the first and third semiconductor chips 2 and 4 protrude about 1.6 mm to the side of the end portion 3 a of the second semiconductor chip 3, and are formed on the upper surface of the first semiconductor chip 2. The distance between the provided electrical connection terminal 2a and the second semiconductor chip 3 was about 1.3 mm.

  On the other hand, in the semiconductor chip stacked body of Comparative Example 1, the lower surface of the third semiconductor chip and the first semiconductor chip between the electrical connection terminal provided on the upper surface of the first semiconductor chip and the second semiconductor chip. A support layer that does not contain particles that regulate the distance between the first semiconductor chip and the third semiconductor chip is formed between the upper surface and the upper surface. The support layer did not reach the electrical connection terminal provided on the upper surface of the first semiconductor chip.

  Moreover, in the semiconductor chip laminated body of the comparative example 2, the above support layers were not formed.

(2) Bonding wire connection failure rate About the obtained semiconductor chip laminated body, the connection failure rate of the bonding wire connected to the electrical connection terminal provided in the upper surface of the 1st semiconductor chip was calculated | required. The number of samples was 20 chips, and 10 pairs were measured per chip. The results are shown in Table 2 below.

(3) Deformation evaluation of third semiconductor chip About the obtained semiconductor chip laminate, the deformation and inclination of the third semiconductor chip were evaluated according to the following criteria in the same manner as in the evaluation of the formation state of the support layer. . The results are shown in Table 2.

  ○: Deformation is not observed for all chips, and the chips are kept horizontal.

  Δ: For a small number of chips, deformation is observed, or the level is inferior, and a slight inclination is confirmed.

  X: Deformation is observed for more than half of the chips, or the horizontality is inferior, and a slight inclination is confirmed.

The partial notch front sectional drawing of the semiconductor chip laminated body which concerns on one Embodiment of this invention. The schematic perspective view for demonstrating the lamination | stacking state of the semiconductor chip laminated body which concerns on one Embodiment of this invention. The schematic perspective view for demonstrating an example of the lamination | stacking state of a semiconductor chip laminated body. (A)-(d) is a partial notch front sectional drawing for demonstrating the manufacturing method of the semiconductor chip laminated body which concerns on one Embodiment of this invention. The partial notch front sectional drawing of the semiconductor chip laminated body which concerns on other embodiment of this invention. The partial notch front sectional drawing of the semiconductor chip laminated body which concerns on another embodiment of this invention. The partial notch front sectional drawing for demonstrating the area | region in which the support layer is formed in the semiconductor chip laminated body obtained by the Example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Semiconductor chip laminated body 2 ... 1st semiconductor chip 2a ... Electrical connection terminal 3 ... 2nd semiconductor chip 3a ... End part 4 ... 3rd semiconductor chip 4A ... Overhang | projection part 4a ... End part 4b ... Electrical connection terminal DESCRIPTION OF SYMBOLS 5 ... Board | substrate 5a, 5b ... Electrode pad 6 ... Adhesive layer 7, 8 ... Bonding wire 9 ... Support layer 9A ... Material which comprises a support layer 10 ... Particle | grain 11 ... Substrate or 1st semiconductor chip 12, 13 ... Second, 3rd semiconductor chip 31 ... Semiconductor chip laminated body 32 ... Coated particle 32a ... Resin particle 32b ... Layer 51 ... Semiconductor chip laminated body 52-56 ... Semiconductor chip 54A, 56A ... Overhang | projection part 52a, 54a, 56a ... Electrical connection terminal 57 ... Substrate 57a ... Electrode pad 58 ... Adhesive layer 59 ... Bonding wire 60 ... Support layer 61 ... Particle

Claims (4)

A substrate having an electrical connection terminal on the upper surface or a first semiconductor chip; a second semiconductor chip laminated on a region of the upper surface of the substrate or the first semiconductor chip in which the electrical connection terminal is not provided; A semiconductor chip stack including a third semiconductor chip stacked on the upper surface of the semiconductor chip of
At least a part of the end portion of the third semiconductor chip protrudes to the side of the end portion of the second semiconductor chip, and the substrate or The electrical connection terminal provided on the upper surface of the first semiconductor chip is located,
Bonding wires are connected to the electrical connection terminals provided on the upper surface of the substrate or the first semiconductor chip,
A support layer is filled between the lower surface of the protruding portion of the third semiconductor chip and the upper surface of the substrate or the upper surface of the first semiconductor chip so as to be in contact with the end of the second semiconductor chip. Has been
The support layer is configured using particles and a resin material, and the support layer regulates an interval between the substrate or the first semiconductor chip and the third semiconductor chip, and an upper surface of the substrate. or seeing containing the particles in contact with the lower surface of the first and the top surface of the semiconductor chip and the third semiconductor chip,
The support layer is filled between the electrical connection terminal provided on the upper surface of the substrate or the first semiconductor chip and an end of the second semiconductor chip so as not to reach the electrical connection terminal. And
The particles are arranged so as not to reach the electrical connection terminal between the electrical connection terminal provided on the upper surface of the substrate or the first semiconductor chip and an end portion of the second semiconductor chip. A semiconductor chip laminated body characterized by the above.   The semiconductor chip laminated body of Claim 1 which has the elasticity modulus in 175 degreeC of the said resin material in the range of 50 Mpa-1 GPa. It is a manufacturing method of the semiconductor chip laminated body according to claim 1 or 2 ,
Laminating a second semiconductor chip on a substrate having an electrical connection terminal on the upper surface or an area of the upper surface of the first semiconductor chip where the electrical connection terminal is not provided;
Connecting a bonding wire to the electrical connection terminal provided on the upper surface of the substrate or the first semiconductor chip;
Disposing a material constituting a support layer containing particles and a resin material on the upper surface of the substrate or the first semiconductor chip;
The substrate so that at least a part of the end portion of the third semiconductor chip protrudes laterally from the end portion of the second semiconductor chip, and below the protruding portion of the third semiconductor chip. Alternatively, the third semiconductor chip is stacked on the upper surface of the second semiconductor chip so that the electrical connection terminal provided on the upper surface of the first semiconductor chip is positioned, and a support layer is formed, The support layer is filled between the lower surface of the protruding portion of the semiconductor chip 3 and the upper surface of the substrate or the upper surface of the first semiconductor chip so as to be in contact with the end portion of the second semiconductor chip. And the support layer regulates an interval between the substrate or the first semiconductor chip and the third semiconductor chip, and the upper surface of the substrate or the upper surface of the first semiconductor chip and the third semiconductor. H Look-containing particles in contact with the lower surface of flops, the support layer, between the end of the substrate or the first of the provided on the upper surface of the semiconductor chip electrically connecting terminal and the second semiconductor chip, the Filled so as not to reach the electrical connection terminal, the particles are between the electrical connection terminal provided on the upper surface of the substrate or the first semiconductor chip and the end of the second semiconductor chip, And a step of obtaining a semiconductor chip laminated body arranged so as not to reach the electrical connection terminal . The support layer is formed on the upper surface of the substrate or the first semiconductor chip between the electrical connection terminal provided on the upper surface of the substrate or the first semiconductor chip and an end portion of the second semiconductor chip. 4. The method of manufacturing a semiconductor chip laminate according to claim 3 , wherein a material is disposed.

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