JP5166324B2 - Control device for power converter - Google Patents

Description

  The present invention relates to a control device for a power converter (hereinafter referred to as an inverter) composed of a plurality of semiconductor switch elements, and more particularly to a control device for a pulse width modulation (hereinafter referred to as PWM) inverter. is there.

When power is supplied to a load using a PWM inverter, the inverter control device often detects the load current and performs current control so that the current value becomes a desired value. The current controller outputs a voltage command by a predetermined method from the current command and the detected current value. The voltage command is converted into a switching pattern command by PWM (Pulse Width Modulation) and used for on / off operation of the switching elements constituting the PWM inverter. Although it is the operation timing of the current controller, since noise is generated when the switching element is turned on / off, it is often set to a timing at which noise is less generated. For example, it is the apex timing of a peak / valley of a triangular wave carrier used for PWM. However, in recent years, there are many cases where the current control system is operated at a higher speed than the triangular wave carrier period regardless of the vertex synchronization of the triangular wave carrier in order to speed up the control response. In such a case, the detection current signal includes the switching noise, and current control may be disturbed.
To solve this problem, the current detection operation is stopped for a predetermined period from the ON / OFF operation of the switching element of the inverter, and the current value held immediately before the ON / OFF operation of the switching element is output as the detection value. A technique for obtaining a detection current signal that does not include a noise component is disclosed (for example, Patent Document 1).

JP 2002-034264 A

However, the technique disclosed in Patent Document 1 has a problem that the ON and OFF timings are close to each other depending on the switching pattern, the period for holding the current value is continuous, and the hold period is increased as a result. For example, the absolute value of the voltage command is large, and the carrier wave and the voltage command waveform cross each other in the vicinity of a peak or valley of a triangular wave carrier. In a multi-phase inverter, switching noise of one phase easily propagates to other phases. Therefore, when each phase voltage command is close, the ON / OFF timing of the switching element is close, and switching noise is generated accordingly. The timing is also close. As a result, the time during which the current value is held increases. When such a phenomenon occurs, it is equivalent to inserting dead time in the current control system, and the current control response is rather reduced.
In addition, in inverters using wide band gap power semiconductor elements such as SiC, GaN, and diamond, which have been attracting attention in recent years, as the switching speed increases, the triangular carrier frequency can be significantly increased compared to Si power semiconductor elements. it can. When the technique of Patent Document 1 is applied to an inverter driven at a high carrier frequency as described above, the number of switching increases due to the increase in the carrier frequency, so that the current value hold period per unit time also increases. As a result, there is a problem that the dead time as described above is greatly increased and the response of the current control system is deteriorated and destabilized.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to obtain an inverter having a control device capable of realizing a stable current control system without an increase in dead time. .

The present invention is a control device for a power converter provided with a semiconductor switching element, the control device including a carrier generator that generates a carrier signal, a current command generator that outputs a current command signal, and a power A current detector that detects a current of a load connected to the converter, a sampling hold device that samples and holds the detected load current at a predetermined sampling timing with a period shorter than the carrier signal period, and outputs a detected current signal; input operation to the current command signal and the detected current signal with a period shorter than the carrier signal period, and a current controller for outputting a voltage command signal by calculating, is provided with a noise section determination unit, determines the noise interval The converter predicts the switching noise generation interval of the power converter from the detected current signal, the voltage command signal, and the carrier signal. Generation section performs the determination of whether or not overlap with the sampling timing, current controller based on the OVERLAPPING determination signal output from the noise section determination unit, is intended to reduce the current control gain.

  Since the control device for the power converter according to the present invention has the above-described configuration, when the noise controller predicts that the current detection signal will be mixed in the next current detection signal, the current controller By reducing the gain, even when switching noise generated by the semiconductor switch element is mixed in the current detection signal, it is possible to suppress the disturbance of the voltage command and suppress the disturbance of the current. Since a series of processing such as PWM pattern generation is continuously performed, no dead time is generated, a stable current control system is realized, and an increase in the number of components is suppressed, and a compact and lightweight control device can be provided. There is.

2 is a block diagram illustrating a control device for a power converter according to Embodiment 1. FIG. 2 is a timing chart of the control device according to Embodiment 1. FIG. FIG. 6 is a diagram illustrating the timing of commutation generation according to the first embodiment. 3 is a block diagram illustrating a noise section determiner according to Embodiment 1. FIG. 6 is a block diagram illustrating a control device for a power converter according to a second embodiment. FIG.

Embodiment 1 FIG.
FIG. 1 is a block diagram showing a control device 20 for an inverter 16 that is a power converter according to the first embodiment. Hereinafter, for the sake of explanation, the inverter 16 is assumed to be a two-level single-phase inverter. The same applies to other embodiments regardless of the number of phases and the number of levels of the inverter 16.
In FIG. 1, a current command signal 2 output from a current command generator 1 in response to a command from a control device or the like of a load 17 is input to a current controller 3. The current controller 3 further receives a detection current signal 10 output from the current detector 9 via the sampling and holding device 14, and a voltage command so that the current flowing through the load 17 connected to the inverter 16 matches the current command. A current control operation for calculating is performed, and a voltage command signal 4 is output. The current controller 3 is composed of a feedback controller such as a PI controller, but may be composed of a two-degree-of-freedom type controller combining a feedback controller and a feedforward controller. The carrier generator 7 outputs a carrier signal 8 for pulse width modulation (PWM). The PWM pattern generator 5 inputs the voltage command signal 4 and the carrier signal 8 and outputs a switching pattern command 6. The inverter 16 drives each semiconductor element according to the switching pattern command 6 and supplies power to the load 17.
The current detector 9 detects the current of the load 17 and outputs a detected current signal 10. The sampling and holding device 14 samples and holds the detected current signal 10 according to the current sampling timing, and this detected current signal 10 is used by the current controller 3 as described above. The timing generator 15 outputs each sampling timing signal. The noise section determiner 11 receives the voltage command signal 4, the carrier signal 8, and the detection current signal 10, and predicts a noise generation section (a section that continues while attenuating after switching noise is generated) in the detection current signal 10. . Further, the current sampling timing is compared with the predicted noise generation interval, and the presence / absence of overlap between the two is output as the determination signal 12. The current controller 3 reduces the current control gain (current feedback control gain) of the feedback controller provided in the current controller 3 based on the determination signal 12 that the noise generation period and the current sampling timing overlap. Let When there is no overlap, the control operation is performed with the normal current control gain without reducing the current control gain. The effect of this current control gain reduction will be described in detail later.
As a result, even when switching noise is mixed in the detected current signal 10, the influence on the voltage command signal 4 can be suppressed, and the stability of the current control system can be ensured and the current control accuracy can be improved.

Next, the operation of the noise section determiner 11 will be described with reference to FIG.
2A is a configuration diagram of the inverter 16, and FIG. 2B is a diagram illustrating a timing chart of the control device 20 according to the first embodiment. In FIG. 2A, the inverter 16 is provided with a P-side switch and an N-side switch that are semiconductor switching elements. The P-side switch and the N-side switch are connected in series to form an upper and lower arm. In this embodiment, IGBTs (Insulated Gate Bipolar Transistors) are used as P-side switches and N-side switches, and FWDs (Free Wheeling Diodes) are connected in reverse parallel to each switch.
In FIG. 2B, the sampling and holding device 14 samples and holds the detected current signal 10 according to the current sampling timing (a). This current sampling timing is repeated at a predetermined period t.
2B is an operation in which the current command generator 1 generates the current command signal 2, and the current controller 3 uses the detected current signal 10, the determination signal 12, and the current command signal 2. The operation of calculating the voltage command signal 4 and the operation of the noise interval determiner 11 calculating the determination signal 12 using the detected current signal 10, the carrier signal 8, and the voltage command 4. Since this series of control calculations requires a predetermined time, a voltage command signal (duty command) 4 is output after a predetermined time from the current sample hold, that is, at the voltage command update timing (b). The update cycle of the voltage command signal 4 is also t. Pay attention to the timing (a) in FIG. The time required for the control calculation is known in advance. A series of operations for current control is performed at a period t, but the value of the carrier signal 8 is updated at a higher speed. If the carrier signal value is known at the timing (a), the rate of change of the carrier signal 8 is constant, so the timing (h) when the voltage command signal 4 and the carrier signal 8 cross based on information such as the voltage command signal 4 and the calculation time. ) Can be predicted. The switching commands for the P-side and N-side switches shown in FIG. 2 (A) based on the predicted cross timing are (c) and (d) in FIG. 2 (B), respectively. However, the dead time (off both the upper and lower switching for device protection) t _D is provided. Generally, it is often provided with a delay in the OFF → ON timing. When the inverter 16 operates according to the switching commands (c) and (d) on the P side and the N side, an output voltage as shown in FIG. Vdc is a DC side voltage. If current during the dead time t _D section is positive (positive a side facing from the inverter 16 to the load 17), the output voltage becomes 0V. When the P-side switching command changes from on to off, the current path changes from the P-side switch to the N-side diode. That is, commutation occurs. For this reason, switching noise as shown in FIG. Switching noise generation start timing is defined as switching noise timing.
Switching noise gradually attenuates but continues for a certain period. This is determined by load wiring, LC appearing in the inverter 16 and the like, but it is possible to grasp in advance the period of decay to a level where there is no problem. In this way, a section in which the influence of switching noise is concerned, that is, a switching noise generation section T is obtained. The switching noise generation period T is compared with the next timing (A) of the timing (A), and if there is an overlap between them, the noise period determiner 11 outputs the determination signal 12 as “with overlap”. The timing of (a) is t “sec” after the timing of (a) and can be easily understood.
When time elapses and the timing (b) is reached, the current controller 3 confirms whether or not the determination signal 12 is overlapped. If there is an overlap (when the detected current signal includes a noise component), the current control system. Reduce the current control gain.
In FIG. 2B, since the polarity of the current is positive (the direction from the inverter 16 toward the load 17 is positive), commutation occurs at the same timing as when the P-side switching command is turned off, and switching noise occurs. That is, it shows a case where the P-side command is ON → OFF, the N-side command is OFF → ON, and the current is positive.
In order to prevent noise, it is important to know the generation timing of commutation that causes noise generation, and there are actually the following cases (a) to (ii). That is,
(A) P side command is ON → OFF, N side command is OFF → ON, current is positive (Yes) P side command is ON → OFF, N side command is OFF → ON, current is negative (U) P side command Is off → on, N side command is on → off, current is positive (e) P side command is off → on, N side command is on → off, current is negative Figure 3 shows carrier signal, voltage command and current The polarity and the timing of occurrence of switching noise are shown.

The noise section determiner 11 has a configuration as shown in the block diagram of FIG. In FIG. 4, the noise section determiner 11 includes a carrier predictor 11a, a cross timing calculator 11c, a commutation timing calculator 11e, and a determiner 11g. The carrier predictor 11a samples the carrier signal 8 at startup, predicts the carrier signal waveform up to the next current sampling timing, and outputs it as a predicted carrier signal 11b. The cross timing calculator 11c obtains the timing at which both cross from the voltage command signal 4 and the predicted carrier signal 11b, and outputs a cross timing signal 11d. In commutation timing calculator 11e, considering the length of the cross timing signal 11d and the detection current signal 10 and the dead time t _D outputs a commutation timing signal 11f. The determination unit 11g compares the switching noise generation period T starting from the commutation timing with the next current sampling timing, and outputs the presence / absence of the overlap as a determination signal 12.
In FIG. 4, the case where the single phase inverter was applied as a power converter was shown. Depending on the number of phases, the number of levels of the inverter, and the dead time correction mechanism, the configuration is different until the commutation timing is predicted, but the function of performing the determination operation after obtaining the commutation timing is the same. In the technique disclosed in Patent Document 1, since the switching noise generation timing is determined based on the on / off command to the inverter switching element, the switching noise generation timing may shift due to the dead time. In Embodiment 1 of the present invention, an accurate switching noise generation timing can be obtained by adopting the configuration described above.
In the above description, the current controller 3 is the current control gain. The current controller 3 decreases the current feedback control gain of the feedback controller provided in the current controller 3 in accordance with the determination signal 12. The gain may be lowered, or the gain of the proportional term output by multiplying the deviation between the detected current signal 10 and the voltage command signal 4 by a predetermined value may be lowered. This is because the proportional term reacts greatly to sudden signals such as switching noise.

Here, the importance of lowering the current control gain will be described.
Lowering the current control gain reduces the current control response bandwidth and lowers the overall system performance. However, when the switching noise is significant, the voltage command is greatly shaken by the noise. As a result, the net current other than noise (current to be controlled) is greatly disturbed, and further, the current control system operates to suppress it, and the voltage command is disturbed. As the current control response band is increased (that is, the current control gain is increased), this phenomenon becomes more prominent and may become unstable.

  As described above, the power converter control device 20 according to the first embodiment determines the influence on the detected current signal 10 even when the switching timing is close or the number of times of switching per unit time increases. Thus, by reducing the current feedback control gain, it is possible to secure the stability of the system and to realize highly accurate current control without excessively reacting to switching noise. In addition, in an inverter using a wide band gap semiconductor such as SiC, it is assumed that switching noise becomes particularly significant due to use at a high carrier frequency and high switching speed. Current disturbance can be suppressed, and highly accurate current control can be realized. As a result, there are effects such as reduction in energy consumption.

Embodiment 2. FIG.
The second embodiment will be described below.
FIG. 5 shows a control device 20 for a power converter according to the second embodiment. Components having the same reference numerals as those in FIG. 1 in the first embodiment have the same functions as those described in the first embodiment, and thus description thereof is omitted. In the second embodiment, the detection current signal 10 is input to the filter 13. The filtered detected current signal 18 output from the filter 13 is input to the current controller 3 and used for current control processing. The noise section determiner 11 has the same function as that described in the first embodiment, and determines whether the detection current signal 10 overlaps the switching noise timing and the current sampling timing. The filter 13 includes a plurality of sub-filters having different cutoff frequencies, and performs filter switching using the determination signal 12 as an input. That is, when it is predicted by the determination signal 12 that switching noise is mixed in the detected current signal 10, the filtered detection current signal 18 is selected by selecting the output of the sub-filter having a low cutoff frequency and capable of removing the switching noise component. Output as. That is, since the filter is used only when switching noise occurs, it is possible to obtain a detection current signal with little phase delay as a whole while avoiding switching noise. When the entire control device is mounted by a fixed-point processor or ASIC, the mounting becomes easier compared to the first embodiment. Needless to say, in addition to the configuration in which the filter 13 switches the sub-filter, the same effect can be obtained by switching the filter gain.

1 Current command generator, 2 Current command signal, 3 Current controller, 4 Voltage command signal,
7 carrier generator, 8 carrier signal, 10 detection current signal,
11 noise section determiner, 12 determination signal, 13 filter,
14 sampling hold device, 17 load, 20 control device.

Claims (2)

A control device for a power converter provided with a semiconductor switching element, the control device including a carrier generator that generates a carrier signal, a current command generator that outputs a current command signal, and the power converter a current detector for detecting a current of the connected load, a sampling hold circuit for outputting a detection current signal samples and holds the said detected load current at a predetermined sampling timing having a period shorter than the carrier signal period, the operates in short cycles than the carrier signal period input and said detection current signal and the current command signal, and a current controller that outputs a voltage command signal by calculating, is provided with a noise section determination unit, the noise The section determiner predicts a switching noise generation section of the power converter from the detected current signal, the voltage command signal, and the carrier signal. Determining whether or not the switching noise generation interval overlaps with the sampling timing, and the current controller reduces the current control gain based on the determination signal with overlap output from the noise interval determiner. A control device for a power converter characterized by the above. In addition to the control device, a filter is provided that inputs the detection current signal and a determination signal from the noise section determination device, filters the detection current signal, and outputs the filtered signal to the current controller. Incorporates a plurality of sub-filters having different cutoff frequencies, and selects a sub-filter having a lower cutoff frequency among the plurality of sub-filters when the determination signal with the overlap is inputted, and filters the detected current signal The control device for the power conversion device according to claim 1.

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