JP5163410B2 - Image sensor and camera - Google Patents

Description

  The present invention relates to an image sensor and a camera that take an image by converting light into an electrical signal.

In recent years, video cameras and electronic cameras using an image sensor that converts light into an electrical signal and captures an image are widely used. The output signals of these image sensors are shifting from conventional analog signals to digital signals, and digital circuits such as A / D conversion are built in the image sensors to perform high-speed digital processing. (For example, refer to Patent Document 1).
JP 2008-072162 A

  However, there is a problem that noise is mixed into a weak image signal read from each pixel by a circuit that operates with a high-speed clock signal used in a digital circuit, and the SN ratio of the image signal is deteriorated.

  An object of the present invention is to provide an imaging device and a camera that can output digital signals and have low noise.

  An image sensor according to the present invention includes a pixel unit that converts light into an electrical signal, a dark signal holding unit that reads and holds a dark signal of the pixel unit, and an image signal holding that reads and holds an image signal of the pixel unit. A reference signal generation unit that generates a reference signal, a dark signal comparison unit that compares the dark signal and the reference signal, an image signal comparison unit that compares the image signal and the reference signal, and the dark An exclusive OR operation unit for calculating an exclusive OR of the output of the signal comparison unit and the output of the image signal comparison unit is provided.

  More preferably, the reference signal generator is configured by a circuit that generates a ramp signal.

  More preferably, the reference signal generating unit generates a reference signal including a gamma characteristic when displaying an image photographed by the image sensor.

  More preferably, the two different pixel portions are a first pixel portion and a second pixel portion, and the exclusive OR operation portions used in the first pixel portion and the second pixel portion are respectively first exclusive. A first differentiation circuit for differentiating an output of the first exclusive OR operation unit with a predetermined time constant; and a second exclusive OR operation unit. A second differentiating circuit for differentiating the output with a time constant different from the time constant of the first differentiating circuit; and an output for calculating an exclusive OR of the output of the first differentiating circuit and the output of the second differentiating circuit. An exclusive OR operation unit is further provided.

  A camera according to the present invention includes the above-described imaging device, a photographing optical system, a photographing control unit, and an image recording unit.

  According to the present invention, it is possible to realize an image sensor and a camera that output a digital signal with less noise.

(First embodiment)
FIG. 1 is a block diagram illustrating a configuration of an image sensor 101 according to the first embodiment. Note that the imaging element 101 corresponds to an imaging device to which a circuit that outputs an image signal with a pulse width or a pulse position is added. Therefore, a photographing optical system composed of a lens, a diaphragm, a shutter, and the like, and a photographing that records an image signal photographed by the image sensor 101 when the shutter is opened and closed by performing exposure control using the diaphragm and the shutter. By providing the control unit, a camera having the features of the present embodiment can be realized.

  In FIG. 1, an image sensor 101 has N × M pixels P (n, m) each having a photoelectric conversion unit that converts light into an electrical signal, arranged in a matrix of N rows and M columns. Here, n is a natural number from 1 to N, and m is a natural number from 1 to M. In addition, the image sensor 101 is provided with a vertical signal line VLINE (m), a constant current source PW (m), and a signal amplification / accumulation unit SGA (m) for each column from 1 to M. Further, a timing generation circuit 102, a horizontal output circuit 103, and a pulse output circuit 104 are provided as circuits related to the operation of the entire image sensor 101.

  A signal output from each pixel P (n, m) is read in units of rows to the vertical signal line VLINE (m) corresponding to each column. Note that a constant current source PW (m) constituting a source follower circuit is arranged for each column in the vertical signal line VLINE (m) of each column.

  The timing generation circuit 102 outputs a timing signal for reading the signal output from the pixel P (n, m) to the vertical signal line VLINE (m) of each column in units of rows. For example, in the first row, a timing signal φSEL (1), a timing signal φRES (1), a timing signal φTX (1) are applied to M pixels from the pixel P (1,1) to the pixel P (1, M). )give. The operation of each timing signal will be described in detail later.

  The signal amplification / accumulation unit SGA (m) includes an image signal including optical information of a captured image read for each column from the M × N pixels P (n, m), and a noise component before the image signal is accumulated. After being amplified by the column amplifiers, the dark signals including are stored in the respective capacitors. The M sets of image signals Vsg (m) and dark signals Vdk (m) accumulated in the capacitors are output to the horizontal output circuit 103 for each column. The configuration of the signal amplification / accumulation unit SGA (m) will be described later in detail.

  The horizontal output circuit 103 reads out one row of the image signal Vsg (m) and the dark signal Vdk (m) from the M signal amplification / accumulation units SGA (m), and outputs a pulse in the CCD method for each pixel. Output to the circuit 104. A circuit in the case of not using the CCD system will be described later.

  The pulse output circuit 104 subtracts the dark signal Vdk from the image signal Vsg output in units of pixels from the horizontal output circuit 103 in order to reduce the variation of the column amplifier in the signal amplification / accumulation unit SGA (m). An image signal IMGout from which variations between column amplifiers provided for each column are removed is output to the outside of the image sensor 101. In particular, in the present embodiment, the image signal IMGout is output with a binary pulse width representing a luminance value.

  Next, the circuit configuration of the pixel P (1,1) in FIG. 1 will be described with reference to FIG. The M × N pixels P (n, m) are the same circuit as the pixel P (1,1) shown in FIG. In FIG. 2, the pixel P (1,1) includes a photodiode PD, a transfer transistor Tr1, an amplification transistor Tr2, a selection transistor Tr3, and a reset transistor Tr4. Note that VDD indicates a power source, GND indicates ground, and FD indicates a floating diffusion portion (floating diffusion region). The timing signal φSEL (1), timing signal φRES (1), timing signal φTX (1), and vertical signal line VLINE (1) are the same as those in FIG.

  In FIG. 2, light incident on the photodiode PD is photoelectrically converted and accumulated as electric charges. The electric charge accumulated in the photodiode PD is transferred to the FD section when the timing signal φTX (1) is input to the gate of the transfer transistor Tr1, and is amplified by the amplifying transistor Tr2. The signal amplified by the amplifying transistor Tr2 is read out to the vertical signal line VLINE (1) when the timing signal φSEL (1) is input to the gate of the selection transistor Tr3. The signal read at this time is an image signal. When the timing signal φRES (1) is input to the gate of the reset transistor Tr4, the FD portion is reset to the reset voltage (VDD). The signal read at this time is a dark signal.

  In this way, after the signals of M × N pixels P (n, m) are read out to the corresponding vertical signal lines VLINE (1) to (M) of the respective columns, the signals are read for each column. The signals are output to the arranged signal amplification / accumulation units SGA (1) to (M).

  Next, the configuration of the signal amplification / accumulation units SGA (1) to (M) will be described with reference to FIG. FIG. 3 shows a circuit after image signals and dark signals are read out from one row of pixels P (n, m) to M vertical signal lines VLINE (1) to (M). Here, the configuration of the signal amplification / accumulation unit SGA (1) in the first column will be described. The signal amplification / accumulation unit SGA (M) in the Mth column in FIG. 3 has the same circuit configuration, and signal amplification / accumulation units SGA (m) in other columns not shown in the figure also have the same circuit configuration.

  In the signal amplification / accumulation unit SGA (1) in the first column, for example, from the pixel P (1,1) in the first row to the vertical signal line VLINE (1) constituting the source follower circuit by the constant current source PW (1). The read signal is input to the capacitor Cin of the signal amplification / accumulation unit SGA (1). The capacitor Cin is connected to the − input terminal of the column amplifier CAMP, and the + input terminal is grounded.

  Here, the column amplifier CAMP is an inverting amplifier in which the ratio of the capacitor Cf and the capacitor Cin is an amplification factor. The source and drain of the amplifier reset transistor Tr5 are connected to both ends of the capacitor Cf of the feedback circuit of the column amplifier CAMP. When the timing signal φCARST output from the timing generation circuit 102 is input to the gate of the transistor Tr5, The source and drain of the transistor Tr5 become conductive, and the charge accumulated in the capacitor Cf is discharged to reset the column amplifier CAMP. In this circuit, the signal component accumulated in the capacitor Cin when the dark signal is being read is subtracted from the image signal to be read next, so that it is possible to remove noise components that differ from pixel to pixel.

  The output CAOUT of the column amplifier CAMP is connected to the drains of the image signal storage transistor Tr6 and the dark signal storage transistor Tr7. When the timing signal φTS output from the timing generation circuit 102 is input to the gate of the transistor Tr6, the transistor Tr6 is turned on and the capacitor Cts is charged until the voltage of the image signal output from the column amplifier CAMP is reached. When the timing signal φTD output from the timing generation circuit 102 is input to the gate of the transistor Tr7, the transistor Tr7 is turned on, and the capacitor Ctd is charged until the voltage of the dark signal output from the column amplifier CAMP is reached. The voltage of the capacitor Cts is input to the horizontal output circuit 103 as the image signal Vsg (1), and the voltage of the capacitor Ctd is input as the dark signal Vdk (1).

  In this way, the signal amplification / accumulation units SGA (1) to (M) for each of the M columns receive the image signal and the dark signal that are read out in units of rows from the pixels P (n, m) of the M columns. Once held in a capacitor, M sets of image signals Vsg (m) and dark signals Vdk (m) are output to the horizontal output circuit 103 for each column.

  The horizontal output circuit 103 outputs M image signals Vsg (m) and dark signals Vdk (m) read out from the M pixels P (n, m) in units of rows in a CCD manner for each pixel in accordance with the timing signal φLM. Read out and output to the pulse output circuit 104 as an image signal Vsg and a dark signal Vdk. Here, the timing signal φLM output from the timing generation circuit 102 is a timing signal serving as a reference for processing for each pixel, and is output for each pixel.

  Next, the configuration of the pulse output circuit 104 will be described with reference to FIG. The pulse output circuit 104 includes a ramp signal generation circuit (LAMP) 105, a comparator (CMP) 106, a comparator (CMP) 107, and an exclusive OR operation unit (EXOR) 108. The LAMP 105 is a circuit that outputs a ramp signal that linearly changes in a sawtooth shape from a start voltage to an end voltage, and repeatedly outputs the ramp signal for each timing signal φLM. Note that the timing signal φLM output from the timing generation circuit 102 gives the timing at which the horizontal output circuit 103 outputs the image signal Vsg (m) and the dark signal Vdk (m) for each pixel as described above. , LAMP 105 is a timing signal that serves as a reference for the generation period of the ramp signal output for each pixel.

  Here, a circuit example of the LAMP 105 will be described with reference to FIG. The LAMP 105 shown in FIG. 4 includes a constant current source CPL1, a capacitor C1, a switch SW1 that turns on and off the supply of power to the constant current source CPL1, a switch SW2 that resets the charge accumulated in the capacitor C1, and an inverter INV1. It consists of. Further, a timing signal φLM output from the timing generation circuit 102 is input as a signal for controlling the switches SW1 and SW2. The timing signal φLM controls the switch SW1 as it is, and controls the switch SW2 via the inverter INV1. That is, the switch SW1 and the switch SW2 perform complementary operations, and the switch SW2 is open while the switch SW1 is closed. Conversely, the switch SW1 is open while the switch SW2 is closed. The switch SW1 is closed when the timing signal φLM is at a high level, and the switch SW2 is closed when the timing signal φLM is at a low level.

  For example, when the timing signal φLM is at a low level, the charge of the capacitor C1 is reset, and when the timing signal φLM is at a high level, the constant current source CPL1 operates to charge the capacitor C1 with a constant current. As a result, the ramp signal LAMPout output from the capacitor C1 rises linearly from the ground voltage to the power supply voltage in a sawtooth shape. When the switch SW1 is turned off and the switch SW2 is turned on again, the charge of the capacitor C1 is reset, and the ramp signal LAMPout output from the capacitor C1 returns to the ground voltage. Thus, the ramp signal LAMPout is output in synchronization with the timing signal φLM. Actually, for example, when the signal voltage range of the image signal Vsg (m) and the dark signal Vdk (m) output from each pixel P (n, m) is 0.2V (volt) to 1.2V, The start voltage and end voltage of the ramp signal output from the LAMP 105 are set to voltages including the signal voltage range of the image signal Vsg (m) and the dark signal Vdk (m), such as 0V to 1.5V, respectively.

  In FIG. 3, the ramp signal LAMPout output from the LAMP 105 is given as a reference voltage for the positive input terminals of the CMP 106 and the CMP 107. On the other hand, the dark signal Vdk for each pixel is input from the horizontal output circuit 103 to the negative input terminal of the CMP 106, and the image signal Vsg for each pixel is input from the horizontal output circuit 103 to the negative input terminal of the CMP 107. The CMP 106 compares the dark signal Vdk with the ramp signal LAMPout and outputs a dark signal CMPdk. Similarly, the CMP 107 compares the image signal Vsg and the ramp signal LAMPout and outputs the image signal CMPsg. Here, the image signal CMPsg and the dark signal CMPdk are converted into binary pulses. That is, the analog image signal Vsg and dark signal Vdk output from the horizontal output circuit 103 are binary values of the image signal CMPsg and the dark signal CMPdk indicated by the pulse widths corresponding to the respective signal voltages by the LAMP 105, the CMP 106, and the CMP 107. Are converted into pulses.

  The dark signal CMPdk and the image signal CMPsg converted into binary pulses are input to the EXOR 108 and subjected to an exclusive OR operation, and output from the image sensor 101 as the image signal IMGout. Here, the EXOR 108 performs processing for obtaining a difference between the image signal CMPsg and the dark signal CMPdk. That is, since the binary signal having a length obtained by subtracting the pulse width of the dark signal CMPdk from the pulse width of the image signal CMPsg is obtained as the output of the EXOR 108, the EXOR 108 includes M column amplifiers arranged for each column. The same function as the correlated double sampling circuit for removing the variation of CAMP (m) is realized. The timing of each pulse will be described in detail later.

  In this way, the pulse output circuit 104 converts the analog image signal Vsg and dark signal Vdk output in units of pixels from the horizontal output circuit 103 into binary pulses, and between column amplifiers provided for each column. The binary image signal IMGout from which the variation of the image is removed is output to the outside of the image sensor 101.

  Here, an operation sequence at the time of reading pixels for one row in the image sensor 101 will be described with reference to FIG. FIG. 5 is a diagram mainly illustrating an operation sequence when reading the n-th row of the image sensor 101. In FIG. 5, the read operation of the (n−1) th row is shown until timing T21, the read operation of the nth row is shown from timing T21 to timing T27, and the read operation of the (n + 1) th row is shown after timing T27. Each is shown. Hereinafter, the read operation of the nth row will be described.

  (Operation from Timing T21 to Timing T22) When reading signals from M pixels in the n-th row, first, signals from M pixels P (n, m) for one row in the n-th row from timing T21 to timing T22. Read simultaneously. The image signal and dark signal read at this time are respectively held in the capacitor Csg (m) and the capacitor Cdk (m) of the signal amplification / accumulation unit SGM (m) of each column.

  (Operation from Timing T22 to Timing T23) The horizontal output circuit 103 includes M pieces of M for one row respectively held by the capacitors Csg (m) and the capacitors Cdk (m) of the M signal amplification / accumulation units SGM (m). The image signal Vsg (m) and the dark signal Vdk (m) are output to the pulse output circuit 104 as the image signal Vsg and the dark signal Vdk pixel by pixel in accordance with the timing signal φPX. As described above, during the period from the timing T22 to the timing T23 in FIG. 5, the capacitor Csg (1) and the capacitor Cdk () of the signal amplification / accumulation unit SGM (1) read out from the pixel P (n, 1) in the first column. The image signal Vsg (1) and the dark signal Vdk (1) held in 1) are output to the pulse output circuit 104, respectively. Then, the pulse output circuit 104 converts the image signal Vsg (1) and the dark signal Vdk (1) of the pixel P (n, 1) into a pulse width by the method described above, and the second row in the first column in the nth row. The image signal 101 is output as a value image signal IMGout.

  (Operation from Timing T23 to Timing T24) The horizontal output circuit 103 reads out the pixel P (n, 2) in the next column (second column) and uses the capacitor Csg (2) of the signal amplification / accumulation unit SGM (2). ) And the capacitor Cdk (2), the image signal Vsg (2) and the dark signal Vdk (2) respectively read out in accordance with the timing signal φPX and output to the pulse output circuit 104. The pulse output circuit 104 converts the image signal Vsg (2) and the dark signal Vdk (2) of the pixel P (n, 2) in the second column into a pulse width, and the binary value in the second column in the nth row. The image signal IMGout is output from the image sensor 101.

  Similarly, from timing T24 to timing T25, the image signal Vsg (3) and the dark signal Vdk (3) of the pixel P (n, 3) in the third column are converted into pulse widths, and three columns in the nth row. Output from the image sensor 101 as a binary image signal IMGout of the eye.

  Also from the last timing T26 to timing T27, the image signal Vsg (M) and the dark signal Vdk (M) of the pixel P (n, M) in the Mth column are converted into pulse widths, and the Mth column in the nth row. Is output from the image sensor 101 as a binary image signal IMGout.

  In this way, the horizontal output circuit 103 sequentially reads out the image signals for M columns in the n-th row for each pixel, and the pulse output circuit 104 converts the image signals for M columns into pulse widths, Is output from the image sensor 101 as a binary image signal IMGout for one row. In the period from timing T27 to timing T28, image signals and dark signals are read from M pixels P (n + 1, m) for one row of the next (n + 1) th row, and signal amplification / accumulation units for each column are read out. The SGM (m) is held in the capacitor Csg (m) and the capacitor Cdk (m), respectively. Thereafter, similarly, image signals for N columns of the image sensor 101 are output as binary image signals IMGout, and reading of the image signals for one image captured by the image sensor 101 is completed.

  Next, the operation of the circuit described with reference to FIGS. 1 to 4 will be described in detail with reference to the timing chart of FIG. FIG. 6 is a diagram illustrating in detail the operation from timing T21 to timing T23 in FIG. 6, the N timing signals φRES (n), φTX (n), φSEL (n) output from the timing generation circuit 102 for each row, and the timing signals φCARST, φTD, φTS, φLM described in FIG. The analog image signal Vsg (m) and the dark signal Vdk (m) output from the horizontal output circuit 103 (there are actually M sets of signals), the ramp signal LAMPout output from the LAMP 105, and the CMP 106 and CMP 107, respectively. 5 is a timing chart depicting a binary dark signal CMPdk and an image signal CMPsg to be output, and a binary image signal IMGout that is finally output by the pulse output circuit 104. FIG.

In FIG. 6, during the period up to the first timing T0, the timing signal φRES (n) is input to the gate of the reset transistor Tr4, and the FD portion of each pixel (n, m) is reset to the reset voltage.
(Timing T0) The timing signal φRES (n) is turned off, and the reset of the FD section is released.
(Timing T1) The timing signal φSEL (n) is input to the gate of the selection transistor Tr3, and the charge accumulated in the FD portion is read to the vertical signal line VLINE (m) via the amplification transistor Tr2. At this time, since the FD portion has been reset to the reset voltage, the voltage read to the vertical signal line VLINE (m) hardly changes.
(Timing T2) When the timing signal φTD is input to the gate of the dark signal storage transistor Tr7, the column amplifier CAMP amplifies the signal of the vertical signal line VLINE (m) and outputs the capacitor Ctd from the output CAOUT via the transistor Tr7. To accumulate. The time accumulated in the capacitor Ctd is the ON period of the timing signal φTD.
(Timing T3) When the timing signal φCARST is input to the gate of the amplifier reset transistor Tr5, the capacitor Cf in the feedback circuit of the column amplifier CAMP is short-circuited. That is, the output CAOUT of the column amplifier CAMP is reset. The time for resetting the column amplifier CAMP is an ON period of the timing signal φCARST.
(Timing T4) When the timing signal φCARST is turned off, the column amplifier CAMP again amplifies the signal of the vertical signal line VLINE (m) and starts accumulation in the capacitor Ctd from the output CAOUT via the dark signal accumulation transistor Tr7. To do. The time accumulated in the capacitor Ctd is a period up to the timing T5 when the timing signal φTD is turned off.
(Timing T5) When the timing signal φTD is turned off, the transistor Tr7 is also turned off, and the accumulation from the output CAOUT of the column amplifier CAMP to the capacitor Ctd is completed.
(Timing T6) A timing signal φTX (n) is input to the gate of the transfer transistor Tr1, and the charge accumulated in the photodiode PD is transferred to the FD portion. At this time, the voltage of the FD portion that has been reset to the reset voltage decreases according to the amount of charge transferred from the photodiode PD, and the vertical signal line VLINE (m) is passed through the amplification transistor Tr2 and the selection transistor Tr3. The signal voltage read out at the same time also decreases.

At timing T6, when the timing signal φTS is input to the gate of the transistor Tr6, the column amplifier CAMP amplifies the signal of the vertical signal line VLINE (m) and outputs the output CAOUT to the capacitor Cts via the transistor Tr6. accumulate. The time accumulated in the capacitor Cts is the ON period of the timing signal φTS.
(Timing T7) The timing signal φTX (n) is turned off, and the transfer of charges from the photodiode PD to the FD portion is completed.
(Timing T8) When the timing signal φTS is turned off, the transistor Tr6 is also turned off, and the accumulation from the output CAOUT of the column amplifier CAMP to the capacitor Cts ends.

  As described above, in each pixel P (n, m), the dark signal of the FD portion before being transferred from the photodiode PD to the FD portion is read and accumulated in the capacitor Ctd, and subsequently accumulated in the photodiode PD. The read image signal is read out and stored in the capacitor Cts. The operation so far corresponds to the operation from the timing T21 to the timing T22 described in FIG.

  Next, in FIG. 6, from the timing T22 to the timing T23, the n-th first column held in the capacitor Csg (1) and the capacitor Cdk (1) of the signal amplification / accumulation unit SGM (1) in the first column, respectively. The image signal Vsg (1) and dark signal Vdk (1) of the pixel P (n, 1) of the pixel P is read out to the pulse output circuit 104 via the horizontal output circuit 103, and the image signal IMGout is output.

  First, when the timing signal φLM is turned on (high level) at timing T8, the horizontal output circuit 103 outputs the image signal Vsg (1) and dark signal Vdk (1) in the first column to the pulse output circuit 104. At the same time, as described with reference to FIG. 4, the ramp signal LAMPout output from the LAMP 105 increases linearly. At timing T9, when the level of the ramp signal LAMPout exceeds the level of the dark signal Vdk (1), the binary dark signal CMPdk output from the comparator CMP106 is inverted and becomes a high level. At the same time, the binary image signal IMGout output from the pulse output circuit 104 is also inverted to a high level.

  Subsequently, when the ramp signal LAMPout increases linearly, the level of the ramp signal LAMPout exceeds the level of the image signal Vsg (1) at timing T10. Then, the binary image signal CMPsg output from the comparator CMP107 is inverted to a high level. At the same time, the binary image signal IMGout output from the pulse output circuit 104 is re-inverted and returns to the Low level.

  Thereafter, the ramp signal LAMPout further increases. However, when the timing signal φLM is turned off (low level) at timing T11, the ramp signal LAMPout output by the LAMP 105 is reset to 0 as described with reference to FIG. Return. At the same time, the binary dark signal CMPdk output from the comparator CMP106 and the binary image signal CMPsg output from the comparator CMP107 are also at the low level. The EXOR 108 is timing-controlled so that whisker-like noise does not occur due to a subtle timing difference between the dark signal CMPdk and the image signal CMPsg. Alternatively, a filter that removes minute whisker-like noise may be provided in the output of the EXOR 108.

  Similarly, the image signal Vsg (1) and the dark signal Vdk (1) in the first column are output from the horizontal output circuit 103 to the pulse output circuit 104, converted into a binary image signal IMGout, and output from the image sensor 101. Is output.

  In this manner, the image signals for M columns are sequentially read, and the image signals for M columns in the nth row are converted into pulse widths and output from the image sensor 101 as image signals IMGout. In particular, in the present embodiment, since the dark signal CMPdk is subtracted from the image signal CMPsg by the EXOR 108, a correlated double sampling circuit that corrects signal variations with a simple circuit can be realized.

  In the present embodiment, a CCD type circuit example is shown in which the horizontal output circuit 103 sequentially outputs M image signals and dark signals for one row for each pixel in accordance with the timing signal φLM. In the case of a circuit, it can be realized by a circuit configuration as shown in FIG. 7 until the image signal Vsg (m) and the dark signal Vdk (m) are read and held in the M signal amplification / accumulation units SGM (m) provided for each column. The M pulse output circuits 104 (m) from the pulse output circuit 104 (1) to the pulse output circuit 104 (M) having the same configuration as the pulse output circuit 104 of FIG. 3 are provided for each column. It has been. Then, M binary image signals IMGouta (m) are output from the image sensor 101 for every M pulse output circuits 104 (m). In this case, it is necessary to provide the image sensor 101 with terminals for outputting M image signals from the image signal IMGout (1) to the image signal IMGout (M).

  In the present embodiment, the example in which the pulse output circuit 104 is configured by the LAMP 105, the CMP 106, the CMP 107, and the EXOR 108 is shown. However, the pulse output circuit 104 may be a circuit that can perform signal generation and timing control similar to those in FIG. The same effect can be obtained. Further, although the LAMP 105 uses a circuit whose output increases linearly, for example, a signal having a shape including a gamma characteristic may be output. In this case, an image signal subjected to gamma conversion can be output from the image sensor 101, so that a gamma conversion circuit in the subsequent stage is not necessary.

(First modification of this embodiment)
Next, a first modification of the above-described embodiment will be described. Note that image signals and dark signals are read out from N × M pixels P (n, m) in units of rows, and capacitors Csg (m) and capacitors Cdk (m) of M signal amplification / storage units SGM (m) are read out. ) And the operation to hold each is the same as in the previous embodiment.

  FIG. 8 is a circuit diagram subsequent to the horizontal output circuit 103 in the first modification. In the first modification, a horizontal output circuit 103a and pulse output circuits 104a and 104b having the same configuration as that of the pulse output circuit 104 are provided instead of the horizontal output circuit 103 described in the above embodiment. A synthesis circuit 201 for synthesizing the outputs of the two pulse output circuits 104a and 104b is provided.

  In FIG. 8, the horizontal output circuit 103a outputs the odd-numbered image signals Vsg (2j-1) and Vdk (2j-1) and the even-numbered image signals Vsg (2j) and Vdk (2j) simultaneously. Here, j is a natural number from 1 to (M / 2). M represents the number of columns used previously, and here, M is an even number.

  The odd-numbered image signals Vsg (2j-1) and Vdk (2j-1) read from the horizontal output circuit 103a are input to the pulse output circuit 104a. The even-numbered image signals Vsg (2j) and Vdk (2j) are input to the pulse output circuit 104b. Then, the pulse output circuit 104 a outputs the binary image signal OUTa in the odd-numbered column and the binary image signal OUTb in the even-numbered column and is input to the synthesis circuit 201. Note that the binary image signals OUTa and OUTb are signals similar to the IMGout described above with reference to FIG.

  Next, a configuration example of the synthesis circuit 201 will be described. As shown in FIG. 8, the synthesis circuit 201 includes a capacitor Ca1, a capacitor Ca2, a resistor R1, a resistor R2, a buffer BUF1, a buffer BUF2, and an exclusive OR operation unit (EXOR) 202. The In the combining circuit 201, a buffer BUF1 that passes through a differentiating circuit a composed of a capacitor Ca1 and a resistor R1 with respect to the binary image signal OUTa in the odd-numbered column so that the differentiating circuit a is not affected by the EXOR 202. Is input to the EXOR 202. Similarly, the binary image signal OUTb of the even-numbered column passes through a differentiating circuit b composed of a capacitor Ca2 and a resistor R2, and the differentiating circuit b is not affected by the EXOR 202 through a buffer BUF2. And input to EXOR 202. The output of the EXOR 202 is a binary image signal IMGouta output from the image sensor 101. Note that the time constants of the differentiation circuit a and the differentiation circuit b are different.

  Next, an operation example of the synthesis circuit 201 will be described with reference to FIG. FIG. 9 is a diagram showing the state of the waveform of each part of the circuit diagram of FIG. 8 denote the same components. FIG. 9 shows pixels P (1,1), pixels P (1,3) and pixels P (1,5) in the odd-numbered column in the first row, and pixels P (1,2) and pixels in the even-numbered column in the first row. This is an example of reading out P (1,4) and pixel P (1,6). First, since the odd-numbered pixels P (1,1) rise at timing T31, a pulse having a predetermined width corresponding to the time constant of the differentiating circuit a is output from the buffer BUF1. Next, since the pixels P (1,2) in the even columns rise at the timing T32, a pulse having a predetermined width corresponding to the time constant of the differentiating circuit b is output from the buffer BUF2. It is assumed that the time constant of the differentiation circuit a is smaller than the time constant of the differentiation circuit b. The rising position (timing T31) of the differentiating circuit a indicates the starting position of the binary image signal OUTa in the odd-numbered column, and the rising position (timing T32) of the differentiating circuit b is the start of the binary image signal OUTb in the odd-numbered column. Indicates the position. On the other hand, the end position of the binary image signal OUTa in the odd-numbered column and the end position of the binary image signal OUTb in the odd-numbered column always coincide with each other at the timing Te1, as shown at the timing T11 in FIG. Similarly, the timing Te2 of the end positions of the pixel P (1,3) and the pixel (1,4) and the timing Te3 of the end positions of the pixel P (1,5) and the pixel (1,6) are also the cycle of one pixel. In the same position as the timing Te1. Therefore, if only the pulse start positions of the image signal OUTa and the image signal OUTb are output from the image sensor 101, the pulse widths of the image signal OUTa and the image signal OUTb can be restored by an external circuit.

  In FIG. 9, in the example of the odd-numbered column pixel P (1,1) and the even-numbered column pixel P (1,2), the output pulse of the odd-numbered column buffer BUF1 and the output pulse of the even-numbered column buffer BUF2 overlap. Therefore, the image signal IMGouta output from the EXOR 202 does not overlap. Therefore, it is possible to determine the pulse start positions of the image signal OUTa and the image signal OUTb in the external circuit of the image sensor 101.

  Next, in the example of the odd-numbered pixel P (1,3) and the even-numbered pixel P (1,4), the pulse width output from the buffer BUF1 of the odd-numbered pixel P (1,3) at the timing T33. However, since it coincides with the rising edge of the pulse output from the buffer BUF2 of the even-numbered pixel P (1, 4) at the timing T34, the image signal IMGouta output from the EXOR 202 becomes one continuous wide pulse. End up. In this case, when discriminating the pulse start positions of the image signal OUTa and the image signal OUTb outside the imaging device 101, an error corresponding to the pulse width of the buffer BUF2 occurs at the maximum, but the error is reduced by narrowing the pulse width. Can be small.

  Furthermore, in the example of the odd-numbered pixel P (1,5) and the even-numbered pixel P (1,6), a pulse output from the buffer BUF1 of the odd-numbered pixel P (1,5) at timing T35; Since the rising edges of the pulses output from the buffer BUF2 of the pixels P (1, 6) in the even columns match, the image signal IMGouta output from the EXOR 202 can only see the pulses output from the buffer BUF2. In this case, when the external circuit of the image sensor 101 determines the pulse start positions of the image signal OUTa and the image signal OUTb, an error corresponding to the pulse width of the buffer BUF1 occurs at the maximum, but the error is reduced by reducing the pulse width. Can be reduced.

  As described above, since the binary image signal OUTa in the odd-numbered column and the binary image signal OUTb in the even-numbered column can be combined and output from the image sensor 101, the output time can be shortened compared to the previous embodiment. Is possible.

  When the present modification is realized with the CMOS circuit configuration as shown in FIG. 7 described in the previous embodiment, the circuit configuration is as shown in FIG. In FIG. 10, the combining circuit of FIG. 8 is provided for every two adjacent columns of M pulse output circuits 104 (m) from the pulse output circuit 104 (1) to the pulse output circuit 104 (M) arranged for each column. A synthesis circuit 201 (M / 2) is provided from the synthesis circuit 201 (1) having the same configuration as that of the 201. Here, the image signal OUTa in FIGS. 8 and 9 corresponds to the output of the pulse output circuit 104 (m) in the odd-numbered columns of the image signal OUTa (M-1) from the image signal OUTa (1) in FIG. The image signal OUTb in FIGS. 8 and 9 corresponds to the output of the pulse output circuit 104 (m) in the even column of the image signal OUTb (2) to the image signal OUTb (M) in FIG. 8 and FIG. 9 corresponds to the image signal IMGoutb (M / 2) from the M / 2 image signals IMGoutb (1) in FIG. Thus, in the embodiment of FIG. 7, M terminals for outputting M image signals from the image signal IMGout (1) to the image signal IMGout (M) are necessary. This can be realized with half the number of M / 2 terminals, so that the package size of the image sensor 101 can be reduced and the price can be reduced.

  In addition, even if the number of terminals remains M, the information of two pixels can be read out simultaneously, so the output time can be shortened compared to the first embodiment, and the frame rate and continuous shooting speed are improved. can do.

(Second modification of this embodiment)
Next, a second modification of the above-described embodiment will be described with reference to FIG. Note that, in the second modified example, as in the first modified example described with reference to FIG. 8, the image sensor is obtained by combining the binary image signal OUTa in the odd-numbered column and the binary image signal OUTb in the even-numbered column. 101, the differentiation circuit b of the synthesis circuit 201 is omitted. In FIG. 11, the same reference numerals as those in FIG. The synthesizing circuit 203 in the second modified example does not have the differentiating circuit b of the synthesizing circuit 201 in FIG. 8, and the output of the pulse output circuit 104 b is input to the EXOR 202 as it is.

  Next, an operation example of the synthesis circuit 203 according to the second modification will be described with reference to FIG. FIG. 12 is a diagram showing the state of the waveform of each part of the circuit diagram of FIG. 11 denote the same components. FIG. 12 shows the pixel P (1,1), the pixel P (1,3) and the pixel P (1,5) in the first row and the pixel P (1,2) and the pixel in the even column in the first row. This is an example of reading out P (1,4) and pixel P (1,6). First, since the odd-numbered pixels P (1,1) rise at timing T31, a pulse having a predetermined width corresponding to the time constant of the differentiating circuit a is output from the buffer BUF1. Here, the rising position (timing T31) of the differentiating circuit a indicates the start position of the binary image signal OUTa in the odd-numbered column. Next, the pixels P (1,2) in the even columns rise at timing T32, and the binary image signal OUTb output from the pulse output circuit 104b is input to the EXOR 202 as it is. On the other hand, as in FIG. 9 of the first modification, the timing Te1, the timing Te2, and the timing Te3 are at the same position in the cycle for each pixel, and the end positions of the pulses of the image signal OUTa and the image signal OUTb. It becomes. If only the pulse start position of the image signal OUTa is output from the image sensor 101 in this way, the pulse width of the image signal OUTa can be restored by an external circuit.

  In FIG. 12, in the example of the odd-numbered pixel P (1,1) and the even-numbered pixel P (1,2), the output pulse of the odd-numbered buffer BUF1 and the even-numbered image signal OUTb do not overlap. The image signal IMGoutb output from the EXOR 202 does not overlap, and an external circuit of the image sensor 101 can discriminate between an odd-numbered column signal and an even-numbered column signal.

  Next, in the example of the odd-numbered pixel P (1,3) and the even-numbered pixel P (1,4), the pulse width output from the buffer BUF1 of the odd-numbered pixel P (1,3) at the timing T33. However, since it overlaps with the rising edge of the pulse of the image signal OUTb output from the even-numbered pixel P (1, 4) at the timing T34, the image signal IMGoutb output from the EXOR 202 becomes one continuous wide pulse. End up. In this case, if the pulse width of the buffer BUF1 is known, the falling edges of the pulses are at the same timing Te2, so that it can be seen that they overlap at the rising portion. Therefore, it can be seen that the position where the rising edge of the pulse of the image signal IMGoutb is delayed by the pulse width of the buffer BUF1 is the falling position of the image signal OUTb, and the signal of the odd-numbered column and the signal of the even-numbered column can be discriminated.

  Further, in the example of the odd-numbered pixel P (1,5) and the even-numbered pixel P (1,6), the pulse output from the buffer BUF1 of the odd-numbered pixel P (1,5) at timing T35 is: They overlap in the middle of the pulse of the image signal OUTb output from the pixels P (1, 6) in the even columns. Therefore, the image signal IMGoutb output from the EXOR 202 is output by inverting the pulse width output from the buffer BUF1 in the middle of the pulse of the image signal OUTb. In this case, if the pulse width of the buffer BUF1 is known, the pulse width before the timing T35 is compared with the pulse width of the buffer BUF1, and if the pulse width before the timing T35 is wider than the pulse width of the buffer BUF1, It can be seen that it is not a pulse of the buffer BUF1. As a result, it can be seen that the portion where the pulse width of the buffer BUF1 is inverted at the timing T35 is the position of the pulse output from the buffer BUF1, and in the external circuit of the image sensor 101, the signal of the odd column and the signal of the even column Can be determined.

  As described above, since the binary image signal OUTa in the odd-numbered column and the binary image signal OUTb in the even-numbered column can be synthesized and output from the image sensor 101, the first embodiment is similar to the first embodiment. The output time can be shortened compared to In addition, when it corresponds to the CMOS type circuit configuration described in FIG. 7, it can be realized by the same circuit configuration as FIG. 10 described in the first modification. As a result, half the number of M / 2 terminals is sufficient as in the first modified example, so that the package size of the image sensor 101 can be reduced and the price can be reduced.

  As described above, as described in the embodiment of the image sensor 101 according to the present invention, the image sensor 101 according to the present invention can output an image signal to be output with a pulse width or pulse position that is resistant to noise.

  Furthermore, by providing a photographing optical system, a photographing control unit, and an image recording unit in addition to the image sensor 101 according to the present invention, a camera capable of recording with a digital signal with less noise can be realized. it can.

It is a block diagram of the image sensor 101 concerning this embodiment. It is a circuit diagram of pixel P (1, 1). 3 is a circuit diagram of an SGA (m) and a pulse output circuit 104. FIG. It is a circuit diagram of LAMP105. It is explanatory drawing which shows the mode of the signal output from the image pick-up element. 3 is a timing chart showing an operation sequence of the image sensor 101. It is a block diagram in the case of having a plurality of output terminals. It is a circuit diagram of the synthetic | combination circuit 201 of a 1st modification. It is a timing chart which shows the operation | movement sequence of a 1st modification. It is a block diagram of a 1st modification and a 2nd modification. It is a circuit diagram of the synthetic | combination circuit 203 of a 2nd modification. It is a timing chart which shows the operation sequence of the 2nd modification.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 ... Image pick-up element 102 ... Timing generation circuit 103, 103a ... Horizontal output circuit 104, 104a, 104b ... Pulse output circuit 105 ... Ramp signal generation circuit (LAMP)
106, 107... Comparator (CMP)
108, 202 ... Exclusive OR operation part (EXOR)
201, 203... Synthesis circuits P (1, 1) to (N, M)... Pixel VLINE (1) to (M)... Vertical signal line CAMP. M) ... Signal amplification / accumulation unit PW (1) to PW (M) ... constant current sources BUF1, BUF2 ... buffer CPL1 ... constant current sources SW1, SW2 ... switch INV1 ... Inverters C1, Ca1, Ca2 ... Capacitors R1, R2 ... Resistors

Claims (6)

A pixel portion that converts light into an electrical signal;
A dark signal holding unit that reads and holds a dark signal of the pixel unit;
An image signal holding unit that reads and holds an image signal of the pixel unit;
A reference signal generator for generating a reference signal;
A dark signal comparison unit that compares the dark signal with the reference signal;
An image signal comparison unit for comparing the image signal and the reference signal;
An image pickup device comprising: an exclusive OR operation unit that calculates an exclusive OR of the output of the dark signal comparison unit and the output of the image signal comparison unit. The imaging device according to claim 1,
The image sensor according to claim 1, wherein the reference signal generator comprises a circuit that generates a ramp signal. The imaging device according to claim 1,
The image pickup device, wherein the reference signal generator generates a reference signal including a gamma characteristic when displaying an image taken by the image pickup device. The imaging device according to claim 1,
Two different pixel portions are defined as a first pixel portion and a second pixel portion,
The exclusive OR operation unit used in the first pixel unit and the second pixel unit is a first exclusive OR operation unit and a second exclusive OR operation unit, respectively.
A first differentiating circuit for differentiating an output of the first exclusive OR operation unit with a predetermined time constant;
A second differentiating circuit for differentiating the output of the second exclusive OR operation unit with a time constant different from the time constant of the first differentiating circuit;
An image pickup device, further comprising: an output exclusive OR operation unit that calculates an exclusive OR of the output of the first differentiating circuit and the output of the second differentiating circuit. The imaging device according to claim 1,
Two different pixel portions are defined as a first pixel portion and a second pixel portion,
The exclusive OR operation unit used in the first pixel unit and the second pixel unit is a first exclusive OR operation unit and a second exclusive OR operation unit, respectively.
A first differentiating circuit for differentiating an output of the first exclusive OR operation unit with a predetermined time constant;
An image pickup device, further comprising: an output exclusive OR operation unit that calculates an exclusive OR of the output of the first differentiating circuit and the output of the second exclusive OR operation unit.   A camera comprising: the imaging device according to claim 1; a photographing optical system; a photographing control unit; and an image recording unit.

Images