JP5162964B2 - Semiconductor device and semiconductor power conversion device - Google Patents

Description

  The present invention relates to a semiconductor device such as a diode or IGBT (insulated gate bipolar transistor) having not only high speed and low loss but also soft recovery characteristics, and a semiconductor power conversion device on which the semiconductor device is mounted.

As power semiconductor devices, there are diodes or IGBTs of a withstand voltage class such as 600V, 1200V or 1700V. Recently, the characteristics of these devices have been improved. Power semiconductor devices are used in power conversion devices such as highly efficient and power-saving converter-inverters, and are indispensable for control of rotary motors and servo motors.
Such power control devices are required to have characteristics such as low loss and power saving, high speed and high efficiency, and environmental friendliness, that is, no adverse effects on the surroundings. In response to such a demand, a broad buffer structure has been proposed in the diode. The broad buffer structure is a structure in which the average concentration distribution of the N ⁻ drift layer has a peak (maximum value) near the middle of the same layer and decreases with an inclination toward the anode and cathode. (For example, refer to Patent Document 1).

  The diode of the broad buffer structure has a high speed operation (for example, carrier frequency: 20 kHz or more) that is difficult with the conventional technique for reducing the emitter injection efficiency and controlling the lifetime distribution (for example, see Patent Document 2). The soft recovery characteristics and the oscillation suppression effect can be realized. Patent Document 1 discloses the following two methods for manufacturing such a broad buffer diode.

The first method is a method in which a region having a phosphorus concentration higher than the initial phosphorus concentration of the semiconductor substrate is formed by an epitaxial growth method in a deep region in the bulk, that is, in a region 30 to 60 μm or deeper than the surface of the semiconductor chip. It is. The second method is a method in which proton ions (H ⁺ ) are irradiated to a FZ (float zone) bulk wafer and heat treatment is performed, whereby protons are converted into donors in the vicinity of the range Rp inside the bulk. Since the bulk wafer is less expensive than the epitaxial wafer, the second method is less expensive than the first method.

In addition to the above-mentioned Patent Document 1, various methods for forming a high concentration N ⁺ layer by utilizing a proton donor phenomenon by proton irradiation and heat treatment have been proposed (for example, Patent Document 3, Patents). Reference 4). In addition, Patent Document 4 discloses a method of forming an N ⁺ layer using a thermal donor using oxygen. In addition, when it is necessary to avoid proton donor formation, there is a proposal of using helium instead of proton (see, for example, Patent Document 5).

  Further, as a method for realizing a broad buffer structure at a low cost, a method for obtaining a high concentration region inside a bulk as a net doping concentration by compensating a donor (phosphorus) concentration of a semiconductor substrate with an acceptor element has been proposed (for example, , See Patent Document 6). In addition, a method is known in which defects are formed in a silicon substrate by proton irradiation and the residual defects are adjusted by heat treatment to locally reduce the lifetime (for example, Patent Document 5, Patent Document 7, Patent Reference 8).

  In the case of IGBTs, trench gate type IGBTs as disclosed in Patent Document 12 have been widely developed and commercialized in response to the above-mentioned demands such as low loss. The trench gate type IGBT increases the cell density (the number of unit gate cells in a unit area) compared to the known DMOS planar gate type IGBT, and eliminates the influence of the JFET effect. Carrier side), the on-voltage is reduced significantly and the switching (turn-off) loss is reduced.

  Further, as in Patent Document 9, the thickness of a conventional semiconductor substrate (for example, a silicon wafer) is reduced by grinding or the like, and an element is ion-implanted and heat-treated from the ground surface side at a predetermined concentration. There is an example in which the semiconductor element is formed to provide a low-cost semiconductor element with low electrical loss. In recent years, the development and manufacture of devices by such low-cost methods are becoming mainstream.

In order to drive these IGBTs safely without malfunction, Patent Documents 13 to 18 disclose the following techniques.
In Patent Document 13, in order to drive the IGBT at high speed, the gate resistance Rg is preferably less than 20Ω on the off side of the IGBT gate drive circuit. Thereby, for example, even when a plurality of IGBT chips are operated in parallel, the current can be safely interrupted while suppressing the uneven distribution of current.

In paragraphs [0005] and [0006] of Patent Document 14, the main current is estimated and controlled from the gate current without sensing the main current by a method of limiting the turn-on di / dt of the IGBT through which the main current flows. A technique is disclosed in which a current is fed back to a drive circuit and gate current control is performed by a regulator.
In paragraph [0010] of Patent Document 15, in order to limit the turn-on di / dt of the main IGBT, an inductance L is inserted between the emitter electrode and a wiring connected to the emitter electrode, and Ldi / dt at the time of overcurrent conduction is set to Vge. A technique is disclosed in which the gate is narrowed by lowering Vge to near Vth during abrupt di / dt.

Paragraph [0010] of Patent Document 16 discloses a technique for suppressing the turn-on dV / dt of an IGBT in an opposing arm of a FWD (Free Wheeling Diode). Two Rg's are arranged in parallel in the drive circuit, and when one dV / dt increases, one side is opened and the combined Rg value is increased to suppress dV / dt.
In paragraph [0007] of Patent Document 17, when an overvoltage is generated in the IGBT from the coil of the automobile igniter circuit, a current is passed through the Zener diode connected between the gate and the collector electrode of the IGBT, and the current and the gate resistance cause the gate to flow into the gate. A technique is disclosed in which a self-bias is generated, the IGBT is energized, and the IGBT is clamped.

In paragraph [0012] of Patent Document 18, in the sense IGBT that detects an overcurrent of the circuit, the gate capacitance of each IGBT and the gate resistance connected to the gate are adjusted, and the gate circuit time constant of the main current IGBT is sensed. A technique has been disclosed in which the response speed of overcurrent sensing is increased and the controllability of overcurrent suppression is improved by making it larger than the time constant of the IGBT.
JP 2003-318812 A JP-A-8-148699 Japanese Patent Laid-Open No. 9-260639 JP 2001-156299 A Japanese Patent Laid-Open No. 2003-249662 JP-A-2005-64429 JP 2001-326366 A Japanese Patent Laid-Open No. 10-74959 Japanese translation of PCT publication No. 2002-52085 JP 2001-127308 A JP-A-7-202226 JP-A-5-243561 JP 2000-40951 A Japanese Patent Laid-Open No. 10-12629 JP 2004-63687 A JP 2002-369553 A JP 2002-235634 A JP-A-7-146722 B. J. et al. Baliga, “Power Semiconductor Devices”, PWS publishing, 1996.

According to Patent Document 1, as a technique for suppressing the oscillation of the voltage / current waveform during reverse recovery (hereinafter referred to as “oscillation”), the integrated concentration of the impurity concentration in the broad buffer layer portion is set to 2 × 10 ¹¹ atoms / cm ^2. It is disclosed that the amount is 8 × 10 ¹¹ atoms / cm ² or less.
Specifically, the following inventions are disclosed. The distribution of the impurity concentration of the N ⁻ drift layer from the P-type anode layer side surface to the wafer back surface (N ⁺ cathode layer side) direction is N _net (x). An average concentration N _dm is a value obtained by dividing the integrated concentration obtained by integrating this N _net in the thickness direction of the N ⁻ drift layer portion (including the broad buffer portion) by the thickness of the same layer portion. A position (x) where N _{net of the} broad buffer portion is equal to N _dm and the position closest to the P-type anode layer is Xc, and the position closest to the N ⁺ cathode layer is Xd. The semiconductor device is configured such that an integrated concentration (1) obtained by integrating N _net in a region sandwiched between Xc and Xd is 2 × 10 ¹¹ atoms / cm ² or more and 8 × 10 ¹¹ atoms / cm ² or less. .

According to the present invention, it is possible to suppress the oscillation phenomenon due to the snappy waveform of the diode during reverse recovery. Patent Document 1 describes that the oscillation suppression effect is lost when the integrated concentration (1) is lower than this concentration range, and that the breakdown voltage decreases when the integrated concentration (1) is higher than this concentration range.
However, it has been found that oscillation may not be suppressed even in the same concentration range.

22 and 23 show reverse recovery waveforms of a diode having a conventional broad buffer structure, and show waveforms with N ^- drift layer thicknesses of 65 μm and 45 μm, respectively. As disclosed in the above-mentioned patent documents and the like, the phenomenon that the diode oscillates during reverse recovery is generally well known when the diode conduction current is sufficiently lower than the rating. The conventional broad buffer diode has a structure that well prevents this, and does not oscillate when the N ⁻ layer thickness is 65 μm as shown in FIG. This thickness is sufficiently thin for a conventional diode that does not have a broad buffer structure. However, in order to achieve higher speed and lower loss characteristics, for example, when the N ⁻ drift layer thickness is reduced to 45 μm, it is clear that the breakdown voltage is lowered, and oscillation and destruction occur (FIG. 23).

24 and 25 show the impurity concentration distribution of a conventional broad buffer diode of 600 V class used in the experiment. The thicknesses of the N ⁻ drift layers are 65 μm and 45 μm, respectively. The basic concentration N ₀ of the N ⁻ drift layer is 7.7 × 10 ¹³ atoms / cm ³ (60 Ωcm). N ^- average concentration of the drift layer, N ^- drift layer thickness when the 65μm is ^{1.7 × 10 14 atoms / cm 3} , the same time of 45μm is ^{1.8 × 10 14 atoms / cm 3} . The integrated concentration of the impurity concentration between the two positions where the impurity concentration of the broad buffer portion matches the average concentration is 7.1 × 10 ¹¹ atoms / cm ^{2 in} the former, and 5.3 × 10 ¹¹ atoms / cm in the latter. ² . The ratio of the basic concentration N _{0 to} the average concentration is 45.2% and 42.3%, respectively.

  FIG. 26 shows a circuit diagram of the reverse recovery test. The switching IGBT is a standard 600V / 100A NPT-IGBT. The stray inductance of the circuit is about 50 nH, the gate resistance is 0Ω on the ON side, and 33Ω on the OFF side. The measurement was performed at room temperature. The initial diode conduction current is 10A, which is 1/10 of the rating, and the DC applied voltage is 400V. For the 1200V element, the IGBT is 1200V / 50A, the DC applied voltage is 600V, and other conditions are the same as in the case of the 600V element.

With the speeding up of IGBTs (for example, 20 kHz or more), diodes are required to have characteristics that suppress oscillation by soft recovery more than ever, and in addition, improvements in high speed and low loss characteristics are required. An object of the present invention is to provide a diode or IGBT having high speed and low loss, and at the same time having a soft recovery characteristic, and a power conversion device on which these are mounted.

  In addition, in order to reduce the loss generated during operation of the inverter, etc. (hereinafter referred to as actual machine loss), electrical loss generated mainly from the semiconductor switching devices (IGBT, MOSFET, etc.) and diodes, etc. It is necessary to lower. The breakdown of the generated loss is mainly (1) IGBT conduction loss (hereinafter referred to as “Esat”), (2) IGBT turn-on loss (hereinafter referred to as “Eon”), (3) IGBT turn-off loss (hereinafter referred to as “Eoff”), (4) FWD conduction loss (hereinafter referred to as Ef), and (5) FWD reverse recovery loss (hereinafter referred to as Err). In addition, the loss due to the leakage current when the IGBT or FWD is OFF can be increased, but it is almost 1/10 compared to these five, so it can be almost ignored. Among them, Esat has the largest loss, followed by Eoff, Eon, Ef, and Err. The value of Eoff has been greatly reduced due to recent improvements in IGBT characteristics as described above, and is decreasing to a level equivalent to Eon. For this reason, the influence on Eon's actual machine loss is increasing.

  In general, reducing the gate resistance is most effective in reducing Eon of actual machine loss. This is because the holding voltage of the IGBT is reduced as early as possible while the current being commutated from the diode flows to the IGBT and the IGBT current is increasing. On the other hand, as shown in the above cited references, when the gate resistance is made smaller than the recommended value of the product, the vibration waveform of the FWD at the time of IGBT turn-on, which is the main cause of radiated electromagnetic noise during actual machine operation. In addition, there is a problem that these steep di / dt and dV / dt are generated. For this reason, in general, the gate resistance must be set large to a certain level (that is, a recommended value or more). Therefore, in the conventional method, there is a limit in reducing Eon, and it has become impossible to reduce the actual device loss only by reducing the switching loss of the IGBT. Hereafter, this problem is examined for each cited document.

  In paragraph [0203] of Patent Document 13, since the turn-on di / dt increases when the gate resistance Rg is too small, the FWD recovery current increases and causes breakdown. And the gate resistance on the off side are separated, and the gate resistance is lowered only on the off side. This means that the on-side gate resistance cannot be reduced, and thus it is suggested that Eon in the actual machine loss cannot be reduced.

  In Patent Document 14, in order to limit the current change rate of the IGBT, the gate current is sensed and the gate is controlled by a regulator. However, there is no description of what value the gate resistance should be set to. Further, from the description of [0002] of the publication, since the purpose is to limit the current rising speed (that is, di / dt) when the IGBT is turned on, the Eon of actual machine loss tends to increase.

Patent Document 15 describes that in order to limit turn-on di / dt, the gate voltage is limited to about a threshold value to suppress the increase. This also increases the time required for turn-on, so that the actual machine loss Eon increases.
In the case of Patent Document 16, in order to limit the dV / dt of the opposing FWD at the time of turn-on, it is described that the increase of the combined value of the gate resistance is limited and the increase is limited at a dV / dt of a certain value or more. That is, this is also in the direction of slowing down the turn-on speed, and it is suggested that the actual machine loss Eon increases in such a situation.

  In Patent Document 17, if the gate resistance of the IGBT is made too small, the current flowing through the Zener diode increases, the self-bias speed of the gate electrode of the IGBT increases, and the clamp voltage decreases. It is described that the gate resistance to be made larger than the resistance of the limiting circuit. For this reason, this is also a direction in which the turn-on speed decreases, and the actual machine loss Eon increases.

In the case of Patent Document 18, in order to increase the gate circuit time constant on the main current side, it is described that the gate circuit time constant on the sense side is increased by 10 times. Specifically, an example of 100Ω is described. is there. Since this also takes a longer time to turn on, the actual machine loss Eon increases.
From the above, it is shown that the conventional driving method and driving device have a limit in reducing the turn-on loss and suppressing the increase in the actual device loss. Therefore, the second object of the present invention is to reduce the loss of switching elements such as IGBTs and also reduce electromagnetic noise by using a diode having not only high speed and low loss but also soft recovery characteristics. It is an object of the present invention to provide an IGBT module, a driving method and a driving device thereof, and a semiconductor power conversion device in which these are mounted and applied.

According to the present invention, the above-described problem is a first conductivity type first semiconductor layer and a second conductivity type formed on one main surface of the first semiconductor layer and having a higher impurity concentration than the first semiconductor layer. A second semiconductor layer and a third semiconductor layer of a first conductivity type formed on the other main surface of the first semiconductor layer and having a higher impurity concentration than the first semiconductor layer, and the first semiconductor layer There is at least one position where the impurity concentration of the first semiconductor layer becomes a maximum, and the impurity concentration of the first semiconductor layer decreases with an inclination from the position where the maximum is reached toward both the second semiconductor layer and the third semiconductor layer. In the semiconductor device, the following formula (1 ) of the impurity concentration of the first semiconductor layer:

The integrated concentration represented by the equation (2)

(Where x is the position on the coordinate axis from one main surface of the first semiconductor layer to the other main surface, N _net (x) is the impurity concentration at the position x of the first semiconductor layer, and Xc is the first the position closest to the second semiconductor layer a x satisfying _N net (x) _{= N dm} semiconductor layer, Xd is most position where the _N net (x) _{= N dm} in the first semiconductor layer (N _dm represents a position close to the third semiconductor layer, N _dm represents an average impurity concentration of the first semiconductor layer, and the coordinate axis is substantially perpendicular to the main surface of the first semiconductor device layer)
The filling,
The impurity concentration N ₀ and the average concentration N _{dm in the} vicinity of the junction of the first semiconductor layer with the second semiconductor layer are _expressed by the following formula (3).

The filling,
The distance index W ₀ defined by the first semiconductor layer thickness W and the following formula (5) is expressed by the following formula (4).


This is solved by a semiconductor device satisfying (BV represents the breakdown voltage of the semiconductor device).
According to the first aspect of the present invention, the reverse recovery time and loss can be greatly reduced, and the soft recovery characteristics can be improved. In addition, the electric field strength of the entire first semiconductor layer can be maintained high, and a decrease in breakdown voltage can be suppressed. In addition, it is possible to prevent the breakdown voltage from decreasing while keeping the reverse recovery loss small.
A semiconductor power conversion device according to a second aspect of the present invention is mounted with the semiconductor device according to any one of the first to third aspects, and the operating frequency of the semiconductor device is 20 kHz or more.

A second object of the present invention, according to the invention of claim 3, in the semiconductor power conversion device having a diode and a semiconductor switching device, a diode and a semiconductor switching device is connected in antiparallel, the diode and the semiconductor switching device The semiconductor device according to claim 1 , wherein either one or both of them is configured such that a control terminal of a drive circuit for controlling the semiconductor switching device is connected to a control electrode of the semiconductor switching device via a resistor of 11 Ωcm ² or less. It is solved by. This resistance is preferably 8 Ωcm ² or less.

The drive circuit according to claim 3 is formed on the first main surface and the other main surface of the semiconductor switching device when the semiconductor switching device is changed from the blocking state to the conductive state. The time when the potential difference between the second electrode and the second electrode, for example, the voltage between the collector and the emitter of the IGBT, reaches a half value of the power supply voltage is earlier than the time when the semiconductor switching device reaches the maximum current from the blocking state. It is preferable to drive by the following driving method.

  In the present invention, “impurity concentration” refers to the absolute value of the concentration difference between the electrically activated donor and acceptor, and may hereinafter be referred to as “net doping concentration”.

  According to the semiconductor device of the present invention, the reverse recovery time and loss can be greatly reduced and the soft recovery characteristics can be improved as compared with the conventional semiconductor device. Furthermore, it is possible to provide an IGBT module and an IPM that take into consideration environmental issues with low electrical loss and radiated electromagnetic noise.

Preferred embodiments of a semiconductor device and a semiconductor power conversion device according to the present invention will be described below with reference to the accompanying drawings. In the present specification and the accompanying drawings, it means that electrons or holes are majority carriers in the layers and regions with N or P, respectively. Further, + and − attached to N and P mean that the impurity concentration is relatively high or low, respectively. Note that, in the following description of the embodiments and the accompanying drawings, the same reference numerals are given to the same components, and duplicate descriptions are omitted.
(Embodiment 1)
FIG. 1 is a diagram showing the configuration and net doping concentration of the semiconductor device according to the first embodiment of the present invention. As shown in a cross-sectional view of the semiconductor device in FIG. 1, a P-type second semiconductor layer 2 that becomes a P-type anode layer is formed on one main surface side of an N-type first semiconductor layer 1 that becomes an N ⁻ drift layer. Is formed. Further, an N-type third semiconductor layer 3 serving as an N ⁺ cathode layer is formed on the other main surface side of the first semiconductor layer 1. An anode electrode 4 is formed on the surface of the second semiconductor layer 2. A cathode electrode 5 is formed on the surface of the third semiconductor layer 3.

  As shown in FIG. 11, the distance x from the anode electrode to the net doping concentration (log) in FIG. 1, the net doping concentration of the first semiconductor layer 1 has a peak (maximum value) near the middle of the first semiconductor layer 1. ) And decreases toward the second semiconductor layer 2 and the third semiconductor layer 3 with an inclination. That is, the semiconductor device of the first embodiment has a broad buffer structure. The net doping concentrations of the second semiconductor layer 2 and the third semiconductor layer 3 are both higher than the net doping concentration of the first semiconductor layer 1. The distance x is based on the interface between the second semiconductor layer 2 and the anode electrode 4.

As an example, the net doping concentration and dimensions of each part when the semiconductor device of the first embodiment is manufactured with a chip size of 7 mm × 5.5 mm so that the withstand voltage is 600 V class and the rated current is 100 A are illustrated. .
The distance to the interface between the second semiconductor layer 2 and the first semiconductor layer 1 is 3 μm. The distance to the interface between the third semiconductor layer 3 and the cathode electrode 5 is 350 μm.

The net doping concentration of the second semiconductor layer 2 is 5 × 10 ¹⁶ atoms / cc at the interface with the anode electrode 4, decreases toward the first semiconductor layer 1, and 5 at the interface with the first semiconductor layer 1. × 10 ¹³ atoms / cc lower. The net doping concentration of the third semiconductor layer 3 is 2 × 10 ¹⁸ atoms / cc at the interface with the first semiconductor layer 1, increases toward the cathode electrode 5, and 1 × 10 ²⁰ at the interface with the cathode electrode 5. atoms / cc. In the following description, atoms / cc and atoms / cm ³ are used as units for indicating the concentration, but “cc” and “cm ³ ” are the same.

The net doping concentration of the first semiconductor layer 1 will be described with reference to FIGS. 2 and 3 show net doping concentration distributions when the thickness of the first semiconductor layer (N ⁻ drift layer), that is, (Wd-3) in FIG. 1 is 65 and 45 μm, respectively. In the first semiconductor layer, the net doping concentration (basic concentration N ₀ ) in the vicinity of the junction with the second semiconductor layer 2 is 5.1 × 10 ¹³ atoms / cc, and the peak (maximum value) is approximately in the middle thereof. ) Is about 1 × 10 ¹⁵ atoms / cc. The net doping concentration of the first semiconductor layer at and near the interface with the third semiconductor layer 3 is 5.1 × 10 ¹³ atoms / cc. The basic concentration corresponds to a resistivity of 90 Ωcm. The vicinity of the junction refers to a region in the vicinity of the junction between the first semiconductor layer and the second semiconductor layer, in which the inclination of the impurity concentration in the first semiconductor layer is sufficiently small in the x direction, and also varies depending on the thickness of the first semiconductor layer. Is a region in the range of about 5 μm to 20 μm from the junction toward the first semiconductor layer.

2 and 3, the basic concentration N ₀ , the average concentration N _{dm of} the first semiconductor layer 1, the integrated concentration of the net doping concentration calculated by the above equation (1), and the ratio of the basic concentration to the average concentration ( N ₀ / N _dm ) are summarized in Table 1.

Next, a manufacturing process of the semiconductor device according to the first embodiment will be described. FIG. 4 is a diagram showing a manufacturing process, and is a fragmentary cross-sectional view of a portion corresponding to a semiconductor chip after the wafer is cut by a scribe line.
A predetermined pretreatment is applied to the bulk wafer 100 (n semiconductor substrate) made of n-type and low specific resistance CZ containing antimony up to the solid solubility (FIG. 4A). The wafer becomes the third semiconductor layer 3. An epitaxial growth layer 101 of a high specific resistance Si crystal containing an n-type impurity is formed on the mirror surface of this wafer to form the first semiconductor layer 1 (FIG. 4B). During growth, a gas containing n-type impurities such as phosphorus is added to the source gas at a predetermined flow rate. By controlling this flow rate, as shown in FIG. 5B, an impurity concentration distribution having a broad buffer structure in which the concentration gradually increases and gradually decreases from a predetermined position is obtained. Thereafter, a p-type anode layer 102 (concentration 5 × 10 ¹⁶ atoms / cm ³ , depth 3 μm) and an n ⁺ layer 103 for obtaining ohmic contact are formed by a conventional method, and an anode electrode 104 (AlSi 1) is formed on each. %) And a cathode electrode 105 (Ti / Ni / Au) are formed (FIG. 4C). In the middle of the process, the wafer may be ground to about 300 μm for the purpose of reducing the on-resistance, or a passivation film such as a guard ring edge structure or polyimide (not shown) may be formed. In this way, a semiconductor device can be manufactured.

  When the flow rate of the phosphorus-containing gas is changed with a monotonic continuous function in time, a smooth impurity concentration distribution is obtained, and when it is changed with small step functions, the impurity concentration distribution changes with small steps. The peak (maximum value) position of the impurity concentration distribution may be at the center of the epitaxial growth layer 101, the p-type anode layer 102 side, or the wafer 100 side.

  FIG. 5 is a distribution diagram of the impurity concentration of an epitaxial growth layer formed for a semiconductor device having a withstand voltage of 1200 V class to be described later. As described above, the impurity concentration may change to wave. In such a case, the present invention considers an envelope A that traces the local peak value of a wavy curve. The broad buffer structure has at least one position where the envelope A is a maximum, and decreases from the position where the envelope A reaches the maximum toward both the second semiconductor layer and the third semiconductor layer. In addition, it is thought that the impurity profile undulates because when the impurity doping amount during epitaxial growth is increased or decreased in small steps, the doping amount overshoots at the transition of the step. The effect of the present invention can be obtained.

6 and 7 show net doping concentration distributions of a semiconductor device having a breakdown voltage of 1200 V class. FIG. 6 shows the present invention, and FIG. 7 shows a conventional broad buffer structure. In both cases, the thickness of the first semiconductor layer (N ⁻ drift layer) is 105 μm. This thickness is 10% or more thinner than the standard thickness in the withstand voltage 1200 V class (see, for example, paragraph 0013 of Patent Document 11 and FIG. 3.7 of Non-Patent Document 1). In this case, in order to suppress the oscillation phenomenon, it is desirable to adopt the structure shown in FIG. 6 rather than the conventional broad buffer structure shown in FIG.

In the broad buffer structure of the semiconductor device described above, the integrated concentration defined by the formula (1) is set to 8 × 10 ¹¹ atoms / cm ² or more, so that the electric field strength of the space charge region spreading during the reverse recovery can be increased. Since it decreases between two points, the expansion of the space charge region can be suppressed. The reverse recovery oscillation occurs because the surplus carriers disappear rapidly due to the expansion of the same region. By suppressing this, the surplus carriers remain sufficiently during the reverse recovery, and the oscillation can be suppressed. In addition, by reducing the ratio of the basic concentration to the average concentration (N ₀ / N _dm ) to 30% or less, the electric field strength of the entire N ⁻ drift layer can be maintained high, and the breakdown voltage can be suppressed from decreasing.

8 and 9 show waveforms obtained by performing a reverse recovery test on the semiconductor device of the first embodiment under the above-described conditions. 8 and 9, the thickness of the first semiconductor layer 1 is 65 μm and 45 μm, respectively. The impurity concentration distributions are shown in FIGS.
From these figures and FIG. 23, it can be seen that when the broad buffer structure of the present invention is used, even if the thickness of the N ⁻ drift layer is reduced to 45 μm, oscillation does not occur and soft recovery is achieved. This is because the surplus carriers during reverse recovery remain sufficiently due to the above-described action.

Furthermore, according to the present invention, the reverse recovery peak voltage due to oscillation can be suppressed at a high DC applied voltage even if the N ^- thickness is sufficiently thin. FIG. 10 is a graph showing the characteristics of the reverse recovery peak voltage when the DC applied voltage (hereinafter referred to as “Vdc”) is 300, 400, and 500 V under the conditions of the reverse recovery test described above. In the conventional broad buffer structure (FIGS. 24 and 25), when the thickness of the N ⁻ drift layer is 65 μm, the peak voltage is sufficiently suppressed even when Vdc is 500 V, but when the thickness is 45 μm, as described above. Since oscillation occurs, the peak voltage (800 to 900 V) becomes higher than the device breakdown voltage, and the device is destroyed. On the other hand, in the case of the semiconductor device having the broad buffer structure of the present invention, the oscillation is suppressed even when the thickness of the N ⁻ drift layer is 45 μm (FIG. 9), and the peak voltage at Vdc = 500V is about 400V. Yes.
(Embodiment 2)
FIG. 11 is a graph showing the relationship between the integrated concentration and the withstand voltage in the equation (1), and the ratio N ₀ / N _dm defined in the first embodiment is used as a parameter. Such a broad buffer structure can be made by appropriately adjusting the flow rate of the phosphorus-containing gas serving as a dopant when the first semiconductor layer 1 is epitaxially grown in the manufacturing process described in the first embodiment.

When the ratio N ₀ / N _dm is 35, 40% (synonymous with the ratio 0.35, 0.40), when the above-mentioned integrated concentration is 8 × 10 ¹¹ atoms / cm ² or more, the withstand voltage is drastically reduced. It becomes 600V or less. On the other hand, if the ratio is 30% or less (synonymous with a ratio of 0.30 or less), a decrease in breakdown voltage at 8 × 10 ¹¹ atoms / cm ² or more can be suppressed. As described above, in the semiconductor device having the broad buffer structure, it is necessary to carefully control the impurity concentration distribution. However, if the ratio N ₀ / N _dm is 30% (0.30) or less, the breakdown voltage is not reduced. This is preferable. This effect can be similarly obtained even in a semiconductor device of a different breakdown voltage class such as 1200V.
(Embodiment 3)
When the thickness of the N ⁻ drift layer is reduced, an oscillation phenomenon occurs and the device breakdown voltage decreases. This phenomenon is explained using the distance index W ₀ represented by the equation (5) and the ratio of the thickness W of the N ^- drift layer to W ₀ .

Here, BV is the breakdown voltage of the semiconductor device, and N _dm is the average concentration of the N ⁻ drift layer.
Formula (5) is demonstrated. From Non-Patent Document 1, when the concentration of the N ⁻ drift layer is N _d , the critical electric field strength Ec is expressed by Expression (6).

In general, the device breakdown voltage BV by the parallel plate approximation is obtained when the maximum electric field strength in the device reaches Ec due to an increase in applied voltage, and the depletion layer width at that time is defined as W ₀ .

It is expressed. Since N _{d in} equation (6) corresponds to the average concentration N _dm , when equation (6) is substituted into Ec in equation (7) and rearranged, equation (5) is obtained for the depletion layer width W ₀ . This depletion layer width W ₀ can be considered as a measure of the N ⁻ drift layer thickness required for the device breakdown voltage BV, that is, a distance index W ₀ .
In the above description, the breakdown voltage determined by the thickness and concentration of the first semiconductor layer is the element breakdown voltage BV. Usually, since the concentration of the second semiconductor layer is sufficiently higher (approximately two orders of magnitude or more) than the first semiconductor layer, it can be considered that the depletion layer extends only to the first semiconductor layer (one-sided step junction). Therefore, the breakdown voltage determined by the first semiconductor layer can be considered as the element breakdown voltage.

Table 2 shows the relationship between the element breakdown voltage BV, the average concentration N _dm, and the distance index W ₀ based on the formula (5). Each of the element breakdown voltages is a value that is set about 10% higher than a typical rated voltage of a commonly used power semiconductor element (FWD, IGBT, etc.) and has a margin. The average concentration N _dm is a typical concentration for obtaining this device breakdown voltage. Although the elements that are actually sold in mass are slightly different from this value, they are close enough in order. As shown in Table 2, the distance index W ₀ obtained from the equation (5) is about 57 μm for 600 V elements and about 126 μm for 1200 V elements.

Table 3 shows the distance index W _{0 in the} case where the average concentration N _dm in Table 2 is slightly reduced to provide a margin for the breakdown voltage.

12 and 13 are trade-off curves showing reverse recovery loss characteristics of a diode having a broad buffer structure according to the present invention. The graph shows the dependence on the thickness of the N ⁻ drift layer when the rated voltage is 600 V and 1200 V, respectively. The horizontal axis is the forward voltage drop that becomes the conduction loss, and the vertical axis is the reverse recovery loss. W ₀ in the figure is as described in Table 2.
FIG. 14 is a graph showing the relationship between the thickness W of the N ⁻ drift layer and the reverse recovery loss Err for (a) 600 V class and (b) 1200 V class, and was obtained from the reverse recovery loss characteristics of FIGS. Is. The horizontal axis is normalized by the distance index W _0. In the case of 600V (a), the reverse recovery loss value or its extrapolated value when the forward voltage in FIG. 12 is 1.6V is used, and in the case of 1200V (b), the forward voltage 1.8V in FIG. Is the reverse recovery loss value. It can be seen that the reverse recovery loss tends to increase sharply when the ratio (W / W ₀ ) of the thickness W of the N ⁻ drift layer to the distance index W ₀ is 1 to 1.1 or more. This is because as the thickness of the N ⁻ drift layer (first semiconductor layer) increases, the resistance in the conduction direction increases and the number of stored carriers also increases. Further, N in the case of 600V (a) ^- the thickness of the drift layer than the loss Err of 45μm (= 0.79W ₀₎ and 65μm (= 1.14W _0), the broad buffer structure according to the present invention, It can be seen that the oscillation of the semiconductor device can be suppressed, and in addition, a loss reduction of about 60% can be achieved.

FIG. 15 is a graph showing the relationship between the thickness W of the N ⁻ drift layer and the element breakdown voltage BV for (a) 600 V class and (b) 1200 V class. Horizontal axis as in FIG 14 is normalized by the distance index W _0. The device breakdown voltage decreases rapidly when the ratio W / W ₀ is less than 0.8.
As described above, in the semiconductor device having the broad buffer structure according to the present invention, the ratio W / W ₀ is desirably 0.8 or more and 1.0 or less.
(Embodiment 4)
FIG. 16 is a diagram showing a configuration, net doping concentration, and proton distribution of a semiconductor device according to the fourth embodiment of the present invention manufactured by a process different from that of the first embodiment. The layer structure of the semiconductor device is the same as the structure described in Embodiment 1 as shown in the cross-sectional view of the semiconductor device in FIG.

  As shown in FIG. 11, the distance from the anode electrode to the net doping concentration (log) in FIG. 16, the net doping concentration of the first semiconductor layer 1 has a peak in the vicinity of the middle of the first semiconductor layer 1. It decreases with an inclination toward the second semiconductor layer 2 and the third semiconductor layer 3. That is, the semiconductor device of the fourth embodiment has a broad buffer structure.

As an example, the net doping concentration and dimensions of each part when the chip size is 10 mm × 10 mm so that the semiconductor device of the fourth embodiment is manufactured with a breakdown voltage of 1200 V class and a rated current of 150 A are illustrated.
The distance to the interface between the second semiconductor layer 2 and the first semiconductor layer 1 is 3 μm. The distance to the interface between the third semiconductor layer 3 and the cathode electrode 5 is 115 μm. This is with respect to the distance index _W 0 = _125.5μm, equivalent to 0.92W _0. The distance from the interface between the first semiconductor layer 1 and the third semiconductor layer 3 to the interface between the third semiconductor layer 3 and the cathode electrode 5, that is, the thickness of the third semiconductor layer 3 is 0.5 μm.

The net doping concentration of the second semiconductor layer 2 is 5 × 10 ¹⁶ atoms / cc at the interface with the anode electrode 4 and decreases toward the first semiconductor layer 1, and 3 at the interface with the first semiconductor layer 1. Less than 8 × 10 ¹³ atoms / cc. The net doping concentration of the first semiconductor layer 1 is lower than 3.8 × 10 ¹³ atoms / cc at the interface with the second semiconductor layer 2, but is 3. 3 near the interface (junction) with the second semiconductor layer 2. 8 × 10 ¹³ atoms / cc.

Then, the net doping concentration at a location where the peak is approximately in the middle of the first semiconductor layer 1 is 2.0 × 10 ¹⁴ atoms / cc. The net doping concentration of the first semiconductor layer 1 at the interface with the third semiconductor layer 3 and in the vicinity thereof is 3.8 × 10 ¹³ atoms / cc. The net doping concentration of the third semiconductor layer 3 is 3.8 × 10 ¹³ atoms / cc at the interface with the first semiconductor layer 1, increases toward the cathode electrode 5, and 1 × at the interface with the cathode electrode 5. 10 ¹⁹ atoms / cc. The average concentration of the first semiconductor layer is 1.0 × 10 ¹⁴ atoms / cm ³ , and the integrated concentration between the two points at which the net doping concentration is equal to the average concentration is 9.5 × 10 ¹¹ atoms / cm ² .

  In FIG. 16, the distance from the anode electrode-proton distribution characteristics As shown in FIG. 12, the distance to the location where the net doping concentration of the first semiconductor layer 1 reaches a peak is 60 μm. This distance is equal to the proton range Rp when the surface of the second semiconductor layer 2 is irradiated with protons in the manufacturing stage. The proton concentration is high before and after the proton range Rp. Oxygen atoms are introduced into the first semiconductor layer 1, and a desired broad buffer structure is formed by a composite donor composed of oxygen atoms and protons.

Next, a manufacturing process of the semiconductor device according to the fourth embodiment will be described. Here, as an example, a case where a semiconductor device having the dimensions and net doping concentration illustrated in FIG. 16 (withstand voltage: 1200 V class, rated current: 150 A) will be described. 17 and 18 are diagrams showing the manufacturing process. First, as shown in a sectional view 200 of FIG. 17, an FZ wafer 201 having a specific resistance of 40 to 200 Ωcm, for example, 120 Ωcm (phosphorus concentration 3.8 × 10 ¹³ atoms / cc) is prepared as a semiconductor substrate.

Then, as shown in a sectional view 210 of FIG. 17, phosphorus glass 211 is applied to both surfaces of the FZ wafer 201, and heat treatment is performed, for example, at 1250 ° C. for 100 hours in a nitrogen and oxygen atmosphere. To diffuse. By this heat treatment, a large amount of oxygen (O) is introduced into the wafer from both sides of the FZ wafer, and the oxygen concentration in the FZ wafer becomes a solid solution limit concentration (about 1 × 10 ¹⁸ atoms / cc).

  Next, as shown by the alternate long and short dash line in the cross-sectional view 210, the FZ wafer 201 is ground to remove the high-concentration phosphorus diffusion layer 212 on the wafer surface. As a result, as shown in the cross-sectional view 220 of FIG. 17, a thin wafer 222 having a third semiconductor layer 221 made of the high-concentration phosphorus layer 212 is obtained. One surface of the thin wafer 222 is polished to a mirror finish. On the mirror finished surface of the FZ wafer, the second semiconductor layer 2, the guard ring edge structure, and the anode electrode 4 are formed in the subsequent diode process step. The thickness of the FZ wafer is selected in advance so as to be, for example, 500 μm after the grinding and polishing.

The specific resistance at the mirror finished surface of the FZ wafer 201 is, for example, 120 Ωcm. The other surface of the FZ wafer is in a state where the phosphorus glass 211 is removed. The surface concentration of this surface is, for example, about 1 × 10 ²⁰ atoms / cm ³ , and high concentration phosphorus is diffused to a depth of, for example, about 80 μm.
Next, as shown in a cross-sectional view 230 of FIG. 17, the second semiconductor layer 2, which is a P anode layer, a guard ring edge structure (not shown), the insulating film 6, and the anode electrode 4 are formed by standard diode process steps. . The concentration of the second semiconductor layer 2 is, for example, 5 × 10 ¹⁶ atoms / cc, and the depth thereof is, for example, 3 μm. The material of the anode electrode 4 is, for example, AlSi 1%.

Next, as shown in a cross-sectional view 240 of FIG. 17, the proton accelerated by the cyclotron is irradiated onto the FZ wafer 201 from the anode electrode 4 side. At this time, the acceleration voltage of the cyclotron is, for example, 7.9 MeV, and the proton dose is, for example, 1.0 × 10 ¹² atoms / cm ² . Further, an aluminum absorber is used and the thickness thereof is adjusted so that the proton range is 60 μm from the interface between the semiconductor of the FZ wafer and the anode electrode 4. In the cross-sectional view 240, the x mark represents a crystal defect 241 generated in the FZ wafer by proton irradiation.

Next, as shown in a cross-sectional view 300 of FIG. 18, for example, heat treatment is performed at 350 ° C. for 1 hour in a hydrogen atmosphere to recover the crystal defects 241. As a result, a high concentration region 301 is formed before and after a depth of 60 μm from the interface between the semiconductor of the FZ wafer 201 and the anode electrode 4. By this high concentration region, a desired broad buffer structure having a peak concentration of 2.0 × 10 ¹⁴ atoms / cm ³ is formed.

Next, as shown in a cross-sectional view 310 of FIG. 18, grinding or wet etching is performed on the surface of the FZ wafer 201 with the phosphor glass 211 removed, to make the FZ wafer have a predetermined thickness. In the case of the 1200 V class, the thickness of the FZ wafer at this stage is typically 100 to 160 μm. In the fourth embodiment, the thickness of the FZ wafer at this stage is, for example, 115 μm (0.92 W ₀ ).

Next, an N-type impurity such as phosphorus is ion-implanted into the surface of the FZ wafer 201 on which grinding or wet etching has been performed. The acceleration voltage at that time is, for example, 50 keV, and the dose amount is, for example, 1 × 10 ¹⁵ atoms / cm ² . Next, the ion-implanted surface is irradiated with a laser beam such as a YAG second harmonic laser by a double pulse method.
Here, the double pulse method is a method of continuously irradiating a plurality of pulse lasers by shifting the irradiation timing by a predetermined delay time from a plurality of laser irradiation apparatuses for each laser light irradiation area. The double pulse method is described in detail in Japanese Patent Application Laid-Open No. 2005-223301.

The energy density at the time of laser beam irradiation by the double pulse method is, for example, 3 J / cm ² in total for each laser beam irradiation area. The delay time of the double pulse is, for example, 300 nsec. By this laser irradiation, an N-type impurity such as phosphorus ion-implanted before that is electrically activated, and the third semiconductor layer 3 serving as an N ⁺ cathode layer is formed.
Finally, as shown in a cross-sectional view 320 of FIG. 18, a metal film is formed on the surface of the third semiconductor layer 3 in the order of titanium, nickel, and gold, and the cathode electrode 5 that is in ohmic contact with the third semiconductor layer 3 is formed. Thus, the semiconductor device (diode) is completed. A portion of the FZ wafer 201 between the second semiconductor layer 2 and the third semiconductor layer 3 becomes the first semiconductor layer 1. A characteristic diagram 330 in FIG. 18 is a net doping concentration profile corresponding to the semiconductor device in the cross-sectional view 320.

In the above example, as a method for manufacturing a wafer containing oxygen, a method has been described in which phosphorus glass containing high-concentration phosphorus is applied to an FZ wafer and heat treatment is performed in an atmosphere such as oxygen.
As an alternative to this method, there is a method of making an FZ wafer containing a high concentration of oxygen using CZ (chocolate ski) crystal (or polycrystal). A high concentration of oxygen is mixed in the CZ crystal or the like, and the concentration is about 1 × 10 ¹⁸ cm ⁻³ which becomes supersaturated at 1300 degrees. When this CZ crystal is used as a raw material for pulling up the FZ wafer, oxygen of 1.0 × 10 ¹⁶ cm ⁻³ or more remains even after the pulling, and contains the same amount of oxygen as that of the DW wafer produced by applying the phosphorous glass described above. An FZ wafer can be produced. If this method is used, an oxygen-containing FZ wafer can be obtained at a low price without performing the above-described oxygen diffusion process at a high temperature.
(Embodiment 5)
19, 20, 21, and 27 are diagrams showing application examples of the semiconductor device of the first to fourth embodiments. A converter-inverter circuit 30 shown in FIG. 19 can efficiently control an induction motor, a servo motor, and the like, and is widely used in industries, electric railways, and the like. A power factor correction circuit (PFC circuit) 40 shown in FIG. 20 is a circuit that improves the waveform by controlling the input current of AC-AC conversion in a sine wave shape, and is used for a switching power supply. A circuit diagram 2000 of FIG. 21 is an overall view of the matrix converter circuit 50, and a circuit diagram 2010 is a diagram showing a configuration of the switching unit 51 of the matrix converter circuit. A circuit diagram 60 of FIG. 27 shows a case where the converter unit of FIG. 19 is configured by a switching element (IGBT, MOSFET, etc.) and the freewheeling diode of the present invention. Thus, if the current at regeneration is controlled by using the switching element in the converter unit, the power generated by the motor at the time of regeneration can be returned to the primary side, and further power saving operation can be achieved. Since the semiconductor device having the broad buffer structure of the present invention can reduce the thickness of the N ⁻ drift layer and increase its operation speed, a conversion device having an operating frequency of 20 kHz or more can be realized.

  As described above, the present invention is not limited to the above-described embodiment, and various modifications can be made. For example, the dimensions and concentrations described in the embodiments are examples, and the present invention is not limited to these values. Moreover, although each example mentioned above is an example of a diode, this invention is applicable also to IGBT and reverse blocking IGBT. Also in this case, not only low loss but also turn-off with suppressed oscillation can be realized. In the case of IGBT, the conductivity type of the third semiconductor layer is P-type. Further, in each of the above-described examples, the first conductivity type is N-type and the second conductivity type is P-type. However, the present invention may be configured such that the first conductivity type is P-type and the second conductivity type is N-type. The same holds true.

  In reverse blocking IGBT, an FZ bulk wafer is used to create the gate, emitter and edge structures on the front surface, and then an electron beam is irradiated at 100 kGy or less, and then the wafer is ground and polished to a final thickness of around 100 μm. However, there is a step of activating the implanted boron element by boron ion implantation on the back side and laser irradiation. At the time of turn-off, the depletion layer spreads from the front side and the carriers disappear as in the reverse recovery of the diode. However, the effect of the present invention can suppress the rapid disappearance of carriers as in the diode, so there is no oscillation. Smooth turn-off is possible.

Therefore, a low-loss and soft-recovery diode and an IGBT that can be smoothly turned off without oscillation can be manufactured. Moreover, in a power converter such as a PWM inverter using an IGBT module having such characteristics, overvoltage breakdown and generation of EMI noise can be suppressed.
Further, although 600 V and 1200 V class semiconductor devices have been described in the embodiments, the present invention can be similarly applied to a withstand voltage class of 1700 V, 3300 V, or higher. For example, 80～200Omucm basic density _{N 0} at 1700V class, N ^- and 120~200μm the thickness of the drift layer, also in the 3300V class 200～500Omucm, and 250~400μm, N ^- the impurity concentration distribution of the drift layer wherein A broad buffer structure satisfying (2) may be used.
(Embodiment 6)
In the following description, the first conductivity type is n-type and the second conductivity type is p-type, but the same effect can be obtained with the opposite polarity.

  FIG. 34 is an enlarged view showing an example of a portion surrounded by a broken-line circle in the circuit of FIG. 19 including the drive circuit. The FWD 500 and the IGBT 501 are connected oppositely in antiparallel, and the anode and cathode of the FWD are connected to the emitter and collector of the IGBT, respectively. The control terminal of the drive circuit 502 is connected to the gate (control electrode) of the IGBT via the gate resistor 503.

One such drive circuit is connected to each IGBT in the upper arm in FIG. 19, and one drive circuit is connected to each IGBT in the lower arm, or a common drive circuit is connected.
Here, the gate resistor 503 may be a method in which a lead type resistor is connected between the IGBT module 504 and the same circuit as shown in FIG. 34 (a), or inside the drive circuit as shown in FIG. 34 (b). Also good. Further, as shown in FIG. 35, there is a method of connecting a known chip resistor or lead resistor between the gate terminal and the gate pad of the IGBT chip inside the module 504. In addition, as shown in FIG. 36, a resistance such as polysilicon is provided between the gate polysilicon of each cell in the IGBT chip 505 and each cell in the same chip (the cell is a basic component part for performing the IGBT operation). There is a method of forming a layer on a chip and using it as a gate resistor, which is more desirable from the viewpoint of area and cost reduction of a module or a power converter.

FIG. 28 shows the FWD when the opposite-side IGBT with the same rating is turned on at a current of 10 A (1/10 of the rating) using the above-described 600 V / 100 A FWD (A) and the conventional FWD. This is a comparison of reverse recovery waveforms. The power supply voltage is 300 V (half rated value). The IGBT is a field stop type (FS-) IGBT having a wafer thickness of 70 μm and an active area of 0.55 cm ² . The gate resistance of the drive circuit is 8Ω, and the gate resistance value per unit area (1 cm ² ) of the IGBT is 4.4Ωcm ² . This value is 1/3 of a general recommended gate resistance value (for example, 24Ω, 13.2Ωcm ² per unit area), and is sufficiently small. In such a case, conventionally, when the opposing diode enters reverse recovery when the IGBT is turned on, the waveform oscillates, and the reverse recovery surge voltage often exceeds the breakdown voltage. As is clear from FIG. 28B, it can be seen that such oscillation and surge voltage are generated in the conventional diode. However, by using the FWD of the present invention, the oscillation and surge voltage as shown in (b) can be sufficiently reduced as shown in FIG.

This effect has a very favorable effect on the IGBT turn-on loss and thus the actual machine loss.
FIG. 29 shows a turn-on waveform of the IGBT when the FWD of the present invention and the above-described IGBT are combined. The current is the rated current, the power supply voltage is 300 V, and the gate resistance is 0Ω. Even when the connection is made without going through the gate resistor in this way, the diode does not oscillate and does not appear in the voltage waveform of the IGBT. The turn-on loss at this time is extremely low as compared with the case where the gate resistance is large.

  FIG. 30 is a graph in which the turn-on loss of the IGBT and the FWD surge voltage at the time of reverse recovery of the FWD (= at the time of IGBT turn-on) are plotted for each drive gate resistance. The horizontal axis is the gate resistance (Ω), the left axis is the FWD surge voltage (peak voltage, V), and the right axis is the IGBT turn-on loss (mJ). The turn-on loss is a value obtained by integrating a value obtained by multiplying the IGBT collector-emitter voltage and the same current by the time required for switching.

  First, when the gate resistance is 18Ω or more, the increase in the IGBT turn-on loss becomes moderate as the gate resistance increases, and is saturated to about 5.2 mJ. At this time, the surge voltage of the diode is a value that does not exceed the power supply voltage. On the other hand, when the gate resistance is decreased, the IGBT turn-on loss is decreased accordingly, and the diode surge voltage is increased. The turn-on loss is drastically reduced at 15Ω or less, and is 1 to 2 mJ at 5Ω or less, which is reduced to about 1/10 of the value at 18Ω.

  On the other hand, the surge voltage increases as the gate resistance decreases, but the ratio of the diode of the present invention is slower, and when it is 5Ω or less, the present invention suppresses it to 570 V, which is the rated voltage or less. On the other hand, in the conventional diode, the voltage is 800 V exceeding the breakdown voltage. Also in the reverse recovery waveform, the conventional type oscillates remarkably when the gate resistance is 12Ω or less, but the diode of the present invention does not oscillate even at 0Ω. Therefore, if the diode of the present invention is used, an inverter with very little electromagnetic noise can be realized.

Accordingly, the gate resistance, the active area of the IGBT 0.55 cm ² in 15~20Ω less, that is, if a unit area 1 cm ^2, or 8.25～11Omucm ² or less, more 8Omucm ² or less.
FIG. 31 is a diagram comparing the behavior of the turn-on waveform when five types of gate resistors are used in relation to the waveform of FIG. A gate resistance of 0Ω to 18Ω was used. Since the turn-on loss is a value obtained by integrating the multiplication of the IGBT collector-emitter voltage and the same current as described above, the turn-on loss increases because the voltage waveform and the current waveform in the graph are both non-zero. The time domain will increase. As a result of this experiment, we found that the time when the voltage is lower than the half-value 150V of the applied voltage (power supply voltage, 300V) in the time region of the non-zero part is the time when the same current is maximum. We found that it increases after (the time when the vertical auxiliary line is inserted). Therefore, in order to keep the turn-on loss low, it is necessary that the time when the voltage falls below the half of the applied voltage be at least before the time when the current becomes the maximum. Furthermore, for this purpose, it is desirable that the gate resistance is approximately equal to 8Ω, that is, lower than 4.4Ωcm ² per 1 cm ^{2 of} unit area.
(Effect of the invention)
FIG. 32 is a graph comparing the actual inverter loss and its breakdown between two types of FWDs using the above-described FWD (the present invention and the conventional one) and IGBT. The inverter is a three-phase PWM inverter, the output frequency is 50 Hz, the effective value of the output current is 54 A_rms, and the operating carrier frequency is 10 kHz. Here, the gate resistance of the drive circuit is selected so that the built-in FWD can sufficiently suppress oscillation. The FWD of the present invention is 8Ω and the conventional diode is 18Ω. As is apparent from the figure, the actual loss is 10% when the FWD of the present invention is driven with a low gate resistance (46.1 W) than when the conventional diode is driven with the conventional method (51.2 W). Low inverter loss could be achieved. Furthermore, since the FWD of the present invention does not oscillate even when the gate resistance is 0Ω, in this case, it becomes 42.5 W, which is a 17% reduction.

FIG. 33 shows a spectrum obtained by measuring the radiation noise of the inverter of FIG. The intensity of the present invention was reduced by -2 dB at the peak time (18 MHz) and by -12 dB at 90 MHz at the high frequency. Further, in the conventional case, damping is observed around 50 MHz, which also affects the noise operation.
From the above, by using the diode of the present invention, it is possible to provide a power converter such as an IGBT module, an IPM, and an inverter with low loss and low radiation noise that could not be obtained by a conventional driving method.

It is a figure which shows the structure and net doping concentration of the semiconductor device concerning Embodiment 1 of this invention. FIG. 3 is a diagram showing net doping concentration distributions in a first semiconductor layer and a second semiconductor layer of the semiconductor device according to the first embodiment; FIG. 3 is a diagram showing net doping concentration distributions in a first semiconductor layer and a second semiconductor layer of the semiconductor device according to the first embodiment; FIG. 6 is a diagram showing a manufacturing process of the semiconductor device according to the first embodiment; It is a distribution map of the impurity concentration actually measured. FIG. 3 is a diagram showing net doping concentration distributions in a first semiconductor layer and a second semiconductor layer of the 1200 V class semiconductor device according to the first embodiment; It is a figure which shows the net doping concentration distribution in the 1st semiconductor layer and 2nd semiconductor layer of the conventional 1200V class semiconductor device. FIG. 3 is a diagram illustrating a reverse recovery waveform of the diode according to the first embodiment. FIG. 3 is a diagram illustrating a reverse recovery waveform of the diode according to the first embodiment. It is a figure which shows the relationship between DC applied voltage and reverse recovery peak voltage in Embodiment 1 and the conventional semiconductor device. It is a figure which shows the relationship between integral density | concentration and pressure | voltage resistance. It is a trade-off curve which shows the reverse recovery loss characteristic of the 600V class diode concerning this invention. It is a trade-off curve which shows the reverse recovery loss characteristic of the diode of 1200V class concerning this invention. N ^- illustrates thickness W and the reverse recovery loss Err relationship for (a) 600V class and (b) 1200 V class drift layer. N ^- is a graph showing the relationship between the thickness W and the breakdown voltage BV for (a) 600V class and (b) 1200 V class drift layer. It is a figure which shows the structure of the semiconductor device concerning Embodiment 4 of this invention, a net doping concentration, and proton distribution. FIG. 10 is a diagram showing a manufacturing process of the semiconductor device according to the fourth embodiment; FIG. 10 is a diagram showing a manufacturing process of the semiconductor device according to the fourth embodiment; It is a figure which shows the structure of a converter-inverter circuit. It is a figure which shows the structure of a power factor improvement circuit. It is a figure which shows the structure of a matrix converter circuit. It is a figure which shows the reverse recovery waveform of the conventional diode. It is a figure which shows the reverse recovery waveform of the conventional diode. It is a figure which shows net doping concentration distribution in the 1st semiconductor layer and 2nd semiconductor layer of the conventional semiconductor device. It is a figure which shows net doping concentration distribution in the 1st semiconductor layer and 2nd semiconductor layer of the conventional semiconductor device. It is a figure which shows the structure of a single phase chopper circuit. It is a figure which shows the structure of the converter-inverter circuit which has a switching element in a converter part. It is the figure which compared the reverse recovery waveform of FWD when the opposite side IGBT of the same rating was turned on using 600V / 100A FWD (a) concerning this invention, and conventional type FWD (b). It is a figure which shows the turn-on waveform of IGBT when FWD concerning this invention and the above-mentioned IGBT are combined. It is the graph which plotted the turn-on loss of IGBT concerning Embodiment 6, and the FWD surge voltage at the time of FWD reverse recovery (= at the time of IGBT turn-on) according to drive gate resistance. It is the figure which compared the behavior of the turn-on waveform when five types of gate resistances were used about the waveform of FIG. It is the graph which compared the inverter actual machine loss concerning Embodiment 6, and the breakdown in the case of FWD (left bar graph) of the present invention, and conventional FWD (right side). The spectrum which measured the radiation noise of the inverter concerning Embodiment 6 (of Drawing 32) is shown. It is an enlarged view which shows an example of the part enclosed with the broken-line circle in the circuit of FIG. It is an enlarged view which shows another example of the part enclosed with the broken-line circle in the circuit of FIG. FIG. 20 is an enlarged view showing still another example of a portion surrounded by a broken-line circle in the circuit of FIG. 19.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 1st semiconductor layer 2 2nd semiconductor layer 3 3rd semiconductor layer 4 Anode electrode 5 Cathode electrode 10 Sectional drawing of a semiconductor device

Claims (6)

A first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type formed on one main surface of the first semiconductor layer and having a higher impurity concentration than the first semiconductor layer; and the first semiconductor A third semiconductor layer of the first conductivity type having a higher impurity concentration than that of the first semiconductor layer, and at least one position where the impurity concentration of the first semiconductor layer is maximized. In the semiconductor device in which the impurity concentration of the first semiconductor layer decreases with an inclination from the position where the first semiconductor layer reaches the maximum toward both the second semiconductor layer and the third semiconductor layer.
The following formula (1 ) of the impurity concentration of the first semiconductor layer

The integrated concentration represented by the equation (2)

(Where x is the position on the coordinate axis from one main surface of the first semiconductor layer to the other main surface, N _net (x) is the impurity concentration at the position x of the first semiconductor layer, and Xc is the first the position closest to the second semiconductor layer a x satisfying _N net (x) _{= N dm} semiconductor layer, Xd is most position where the _N net (x) _{= N dm} in the first semiconductor layer the position closer to the third semiconductor layer, the N _dm is the average concentration of the impurity concentration of the first semiconductor layer, representing respectively)
The filling,
The impurity concentration N ₀ and the average concentration N _{dm in the} vicinity of the junction of the first semiconductor layer with the second semiconductor layer are _expressed by the following formula (3).

The filling,
The distance index W ₀ defined by the first semiconductor layer thickness W and the following formula (5) is expressed by the following formula (4).


(BV represents the breakdown voltage of the semiconductor device)
The semiconductor device characterized by satisfy | filling. A semiconductor power conversion device, wherein the semiconductor device according to claim 1 is mounted, and the operating frequency of the semiconductor device is 20 kHz or more. A drive circuit used in a semiconductor power converter having a diode and a semiconductor switching device,
The diode and the semiconductor switching device are connected in antiparallel, and either or both of the diode and the semiconductor switching device are the semiconductor device according to claim 1,
11 Ωcm between the control terminal of the drive circuit and the control electrode of the semiconductor switching device ² A drive circuit having the following resistors. 4. The drive circuit according to claim 3, wherein a control terminal of the drive circuit is 8 Ωcm between the control electrode of the semiconductor switching device. ² A drive circuit having the following resistors. 4. The method of driving a drive circuit according to claim 3, wherein when the semiconductor switching device is switched from a blocking state to a conductive state, the first electrode formed on one main surface of the semiconductor switching device and the other main A driving method characterized in that the time at which the potential difference between the second electrode formed on the surface reaches a half value of the power supply voltage is earlier than the time at which the semiconductor switching device reaches the maximum current from the blocking state. A semiconductor power conversion device comprising the drive circuit according to claim 3, wherein the semiconductor switching device is controlled by the drive method according to claim 5.