JP5152278B2 - Manufacturing method of laminated electronic component and laminated electronic component - Google Patents

Description

  The present invention relates to a method for manufacturing a laminated electronic component and a laminated electronic component.

  In manufacturing a laminated electronic component such as a capacitor, an internal electrode pattern is formed on a ceramic green sheet, and a green laminate is obtained by laminating and pressing the ceramic green sheet on which the internal electrode pattern is formed. By the way, in this manufacturing method, since the non-formation area | region (gap | interval) in which an internal electrode pattern is not formed will be formed on a ceramic green sheet, if it laminates and presses as it is, it will be between a non-formation area | region and an internal electrode pattern. In some cases, the steps cause internal structural defects such as cracks.

  Therefore, in the manufacturing method described in Patent Document 1, a step absorption layer is provided by applying a paste containing the same dielectric material as the material of the ceramic green sheet to a non-formation region where the internal electrode pattern is not formed on the ceramic green sheet. The step absorption layer prevents such a step from occurring. And in the manufacturing method of patent document 1, after canceling | dissolving this level | step difference, a ceramic green sheet is laminated | stacked and crimped | bonded, thereby manufacturing a multilayer electronic component, suppressing generation | occurrence | production of an internal structural defect.

JP-A-52-135051

  However, since the demand for miniaturization of multilayer electronic components such as capacitors has become stronger, in manufacturing these electronic components, the step absorption layer is formed so as to be shifted from the non-formation region. In some cases, a gap is formed between the electrode pattern and the internal electrode pattern. If such a gap is formed, there is a risk of causing internal structural defects. Therefore, as shown in the plan view of the internal electrode layer and the like in FIG. 26, when the step absorption layers 213 to 216 are formed in the non-formation regions R201 to R204, the step absorption layer is intentionally formed on the outer edges of the internal electrode patterns 207 to 210. Manufacture is performed so that the portions 217 to 220 overlap each other, thereby completely eliminating the gap between the step absorption layers 213 to 216 formed in the non-forming regions R201 to R204 and the internal electrode patterns 207 to 210. The generation of structural defects is suppressed.

  By the way, when it is going to laminate | stack the some ceramic green sheet comprised so that the level | step difference absorption layers 217-220 may overlap with the outer edge of the internal electrode patterns 207-210, as shown in FIG. 27 and FIG. There may be a place where there is a step absorption layer and a place where there is no step absorption layer. For example, a step portion (gap) S may be formed at the connection portion between the main surface electrodes 207a to 210a and the extraction electrodes 207b to 210b. there were. When a laminated body including such a stepped portion S is pressure-bonded as it is (see FIG. 29A), stress concentrates on the stepped portion, and as a result, the opposing main surface electrode portions may come into contact with or be close to each other. (See FIGS. 29B and 29C). Thus, if contact etc. of main surface electrode 207a-210a will arise, it will become difficult for a multilayer electronic component to fully exhibit the intended performance.

  An object of this invention is to provide the manufacturing method which can manufacture the multilayer electronic component which suppressed generation | occurrence | production of the internal structural defect, and the multilayer electronic component manufactured by this manufacturing method.

  The method for manufacturing a multilayer electronic component according to the present invention includes a step of forming an internal electrode pattern including at least a main surface electrode portion on a ceramic green sheet, a non-formation region where the internal electrode pattern is not formed on the ceramic green sheet, and an internal electrode Forming a step-absorbing layer on the entire periphery of the main surface electrode portion of the pattern; and laminating and pressing a ceramic green sheet on which the internal electrode pattern and the step-absorbing layer are formed; and forming a green laminate It has.

  In the method for manufacturing a laminated electronic component according to the present invention, in the step of forming the step absorption layer, the step absorption layer is formed over the entire periphery of the main surface electrode portion of the internal electrode pattern. In this case, even if the ceramic green sheet is laminated and pressure-bonded by the step absorption layer formed on the entire periphery of the main surface electrode portion, it is possible to prevent the step portion from being formed on the main surface electrode portion. The resulting stress concentration can be avoided. As a result, the occurrence of internal structural defects such as cracks in the laminate is suppressed, and for example, contact and proximity between main surface electrode portions can be avoided.

  In the method for manufacturing a laminated electronic component according to the present invention, in the step of forming the internal electrode pattern, in the step of forming the internal electrode pattern on the ceramic green sheet so as to further include the extraction electrode portion, and forming the step absorption layer, It is preferable to form a step absorption layer in the extraction electrode portion of the internal electrode pattern. In this case, even if the ceramic green sheet is laminated and pressure-bonded, the step absorption layer formed in the extraction electrode portion can prevent the formation of the step portion in the extraction electrode portion, and stress concentration caused by the step portion can be reduced. It can be avoided. As a result, the occurrence of internal structural defects in the laminate is further suppressed.

  As described above, when the step absorption layer is formed in the extraction electrode portion, the step absorption layer may be formed at the edge of the extraction electrode portion on the non-formation region side in the step of forming the step absorption layer. Alternatively, a step absorption layer may be formed on the entire extraction electrode portion.

  In the method of manufacturing a laminated electronic component according to the present invention, in the step of forming the step absorption layer, the step absorption layer may be formed substantially simultaneously on the entire periphery of the main surface electrode portion and the extraction electrode portion. Further, the step absorption layer may be formed substantially simultaneously in the non-formation region and the entire periphery of the main surface electrode portion. Further, in the step of forming the step absorption layer, the step absorption layer may be formed almost simultaneously in the non-formation region, the entire periphery of the main surface electrode portion, and the extraction electrode portion. By forming each step absorption layer substantially simultaneously, the manufacturing process can be simplified.

  A multilayer electronic component according to the present invention includes an element body in which a plurality of dielectric layers are laminated, an internal electrode layer disposed in the element body so as to be sandwiched between the dielectric layers, and including at least a main surface electrode, and a dielectric layer There is provided a non-formation region where no internal electrode layer is disposed above and a step absorption layer disposed on the entire periphery of the main surface electrode of the internal electrode layer.

  In the multilayer electronic component according to the present invention, the step absorption layer is disposed over the entire periphery of the main surface electrode of the internal electrode layer. In this case, the step absorption layer is interposed between the main surface electrodes, so that the main surface electrodes do not come into contact with or approach each other. For this reason, it can be set as a laminated electronic component which can exhibit a predetermined performance by suppressing generation | occurrence | production of an internal structural defect by such a level | step difference absorption layer.

  In the multilayer electronic component according to the present invention, it is preferable that the internal electrode layer further includes an extraction electrode, and the step absorption layer is further disposed on the extraction electrode. In this case, a step absorption layer is also interposed between the extraction electrodes. For this reason, such a step absorption layer can suppress the occurrence of internal structure defects even in the vicinity of the extraction electrode.

  In the multilayer electronic component according to the present invention, the internal electrode layers may be at least four types or more, and may further include a terminal electrode connected to each of the four or more types of internal electrodes. When the internal electrode layer is composed of many types, the stepped portion varies in the surface direction of the internal electrode layer, resulting in a stepped portion every other multiple layers in the stacking direction. Stress concentrates on the stepped portions generated every other layer, and internal structural defects are likely to occur. However, in the case of the multilayer electronic component having the configuration of the present invention, even in the case where the internal electrode layer is composed of a large number of four or more types, the step portion that may occur every other multiple layers in this way. The occurrence of such internal structural defects can be suppressed.

  ADVANTAGE OF THE INVENTION According to this invention, the manufacturing method which can manufacture the multilayer electronic component which suppressed generation | occurrence | production of an internal structural defect, and the multilayer electronic component manufactured by this manufacturing method can be provided.

1 is a perspective view of a multilayer capacitor according to a first embodiment of the present invention. It is a top view which shows the state in which the level | step difference absorption layer was formed in the internal electrode layer and the dielectric material layer. It is a top view which shows typically the overlapping condition of the level | step difference absorption layer at the time of laminating | stacking an internal electrode layer. FIG. 4 is a cross-sectional view schematically showing the stacking order of internal electrode layers and the like along the line VI-VI in FIG. 3. It is typical sectional drawing which shows that internal electrode layers do not contact in the multilayer capacitor which concerns on 1st embodiment. It is a top view which shows the modification which changed the formation location of the level | step difference absorption layer in the multilayer capacitor which concerns on 1st embodiment. It is a perspective view of the multilayer capacitor concerning a second embodiment of the present invention. It is a top view which shows the state in which the level | step difference absorption layer was formed in the internal electrode layer and the dielectric material layer. It is a top view which shows typically the overlapping condition of the level | step difference absorption layer at the time of laminating | stacking an internal electrode layer. FIG. 10 is a cross-sectional view schematically showing the stacking order of internal electrode layers and the like along the line XX in FIG. 9. It is a perspective view of the multilayer capacitor concerning a third embodiment of the present invention. It is a top view which shows the state in which the level | step difference absorption layer was formed in the internal electrode layer and the dielectric material layer. It is a top view which shows typically the overlapping condition of the level | step difference absorption layer at the time of laminating | stacking an internal electrode layer. FIG. 14 is a cross-sectional view schematically showing the stacking order of internal electrode layers and the like along the line XIV-XIV in FIG. 13. It is a perspective view of the multilayer capacitor which concerns on 4th embodiment of this invention. It is a top view which shows the state in which the level | step difference absorption layer was formed in the internal electrode layer and the dielectric material layer. It is a top view which shows typically the overlapping condition of the level | step difference absorption layer at the time of laminating | stacking an internal electrode layer. FIG. 18 is a cross-sectional view schematically illustrating the stacking order of internal electrode layers and the like along the line XVIII-XVIII in FIG. 17. In the multilayer capacitor in accordance with the fourth embodiment, it is a plan view showing a modification in which the shape of the internal electrode layer is changed. FIG. 20 is a cross-sectional view schematically illustrating the stacking order of internal electrode layers and the like along the line XX-XX in FIG. 19. It is a perspective view of the multilayer capacitor concerning a fifth embodiment of the present invention. It is a top view which shows the state in which the level | step difference absorption layer was formed in the internal electrode layer and the dielectric material layer. It is a top view which shows typically the overlapping condition of the level | step difference absorption layer at the time of laminating | stacking an internal electrode layer. FIG. 24 is a cross-sectional view schematically illustrating the stacking order of internal electrode layers and the like along the line XXIV-XXIV in FIG. 23. FIG. 24 is a cross-sectional view schematically illustrating the stacking order of internal electrode layers and the like along the line XXV-XXV in FIG. 23. It is a top view which shows the state by which the level | step difference absorption layer was formed in the internal electrode layer and dielectric material layer of the conventional multilayer capacitor. It is a top view which shows typically the overlap condition of the level | step difference absorption layer at the time of laminating | stacking the internal electrode layer etc. of the conventional multilayer capacitor. It is sectional drawing which shows typically the lamination | stacking order of the internal electrode layers of a conventional multilayer capacitor along the line XXVIII-XXVIII in FIG. It is typical sectional drawing which shows that internal electrode layers will contact in the conventional multilayer capacitor.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the description, the same reference numerals are used for the same elements or elements having the same function, and redundant description is omitted.

  First, with reference to FIG.1 and FIG.2, the structure of the multilayer capacitor 1 manufactured by the manufacturing method which concerns on this embodiment is demonstrated. The multilayer capacitor 1 includes a substantially rectangular parallelepiped capacitor element 2, terminal electrodes 3 to 6 disposed on the outer surface of the capacitor element 2, and internal electrode layers 7 to 10 disposed in the capacitor element 2. It is prepared for.

The capacitor body 2 is formed by laminating a plurality of dielectric layers 12 and has a substantially rectangular parallelepiped shape. Capacitor body 2 has main surfaces 2a and 2b that are opposed to each other and substantially rectangular, end surfaces 2c and 2d that are opposed to each other and substantially rectangular, and side surfaces 2e and 2f that are opposed to each other and are substantially rectangular. doing. The end surfaces 2c and 2d and the side surfaces 2e and 2f extend so as to connect the main surfaces 2a and 2b. The dielectric layer 12 is formed of a dielectric material having electrostrictive characteristics such as a BaTiO ₃ system, a Ba (Ti, Zr) O ₃ system, and a (Ba, Ca) TiO ₃ system. The thickness of the dielectric layer 12 is, for example, about 0.5 to 3 μm.

  Two terminal electrodes 3 to 6 are arranged in parallel on each of the side surfaces 2e and 2f of the capacitor body 2, and the terminal electrodes 3 and 4 and the terminal electrodes 6 and 5 spaced apart in parallel are arranged on the side surfaces 2e and 2f. Opposing each other in the facing direction. Each of the terminal electrodes 3 to 6 is formed, for example, by applying a conductive paste containing conductive metal powder and glass frit to predetermined locations such as the side surfaces 2e and 2f of the capacitor body 2 and baking it. If necessary, a plating layer may be formed on the baked electrode.

  Each of the internal electrode layers 7 to 10 is sequentially laminated in the capacitor body 2 with at least one dielectric layer 12 interposed therebetween (see FIG. 4). As shown in FIG. 2, each of the internal electrode layers 7 to 10 has main surface electrodes 7 a to 10 a that form a capacitance portion facing the other internal electrode layers 7 to 10 adjacent in the stacking direction, The surface electrodes 7a to 10a are respectively configured to include extraction electrodes 7b to 10b that lead out toward the terminal electrodes 3 to 6, respectively. Main surface electrodes 7 a to 10 a have a substantially rectangular shape, and are arranged so as to be located at a substantially central portion of dielectric layer 12.

  The internal electrode layer 7 is drawn to the side surface 2 e by the lead electrode 7 b and is electrically and mechanically connected to the terminal electrode 3. The internal electrode layer 8 is drawn to the side surface 2 e by the lead electrode 8 b and is electrically and mechanically connected to the terminal electrode 4. The internal electrode layer 9 is drawn to the side surface 2 f by the lead electrode 9 b and is electrically and mechanically connected to the terminal electrode 5. The internal electrode layer 10 is drawn to the side surface 2 f by the lead electrode 10 b and is electrically and mechanically connected to the terminal electrode 6. The internal electrode layers 7 to 10 are made of, for example, a sintered body of a conductive paste. The thickness of the internal electrode layers 7 to 10 is, for example, about 0.5 to 3 μm.

  2 to 4, the multilayer capacitor 1 includes first step absorption layers 13 to 16 in the non-formation regions R1 to R4 where the internal electrode layers 7 to 10 are not formed on the dielectric layer 12, respectively. I have. These non-formation regions R1 to R4 are regions surrounding the internal electrode layers 7 to 10 on the dielectric layers 12. The first step absorption layers 13 to 16 are made of the same dielectric material as that of the dielectric layer 12, for example. The thickness of the first step absorption layers 13 to 16 is substantially the same as that of the internal electrode layers 7 to 10, for example, about 0.5 to 3 μm. The same applies to the materials and thicknesses of other step absorption layers described later.

  In addition to the first step absorption layers 13 to 16, the multilayer capacitor 1 includes the second step absorption layers 17 to 20 on the entire peripheral edges of the main surface electrodes 7 a to 10 a of the internal electrode layers 7 to 10. A pair of third step absorption layers 23 to 26 are provided at the edges of the 10 to 10 extraction electrodes 7b to 10b on the non-forming regions R1 to R4 side. The second step absorption layers 17 to 20 are connected to the first portions 17a to 20a formed along the edges on the non-forming regions R1 to R4 side, the main surface electrodes 7a to 10a, and the extraction electrodes 7b to 10b. It is comprised from the 2nd part 17b-20b located in.

  Then, the manufacturing method of the multilayer capacitor 1 which has the structure mentioned above is demonstrated.

  In manufacturing the multilayer capacitor 1, first, the ceramic paste P <b> 1 for forming the dielectric layer 12 and the step absorption layers 13 to 16, 17 to 20, and 23 to 26, and the internal electrode layers 7 to 10 are formed. For this purpose, a conductive paste P2 is prepared.

The ceramic paste P1 is a paste obtained by mixing and kneading an organic vehicle or the like with the raw material of the dielectric material constituting the dielectric layer 12 or the like. Examples of the dielectric material include oxides, carbonates, nitrates and hydroxides of metal atoms contained in complex oxides such as BaTiO ₃ , (Ti, Zr) O ₃ , and (Ba, Ca) TiO ₃ , for example. And combinations of organometallic compounds. The conductive paste P2 is a paste-like composition obtained by mixing a binder resin, a solvent, or the like with a metal powder such as Ni, Ag, or Pd.

  After preparing the ceramic paste P1 and the conductive paste P2, the ceramic paste P1 is applied on a carrier sheet made of PET or the like by using, for example, a doctor blade method, and a plurality of ceramic greens that are precursors of the dielectric layer 12 A sheet 32 is generated.

  Subsequently, as shown in FIG. 2, for example, a conductive paste P <b> 2 is applied to a predetermined position of each ceramic green sheet 32 by screen printing, and the internal electrode layers 7 to 10 are applied on each ceramic green sheet 32. Internal electrode patterns 37 to 40 to be formed are respectively formed. By the process of forming the internal electrode patterns 37 to 40, on the ceramic green sheet 32, a portion corresponding to the main surface electrodes 7a to 10a (main surface electrode portion) and a portion corresponding to the extraction electrodes 7b to 10b (extraction electrode portion) Is formed. In this embodiment, a case where there is one internal electrode layer 7 to 10 will be described as an example. However, a plurality of (for example, 16) portions corresponding to the internal electrode layers 7 to 10 are formed on each ceramic green sheet 32. It may be.

  Subsequently, the non-formation regions R1 to R4 in which the internal electrode patterns 37 to 40 are not formed on the ceramic green sheets 32 on which the internal electrode patterns 37 to 40 are respectively formed, and the main surface electrodes 7a to 7a of the internal electrode patterns 37 to 40. The ceramic paste P1 is applied to the entire periphery of the portion corresponding to 10a and the edges on the non-formation regions R1 to R4 side of the portions corresponding to the extraction electrodes 7b to 10b of the internal electrode patterns 37 to 40 by, for example, screen printing. To do. The application of the ceramic paste P1 is performed substantially simultaneously, whereby the first step absorption layers 13 to 16, the second step absorption layers 17 to 20, and the third step absorption layers 23 to 26 are generated.

  Subsequently, when the internal electrode patterns 37 to 40 and the step absorption layers 13 to 16, 17 to 20, and 23 to 26 are formed on the plurality of ceramic green sheets 32, the internal electrode patterns 37 to 40 are formed. The plurality of green sheets 32 are stacked in the order shown in FIG. 4, and the ceramic green sheets 32 are aligned so that portions corresponding to the adjacent main surface electrodes 7a to 10a face each other substantially in the stacking direction. .

  FIG. 3 is a plan view schematically showing how the step absorption layers overlap when the internal electrode layers 7 to 10 are laminated in this manner. As shown in the figure, the second step absorption layers 17 to 20 are arranged at the same position when viewed from above in the stacking direction on the entire periphery of the main surface electrodes 7a to 10a of the internal electrode layers 7 to 10. Has been. That is, the second step absorption layers 17 to 20 are surely positioned between the peripheral portions of the main surface electrodes 7a to 10a in the stacking direction. In the present embodiment, for example, the ceramic green sheets 32 are laminated so that there are about 2 to 5 sets of internal electrode patterns 37 to 40 in the lamination direction, and the internal electrode patterns 37 to 40 are provided at the top. The ceramic green sheets 32 that are not to be laminated are arranged.

  Subsequently, when the green laminated body 45a is formed by laminating the ceramic green sheets 32 as described above, the green laminated body 45a is pressed and pressure-bonded as shown in FIG. A green laminate 45b as shown in b) is obtained. In this laminated body 45b, for example, the second portion 17b of the second step absorption layer 17 corresponds to the main surface electrodes 7a to 10a of the internal electrode patterns 37 to 40 as shown in FIG. They are not in contact with each other.

Subsequently, the green laminated body 45b is fired, whereby the capacitor body 2 is obtained. Firing is performed by heating the green laminate 45 to, for example, about 1100 to 1300 ° C. in a reducing atmosphere. Prior to the firing treatment, the green laminate 45b may be subjected to a binder removal treatment. The binder removal process is performed by placing the green laminated body 45b in a reducing atmosphere such as in the air or a mixed gas of N ₂ and H ₂ and heating to about 200 to 600 ° C. When a plurality of portions corresponding to the internal electrode layers 7 to 10 are provided on each ceramic green sheet 32, a process of cutting each chip is performed prior to firing.

  Subsequently, when the firing or the like is completed, the conductive paste P3 is applied and baked so as to cover the portions where the lead electrodes 7b to 10b of the side surfaces 2e and 2f of the capacitor body 2 are exposed, and further plated. Thereby, terminal electrodes 3 to 6 as shown in FIG. 1 are formed. As the conductive paste P3, for example, a metal powder mainly containing Cu mixed with glass frit and an organic vehicle can be used. The metal powder may contain Ni, Ag—Pd or Ag as a main component. For the plating, metal plating such as Ni, Sn, Ni—Sn alloy, Sn—Ag alloy, Sn—Bi alloy is used. Further, the metal plating may be a multi-layer structure in which two or more layers of Ni and Sn are formed, for example. Thus, the multilayer capacitor 1 shown in FIG. 1 is completed.

  As described above, in the method for manufacturing the multilayer capacitor 1 according to the present embodiment, in the step of forming the step absorption layer, the second portion is formed on the entire periphery of the portion corresponding to the main surface electrodes 7a to 10a of the internal electrode patterns 37 to 40. Step absorption layers 17 to 20 are formed. Therefore, for example, as shown in FIG. 29, conventionally, a step S is formed in the vicinity of the connecting portion between the main surface electrodes 207a to 210a and the extraction electrodes 207b to 210b, stress concentration occurs, and the main surface electrode Although a short circuit may occur between 207a to 210a, according to the present embodiment, the second step absorption layers 17 to 20 formed on the entire periphery of the portion corresponding to the main surface electrodes 7a to 10a. As shown in FIG. 5, even if the ceramic green sheet 32 is laminated and pressure-bonded, it is possible to prevent the stepped portion (gap) S from being formed in the portions corresponding to the main surface electrodes 7a to 10a. As a result, stress concentration caused by the stepped portion S can be avoided, generation of internal structural defects such as cracks in the green multilayer body 45b can be suppressed, and in the multilayer capacitor 1, for example, contact and proximity between the main surface electrodes 7a to 10a can be avoided. can do.

  In the method of manufacturing the multilayer capacitor 1 according to this embodiment, in the step of forming the internal electrode pattern, the internal electrode patterns 37 to 40 are placed on the ceramic green sheet 32 so as to include portions corresponding to the lead electrodes 7b to 10b. Forming. In the step of forming the step absorption layer, third step absorption layers 23 to 26 are formed in portions corresponding to the extraction electrodes 7b to 10b of the internal electrode patterns 37 to 40. For this reason, even if the ceramic green sheet 32 is laminated and pressure-bonded, the step portions are formed in the portions corresponding to the extraction electrodes 7b to 10b by the third step absorption layers 23 to 26 formed in the portions corresponding to the extraction electrodes 7b to 10b. It can be prevented from being formed, and stress concentration caused by the step portion can be avoided. As a result, the occurrence of internal structural defects in the green laminate 45b is further suppressed.

  Further, in the method for manufacturing the multilayer capacitor 1 in the present embodiment, in the step of forming the step absorption layer, the non-formation regions R1 to R4, the entire periphery of the portion corresponding to the main surface electrodes 7a to 10a, and the extraction electrodes 7b to Step absorption layers 13-16, 17-20, 23-26 are formed almost simultaneously with a part corresponding to 10b. For this reason, a manufacturing process can be simplified.

  The multilayer capacitor 1 according to this embodiment includes a capacitor body 2 in which a plurality of dielectric layers 12 are laminated, and a capacitor body 2 that is sandwiched between the dielectric layers 12 and includes main surface electrodes 7a to 10a. Including internal electrode layers 7 to 10, non-formation regions R <b> 1 to R <b> 4 where the internal electrode layers 7 to 10 are not disposed on the dielectric layer 12, and the entire periphery of the main surface electrodes 7 a to 10 a of the internal electrode layers 7 to 10 2nd level | step difference absorption layers 17-20 arrange | positioned.

  In the multilayer capacitor 1, the step absorption layers 17 to 20 are disposed on the entire periphery of the main surface electrodes 7 a to 10 a of the internal electrode layers 7 to 10. For this reason, the second step absorption layers 17 to 20 are interposed between the main surface electrodes 7a to 10a, and the main surface electrodes 7a to 10a can be prevented from contacting or coming close to each other (FIG. 5). As a result, the multilayer capacitor 1 can be a multilayer electronic component that can exhibit predetermined performance while suppressing the occurrence of internal structural defects.

  In the multilayer capacitor 1, the internal electrode layers 7 to 10 also include the extraction electrodes 7 b to 10 b, and the third step absorption layers 23 to 26 are disposed on the extraction electrodes 7 b to 10 b. For this reason, the third step absorption layers 23 to 26 are interposed between the extraction electrodes 7 b to 10 b. Therefore, in the multilayer capacitor 1, the occurrence of internal structural defects can be suppressed even in the vicinity of the extraction electrodes 7b to 10b.

  In the multilayer capacitor 1, there are four types of internal electrode layers 7 to 10, and terminal electrodes 3 to 6 are respectively connected to the four types of internal electrode layers 7 to 10. When the internal electrode layer is composed of many types, the stepped portion varies in the surface direction of the internal electrode layer, resulting in a stepped portion every other multiple layers in the stacking direction. Stress concentrates on the stepped portions generated every other layer, and internal structural defects are likely to occur. However, in the multilayer capacitor 1 having the configuration of the present embodiment, even if the internal electrode layers 7 to 10 are composed of many types such as four types, they may occur every other layer in this way. The generation | occurrence | production of the level | step difference part which is not present can be prevented, and generation | occurrence | production of an internal structural defect can be suppressed.

  Further, in the multilayer capacitor 1 described above, the third step absorption layers 23 to 26 are provided only at the edges on the non-formation regions R1 to R4 side of the extraction electrodes 7b to 10b. However, as shown in FIG. 6, the third step absorption layers 23a to 26a may be formed so as to cover substantially the entire surface of the extraction electrodes 7b to 10b. In this case, when the first to third step absorption layers 13 to 16, 17 to 20, and 23a to 26a are formed, a portion of the main surface electrodes 7a to 10a where the step absorption layers 17 to 20 are not formed is closed. Screen printing or the like can be performed using a plate making with a simple structure, and the step absorption layers 13-16, 17-20, 23a-26a can be easily formed substantially simultaneously, and the manufacturing process can be further simplified. it can.

(Second embodiment)
Next, the configuration of the multilayer capacitor 51 according to the second embodiment and the manufacturing method thereof will be described. In the present embodiment, unlike the first embodiment, the multilayer capacitor 51 has a two-terminal structure, and the location of the terminal electrodes and the shape of the internal electrode layers are somewhat different. Hereinafter, a description will be given focusing on differences from the first embodiment.

  First, the configuration of the multilayer capacitor 51 will be described with reference to FIGS. The multilayer capacitor 51 includes a capacitor body 52, terminal electrodes 53 and 54, and internal electrode layers 57 and 58. The capacitor body 52 is formed in a substantially rectangular parallelepiped shape by laminating a plurality of dielectric layers 12, and has main surfaces 52a and 52b, end surfaces 52c and 52d, and side surfaces 52e and 52f. The terminal electrodes 53 and 54 are disposed so as to cover the end faces 52 c and 52 d of the capacitor body 52.

  The internal electrode layers 57 and 58 are sequentially stacked in the capacitor body 2 with at least one dielectric layer 12 interposed therebetween (see FIG. 10). The internal electrode layers 57, 58 are principal surface electrodes 57a, 58a that form a capacitance portion facing the other adjacent internal electrode layers 57, 58, and the principal surface electrodes 57a, 58a are used as terminal electrodes 53, 54. The lead-out electrodes 57b and 58b are drawn out. The main surface electrodes 57 a and 58 a have a substantially rectangular shape and are arranged so as to be positioned at a substantially central portion of the dielectric layer 12. The internal electrode layer 57 is drawn to the end face 52 c by the lead electrode 57 b and connected to the terminal electrode 53. The internal electrode layer 58 is drawn to the end face 52d by the lead electrode 58b and connected to the terminal electrode 54.

  8 to 10, the multilayer capacitor 51 includes first step absorption layers 63 and 64 in the non-formation regions R51 and R52 where the internal electrode layers 57 and 58 are not formed on the dielectric layer 12. ing. These non-formation regions R51 and R52 are regions surrounding the internal electrode layers 57 and 58, respectively. In the multilayer capacitor 51, the second step absorption layers 65 and 66 are disposed on the entire periphery of the main surface electrodes 57a and 58a, and the third step absorption layers 67 and 66 are disposed on the edges of the lead electrodes 57b and 58b on the non-formation regions R51 and R52 side. 68 respectively. The second step absorption layers 65, 66 are first portions 65a, 66a formed along the edges on the non-forming regions R51, R52 side, and connecting portions between the main surface electrodes 57a, 58a and the extraction electrodes 57b, 58b. It is comprised from the 2nd part 65b, 66b located in.

  Next, a method for manufacturing the multilayer capacitor 51 having the above-described configuration will be described. In manufacturing the multilayer capacitor 51, as in the first embodiment, first, a ceramic paste P1 and a conductive paste P2 are prepared. Thereafter, a plurality of ceramic green sheets 32 that are precursors of the dielectric layer 12 are generated.

  Subsequently, as shown in FIG. 8, for example, a conductive paste P <b> 2 is applied to a predetermined position of each ceramic green sheet 32 by screen printing, and the internal electrode layers 57 and 58 are applied on each ceramic green sheet 32. Internal electrode patterns (reference numerals are omitted) are formed. By the step of forming the internal electrode pattern, portions corresponding to the main surface electrodes 57a and 58a and portions corresponding to the extraction electrodes 57b and 58b are formed on the ceramic green sheet 32.

  Subsequently, the non-formation regions R51 and R52 where the internal electrode pattern is not formed on each ceramic green sheet 32 on which the internal electrode pattern is formed, and the entire peripheral edge of the portion corresponding to the main surface electrodes 57a and 58a of the internal electrode pattern And ceramic paste P1 is apply | coated to the edge by the side of the non-formation area | regions R51 and R52 of the part corresponding to the extraction electrodes 57b and 58b of an internal electrode pattern, for example by the screen printing method. The application of the ceramic paste P1 is performed substantially simultaneously, whereby the first step absorption layers 63 and 64, the second step absorption layers 65 and 66, and the third step absorption layers 67 and 68 are generated.

  Subsequently, a plurality of green sheets 32 on which internal electrode patterns and the like are formed are stacked in the order shown in FIG. 10 so that the portions corresponding to the adjacent main surface electrodes 57a and 58a face each other substantially over the entire surface in the stacking direction ( 9), the ceramic green sheet 32 is aligned. The ceramic green sheets 32 are stacked so that the above-described internal electrode patterns are, for example, about 10 sets in the stacking direction, and the ceramic green sheets 32 having no internal electrode pattern are stacked on the top.

  Subsequently, when the green laminate is formed by laminating the ceramic green sheets 32 as described above, the green laminate is pressurized and pressure-bonded as in the first embodiment. In this laminated body, the second step absorption layers 65 and 66 (second portions 65b and 66b) prevent the portions corresponding to the main surface electrodes 57a and 58a of the internal electrode pattern from contacting each other. Next, this green laminate is fired to obtain a capacitor body 52. When the firing or the like is finished, the conductive paste P3 is applied and baked so as to cover the portions where the lead electrodes 57b and 58b of the end faces 52c and 52d of the capacitor body 52 are exposed, and further plated. As a result, terminal electrodes 53 and 54 as shown in FIG. 7 are formed. Thus, the multilayer capacitor 51 shown in FIG. 7 is completed.

  As described above, in the method of manufacturing the multilayer capacitor 51 according to this embodiment, as in the first embodiment, in the step of forming the step absorption layer, the peripheral edge of the portion corresponding to the main surface electrodes 57a and 58a of the internal electrode pattern Second step absorption layers 65 and 66 are formed as a whole. Therefore, even if the ceramic green sheet 32 is laminated and pressure-bonded by the second step absorption layers 65 and 66 formed on the entire periphery of the portion corresponding to the main surface electrodes 57a and 58a, it corresponds to the main surface electrodes 57a and 58a. A step portion (gap) can be prevented from being formed in the portion, and stress concentration caused by the step portion can be avoided. As a result, the occurrence of internal structural defects such as cracks in the green multilayer body is suppressed, and in the multilayer capacitor 51, for example, contact and proximity between the main surface electrodes 57a and 58a can be avoided.

  Also in the multilayer capacitor 51, the step absorption layers 65 and 66 are disposed on the entire periphery of the main surface electrodes 57a and 58a of the internal electrode layers 57 and 58, as in the first embodiment. For this reason, the second step absorption layers 65 and 66 are interposed between the main surface electrodes 57a and 58a, so that the main surface electrodes 57a and 58a can be prevented from contacting or approaching each other. As a result, the multilayer capacitor 51 can be a multilayer electronic component capable of exhibiting predetermined performance while suppressing the occurrence of internal structural defects.

(Third embodiment)
Next, a configuration of the multilayer capacitor 71 according to the third embodiment and a manufacturing method thereof will be described. In the present embodiment, unlike the first and second embodiments, the multilayer capacitor 71 has a feedthrough capacitor structure, and the arrangement positions of the terminal electrodes and the shapes of the internal electrode layers are slightly different. Hereinafter, a description will be given focusing on differences from the first and second embodiments.

  First, the configuration of the multilayer capacitor 71 will be described with reference to FIGS. 11 and 12. The multilayer capacitor 71 includes a capacitor body 72, terminal electrodes 73 to 76, and internal electrode layers 77 and 78. The capacitor body 72 is formed in a substantially rectangular parallelepiped shape by laminating a plurality of dielectric layers 12, and has main surfaces 72a and 72b, end surfaces 72c and 72d, and side surfaces 72e and 72f. The terminal electrodes 73 and 74 are disposed so as to cover the end faces 72 c and 72 d of the capacitor body 72, and the terminal electrodes 75 and 76 are disposed at substantially central portions of the side surfaces 72 e and 72 f of the capacitor body 72.

  The internal electrode layers 77 and 78 are sequentially stacked in the capacitor body 2 with at least one dielectric layer 12 interposed therebetween (see FIG. 14). The internal electrode layers 77 and 78 form main surface electrodes 77a and 78a that form a capacitance portion facing the other adjacent internal electrode layers 77 and 78, and the main surface electrodes 77a and 78a as terminal electrodes 73 to 76. The lead-out electrodes 77b and 78b are drawn out. Main surface electrodes 77a and 78a have a substantially rectangular shape, and are arranged so as to be located at a substantially central portion of dielectric layer 12. The internal electrode layer 77 is drawn out to the end faces 72c and 72d by a pair of lead electrodes 77b and connected to the terminal electrodes 73 and 74. The internal electrode layer 78 is drawn out to the side faces 72e and 72f by a pair of lead electrodes 78b and is connected to the terminal electrodes 75 and 76.

  The multilayer capacitor 71 includes first step absorption layers 83 and 84 in the non-formation regions R71 and R72 where the internal electrode layers 77 and 78 are not formed on the dielectric layer 12, as shown in FIGS. ing. The pair of non-formation regions R71 and R72 are regions that sandwich the internal electrode layers 77 and 78 therebetween. The multilayer capacitor 71 has second step absorption layers 85 and 86 on the entire periphery of the main surface electrodes 77a and 78a, and third step absorption layers 87 and 86 on the edges of the lead electrodes 77b and 78b on the non-formation regions R71 and R72 side. 88 respectively. The second step absorption layers 85, 86 are first portions 85a, 86a formed along the edges on the non-forming regions R71, R72 side, and connecting portions between the main surface electrodes 77a, 78a and the extraction electrodes 77b, 78b. The second portions 85b and 86b are located on the left side.

  Next, a method for manufacturing the multilayer capacitor 71 having the above-described configuration will be described. In manufacturing the multilayer capacitor 71, as in the first and second embodiments, first, a ceramic paste P1 and a conductive paste P2 are prepared. Thereafter, a plurality of ceramic green sheets 32 that are precursors of the dielectric layer 12 are generated.

  Subsequently, the conductive paste P2 is applied to a predetermined position of each ceramic green sheet 32 by, for example, screen printing, as shown in FIG. 12, and the internal electrode layers 77 and 78 are applied on each ceramic green sheet 32. Internal electrode patterns (reference numerals are omitted) are formed. By the step of forming the internal electrode pattern, portions corresponding to the main surface electrodes 77a and 78a and portions corresponding to the lead electrodes 77b and 78b are formed on the ceramic green sheet 32.

  Subsequently, the non-formation regions R71 and R72 where the internal electrode pattern is not formed on each ceramic green sheet 32 on which the internal electrode pattern is formed, and the entire peripheral edge of the portion corresponding to the main surface electrodes 77a and 78a of the internal electrode pattern The ceramic paste P1 is applied to the edges on the non-forming regions R71, R72 side of the portions corresponding to the extraction electrodes 77b, 78b of the internal electrode pattern. The application of the ceramic paste P1 is performed substantially simultaneously, whereby the first step absorption layers 83 and 84, the second step absorption layers 85 and 86, and the third step absorption layers 87 and 88 are generated.

  Subsequently, a plurality of green sheets 32 on which internal electrode patterns and the like are formed are stacked in the order shown in FIG. 14 so that portions corresponding to adjacent main surface electrodes 77a and 78a face each other in substantially the entire surface in the stacking direction ( 13), the ceramic green sheet 32 is aligned. The ceramic green sheets 32 are stacked so that the above-described internal electrode patterns are, for example, about 10 sets in the stacking direction, and the ceramic green sheets 32 having no internal electrode pattern are stacked on the top.

  Subsequently, when the green laminate is formed by laminating the ceramic green sheets 32 as described above, the green laminate is pressurized and pressure-bonded as in the first and second embodiments. In this laminate, the second step absorption layers 85 and 86 (second portions 85b and 86b) prevent the portions corresponding to the principal surface electrodes 77a and 78a of the internal electrode pattern from contacting each other. Next, this green laminate is fired to obtain a capacitor body 72. Then, after the firing or the like is finished, the conductive paste P3 is applied and baked so as to cover the portions where the end electrodes 72c and 72d of the capacitor body 72 and the lead electrodes 77b and 78b of the side surfaces 72e and 72f are exposed, Further, terminal electrodes 73 to 76 as shown in FIG. 11 are formed by plating. Thus, the multilayer capacitor 71 shown in FIG. 11 is completed.

  As described above, in the method of manufacturing the multilayer capacitor 71 according to this embodiment, as in the first and second embodiments, in the step of forming the step absorption layer, it corresponds to the main surface electrodes 77a and 78a of the internal electrode pattern. Second step absorption layers 85 and 86 are formed on the entire periphery of the portion. For this reason, even if the ceramic green sheet 32 is laminated and pressure-bonded by the second step absorption layers 85 and 86 formed on the entire periphery of the portion corresponding to the main surface electrodes 77a and 78a, it corresponds to the main surface electrodes 77a and 78a. A step portion can be prevented from being formed in the portion, and stress concentration caused by the step portion can be avoided. As a result, the occurrence of internal structural defects such as cracks in the green multilayer body is suppressed, and in the multilayer capacitor 71, for example, contact and proximity between the principal surface electrodes 77a and 78a can be avoided.

  In the multilayer capacitor 71 as well, the step absorption layers 85 and 86 are disposed on the entire periphery of the main surface electrodes 77a and 78a of the internal electrode layers 77 and 78, as in the first and second embodiments. For this reason, the second step absorption layers 85 and 86 are interposed between the main surface electrodes 77a and 78a, so that the main surface electrodes 77a and 78a can be prevented from contacting or approaching each other. As a result, the multilayer capacitor 71 can be a multilayer electronic component capable of exhibiting predetermined performance while suppressing the occurrence of internal structural defects.

(Fourth embodiment)
Next, a configuration of the multilayer capacitor 91 according to the fourth embodiment and a manufacturing method thereof will be described. In the present embodiment, unlike the first to third embodiments, the multilayer capacitor 91 has an array structure, and the arrangement positions of the terminal electrodes and the shapes of the internal electrode layers are slightly different. Hereinafter, a description will be given focusing on differences from the first to third embodiments.

  First, the configuration of the multilayer capacitor 91 will be described with reference to FIGS. 15 and 16. The multilayer capacitor 91 includes a capacitor body 92, terminal electrodes 93 to 96, and internal electrode layers 97 and 98. The capacitor body 92 is formed in a substantially rectangular parallelepiped shape by laminating a plurality of dielectric layers 12, and has main surfaces 92a and 92b, end surfaces 92c and 92d, and side surfaces 92e and 92f. The terminal electrodes 93 and 94 are spaced apart in parallel with the side surface 92e of the capacitor body 92, and the terminal electrodes 95 and 96 are spaced apart in parallel with the side surface 92f of the capacitor body 92.

  The internal electrode layers 97 and 98 are sequentially stacked in the capacitor body 2 with at least one dielectric layer 12 interposed therebetween (see FIG. 18). The internal electrode layers 97, 98 are principal surface electrodes 97a, 98a that form a capacitance portion facing the other adjacent internal electrode layers 97, 98, and the principal surface electrodes 97a, 98a are terminal electrodes 93-96. The lead-out electrodes 97b and 98b are drawn out. The main surface electrodes 97a and 98a have a substantially rectangular shape, and two main surface electrodes 97a and 98a are arranged so as to be positioned at a substantially central portion of the dielectric layer 12 in the opposing direction of the side surfaces 92e and 92f. The pair of internal electrode layers 97 are drawn to the side surface 92 e by the lead electrode 97 b and connected to the terminal electrodes 93 and 94. The pair of internal electrode layers 98 are drawn to the side surface 92 f by the lead electrode 98 b and connected to the terminal electrodes 95 and 96.

  The multilayer capacitor 91 includes first step absorption layers 103 and 104 in the non-formation regions R91 and R92 where the internal electrode layers 97 and 98 are not formed on the dielectric layer 12, as shown in FIGS. ing. The non-formation regions R91 and R92 are regions that surround the internal electrode layers 97 and 98. The multilayer capacitor 91 includes the second step absorption layers 105 and 106 on the entire periphery of the main surface electrodes 97a and 98a, and the third step absorption layer 107 and the edge on the non-formation regions R91 and R92 side of the extraction electrodes 97b and 98b. 108 are provided. The second step absorption layers 105, 106 are first portions 105a, 106a formed along the edges on the non-forming regions R91, R92 side, and connecting portions between the main surface electrodes 97a, 98a and the extraction electrodes 97b, 98b. It is comprised from the 2nd part 105b and 106b located in.

  Next, a method for manufacturing the multilayer capacitor 91 having the above-described configuration will be described. In manufacturing the multilayer capacitor 91, as in the first to third embodiments, first, a ceramic paste P1 and a conductive paste P2 are prepared. Thereafter, a plurality of ceramic green sheets 32 that are precursors of the dielectric layer 12 are generated.

  Subsequently, for example, by screen printing, as shown in FIG. 16, a conductive paste P2 is applied to a predetermined position of each ceramic green sheet 32, and two internal electrode layers 97 or 2 are applied on each ceramic green sheet 32. Internal electrode patterns (reference numerals are omitted) corresponding to the two internal electrode layers 98 are formed. By the step of forming the internal electrode pattern, portions corresponding to the main surface electrodes 97a and 98a and portions corresponding to the extraction electrodes 97b and 98b are formed on the ceramic green sheet 32.

  Subsequently, the non-formation regions R91 and R92 where the internal electrode pattern is not formed on each ceramic green sheet 32 on which the internal electrode pattern is formed, and the entire peripheral edge of the portion corresponding to the main surface electrodes 97a and 98a of the internal electrode pattern Then, the ceramic paste P1 is applied to the edges on the non-forming regions R91, R92 side of the portions corresponding to the extraction electrodes 97b, 98b of the internal electrode pattern. Thus, the first step absorption layers 103 and 104, the second step absorption layers 105 and 106, and the third step absorption layers 107 and 108 are generated.

  Subsequently, a plurality of green sheets 32 on which internal electrode patterns and the like are formed are stacked in the order shown in FIG. 18 so that portions corresponding to adjacent main surface electrodes 97a and 98a face each other in substantially the entire surface in the stacking direction ( 17), the ceramic green sheet 32 is aligned. The ceramic green sheets 32 are stacked so that the above-described internal electrode patterns are, for example, about 10 sets in the stacking direction, and the ceramic green sheets 32 having no internal electrode pattern are stacked on the top.

  Subsequently, when the green laminate is formed by laminating the ceramic green sheets 32 as described above, the green laminate is pressurized and pressure-bonded as in the first to third embodiments. In this laminate, the second step absorption layers 105 and 106 (second portions 105b and 106b) prevent the portions corresponding to the main surface electrodes 97a and 98a of the internal electrode pattern from contacting each other. Next, this green laminate is fired to obtain a capacitor body 92. When the firing or the like is completed, the conductive paste P3 is applied and baked so as to cover the portions where the lead electrodes 97b and 98b of the side surfaces 92e and 92f of the capacitor body 92 are exposed, and further plated. As a result, terminal electrodes 93 to 96 as shown in FIG. 15 are formed. Thus, the multilayer capacitor 91 shown in FIG. 15 is completed.

  As described above, in the method of manufacturing the multilayer capacitor 91 according to this embodiment, as in the first to third embodiments, in the step of forming the step absorption layer, it corresponds to the main surface electrodes 97a and 98a of the internal electrode pattern. Second step absorption layers 105 and 106 are formed on the entire periphery of the portion. For this reason, even if the ceramic green sheet 32 is laminated and pressure-bonded by the second step absorption layers 105 and 106 formed on the entire periphery of the portion corresponding to the main surface electrodes 97a and 98a, it corresponds to the main surface electrodes 97a and 98a. A step portion can be prevented from being formed in the portion, and stress concentration caused by the step portion can be avoided. As a result, the occurrence of internal structural defects such as cracks in the green multilayer body is suppressed, and in the multilayer capacitor 91, for example, contact and proximity between the main surface electrodes 97a and 98a can be avoided.

  In the multilayer capacitor 91 as well, the step absorption layers 105 and 106 are disposed on the entire periphery of the main surface electrodes 97a and 98a of the internal electrode layers 97 and 98, as in the first to third embodiments. For this reason, the second step absorption layers 105 and 106 are interposed between the main surface electrodes 97a and 98a, and the main surface electrodes 97a and 98a can be prevented from contacting or approaching each other. As a result, the multilayer capacitor 91 can be a multilayer electronic component capable of exhibiting predetermined performance while suppressing the occurrence of internal structural defects.

  In the multilayer capacitor 91 described above, each of the internal electrode layers 97 and 98 is drawn out to the same side surface 92e or 92f, but is disposed on the same dielectric layer 12 as shown in FIG. The two internal electrode layers 97 or 98 may be drawn out to different side surfaces 92e and 92f, respectively. Even in this case, as shown in FIG. 20, the second step absorption layers 105 and 106 (second portions 105b and 106b) formed on the entire periphery of the portions corresponding to the main surface electrodes 97a and 98a, It is possible to prevent the formation of a stepped portion in the portion corresponding to the main surface electrodes 97a and 98a, and to avoid stress concentration caused by the stepped portion. As a result, generation of internal structural defects such as cracks in the green laminate can be suppressed.

(Fifth embodiment)
Next, a configuration of the multilayer capacitor 111 according to the fifth embodiment and a manufacturing method thereof will be described. In the present embodiment, unlike the first to fourth embodiments, the multilayer capacitor 111 is provided with an ESR (equivalent series resistance) control unit. ing. Hereinafter, a description will be given focusing on differences from the first to fourth embodiments.

  First, the configuration of the multilayer capacitor 111 will be described with reference to FIGS. 21 and 22. The multilayer capacitor 111 includes a capacitor body 112, terminal electrodes 113 and 114, external connection conductors 115 and 116, and internal electrode layers 117 to 120. The capacitor body 112 is formed in a substantially rectangular parallelepiped shape by laminating a plurality of dielectric layers 12, and has main surfaces 112a and 112b, end surfaces 112c and 112d, and side surfaces 112e and 112f. The terminal electrodes 113 and 114 are disposed so as to cover the end surfaces 112c and 112d of the capacitor body 112, and the external connection conductors 115 and 116 are disposed at substantially the center of the side surfaces 112e and 112f of the capacitor body 112. The external connection conductor 115 is a conductor for connecting the internal electrode layers 117 and 119, and the external connection conductor 116 is a conductor for connecting the internal electrode layers 118 and 120.

  The internal electrode layers 117 to 120 are sequentially stacked in the capacitor body 112 with at least one dielectric layer 12 interposed therebetween (see FIGS. 24 and 25). The internal electrode layers 117 to 120 have main surface electrodes 117a to 120a that form a capacitance portion facing the other adjacent internal electrode layers 117 to 120, and main surface electrodes 117a and 118a as terminal electrodes 113 and 114, respectively. Lead electrodes 117b and 118b that lead out toward the outside, and lead electrodes 117c to 120c that lead out the main surface electrodes 117a to 120a toward the external connection conductors 115 and 116, respectively. Main surface electrodes 117 a to 120 a have a substantially rectangular shape, and are arranged so as to be located at a substantially central portion of dielectric layer 12. In the multilayer capacitor 111 according to the present embodiment, a desired ESR value is obtained by adjusting the number of laminated internal electrode layers 117 and 118, the laminated position of the internal electrode layers 117 to 120, and the like. That is, the internal electrode layers 117, 118 and the like function as an ESR control unit.

  The internal electrode layer 117 is drawn to the end face 112d by the lead electrode 117b and connected to the terminal electrode 114, and is drawn to the side face 112e by the lead electrode 117c and connected to the external connection conductor 115. The internal electrode layer 118 is drawn to the end face 112c by the lead electrode 118b and connected to the terminal electrode 113, and is drawn to the side face 112f by the lead electrode 118c and connected to the external connection conductor 116. The internal electrode layer 119 is extracted to the side surface 112e by the extraction electrode 119c and connected to the external connection conductor 115. The internal electrode layer 120 is drawn to the side surface 112f by the lead electrode 120c and connected to the external connection conductor 116.

  In addition, as shown in FIGS. 22 to 25, the multilayer capacitor 111 includes first step absorption layers 123 to 126 in the non-formation regions R111 to R114 where the internal electrode layers 117 to 120 are not formed on the dielectric layer 12. ing. The non-formation regions R111 to R114 are regions that surround the internal electrode layers 117 to 120. The multilayer capacitor 111 includes second step absorption layers 127 to 130 on the entire periphery of the main surface electrodes 117a to 120a, and the second step absorption layers 127 to 130 on the edges of the extraction electrodes 117b and 118b and the extraction electrodes 117c to 120c on the non-forming region R111 to R114 side. Three step absorption layers 133 to 136 are provided. The second step absorption layers 127 to 130 include first portions 127a to 130a formed along the edges on the non-forming regions R111 to R114 side, main surface electrodes 117a to 120a, extraction electrodes 117b and 118b, and extraction electrodes 117c. It is comprised from 2nd part 127b-130b located in a connection part with -120c.

  Next, a method for manufacturing the multilayer capacitor 111 having the above-described configuration will be described. In manufacturing the multilayer capacitor 111, as in the first to fourth embodiments, first, a ceramic paste P1 and a conductive paste P2 are prepared. Thereafter, a plurality of ceramic green sheets 32 that are precursors of the dielectric layer 12 are generated.

  Subsequently, as shown in FIG. 22, for example, by applying a conductive paste P <b> 2 to a predetermined position of each ceramic green sheet 32 by screen printing, and corresponding to the internal electrode layers 117 to 120 on each ceramic green sheet 32. Internal electrode patterns (reference numerals are omitted) are formed. By the step of forming the internal electrode pattern, portions corresponding to the main surface electrodes 117a to 120a and portions corresponding to the extraction electrodes 117b and 118b and the extraction electrodes 117c to 120c are formed on the ceramic green sheet 32.

  Subsequently, the non-formation regions R111 to R114 where the internal electrode pattern is not formed on each ceramic green sheet 32 on which the internal electrode pattern described above is formed, and the entire periphery of the portion corresponding to the main surface electrodes 117a to 120a of the internal electrode pattern The ceramic paste P1 is applied to the edges on the non-forming regions R111 to R114 side of the portions corresponding to the extraction electrodes 117b and 118b and the extraction electrodes 117c to 120c of the internal electrode pattern. Thereby, the 1st level | step difference absorption layers 123-126, the 2nd level | step difference absorption layers 127-130, and the 3rd level | step difference absorption layers 133-136 are produced | generated.

  Subsequently, a plurality of green sheets 32 on which internal electrode patterns and the like are formed are stacked in the order shown in FIGS. 24 and 25 so that the portions corresponding to the adjacent main surface electrodes 117a to 120a face each other on substantially the entire surface in the stacking direction. (Refer to FIG. 23), the ceramic green sheet 32 is aligned. The above-mentioned internal electrode patterns are laminated with ceramic green sheets 32 so that there are, for example, about 2 to 5 sets in the laminating direction, and the ceramic green sheets 32 having no internal electrode pattern are laminated on the top. .

  Subsequently, when the green laminate is formed by laminating the ceramic green sheets 32 as described above, the green laminate is pressurized and pressure-bonded as in the first to fourth embodiments. In this laminate, the second step absorption layers 127 to 130 (second portions 127b to 130b) prevent the portions corresponding to the principal surface electrodes 117a to 120a of the internal electrode pattern from contacting each other. Next, this green laminate is fired to obtain a capacitor body 112. When the firing or the like is finished, the conductive paste P3 is applied and baked on predetermined portions of the end surfaces 112c and 112d and the side surfaces 112e and 112f of the capacitor body 112, and further plated, as shown in FIG. Such terminal electrodes 113 and 114 and external connection conductors 115 and 116 are formed. Thus, the multilayer capacitor 111 shown in FIG. 21 is completed.

  As described above, in the method of manufacturing the multilayer capacitor 111 according to this embodiment, as in the first to fourth embodiments, in the step of forming the step absorption layer, it corresponds to the main surface electrodes 117a to 120a of the internal electrode pattern. Second step absorption layers 127 to 130 are formed on the entire periphery of the portion. Therefore, even if the ceramic green sheet 32 is laminated and pressure-bonded by the second step absorption layers 127 to 130 formed on the entire periphery of the portion corresponding to the main surface electrodes 117a to 120a, it corresponds to the main surface electrodes 117a to 120a. A step portion can be prevented from being formed in the portion, and stress concentration caused by the step portion can be avoided. As a result, the occurrence of internal structural defects such as cracks in the green multilayer body is suppressed, and in the multilayer capacitor 111, for example, contact and proximity between the principal surface electrodes 117a to 120a can be avoided.

  In the multilayer capacitor 111 as well, step absorption layers 127 to 130 are disposed on the entire periphery of the main surface electrodes 117a to 120a of the internal electrode layers 117 to 120, as in the first to fourth embodiments. For this reason, the second step absorption layers 127 to 130 are interposed between the main surface electrodes 117a to 120a, and the main surface electrodes 117a to 120a can be prevented from contacting or coming close to each other. As a result, the multilayer capacitor 111 can be a multilayer electronic component capable of exhibiting predetermined performance while suppressing the occurrence of internal structural defects.

  The preferred embodiments of the present invention have been described in detail above, but the present invention is not limited to the above-described embodiments, and various modifications are possible. For example, in the above embodiment, 2 to 5 or 10 sets of internal electrode layers are stacked to form a capacitor body. However, the number of stacked layers (number of sets) is not limited to these, and the number of other stacked layers Of course, it may be (number of sets).

  In the above embodiment, the manufacturing method of forming the first step absorption layer, the second step absorption layer, and the third step absorption layer substantially simultaneously has been described, but each step absorption layer may be manufactured separately, The first and second step absorption layers may be formed substantially simultaneously, the first and third step absorption layers may be formed substantially simultaneously, or the second and third step absorption layers may be formed substantially simultaneously. In the above embodiment, the method of manufacturing the dielectric layer and the step absorption layer from the same dielectric material has been described. However, the step absorption layer may be formed from a dielectric material different from the dielectric layer. .

  In the above-described embodiment, the multilayer capacitor having two or four types of internal electrode layers has been described. However, the above-described embodiment is applied to the multilayer capacitor having more than four types of internal electrode layers. Of course, it can be applied. When the internal electrode layer is composed of more than four types, the stepped portion will be further dispersed in the plane direction of the internal electrode layer, and thereby, every other layer in the stacking direction. As a result, stepped portions are generated, and as a result, stress is further concentrated on these stepped portions at the time of laminate crimping, and internal structural defects are likely to occur. However, if the multilayer capacitor has the configuration of the present embodiment, different types of internal electrodes are used. Even when the number of layers is increased, it is possible to prevent the occurrence of a step portion that may occur in this way, and to suppress the occurrence of internal structural defects. In the above embodiment, the multilayer capacitor is described as an example of the multilayer electronic component. However, the present embodiment may be applied to other multilayer electronic components.

1, 51, 71, 91, 111 ... multilayer feedthrough capacitor, 2, 52, 72, 92, 112 ... capacitor body, 3-6, 53, 54, 73-76, 93-96, 113, 114 ... terminal electrode 7-10, 57, 58, 77, 78, 97, 98, 117-120 ... internal electrodes, 7a-10a, 57a, 58a, 77a, 78a, 97a, 98a, 117a-120a ... main surface electrodes, 7b- 10b, 57b, 58b, 77b, 78b, 97b, 98b, 117b, 118b, 117c to 120c ... extraction electrode, 13 to 16, 63, 64, 83, 84, 103, 104, 123 to 126 ... first step absorption layer 17-20, 65, 66, 85, 86, 105, 106, 127-130 ... second step absorption layer, 17a-20a, 65a, 66a, 85a, 86a, 105a 106a, 127a-130a ... first part, 17b-20b, 65b, 66b, 85b, 86b, 105b, 106b, 127b-130b ... second part, 23-26, 67, 68, 87, 88, 107, 108, 133-136 ... third step absorption layer.

Claims (10)

Forming an internal electrode pattern including at least a main surface electrode portion and an extraction electrode portion on the ceramic green sheet;
Forming a step-absorbing layer on a non-formation region where the internal electrode pattern is not formed on the ceramic green sheet and the entire periphery of the main surface electrode portion of the internal electrode pattern;
The internal electrode pattern and said the ceramic green sheet and the step absorption layer is formed by laminating and pressure bonding, e Bei forming a green laminate, and,
In the step of forming the step absorption layer, the step absorption layer is formed at a connection portion between the main surface electrode portion and the extraction electrode portion . In the step of forming the pre-Symbol step absorption layer, manufacturing method of a multilayer electronic component according to claim 1, characterized by forming the step absorption layer to the lead electrode portion of the internal electrode pattern.   3. The method for manufacturing a laminated electronic component according to claim 2, wherein in the step of forming the step absorption layer, the step absorption layer is formed at an edge of the extraction electrode portion on the non-formation region side.   3. The method for manufacturing a laminated electronic component according to claim 2, wherein in the step of forming the step absorption layer, the step absorption layer is formed over the entire extraction electrode portion.   5. The step absorption layer is formed in the step of forming the step absorption layer substantially simultaneously with the entire periphery of the main surface electrode portion and the extraction electrode portion. The manufacturing method of the multilayer electronic component as described in any one of.   6. The step absorbing layer is formed in the step of forming the step absorbing layer substantially simultaneously with the non-forming region and the entire periphery of the main surface electrode portion. The manufacturing method of the multilayer electronic component as described in any one of. An element body in which a plurality of dielectric layers are laminated;
An internal electrode layer disposed in the element body so as to be sandwiched between the dielectric layers and including at least a main surface electrode and an extraction electrode ;
E Bei and a step absorption layer disposed on the entire the peripheral edge of the main surface electrodes of the internal electrode layer is not disposed non-formation region and the internal electrode layer by the dielectric layer,
The stepped absorption layer is formed at a connection portion between the main surface electrode and the extraction electrode . Prior Symbol step absorption layer, laminated electronic component according to claim 7, characterized in that it is further disposed on the lead electrodes. The internal electrode layers are at least four types,
The multilayer electronic component according to claim 7, further comprising a terminal electrode connected to each of the four or more types of internal electrodes. The connecting portion between the main surface electrode and the extraction electrode, the internal electrode layer including the main surface electrode and the extraction electrode, and a peripheral portion of another internal electrode layer adjacent in the stacking direction are in the stacking direction. The multilayer electronic component according to claim 7, wherein the multilayer electronic component is bent in the same direction.

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