JP5150933B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly, to a semiconductor device including a plurality of readout circuits that output data read from memory cells to a common signal line.

  MRAM (Magnetic Random Access Memory) is a general term for a solid-state memory that stores data using the magnetization direction of a ferromagnetic material. In the MRAM, “1” and “0” correspond to whether the magnetization direction of the ferromagnetic material constituting the memory cell is parallel or antiparallel to a certain reference direction. Further, a GMR element using a giant magnetoresistance effect (Giant Magneto Resistive effect: GMR (Giant Magneto Resistive) effect) and a magnetic tunnel effect (Tunneling Magneto Resistance effect: TMR (Tunneling Magneto) An MTJ (Magnetic Tunneling Junction) element or the like that utilizes the (resistive) effect) is used in the MRAM.

  The MTJ element is composed of a three-layer film of ferromagnetic layer / insulating layer / ferromagnetic layer, and a tunnel current flows through the insulating layer. The resistance value to the tunnel current changes according to the relationship between the magnetization directions of the two ferromagnetic layers.

In a semiconductor memory such as an MRAM, a sense amplifier is used to read data stored in a memory cell. For example, FIG. 26.5.2 of Non-Patent Document 1 discloses a configuration in which a read operation is performed by amplifying a read signal of data stored in a memory cell using a latch type sense amplifier.
T. Kawahara et al. "ISSCC 2007 26.5 2Mb Spin-Transfer Torque RAM (SPRAM) with Bit-by-Bit Bidirectional Current Write and Parallelizing-Direction Current Read" 2007 IEEE International Solid-State Circuits Conference

  In the MRAM described in Non-Patent Document 1, a plurality of memory cell blocks are provided, a sense amplifier is provided for each memory cell block, and outputs of these sense amplifiers are connected to a common global read line.

  However, in such a configuration, in order to prevent the output signals of the respective sense amplifiers from colliding on the global read line, it is necessary that the periods during which the outputs of the respective sense amplifiers are enabled do not overlap. That is, since it becomes necessary to enable the outputs of the sense amplifiers at intervals, the data read time increases.

  Therefore, an object of the present invention is to provide a semiconductor device capable of shortening a data reading time.

  In summary, a semiconductor device according to an embodiment of the present invention, in summary, outputs data having the same logic level as the data on the global read line when the corresponding sense amplifier is not activated. When the data is output to the global read line and the corresponding sense amplifier is activated, the data based on the signal received from the sense amplifier is output to the global read line.

  According to the embodiment of the present invention, even when the output enable periods of the output circuits overlap, it is possible to prevent the output data of the output circuits from colliding with each other. Therefore, the data reading time can be shortened.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

  FIG. 1 is a schematic block diagram showing an overall configuration of a semiconductor device according to an embodiment of the present invention.

  Referring to FIG. 1, a semiconductor device 101 is, for example, an MRAM, and includes a control circuit 5 and a memory array 10 including MTJ memory cells MC (hereinafter also simply referred to as memory cells MC) arranged in a matrix. It includes a row selection circuit 20, a column decoder 25, a read / write control circuit 30, a plurality of word lines WL, a plurality of bit lines BL, and a plurality of source lines SL.

  Hereinafter, the rows and columns of the plurality of memory cells MC that are integrated and arranged in a matrix included in the memory array 10 are also referred to as memory cell rows and memory cell columns, respectively.

  The row selection circuit 20 performs a memory cell row selection operation in the memory array 10 to be accessed based on the row address RA included in the address signal ADD. The column decoder 25 performs a memory cell column selection operation in the memory array 10 to be accessed based on the column address CA included in the address signal ADD.

  The read / write control circuit 30 writes data to the memory cell MC based on the input data DIN. The read / write control circuit 30 reads data from the memory cell MC and outputs it as read data DOUT to the outside.

  The control circuit 5 controls the overall operation of the semiconductor device 101 in response to the control signal CMD.

  Word line WL and source line SL are provided corresponding to the memory cell rows, respectively. Bit line BL is provided corresponding to the memory cell column. FIG. 1 representatively shows one memory cell MC, and one word line WL is typically shown corresponding to the memory cell row of the memory cell MC. Further, one bit line BL is representatively shown corresponding to the memory cell column of the memory cells MC.

  FIG. 2 is a diagram showing in detail the configuration of the memory array 10 and the read / write control circuit 30 according to the embodiment of the present invention.

  Referring to FIG. 2, memory array 10 is divided into a plurality of memory array blocks MLAB including a plurality of memory cells MC arranged in a matrix. Memory array block MLAB includes a plurality of dummy memory cells DMC provided corresponding to the memory cell rows.

  In each memory array block MLAB, the word line WL and the column selection line SCL respectively corresponding to the selected memory cell row and the selected memory cell column are driven to the selected state, so that the memory cell MC to be read data passes through the bit line BL. Apply current.

  Further, when the word line WL corresponding to the selected memory cell row and the column selection line DSCL are driven to the selected state, the dummy memory cell DMC corresponding to the memory cell MC from which data is to be read flows through the dummy bit line DBL. Shed.

  The data read circuit RDC coupled to the memory array block MLAB to which the memory cell MC to which data is read belongs compares the current flowing through the corresponding bit line BL with the current flowing through the corresponding dummy bit line DBL. Based on the comparison result, the data stored in the memory cell MC to be read is read and output to the global read line GRIO.

  FIG. 3 is a diagram showing in detail the configuration of the read circuit RDC according to the embodiment of the present invention. FIG. 3 representatively shows one memory cell MC in each of two memory array blocks MLAB and a circuit corresponding thereto.

  Referring to FIG. 3, read circuit RDC1 includes a sense amplifier SA1 and an output circuit OUTC1. The read circuit RDC2 includes a sense amplifier SA2 and an output circuit OUTC2.

  Hereinafter, each of the sense amplifiers SA1 and SA2 may be referred to as a sense amplifier SA, and each of the output circuits OUTC1 and OUTC2 may be referred to as an output circuit OUTC.

  Sense amplifier SA1 includes N channel MOS transistors M1 to M4 and M12, and P channel MOS transistors M5 to M11. Output circuit OUTC1 includes NOT gates G1 and G2, OR gate G3, AND gate G4, NAND gate G5, AND gate G6, P-channel MOS transistor M13, and N-channel MOS transistor M14.

  Sense amplifier SA1 is a cross-coupled latch type sense amplifier in which N channel MOS transistor M1 and P channel MOS transistor M5, N channel MOS transistor M2 and P channel MOS transistor M6 are connected to each other at their gates and drains. is there.

  The drain of N channel MOS transistor M1, the drains of P channel MOS transistors M5 and M7, the source of P channel MOS transistor M9, the gate of N channel MOS transistor M2, and the gate of P channel MOS transistor M6 are at node NT. It is connected. The drain of N channel MOS transistor M2, the drains of P channel MOS transistors M6, M8 and M9, the gate of N channel MOS transistor M1, and the gate of P channel MOS transistor M5 are connected to node NB. The source of the N channel MOS transistor M1 and the drain of the N channel MOS transistor M3 are connected. The source of N channel MOS transistor M2 and the drain of N channel MOS transistor M4 are connected. The sources of N channel MOS transistors M3 and M4 are connected to the drain of N channel MOS transistor M12. The source of N channel MOS transistor M12 and the gates of P channel MOS transistors M10 and M11 are coupled to a ground voltage source. The sources of P channel MOS transistors M5-M8 and the sources of P channel MOS transistors M10 and M11 are coupled to a positive voltage source. The drain of P channel MOS transistor M10 and the gate of N channel MOS transistor M3 are connected to bit line BL1. The drain of P channel MOS transistor M11 and the gate of N channel MOS transistor M4 are connected to dummy bit line DBL1.

  Control signal SAE1 is applied to the gate of N channel MOS transistor M12. Control signal PC1 is applied to the gates of P-channel MOS transistors M7 to M9.

  In the output circuit OUTC1, the NOT gate G1 inverts the logic level of the sense signal SALT1 and outputs it. The NOT gate G2 inverts the logic level of the control signal YSK1 and outputs it. OR gate G3 outputs a signal indicating the logical sum of the signal received from NOT gate G1 and the signal on global read line GRIO. NAND gate G5 outputs a signal obtained by inverting the logical product of control signal YSK1 and the signal received from OR gate G3 to the gate of P-channel MOS transistor M13. The AND gate G4 outputs a signal indicating a logical product of the sense signal SALB1 and a signal on the global read line GRIO. AND gate G6 provides a signal indicating the logical product of a signal obtained by inverting the logic level of the signal received from AND gate G4 and a signal obtained by inverting the logic level of the signal received from NOT gate G2, to the gate of P channel MOS transistor M14. Output. The source of P-channel MOS transistor M13 is coupled to the positive voltage source, and the drain is connected to global read line GRIO. The source of N channel MOS transistor M14 is coupled to the ground voltage source, and the drain is connected to global read line GRIO.

  Memory cell MC1 includes an MTJ element (variable magnetoresistive element) S and an access transistor TRS connected in series between bit line BL1 and a ground voltage source. Dummy memory cell DMC1 includes an MTJ element SD and an access transistor TRSD connected in series between dummy bit line DBL1 and the ground voltage source.

  When the access transistor TRS is turned on when reading data, the memory cell MC1 passes a current based on the stored data through the bit line BL1. That is, the potential of the bit line BL1 is a potential based on the resistance value of the MTJ element S. The dummy memory cell DMC1 causes a reference current to flow through the dummy bit line DBL1 when the access transistor TRSD is turned on during data reading. That is, the potential of the dummy bit line DBL1 is a potential based on the resistance value of the MTJ element SD.

  Sense amplifier SA1 has an output node pair, that is, nodes NT and NB. When activated, sense amplifier SA1 amplifies the difference between the potential of bit line BL1 and the potential of dummy bit line DBL1, and outputs complementary signals indicating the amplification results to nodes NT and NB as sense signals SALT1 and SALB1, respectively. On the other hand, when inactive, sense amplifier SA1 outputs a logic high level signal as sense signals SALT1 and SALB1 to nodes NT and NB, respectively.

  When output circuit OUTC1 receives sense signals SALT1 and SALB1 which are complementary signals from sense amplifier SA via nodes NT and NB, output circuit OUTC1 outputs data having a logic level based on the complementary signals to global read line GRIO. On the other hand, when output circuit OUTC receives sense signals SALT1 and SALB1 having a logic high level from sense amplifier SA1 via nodes NT and NB, data having the same logic level as global read line GRIO, that is, global read line Data having the same logic level as the data on GRIO is output to global read line GRIO.

  Since the configuration of the readout circuit RDC2 is the same as that of the readout circuit RDC1, detailed description thereof will not be repeated here. The configurations of memory cell MC2 and dummy memory cell DMC2 are the same as those of memory cell MC1 and dummy memory cell DMC1, respectively. Therefore, detailed description thereof will not be repeated here.

  Next, a data read operation of the semiconductor device according to the embodiment of the present invention will be described. Here, a case will be described in which the storage data of the memory cell MC1 is first read and then the storage data of the memory cell MC2 is read.

  FIG. 4 is a time chart showing the data read operation of the semiconductor device according to the embodiment of the present invention. Each control signal shown in FIG. 4 is generated by the control circuit 5, for example.

  Referring to FIG. 4, first, control signal PC1 is set to a logic low level. Then, P channel MOS transistors M7 to M9 in sense amplifier SA1 are turned on, and nodes NT and NB are precharged to a logic high level. Further, the control signal SAE1 is set to a logic low level. At this time, the sense amplifier SA1 is deactivated. Further, the control signal YSK1 is set to a logic low level. At this time, the output of the output circuit OUTC1 is in a high impedance state, that is, the output circuit OUTC1 stops outputting data to the global read line GRIO.

  Similarly, the control signal PC2 is set to a logic low level. Then, P channel MOS transistors M7 to M9 in sense amplifier SA2 are turned on, and nodes NT and NB are precharged to a logic high level. Further, the control signal SAE2 is set to a logic low level. At this time, the sense amplifier SA2 is deactivated. Further, the control signal YSK2 is set to a logic low level. At this time, the output of the output circuit OUTC2 is in a high impedance state, that is, the output circuit OUTC2 stops outputting data to the global read line GRIO.

  Next, the control signals PC1 and SAE1 are set to a logic high level. Then, sense amplifier SA1 is activated, the difference between the potential of bit line BL1 and the potential of dummy bit line DBL1 is amplified, and complementary signals indicating the amplification results are output to nodes NT and NB as sense signals SALT1 and SALB1, respectively. . Here, the sense signal SALT1 is at a logic high level, and the sense signal SALB1 is at a logic low level (timing T1).

  Also, the control signal YSK1 is set to a logic high level. Then, the output circuit OUTC1 outputs data having a logic level based on the complementary signal received from the sense amplifier SA1 to the global read line GRIO (timing T1).

  Next, the control signals PC1 and SAE1 are set to a logic low level. Then, sense amplifier SA1 is deactivated, and nodes NT and NB in sense amplifier SA1 are precharged again to a logic high level (timing T2).

  Next, the control signal YSK2 is set to a logic high level. At this time, since the sense signals SALT and SALB from the sense amplifier SA2 are at a logic high level, the output circuit OUTC2 globally reads the output data of the output circuit OUTC1, that is, data having the same logic level as the data on the global read line GRIO. Output to the line GRIO (timing T3).

  Next, the control signal YSK1 is set to a logic low level. Then, the output of the output circuit OUTC1 enters a high impedance state (timing T4).

  Next, control signals PC2 and SAE2 are set to a logic high level. Then, sense amplifier SA2 is activated, the difference between the potential of bit line BL2 and the potential of dummy bit line DBL2 is amplified, and complementary signals indicating the amplification results are output to nodes NT and NB as sense signals SALT2 and SALB2, respectively. . Here, the sense signal SALT2 is at a logic low level, and the sense signal SALB2 is at a logic high level. Then, the output circuit OUTC2 outputs data having a logic level based on the complementary signal received from the sense amplifier SA2 to the global read line GRIO (timing T5).

  By the way, in the MRAM described in Non-Patent Document 1, it is necessary to enable the outputs of the sense amplifiers at intervals in order to prevent the output signals of the sense amplifiers from colliding on the global read line. There was a problem that time would increase.

  However, in the semiconductor device according to the embodiment of the present invention, the output circuit OUTC2 in the read circuit RDC2 is sensed even when the output of the output circuit OUTC2 is enabled by setting the control signal YSK2 to a logic high level. When the amplifier SA2 is not activated (timing T3), data having the same logic level as the data on the global read line GRIO is output to the global read line GRIO. That is, the output circuit OUTC2 outputs data having the same logic level as the output data of the output circuit OUTC1 to the global read line GRIO. Thereby, even if the output enable period of the output circuit OUTC1 and the output enable period of the output circuit OUTC2 overlap, it is possible to prevent the output data of the output circuit OUTC1 and the output data of the output circuit OUTC2 from colliding with each other. .

  That is, since it is not necessary to enable the outputs of the read circuits RDC1 and RDC2 at intervals, the data read time can be shortened.

  Further, in the MRAM described in Non-Patent Document 1, in order to process the output signal of the sense amplifier and read out the storage data of a new memory cell by the sense amplifier, the sense amplifier output and the global read line Consider a configuration in which a latch circuit is provided between the two.

  Such a configuration has the following problems when the read data output enable periods of the two read circuits (hereinafter referred to as read circuits A and B) overlap as described above.

  That is, in the read circuit B corresponding to the next memory cell to be read, the output of the latch circuit is enabled when the level of the output signal of the sense amplifier is uncertain.

  At this time, if the logical level of the data on the global read line output from the read circuit A is different from the logical level of the data held in the latch circuit in the read circuit B, the level of the global read line changes. Become. When the level of the output signal of the sense amplifier in the read circuit B is determined, and the logic level of the output signal is different from the current logic level of the data on the global read line, the level of the global read line is further changed. become. That is, when reading the storage data of a new memory cell corresponding to a different read circuit, the level of the global read line is inverted twice in the worst case, resulting in an increase in power consumption.

  However, in the semiconductor device according to the embodiment of the present invention, the output circuit OUTC, when the output is enabled, when the corresponding sense amplifier SA is not activated, the data on the global read line GRIO and the logic Data having the same level is output to the global read line GRIO. With such a configuration, unnecessary inversion of the level of the global read line as described above can be prevented, so that power consumption can be reduced.

  In the semiconductor device according to the embodiment of the present invention, the sense amplifier SA outputs a complementary signal to the output circuit OUTC when activated, and outputs two signals having the same level when not activated. Output to OUTC. Then, the output circuit OUTC determines whether the sense amplifier SA is activated or deactivated based on whether or not the two signals received from the sense amplifier SA are complementary signals, and the global read line Switch the data contents to be output to GRIO. With such a configuration, it is not necessary to separately output a control signal indicating whether or not the sense amplifier SA is activated to the output circuit OUTC, and the circuit configuration can be simplified.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 is a schematic block diagram showing an overall configuration of a semiconductor device according to an embodiment of the present invention. 2 is a diagram showing in detail the configuration of a memory array 10 and a read / write control circuit 30 according to an embodiment of the present invention. FIG. It is a figure which shows the structure of the read-out circuit RDC which concerns on embodiment of this invention in detail. 4 is a time chart showing a data read operation of the semiconductor device according to the embodiment of the present invention.

Explanation of symbols

  5 control circuit, 10 memory array, 20 row selection circuit, 25 column decoder, 30 read / write control circuit, 101 semiconductor device, WL, WL0, WL1 word line, BL0, BL1 bit line, SCL, DSCL column selection line, GRIO Global read line, DBL0, DBL1 dummy bit line, MC0 to MC5, MC, MC1, MC2 memory cell, S, SD MTJ element (magnetoresistance element), TRS, TRSD access transistor, DMC1, DMC2 dummy memory cell, SA1, SA2 Sense amplifier, OUTC1, OUTC2 output circuit, RDC1, RDC2 read circuit, M1-M4, M12, M14 N-channel MOS transistors, M5-M11, M13 P-channel MOS transistors, G1, G2 NOT gate Door, G3 OR gate, G4 AND gate, G5 NAND gate, G6 AND gate.

Claims (3)

Multiple bit lines,
A global readout line;
A plurality of memory cells provided corresponding to the bit lines, each coupled to the corresponding bit line, storing data, and passing a current based on the stored data through the corresponding bit line;
A plurality of read circuits provided corresponding to the bit lines, each of which reads storage data of the memory cell coupled to the corresponding bit line and outputs the read data to the global read line;
Each of the readout circuits includes
A sense amplifier that outputs a signal based on a current flowing through the corresponding bit line when activated;
When coupled to the global read line and the sense amplifier is not activated, data having the same logic level as the data on the global read line is output to the global read line, and the sense amplifier is activated. And an output circuit that outputs data based on a signal received from the sense amplifier to the global read line. Each of the output circuits outputs data to the global read line when enabled, and stops data output to the global read line when disabled.
The semiconductor device further includes:
Enabling the output circuit corresponding to the memory cell from which data is to be read and then disabling the output circuit corresponding to the memory cell from which data is to be read next during the period of enabling the memory cell; The semiconductor device according to claim 1, further comprising a control circuit for enabling. The sense amplifier has an output node pair. When the sense amplifier is not activated, the sense amplifier outputs a signal having the same logic level to the output node pair. When activated, the sense amplifier is based on a current flowing through the corresponding bit line. Output complementary signals to the output node pair;
When the output circuit receives a signal having the same logic level from the output node pair, the output circuit outputs data having the same logic level as the data on the global read line to the global read line. The semiconductor device according to claim 1, wherein when a complementary signal is received, data based on the complementary signal received from the sense amplifier is output to the global read line.

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