JP5143415B2 - Phase change memory device having multi-bit cell and diameter adjustable contact, method for manufacturing the same, and method for programming the same - Google Patents

Description

  The present invention relates to a phase change memory element, a manufacturing method thereof, and a programming method thereof, and more particularly to a phase change memory element including a multi-bit cell and a contact whose diameter is adjusted, a manufacturing method thereof, and a programming method thereof.

Recently, phase change memory elements have been developed. The phase change memory element has a non-volatile characteristic that maintains stored information even when power supply is interrupted. The unit cell of the phase change memory element uses a phase change material such as a data storage medium. The phase change material has a plurality of stable states, that is, a crystalline state and an amorphous state. The state is controlled by heat supplied to the cell structure via an applied current. A generally known phase change material, that is, chalcogenide, is a compound composed of Ge, Sb and Te, usually referred to as GST (Ge-Sb-Te) material. In particular, one form of the GST material is Ge ₂ Sb ₂ Te ₅ . When the GST material is heated at a temperature close to the melting point of the material for a short time, and then rapidly cooled or quenched (quenched), the GST material is in an amorphous state. When the GST material is heated at a crystallization temperature lower than the melting point for a long time and then slowly cooled, the GST material is in a crystalline state. The amorphous GST has a specific resistance higher than that of the crystalline GST. Accordingly, whether the information stored in the phase change memory cell is logic “1” or “0” is determined by sensing the amount of current flowing through the phase change material. The

  Joule heat is used as the heat supplied to the phase change material. That is, when an electric current is supplied to the electrode connected to the phase change material, Joule heat is generated from the electrode and supplied to the phase change material. The temperature of the heat supplied to the phase change material depends on the amount of current supplied.

  FIG. 1 is a cross-sectional view illustrating the structure of a conventional phase change memory cell. Referring to FIG. 1, a lower insulating film 102 is formed on a semiconductor substrate. An upper insulating film 122 is formed on the lower insulating film 102. A first contact hole 105 penetrating the lower insulating film 102 is formed, and a second contact hole 125 penetrating the upper insulating film 122 is formed. The second contact hole 125 is filled with an upper conductive contact plug 127 formed of a conductive material such as tungsten (W), aluminum (Al), or copper (Cu). The first contact hole 105 is filled with a heater 113a and a lower conductive contact plug formed of a conductive material such as TiAlN, TiN, or a similar material.

  A GST phase change material layer 115 is formed in the upper insulating layer 122 on the lower insulating layer 102. A conductive upper electrode 119 made of TiN, TaN, WN, or a similar material is formed on the upper surface of the GST phase change material film 115. The lower surface of the phase change material layer 115 is electrically connected to the lower plug or heater 113a, and the upper surface of the phase change material layer 115 is electrically connected to the upper electrode 119 and the upper contact plug 127. A conductive metal pattern 129 formed of a conductive material such as W, Al, Cu, or a similar material is electrically connected to the upper contact plug 127 and the upper electrode 119.

  When the memory cell is programmed, a current is applied to the metal pattern 129, the lower contact, and the heater 113a. Heat is generated by the flow of current through the heater 113a, and the generated heat affects the state of the programmable region 117 in the GST material film 115. In connection with the applied program process, the GST material in the programmable region 117 changes to a crystalline state or an amorphous state. For example, to program the programmable region into the crystalline state, after heating the GST material at about 150 ° C. with a current of about 0.56 mA flowing through the GST material, a time of about 500 ns Cooling. Further, for example, to program the programmable region in the amorphous state, after heating the GST material to about 620 ° C. with a current of about 1.2 mA flowing through the GST material, about 4 Cool for -5 ns.

  FIG. 2A is a schematic configuration diagram of the memory cell of FIG. FIG. 2B is a schematic equivalent circuit diagram in which the memory cell of FIG. 1 is used. Referring to FIGS. 2A and 2B, when a current flows from the bit line BL through the upper electrode 119 and the GST phase change material layer 115, the programmable region 117 is programmed to a desired state. The GST material film 115 is shown as a variable resistance. The word line is used to adjust transistor 121 and the program process proceeds. A current through the heater 113a heats the GST material film 115 to program the programmable region 117 to a desired state. For example, if the programmable region 117 is in an amorphous state, the memory cell is programmed to a logic “0” state, and if the programmable region 117 is in a crystalline state, the memory cell is in a logic “1” state. Programmed.

  The memory cell described above stores one of a plurality of possible states, a logic “0” state or a logic “1” state. In general, multi-bit memory cells that can store multiple possible states are preferred to increase the data storage capacity of the memory. Multi-bit phase change storage elements have been developed that use the programmable area in a hybrid state to store more than one bit of information per cell. In general, the programmable area is programmed to one of three possible states. In a first state, referred to as a complete reset state, the entire programmable region is programmed to an amorphous state. In a second state, referred to as a fully set state, the entire programmable area is programmed to a crystalline state. In the third state, a portion of the programmable region is programmed to a crystalline state and another portion of the programmable region is programmed to an amorphous state.

In the hybrid element of this form, the volume fraction X of the programmable region, that is, the fraction of the programmable region in the amorphous state is the magnitude of the program current and / or after the program current is removed. Adjusted by controlling the quenching time carried out. In general, the volume fraction X is a value between 0 and 1. In the complete reset state, X = 1, and in the complete set state, X = 0. In the hybrid or mixed state, X is between 0 and 1, that is, 0 <X <1. This theoretically allows the hybrid memory cell to store three possible states. However, it is actually very difficult to program such an element. The volume fraction cannot be accurately adjusted through the program process, resulting in a very high program error and the lowest program reliability.
It is used practically as a memory device.

US Pat. No. 3,271,591

  It is an object of the present invention to provide a phase change memory element that can store multi-bit information of 2 bits or more per cell with a simple structure, a manufacturing method thereof, and a programming method thereof.

  The phase change memory element according to an embodiment of the present invention includes a first chalcogenide information storage element including a material that changes to a crystalline state or an amorphous state upon application of a heating current. A first contact connected to a first region of the first chalcogenide information storage element and having a first cross-sectional region is provided. A second contact connected to a second region of the first chalcogenide information storage element and having a second cross-sectional region; A first programmable region having a state programmed by a first resistor associated with the first contact and limited within a first region of the first chalcogenide information storage element; A second programmable region having a state programmed by a second resistor associated with the second contact and limited within a second region of the first chalcogenide information storage element;

In some embodiments according to an aspect of the present invention, the material forming the first contact may have a resistance different from the resistance of the material forming the second contact.
In another embodiment, the material forming the first contact may have a resistance that is substantially equal to the resistance of the material forming the second contact.
In still another embodiment, the first contact and the second contact are made of different materials.
In still another embodiment, the first contact and the second contact are made of substantially the same material.
In yet another embodiment, further comprising a second chalcogenide information storage element, the second chalcogenide information storage element comprising a third programmable area limited within a third area of the second chalcogenide information storage element. Can do.
In yet another embodiment, one of the first and second contacts is connected to the third region of the second chalcogenide information storage element, and the state of the third programmable region is in the third region. One of the connected first and second contacts can be programmed with a resistor.
In still another embodiment, the material forming the first contact may have a resistance different from that of the material forming the second contact.
In still other embodiments, the first and second contacts may be formed of different materials.
In still other embodiments, at least one of the first and second contacts may have one or more cross-sectional areas.
In still other embodiments, at least one of the first and second contacts may have a taper shape.
In still other embodiments, the material forming the first contact may have a resistance different from that of the material forming the second contact.
In still other embodiments, the first and second contacts may be formed of different materials.
In yet another embodiment, the semiconductor device may further include a third contact having a third cross-sectional area and connected to a fourth area of the second chalcogenide information storage element. In this case, the fourth area of the second chalcogenide information storage element may include a fourth programmable area. In addition, the state of the fourth programmable region can be programmed by a resistor related to the third contact connected to the fourth region.
In still other embodiments, the third cross-sectional area may have the same size as one of the first and second cross-sectional areas.
In still other embodiments, the third cross-sectional area may have a size different from one of the first and second cross-sectional areas.
In still another embodiment, the material forming the third contact may have a resistance different from that of the material forming at least one of the first and second contacts.
In still another embodiment, at least one of the first and second contacts and the third contact may be formed of different materials.
In still other embodiments, the third contact may have one or more cross-sectional areas.
In still another embodiment, the third contact may have a tapered shape.
In still other embodiments, the phase change memory element can store data that can have multiple values.

  The phase change memory element according to another aspect of the present invention includes a first chalcogenide information storage element including a material that changes to a crystalline state or an amorphous state upon application of a heating current. A first contact connected to a first region of the first chalcogenide information storage element and having a first cross-sectional region is provided. A second contact connected to a second region of the first chalcogenide information storage element and having a second cross-sectional region different from the first cross-sectional region; and a first programmable region of the first chalcogenide information storage element is Limited to a first region of the first chalcogenide information storage element, the state of the first programmable region is programmed by a first resistor associated with the first contact. A second programmable area of the first chalcogenide information storage element limited within the second area of the first chalcogenide information storage element, wherein the state of the second programmable area is the second contact associated with the second contact; Programmed with two resistors.

In some embodiments according to other aspects of the present invention, the material forming the first contact may have a resistance different from the resistance of the material forming the second contact.
In other embodiments, the first and second contacts may be formed of different materials.
In yet another embodiment, further comprising a second chalcogenide information storage element, wherein the second chalcogenide information storage element comprises a third programmable area limited to a third area of the second chalcogenide information storage element. Can do.
In yet another embodiment, one of the first and second contacts is connected to the third region of the second chalcogenide information storage element, and the state of the third programmable region is in the third region. It can be programmed by a resistor associated with one of the first and second contacts to be connected.
In still another embodiment, the material forming the first contact may have a resistance different from that of the material forming the second contact.
In still other embodiments, the first and second contacts may be formed of different materials.
In still other embodiments, at least one of the first and second contacts may have one or more cross-sectional areas.
In still other embodiments, at least one of the first and second contacts may have a taper shape.
In still another embodiment, the material forming the first contact may have a resistance different from that of the material forming the second contact.
In still other embodiments, the first and second contacts may be formed of different materials.
In yet another embodiment, the semiconductor device may further include a third contact having a third cross-sectional area and connected to a fourth area of the second chalcogenide information storage element. In this case, the fourth region of the second chalcogenide information storage element includes a fourth programmable region, and the state of the fourth programmable region is a resistance associated with the third contact connected to the fourth region. Can be programmed.
In still other embodiments, the third cross-sectional area may have the same size as one of the first and second cross-sectional areas.
In still other embodiments, the third cross-sectional area may have a size different from one of the first and second cross-sectional areas.
In still another embodiment, the material forming the third contact may have a resistance different from the resistance of the material forming at least one of the first and second contacts.
In still another embodiment, at least one of the first and second contacts and the third contact may be formed of different materials.
In still other embodiments, the third contact may have one or more cross-sectional areas.
In still another embodiment, the third contact may have a tapered shape.
In still other embodiments, the phase change memory element can store data that can have multiple values.

  According to still another aspect of the present invention, the phase change memory element includes a first chalcogenide information storage element including a material that changes to a crystalline state or an amorphous state upon application of a heating current. A first contact connected to a first region of the first chalcogenide information storage element and having a first cross-sectional region is provided. A second contact connected to a second region of the first chalcogenide information storage element and having a second cross-sectional area substantially equal to the first cross-sectional area; A first programmable region having a state programmed by a first resistor associated with the first contact and limited within a first region of the first chalcogenide information storage element; A second programmable region having a state programmed by a second resistor associated with the second contact and limited within a second region of the first chalcogenide information storage element;

In some other embodiments of the present invention, the material forming the first contact may have a resistance different from the resistance of the material forming the second contact.
In another embodiment of the present invention, the first and second contacts may be formed of different materials.
In still other embodiments of the present invention, a second chalcogenide information storage element may be further included. In this case, the second chalcogenide information storage element may include a third programmable area limited to a third area of the second chalcogenide information storage element.
In still another embodiment of the present invention, one of the first and second contacts is connected to the third region of the second chalcogenide information storage element, and the state of the third programmable region is the first It can be programmed with a resistor associated with one of the first and second contacts connected to three regions.
In another embodiment of the present invention, the material forming the first contact may have a resistance different from that of the material forming the second contact.
In still other embodiments of the present invention, the first and second contacts may be formed of different materials.
In still another embodiment of the present invention, at least one of the first and second contacts may have one or more cross-sectional areas.
In still another embodiment of the present invention, at least one of the first and second contacts may have a tapered shape.
In another embodiment of the present invention, the material forming the first contact may have a resistance different from that of the material forming the second contact.
In still other embodiments of the present invention, the first and second contacts may be formed of different materials.
In yet another embodiment of the present invention, a third contact having a third cross-sectional region and connected to a fourth region of the second chalcogenide information storage element may be further included. In this case, the fourth area of the second chalcogenide information storage element may include a fourth programmable area. In addition, the state of the fourth programmable region can be programmed by a resistor related to the third contact connected to the fourth region.
In still another embodiment of the present invention, the third cross-sectional area may have the same size as one of the first and second cross-sectional areas.
In still other embodiments of the present invention, the third cross-sectional area may have a size different from one of the first and second cross-sectional areas.
In another embodiment of the present invention, the material forming the third contact may have a resistance different from that of the material forming at least one of the first and second contacts.
In still other embodiments of the present invention, at least one of the first and second contacts and the third contact may be formed of different materials.
In still another embodiment of the present invention, the third contact may have one or more cross-sectional areas.
In another embodiment of the present invention, the third contact may have a tapered shape.
In still another embodiment of the present invention, the phase change memory element may store data that can have a plurality of values.

  The method of manufacturing a phase change memory element according to still another aspect of the present invention includes providing a first chalcogenide information storage element including a material that changes to a crystalline state or an amorphous state by applying a heating current. . A first contact having a first cross-sectional area is formed, connected to the first area of the first chalcogenide information storage element. A second contact connected to the second region of the first chalcogenide information storage element and having a second cross-sectional region is formed. The first programmable area of the first chalcogenide information storage element is limited to the first area of the first chalcogenide storage information element, and the state of the first programmable area is determined by a first resistance associated with the first contact. To be programmed. The second programmable area of the first chalcogenide information storage element is limited to the second area of the first chalcogenide storage information element, and the state of the second programmable area is a second resistance associated with the second contact. Programmed.

In some embodiments according to yet another aspect of the present invention, the first and second cross-sectional regions can be formed to have substantially the same size.
In another embodiment of the present invention, the first and second cross-sectional areas may be formed to have different sizes.
In still another embodiment of the present invention, the material forming the first contact may have a resistance different from that of the material forming the second contact.
In still another embodiment of the present invention, the material forming the first contact may be formed to have a resistance substantially equal to the resistance of the material forming the second contact.
In another exemplary embodiment of the present invention, the first contact and the second contact may be formed of different materials.
In still other embodiments of the present invention, the first contact and the second contact may be formed of substantially the same material.
In still other embodiments of the present invention, the method may further include forming a second chalcogenide information storage element. In this case, the second chalcogenide information storage element may include a third programmable area limited to a third area of the second chalcogenide information storage element.
In still other embodiments of the present invention, one of the first and second contacts may be formed to be connected to the third region of the second chalcogenide information storage element. In this case, the state of the third programmable region can be programmed by a resistor associated with one of the first and second contacts connected to the third region.
In still another embodiment of the present invention, the material forming the first contact may have a resistance different from that of the material forming the second contact.
In still other embodiments of the present invention, the first and second contacts may be formed of different materials.
In still another embodiment of the present invention, at least one of the first and second contacts may be formed to have one or more cross-sectional areas.
In still another embodiment of the present invention, at least one of the first and second contacts may be formed to have a taper shape.
In still another embodiment of the present invention, the material forming the first contact may have a resistance different from that of the material forming the second contact.
In still other embodiments of the present invention, the first and second contacts may be formed of different materials.
In yet another embodiment of the present invention, the method may further include forming a third contact having a third cross-sectional area and connected to a fourth area of the second chalcogenide information storage element. In this case, the fourth region of the second chalcogenide information storage element may be formed to include a fourth programmable region. In addition, the state of the fourth programmable region can be programmed by a resistor related to the third contact connected to the fourth region.
In still another embodiment of the present invention, the third cross-sectional area may be formed to have the same size as one of the first and second cross-sectional areas.
In still another embodiment of the present invention, the third cross-sectional area may be formed to have a size different from one of the first and second cross-sectional areas.
In another exemplary embodiment of the present invention, the material forming the third contact may have a resistance different from that of the material forming at least one of the first and second contacts. .
In still another embodiment of the present invention, at least one of the first and second contacts and the third contact may be formed of different materials.
In still another embodiment of the present invention, the third contact may be formed to have one or more cross-sectional areas.
In still another embodiment of the present invention, the third contact may be formed to have a taper shape.
In still other embodiments of the present invention, the phase change memory element may be formed to store data that may have a plurality of values.

  The phase change memory device according to the present invention has a simple structure and can store multi-bit information of 2 bits or more per cell. In addition, since information of 2 bits or more per cell can be stored, the degree of integration of the phase change memory element can be dramatically improved.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein, and may be embodied in other forms. Rather, the embodiments introduced herein are provided to demonstrate that the disclosed invention has been completed and to fully convey the spirit of the invention to those skilled in the art. Like reference numerals refer to like elements throughout the specification. Also, if a layer is said to be “on” another layer, or substrate, it can be formed directly on the other layer, or substrate, or a third layer interposed between them. Sometimes it is done.

  In general, the lower contact or the heater cross-sectional area will have an effect on the programming process applied to program the programmable area to the desired state. FIG. 3 shows a schematic cross-sectional view of the phase change memory cell 10 for illustrating the two cases of a lower contact or heater 5 having one of two possible cross-sectional areas. The phase change memory cell 10 of FIG. 3 includes a substrate 1 on which an insulating film 3 is formed. An upper metal pattern 11 is formed on the insulating film 3. A chalcogenide GST phase change material film 7 is formed in the insulating film 3, and its lower surface is in contact with the lower contact 5. An upper electrode 9 is formed on the GST phase change material layer 7. In this case, the upper electrode 9 is in contact with the GST phase change material layer 7 and the upper metal pattern 11. As shown in FIG. 3, the lower contact may comprise one of two possible cross-sectional areas to illustrate the above-described invention. The two possible cross-sectional areas can be limited by the two possible diameters D1, D2 that the lower contact 5 can have.

  FIG. 4 shows schematic waveform diagrams of current-resistance (IR) characteristics for the two cases of the phase change memory cell 10 shown in FIG. The waveform of FIG. 4 shows the program of memory cell 10 in FIG. 3 under two conditions in the lower contact cross-sectional area. More specifically, curve G1 represents a program for memory cell 10 having a lower contact having a diameter D1, and curve G2 represents a program for memory cell 10 having a lower contact having a diameter D2.

As shown in the waveform G1 of FIG. 4, when the memory cell having the lower contact having a smaller cross-sectional area is in the reset state, the above-described programmable region is in an amorphous state, and the resistance of the memory cell R _RS1 is relatively high. When the set current I _S1 is applied, the memory cell is in a set state in which the programmable region is in a crystalline state, and the resistance R _{S1 of the} memory cell in the set state is substantially reduced. When the reset current I _RS1 is applied during the set state, the memory cell is in a reset state in which the programmable region is in an amorphous state. In this case, the resistance of the memory cell is the reset resistor. Return to value R _RS1 .

As shown in the waveform G2 of FIG. 4, when the memory cell having the lower contact having a larger cross-sectional area is in the reset state, the above-described programmable region is in an amorphous state, and the memory cell The resistance R _RS2 is relatively high and lower than the reset resistance R _{RS1 of the} memory cell with a lower contact having a smaller cross-sectional area. When the set current I _S2 is applied, the memory cell is in a set state in which the programmable region is in a crystalline state, and the resistance R _{S1 of the} memory cell in the set state is substantially lowered, In some cases, the resistance R _S1 has a lower value than the set resistance R _{S1 of the} memory cell including the lower contact having a smaller cross-sectional area. When the reset current _IRS2 is applied during the set state, the memory cell is in a reset state in which the programmable region is in an amorphous state, and in this case, the resistance of the memory cell is the reset resistor. Return to value R _RS2 .

As shown in FIG. 4, the resistance of the memory cell in the reset state and the resistance of the memory cell in the set state are different from each other due to the difference in the cross-sectional area in the lower contact of the memory cell in the two cases. A memory cell having a lower contact having a relatively large cross-sectional area exhibits a lower reset resistance and a lower set resistance than a memory cell having a lower contact having a relatively small cross-sectional area. Due to the difference in cell resistance between the two memory cells, the set current and the reset current of the two memory cells are different from each other. More specifically, the set current I _S2 of the memory cell having a relatively large lower contact is higher than the set current I _{S1 of the} memory cell having a relatively small lower contact. Further, the reset current I _RS2 of the memory cell having a relatively large lower contact is higher than the reset current I _{RS1 of the} memory cell having a relatively small lower contact.

FIG. 5 is a graph obtained by linear regression analysis for explaining the relationship between the diameter CD of the lower contact and the reset current I _RESET in the phase change memory cell. In the graph of FIG. 5, a square point indicates a case of a lower contact formed of TiN, and a round point indicates a case of a lower contact formed of TiAlN. The reset current I _RESET is a current necessary for changing the program of the memory cell from the crystalline state to the amorphous state. As shown in FIG. 5, a decrease in the reset current I _RESET ratio with respect to the diameter CD of the lower contact indicates a linear regression analysis. Referring to the curve of FIG. 5, in the TiN lower contact, the reset current ratio to the lower diameter CD is 38.9 μA / nm, and in the TiAlN lower contact, the reset current ratio to the lower diameter CD is 27.4 μA / nm. The reset current is 0.8 mA for a 44 nm TiAlN bottom contact and a 36 nm TiN bottom contact.

FIG. 6 is a graph obtained by second order regression analysis to explain the relationship between the lower contact diameter CD and the reset current I _RESET in the phase change memory cell. Referring to FIG. 6, the reset current I _RESET is proportional to the square of the lower contact diameter CD. In the graph of FIG. 6, a square point indicates a case of a lower contact formed of TiN, and a round point indicates a case of a lower contact formed of TiAlN. The reset current I _RESET is a current necessary for changing the program of the memory cell from the crystalline state to the amorphous state. Referring to the curve of FIG. 6, the reset current is 0.8 mA for a 39 nm TiAlN bottom contact and a 32 nm TiN bottom contact.

FIG. 7 is a graph illustrating the relationship between the lower contact diameter CD and the set resistance R _{SET in} order to show that the set resistance R _SET is inversely proportional to the square of the lower contact diameter CD in the phase change memory cell. In the graph of FIG. 7, a square point indicates a case of a lower contact formed of TiN, and a round point indicates a case of a lower contact formed of TiAlN. Referring to the curve of FIG. 7, for a 0.8 mA reset current I _RESET and a TiAlN bottom contact, the set resistance R _SET is 2.5-3 kΩ and for a 0.8 mA reset current I _RESET and a TiN bottom contact The set resistance R _SET is 2.2-2.9 kΩ.

  Each of the phase change memory cells according to the present invention may include multiple programmable regions of chalcogenide GST phase change material films. Since the multiple programmable regions are programmed independently of each other, each of the storage cells can store a number of bits of data. Each programmable area according to the present invention is connected to a respective contact. Each of the contacts is controlled by adjusting the cross-sectional area so that the program current flowing through all the contacts can be independently programmed with the program area selected.

  FIG. 8 is a cross-sectional view illustrating a multi-bit phase change memory cell 200 according to an embodiment of the present invention. Referring to FIG. 8, the memory cell 200 includes a substrate 210 on which an insulating film 213 is formed. A phase change GST material pattern 217 is formed in the insulating layer 213. A lower contact 215 having a diameter D3 is formed in the insulating layer 213 in contact with the lower surface of the phase change material pattern 217. The lower contact 215 defines a first programmable region P1 in the phase change material pattern 217. An upper contact 219 having a diameter D4 is formed in the insulating layer 213 in contact with an upper surface of the phase change material pattern 217. The upper contact 219 defines a second programmable region P2 in the phase change material pattern 217. The conductive plate line 221 is formed on the upper part of the structure in which the upper contact 219 is in contact with the upper end.

  According to the present invention, the resistance of the plurality of contacts 215 and 219 is independently adjusted by applying a constant program current to independently program the programmable regions P1 and P2 in a desired state. The When the resistances are different from each other, the heat generated in the programmable areas P1 and P2 is different, and the programmable areas P1 and P2 can be programmed independently. For example, the diameters D3 and D4 may be formed to be different from each other such that the resistances of their respective contacts 215 and 219 are different from each other. For example, one of the contacts 215, 219 is made of TiAlN and the other is made of TiN. Also, not only different resistances but also combinations of different diameters D3 and D4 can be used to adjust the resistance difference. The diameters D3 and D4 of the contacts 215 and 219, which can be the same or different from each other, are usually 50 nm or less and can act as a heating element.

FIG. 9 is a schematic waveform diagram for explaining current-resistance (IR) characteristics for phase change memory cell 200 shown in FIG. In the graph of FIG. 9, each of the reference number R indicating resistance and the reference number I indicating current includes the suffix “A” or “B”, and the suffix indicates the amorphous state of the programmable regions P1 and P2. Or shows a crystalline state. More specifically, the first subscript of the subscripts indicates the first programmable area P1, and the second subscript of the subscripts indicates the second programmable area P2. The resistor _RAA is the cell resistance of the programmable regions P1 and P2 in the amorphous state. A program current I _CA is used so that the programmable region P1 is programmed to a crystalline state while the programmable region P2 is in an amorphous state, and in this case, the resistance of the cell is R _CA. The current I _CC is a current used to program the cell so that the programmable regions P1 and P2 are in a crystalline state, and in this case, the resistance of the cell is R _CC . While the programmable region P2 remains in the crystalline state, the current I _AC is the current used to program the cell so that the programmable region P1 returns to the amorphous state, in this case The resistance of the cell is _RAC . The current _IAA is a current used to program the cell so that the programmable regions P1 and P2 return to an amorphous state, and in this case, the resistance of the cell is _RAA . Since the resistances of the contacts 215, 219 are different from each other, the cell can be programmed to one of four possible resistances. Thereby, the cell is a multi-bit cell capable of storing four possible values or two bits of data per chalcogenide element.

  FIG. 10 is a cross-sectional view illustrating a multi-bit phase change memory cell 300 according to another embodiment of the present invention. Referring to FIG. 10, the memory cell 300 includes a substrate 310 on which an insulating layer 313 is formed. According to an embodiment of the present invention, three phase change GST material patterns 337a, 337b, and 337c are formed in the insulating layer 313. A lower contact 335 having a diameter D5 is formed in the insulating layer 313 in contact with the lower surface of the lower phase change material pattern 337a. The lower contact 335 defines a programmable area in the lower phase change material pattern 337a. An upper contact 339 having a diameter D8 is formed in the insulating layer 313 in contact with the upper surface of the upper phase change material pattern 337c. The upper contact 339 defines a programmable region P8 in the upper phase change material pattern 337c. A contact 336a having a diameter D6 is connected between the lower phase change material pattern 337a and the intermediate phase change material pattern 337b. The upper end of the contact 336a defines a programmable region P6 in the intermediate phase change material pattern 337b, and the lower end of the contact 336a defines a programmable region P6 in the lower phase change material pattern 337a. A contact 336b having a diameter D7 is connected between the upper phase change material pattern 337c and the intermediate phase change material pattern 337b. The lower end of the contact 336b defines a programmable region P7 in the intermediate phase change material pattern 337b, and the upper end of the contact 336b defines a programmable region P7 in the upper phase change material pattern 337c. A conductive plate line 321 is formed on the upper portion of the structure in contact with the upper end of the upper contact 339.

  According to the present invention, the resistance of the contact is controlled so that the programming of the multiple programmable region can be adjusted. In an embodiment of the present invention, the diameters D5, D6, D7, and D8 may have different sizes so that each of the contacts has a different resistance. On the other hand, the contacts may be formed of different materials so as to have different resistances. These two approaches can be used by combining the contacts. By controlling the resistance of the contacts, the programmable regions can be independently programmed in different states. As described above, the diameters D5, D6, D7, and D8 are preferably 50 nm or less so that each of the contacts acts as a heating element. As shown in FIG. 10, the contacts 336a and 336b have a substantially cylindrical shape so that the programmable regions on both sides of the phase change material pattern with which the contacts 336a and 336b are in contact have the same size. That is, the contact 336a defines a plurality of similar programmable regions P6 located in the phase change material patterns 337a, 337b, and the contact 336b includes a plurality of similar programs located in the phase change material patterns 337b, 337c. The programmable area P7 is limited.

  FIG. 11 is a cross-sectional view illustrating a multi-bit phase change memory cell 400 according to still another embodiment of the present invention. Referring to FIG. 11, the memory cell 400 includes a substrate 410 on which an insulating layer 413 is formed. In the above-described embodiment, a plurality of phase change GST material patterns 457 a and 457 b are formed in the insulating layer 413. A lower contact 435 having a diameter D10 is formed in the insulating layer 413 in contact with the lower surface of the lower phase change material pattern 457a. The lower contact 435 defines a programmable region P10 in the lower phase change material pattern 457a. An upper contact 439 having a diameter D13 is formed in the insulating layer 413 in contact with the upper surface of the upper phase change material pattern 457b. The upper contact 439 defines a programmable region P13 in the upper phase change material pattern 457b. The tapered contact 456 defining the plurality of diameters D11 and D12 is connected between the lower phase change material pattern 457a and the upper phase change material pattern 457b. The upper end of the tapered contact 456 defines a programmable region P12 in the upper phase change material pattern 457b, and the lower end of the tapered contact 456 is programmable in the lower phase change material pattern 457a. The region P11 is limited. Since the diameter D12 of the tapered contact 456 is different from the diameter D11 of the tapered contact 456, a plurality of independent programmable regions P12 and P11 are a plurality of the phase change material patterns 457a and 457b. Limited to within. A conductive plate line 321 is formed on the upper portion of the structure in contact with the upper end of the upper contact 339.

  According to the present invention, the resistance of the contact is independently adjusted so that a constant program current is applied to independently program the programmable region in a desired state. Adjustment above the resistance of the contact can be performed by one or more means. For example, the diameters may be different from each other in order to make resistances of the contacts different from each other. The contacts may be formed of different materials in order to make the respective resistances of the contacts different from each other. Also, combinations having different resistances and different diameters can be used to adjust the difference in resistance. The diameters of contacts that are equal or different from each other are typically formed below 50 nm so that the contacts act as heating elements.

FIG. 12 is a schematic timing diagram for explaining the program timing of the phase change memory cell shown in FIG. Referring to FIGS. 8, 9 and 12, programming the memory device has an initial current magnitude H1 and includes first applying an initial programming current pulse Φ _IP . Said initial programming current pulses [Phi _IP is used for the cell resistance to program the programmable region P1, P2 to the amorphous state such that the R _AA state. The magnitude of the current H1 is defined in _{I AA.} The programming pulse is shown as having an arbitrary width at the time of W1. The period includes its own current pulse with a relatively short quench time of a few nanoseconds so that the programmable region reaches the amorphous state.

Waveforms A, B, C, and D shown in FIG. 12 show the program process according to the final state of the desired cell. For example, if the desired final state is _RAA , curve A represents the programming process, in which case the plurality of programmable regions are programmed to an amorphous state. In this case, the program process ends in application after the initial programming pulse [Phi _IP. When the desired final state is _RAC , curve B shows the programming process, where the programmable region P1 is in an amorphous state and the programmable region P2 is in a crystalline state. Become. If the desired final state is R _CC , curve C shows the programming process, in which case the programmable regions P1, P2 are in a crystalline state. When the desired final state is _RCA , the programmable region P1 is in a crystalline state and the programmable region P2 is in an amorphous state. In each of processes B, C, and D, an additional programming pulse Φ _AP is applied after the initial programming pulse Φ _IP to program the cell from the R _AA state to the desired final state.

Referring to curve B, and 9 in FIG. 12, the additional programming pulses [Phi ₃ is located between the above-mentioned H1 and H3, it is applied at a magnitude of H4 defined in I _AC. The current is to ensure proper programming of the programmable regions P1, P2, that is, the programmable region P1 is maintained in an amorphous state, and the programmable region P2 is converted into a crystalline state. It is in the range between approximately I _AC and I _AA to ensure. The additional programming pulse is activated during a time period W2, which includes the actual current pulse time and a relatively long quench time required for the programmable region P2 to become crystalline.

Referring to curves C and 9 of FIG. 12, the additional program pulses [Phi ₂ is greater than the above-mentioned H2, is applied at a magnitude of H3 defined by I _CC. The current is approximately I _CC and I _AC to ensure proper programming of the programmable regions P1, P2, ie, to ensure that the programmable regions P1, P2 are converted to a crystalline state. Is in the range between. The additional programming pulse is activated during a time period W2, which includes the actual current pulse time and a relatively long quench time required for the programmable regions P1, P2 to become crystalline. .

Referring to curve D of FIG. 12 and FIG. 9, the additional program pulse Φ ₁ is applied with a magnitude of H2 defined by I _CA. The current is to ensure proper programming of the programmable regions P1, P2, that is, the programmable region P1 is converted to a crystalline state and the programmable region P2 is maintained in an amorphous state. In order to ensure that it is approximately in the range between I _CA and I _CC . The additional programming pulse is activated during a time period W2, which includes the actual current pulse time and a relatively long quench time required for the programmable region P1 to become crystalline.

  In accordance with the present invention, a multi-bit phase change memory device is provided that can be easily manufactured by providing a phase change material pattern having a number of independent programmable regions.

  In the chalcogenide phase change material pattern, the heating contact used to program the programmable region is formed in a circular cross section. However, since the contacts can include contacts having a circular cross section, a right angle, or other configurations, the contacts can have any configuration.

  Although the foregoing has been described with reference to preferred embodiments of the invention, those skilled in the art will recognize that the invention may be practiced without departing from the spirit and scope of the invention as set forth in the appended claims. Various modifications and changes can be made to the invention.

It is sectional drawing explaining the structure of the conventional phase change memory cell. FIG. 2 is a schematic configuration diagram of the memory cell of FIG. 1. FIG. 2 is a schematic equivalent circuit diagram in which the memory cell of FIG. 1 is used. 6 is a schematic cross-sectional view of a phase change memory cell for explaining a lower contact or heater in a case where the lower contact or heater according to an embodiment of the present invention has a plurality of possible cross-sectional areas. FIG. 4 is a schematic waveform diagram for explaining current-resistance (IR) characteristics for a phase change memory element having a plurality of cases shown in FIG. 3. FIG. 6 is a graph of a linear regression analysis for explaining a relationship between a lower contact diameter CD and a reset current I _{RESET in} a phase change memory cell. FIG. 6 is a graph of a quadratic regression analysis for explaining a relationship between a lower contact diameter CD and a reset current I _{RESET in} a phase change memory cell. 6 is a graph illustrating a relationship between a lower contact diameter CD and a set resistance R _{SET in} order to show that the area of the lower contact diameter CD and the set resistance R _SET are inversely proportional to each other in the phase change memory cell. 1 is a cross-sectional view illustrating a multi-bit phase change memory cell according to an embodiment of the present invention. FIG. 9 is a schematic waveform diagram illustrating current-resistance (IR) characteristics for the phase change memory cell shown in FIG. 8. FIG. 6 is a cross-sectional view illustrating a multi-bit phase change memory cell according to another embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a multi-bit phase change memory cell according to still another embodiment of the present invention. FIG. 9 is a schematic timing diagram for explaining a program timing of the phase change memory cell shown in FIG. 8.

Explanation of symbols

200 Memory Cell 210 Substrate 213 Insulating Film 215 Lower Contact 217 Phase Change Material Pattern 219 Upper Contact 221 Conductive Plate Line P1, P2 Programmable Area D3, D4 Diameter

Claims (21)

A first chalcogenide information storage element comprising a material that changes to a crystalline state or an amorphous state upon application of a heating current;
A first contact connected to a first region of the first chalcogenide information storage element and having a first cross-sectional region;
A second contact connected to a second region of the first chalcogenide information storage element and having a second cross-sectional region;
A first programmable region having a state programmed by a first resistor associated with the first contact and limited within a first region of the first chalcogenide information storage element;
A second programmable region having a state programmed by a second resistor associated with the second contact and limited within a second region of the first chalcogenide information storage element;
Only including,
The phase change memory element according to claim 1, wherein the material forming the first contact has a resistance different from that of the material forming the second contact . A first chalcogenide information storage element comprising a material that changes to a crystalline state or an amorphous state upon application of a heating current;
A first contact connected to a first region of the first chalcogenide information storage element and having a first cross-sectional region;
A second contact connected to a second region of the first chalcogenide information storage element and having a second cross-sectional region;
A first programmable region having a state programmed by a first resistor associated with the first contact and limited within a first region of the first chalcogenide information storage element;
A second programmable region having a state programmed by a second resistor associated with the second contact and limited within a second region of the first chalcogenide information storage element;
  Including
The phase change memory element, wherein the first contact and the second contact are made of different materials. The first material forming the contact is characterized by having a resistor and a constant correct resistance of the material forming the second contact, a phase change memory device according to claim 2.   The phase change memory device of claim 1, wherein the first contact and the second contact are made of different materials. Said first contact and said second contact is characterized in that it consists of equal substance physician each other, the phase change memory element according to claim 1.   The storage device further comprises a second chalcogenide information storage element, wherein the second chalcogenide information storage element comprises a third programmable area limited within a third area of the second chalcogenide information storage element. 2. The phase change memory element according to 1.   One of the first and second contacts is connected to the third region of the second chalcogenide information storage element, and the state of the third programmable region is connected to the third region. The phase change memory element of claim 6, wherein the phase change memory element is programmed by a resistor associated with one of the second contact and the second contact.   The phase change memory device of claim 7, wherein the material forming the first contact has a resistance different from that of the material forming the second contact.   The phase change memory device of claim 7, wherein the first and second contacts are formed of different materials.   The phase change memory element according to claim 7, wherein at least one of the first and second contacts has one or more cross-sectional regions.   The phase change memory device of claim 7, wherein at least one of the first and second contacts has a tapered shape.   The phase change memory device of claim 6, wherein the material forming the first contact has a resistance different from that of the material forming the second contact.   The phase change memory device of claim 6, wherein the first and second contacts are formed of different materials.   And a third contact having a third cross-sectional area and connected to a fourth area of the second chalcogenide information storage element, wherein the fourth area of the second chalcogenide information storage element includes a fourth programmable area. The phase change memory device of claim 6, wherein the state of the fourth programmable region is programmed by a resistor associated with the third contact connected to the fourth region.   The phase change memory device of claim 14, wherein the third cross-sectional area has the same size as one of the first and second cross-sectional areas. A first chalcogenide information storage element comprising a material that changes to a crystalline state or an amorphous state upon application of a heating current;
A first contact connected to a first region of the first chalcogenide information storage element and having a first cross-sectional region;
A second contact connected to a second region of the first chalcogenide information storage element and having a second cross-sectional region;
A first programmable region having a state programmed by a first resistor associated with the first contact and limited within a first region of the first chalcogenide information storage element;
A second programmable region having a state programmed by a second resistor associated with the second contact and limited within a second region of the first chalcogenide information storage element;
Including
A second chalcogenide information storage element, wherein the second chalcogenide information storage element comprises a third programmable area limited within a third area of the second chalcogenide information storage element;
And a third contact having a third cross-sectional area and connected to a fourth area of the second chalcogenide information storage element, wherein the fourth area of the second chalcogenide information storage element includes a fourth programmable area. The state of the fourth programmable region is programmed by a resistor associated with the third contact connected to the fourth region;
The phase change memory element according to claim 3, wherein the third cross-sectional area has a different size from one of the first and second cross-sectional areas.   The phase change memory device of claim 14, wherein the material forming the third contact has a resistance different from that of the material forming at least one of the first and second contacts.   The phase change memory device of claim 14, wherein at least one of the first and second contacts and the third contact are made of different materials.   The phase change memory device of claim 14, wherein the third contact has one or more cross-sectional regions.   The phase change memory device of claim 14, wherein the third contact has a tapered shape.   The phase change memory element according to claim 14, wherein the phase change memory element is capable of storing data that can have a plurality of values.