JP5142644B2 - Data processing circuit - Google Patents

Description

  The present invention relates to a data processing circuit that executes data writing and data reading for any of a plurality of memory devices.

An example of this type of device is disclosed in Patent Document 1. According to this background art, image data of a document read by an image input device is once stored in a memory and then output to a printer engine for printing on paper. The image data stored in the memory is also compressed by the compressor, and the compressed image data is stored in the HDD via the memory. The memory has an input / output area for storing image data read by the image input device and a storage area for storing image data compressed by the compressor. Such input / output of image data to the memory is arbitrated by an arbiter.
JP 2005-332372 A [G06F 13/36]

  However, in the background art, which image data is stored in the input / output area and which image data is stored in the storage area is fixed in advance. That is, the storage destination of the image data of interest is not changed between the input / output area and the storage area in accordance with the operation status. For this reason, in the background art, the load applied to the memory access operation may be biased to one side.

  Therefore, a main object of the present invention is to provide a data processing circuit capable of adaptively controlling loads of a plurality of memories.

A data processing circuit (IC1: reference number corresponding to the embodiment; the same applies hereinafter) according to the invention of claim 1 has a plurality of output terminals respectively connected to a plurality of memory devices, a plurality of output means, each data output process of outputting the data from the specified output end run (58, 78a, 78b, 108 , 122), each having a plurality of inputs connected to a plurality of memory devices , A plurality of input means (60, 80, 88, 96, 110) each for executing data input processing for inputting data from a designated input terminal among a plurality of input terminals , each assigned to a plurality of output means and designated output A plurality of first holding means (R1, R3, R4, R8, R10) each holding first identification information for identifying an end, and a second identification information assigned to each of the plurality of input means and for identifying a designated input end A plurality of second holding means (R2, R5, R6, R7, R9) each holding And changing means (S1, S11) for changing a part of the first identification information held by each of the plurality of first holding means and the second identification information held by each of the plurality of second holding means according to the mode. , S23) .

  That is, the write destination of the data output from the output means depends on the first identification information held by the first holding means, and the read source of the data input by the input means is the second held by the second holding means. Depends on identification information. Therefore, by updating the first identification information and the second identification information respectively held by the first holding unit and the second holding unit, it is possible to adaptively control the loads on the plurality of memories.

  A data processing circuit according to a second aspect of the present invention is dependent on the first aspect, further comprising a fetching means (54) for fetching desired data, and the plurality of output means perform data output processing on the data fetched by the fetching means. Incorporated data output means (58) is included.

  A data processing circuit according to the invention of claim 3 is dependent on claim 1 or 2, and further comprises first conversion means (66, 68, 70, 72a, 72b) for performing a first conversion process on desired data, The input means includes first conversion data input means (60) for inputting data to be converted by the first conversion means.

  The data processing circuit according to the invention of claim 4 is dependent on claim 3, and the plurality of output means include first converted data output means (78a, 78b) for performing data output processing on the data converted by the first conversion means. Including.

  A data processing circuit according to a fifth aspect of the present invention is dependent on any one of the first to fourth aspects, further comprising external output means (26) for outputting desired data to the outside, wherein the plurality of input means are provided by external output means. External output data input means (80) for inputting data for output is included.

  A data processing circuit according to the invention of claim 6 is dependent on any one of claims 1 to 5, further comprising second conversion means (102, 116) for applying a second conversion process to desired data, and a plurality of input means. Includes second conversion data input means (96, 110) for inputting data to be converted by the second conversion means.

  The data processing circuit according to the invention of claim 7 is dependent on claim 6, and the plurality of output means includes second conversion data output means (108, 122) for performing data output processing on the data converted by the second conversion means. Including.

  An electronic device (10) according to the invention of claim 8 comprises the data processing circuit according to any one of claims 1 to 7.

  According to this invention, the writing destination of the data output from the output means depends on the first identification information held by the first holding means, and the reading source of the data input by the input means is held by the second holding means. Depends on the second identification information. Therefore, by updating the first identification information and the second identification information respectively held by the first holding unit and the second holding unit, it is possible to adaptively control the loads on the plurality of memories.

  The above object, other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings.

  Referring to FIG. 1, the video camera 10 of this embodiment includes an optical lens 12. The optical image of the object scene is irradiated on the imaging surface of the CMOS type imaging device 14 through the optical lens 12. A plurality of pixels are two-dimensionally arranged on the imaging surface, and charges corresponding to the amount of light are generated at each pixel. Note that the imaging surface is covered with a primary color Bayer array color filter (not shown), and the charge generated in each pixel has color information of R (Red), G (Green), or B (Blue).

  When the power is turned on, the CPU 40 gives corresponding commands to the imaging device 14, the preprocessing circuit 18, the postprocessing circuit 24, and the video display circuit 26 in order to execute through image processing on the imaging task.

  In response to a vertical synchronization signal Vsync output from an SG (Signal generator) 16, the imaging device 14 exposes the imaging surface and reads out the charges generated on the imaging surface by exposure in a raster scanning manner. The imaging surface has a resolution (number of pixels) of 6 million pixels, and the vertical synchronization signal Vsync is output every 1/30 seconds. From the imaging device 14, raw image data of 6 million pixels based on the charges generated on the imaging surface is output at a frame rate of 30 fps.

The data processing circuit IC1 performs various types of data processing on the raw image data output from the imaging device 14 using the memory devices MD1 and MD2 connected to the data buses A and B, respectively. In the following, for convenience of explanation, reference is made to Table 1 showing the allocation state of the memory devices MD1 and MD2.

  The preprocessing circuit 18 performs processing such as digital clamping, pixel defect correction, and gain control on the raw image data output from the imaging device 14, and the processed raw image data is processed by a data bus in the manner shown in FIG. Output to A. The raw image data output to the data bus A is given to the memory control circuit 20a constituting the memory device MD1, and written to the SDRAM 22a by the memory control circuit 20a.

  The post-processing circuit 24 reads the raw image data stored in the SDRAM 22a every 1/30 seconds through the memory control circuit 20a. The read raw image data is input to the input terminal IN of the post-processing circuit 24 via the data bus A and subjected to processing such as color separation, white balance adjustment, YUV conversion, and reduction zoom. As a result, YUV image data corresponding to 2 million pixels is output from the moving image output terminal M_OUT to the data bus B in the manner shown in FIG. The YUV image data output to the data bus B is given to the memory control circuit 20b constituting the memory device MD2, and is written into the SDRAM 22b by the memory control circuit 20b.

  The video display circuit 26 reads the YUV image data stored in the SDRAM 22b every 1/30 seconds through the memory control circuit 20b. The read YUV image data is input to the video display circuit 26 via the data bus B. The video display circuit 26 drives the LCD monitor 30 based on the input YUV image data, whereby a real-time moving image representing a scene, that is, a through image is displayed on the monitor screen.

  When a still image recording operation is executed by the key input device 42 in the middle of such a through image processing (the moving image recording task described later is stopped), the CPU 40 issues a corresponding command to execute the still image recording processing. This is applied to the post-processing circuit 24, the JPEG encoder 34, and the I / F circuit 36.

  The post-processing circuit 24 extracts one frame of YUV image data representing the object scene image at the time when the still image recording operation is performed. The extracted YUV image data is image data corresponding to 6 million pixels before being subjected to the reduction zoom, and is output from the still image output terminal S_OUT to the data bus B in the manner shown in FIG. The output YUV image data is given to the memory control circuit 20b via the data bus B, and is written into the SDRAM 22b by the memory control circuit 20b.

  The JPEG encoder 34 reads one frame of YUV image data stored in the SDRAM 22b through the memory control circuit 20b, inputs the read YUV image data via the data bus B, and applies the JPEG to the input YUV image data. Perform compression processing according to the method. Image data subjected to JPEG compression, that is, JPEG data, is applied to the memory control circuit 20b via the data bus B, and is written into the SDRAM 22b by the memory control circuit 20b.

  The I / F circuit 36 reads one frame of JPEG data stored in the SDRAM 22b through the memory control circuit 20b, inputs the read JPEG data from the data bus B, and records the input JPEG data in a file format. Recording on the medium 38. In this way, a still image file storing the scene image at the time when the still image recording operation is performed is obtained in the recording medium 38.

  When the moving image recording start operation is performed by the key input device 42 during the through image processing, the CPU 40 activates the moving image recording task in parallel with the imaging task, and the H264 encoder 32 and the I / F 36 on the activated moving image recording task. Is given a processing instruction.

  The H264 encoder 32 reads YUV image data corresponding to 2 million pixels stored in the SDRAM 22b every 1/30 seconds through the memory control circuit 20b, and inputs the read YUV image data from the data bus B. The YUV image data is compressed according to the H264 format. The H264-compressed image data, that is, H264 data is given to the memory control circuit 20b via the data bus B, and is written into the SDRAM 22b by the memory control circuit 20b.

  The I / F circuit 36 reads the H264 data of a plurality of frames stored in the SDRAM 22b through the memory control circuit 20b, inputs the read H264 data from the data bus B, and records the input H264 data in a file format. Recording on the medium 38. A plurality of frames of H264 data generated in response to the moving image recording start operation are accumulated in the same moving image file in the recording medium 38. When the moving image recording end operation is performed on the key input device 42, the moving image recording task is stopped. When the moving image recording task is stopped, the above-described operations by the H264 encoder 32 and the I / F circuit 36 are also stopped, whereby a moving image file is completed.

  If a still image recording operation is performed by the key input device 42 while the moving image recording task is being activated, the CPU 40 sends corresponding instructions to the post-processing circuit 24, the JPEG encoder 34, and the I to execute the still image recording process. / F circuit 36. However, since the H264 encoder 32 uses the memory device MD2 under the moving image recording task, if the memory device MD2 is allocated to the still image output terminal S_OUT of the post-processing circuit 24 and the JPEG encoder 34, the load on the memory access operation Is biased toward the memory device MD2.

  Therefore, in this embodiment, when a still image recording operation is performed while the moving image recording task is activated, the memory device MD1 is assigned to the still image output terminal S_OUT and the JPEG encoder 34 of the post-processing circuit 24. Yes. As a result, the post-processing circuit 24, the JPEG encoder 34, and the I / F circuit 36 operate as follows.

  The post-processing circuit 24 outputs 1 frame (resolution: 6 million pixels) of YUV image data representing a scene image at the time when the still image recording operation is performed to the data bus A from the still image output terminal S_OUT. The YUV image data output to the data bus A is given to the memory control circuit 20a and written to the SDRAM 22a by the memory control circuit 20a.

  The JPEG encoder 34 reads one frame of YUV image data stored in the SDRAM 22a through the memory control circuit 20a, inputs the read YUV image data from the data bus A, and performs JPEG compression on the input YUV image data. Apply. JPEG data obtained by JPEG compression is given to the memory control circuit 20a via the data bus A, and is written to the SDRAM 22a by the memory control circuit 20a.

  The I / F circuit 36 reads the JPEG data stored in the SDRAM 22a through the memory control circuit 20a, inputs the read JPEG data from the data bus A, and records a still image file that stores the input JPEG data. Create in media 38.

  Under the character control task executed in parallel with the imaging task, the CPU 40 writes the character code corresponding to the various operations described above into the SDRAM 20a (or 20b) through the memory control circuit 20a (or 20b). The character display circuit 28 reads out the character code stored in the SDRAM 22a (or 22b) through the memory control circuit 20a (or 20b), inputs the read character code from the data bus A (or B), and is inputted. The LCD monitor 30 is driven based on the character code. As a result, the character that guides the various operations described above is displayed on the monitor screen in the OSD manner.

  In the following explanation, the mode in which through image processing is activated but the movie recording task is stopped is defined as “movie display mode”, and the mode in which both the through image processing and movie recording task are activated is defined. It is defined as “Movie recording mode”.

  The preprocessing circuit 18 is configured as shown in FIG. The raw image data output from the imaging device 14 in a raster scanning manner is given to the distributor 46. The distributor 46 divides the given raw image data into four in the horizontal direction, and inputs the divided four blocks of raw image data to the preprocessing blocks PB1 to PB4, respectively.

  The preprocessing block PB1 is configured by a digital clamp circuit 48a, a pixel defect correction circuit 50a, and a gain control circuit 52a, and the preprocessing block PB2 is configured by a digital clamp circuit 48b, a pixel defect correction circuit 50b, and a gain control circuit 52b. The preprocessing block PB3 includes a digital clamp circuit 48c, a pixel defect correction circuit 50c, and a gain control circuit 52c. The preprocessing block PB4 includes a digital clamp circuit 48d, a pixel defect correction circuit 50d, and a gain control circuit 52d. .

  Therefore, the raw image data of any block is commonly subjected to digital clamping, pixel defect correction, and gain control. The raw image data output from the preprocessing blocks PB1 to PB4 is then written into the SRAM 54.

  The controller 56 issues a write request to the memory control circuit 20a or 20b every time the amount of data stored in the SRAM 54 reaches a threshold value, and generates a predetermined amount of raw image data when an approval signal is returned from the issue destination. Read from SRAM 54. The selector 58 has two output terminals respectively connected to the data buses A and B, and outputs the read raw image data from one of the two output terminals.

  The controller 56 refers to the register R1 to specify the issue destination of the write request, and the selector 58 refers to the register R1 to specify the output destination of the raw image data. Identification information for identifying the memory device MD1 is registered in the register R1. Therefore, the write request is issued toward the memory control circuit 20a constituting the memory device MD1, and the raw image data read from the SRAM 54 is output toward the data bus A.

  Each pixel forming the raw image data is represented by 12 bits, and the 12-bit pixel data output from each of the preprocessing blocks PB1 to PB4 is written in the SRAM 54 in a time division manner. However, 48-bit pixel data corresponding to four horizontal pixels is simultaneously read from the SRAM 54.

  The post-processing circuit 24 is configured as shown in FIG. The controller 64 issues a read request to the memory control circuit 20a or 20b every time the amount of data stored in the SRAM 62 falls below the threshold value, and executes data writing to the SRAM 62 when an approval signal is returned from the issue destination. To do. The raw image data to be written in the SRAM 62 is a predetermined amount of data output from the read request issuing destination, and is transferred to the data bus A or B. The selector 60 has two input terminals respectively connected to the data buses A and B, and has one output terminal connected to the SRAM 62. The raw image data transferred through the data bus A or B is given to the SRAM 62 through such a selector 60.

  The controller 64 refers to the register R2 to identify the issue destination of the read request, and the selector 60 refers to the register R2 to identify the input source of the raw image data. Identification information indicating the memory device MD1 is registered in the register R2. Therefore, the read request is issued toward the memory control circuit 20a constituting the memory device MD1, and the raw image data is input to the selector 60 via the data bus A.

  The color separation circuit 66 performs color separation processing on the raw image data stored in the SRAM 62. As a result, RGB image data in which each pixel has all the R, G, and B color information is generated. The white balance adjustment circuit 68 adjusts the white balance of the RGB image data output from the color separation circuit 66, and the YUV conversion circuit 70 converts the RGB image data output from the white balance adjustment circuit 68 into YUV image data.

  The zoom circuit 72a performs reduction zoom on the YUV image data output from the YUV conversion circuit 70, and reduces the resolution (number of pixels) from 6 million pixels to 2 million pixels. The YUV image data having a reduced resolution is written to the SRAM 76a.

  Similar to the controller 54 shown in FIG. 3, the controller 74a issues a write request to the memory control circuit 20a or 20b every time the amount of data stored in the SRAM 76a reaches a threshold value, and an approval signal is returned from the issue destination. Sometimes a predetermined amount of YUV image data is read from the SRAM 76a. The selector 78a has two output terminals respectively connected to the data buses A and B, and outputs YUV image data read from the SRAM 76a from one of the two output terminals.

  The controller 74a refers to the register R3 to specify the issue destination of the write request, and the selector 78a refers to the register R3 to specify the output destination of the YUV image data. Identification information indicating the memory device MD2 is registered in the register R3. Therefore, the write request is issued toward the memory control circuit 20b constituting the memory device MD2, and the raw image data read from the SRAM 54 is output toward the data bus B.

  The zoom circuit 72b extracts one frame of YUV image data at the time when the still image recording operation is performed, and writes the extracted YUV image data in the SRAM 76b with a resolution of 6 million pixels. As described above, the controller 74b issues a write request to the memory control circuit 20a or 20b every time the amount of data stored in the SRAM 76b reaches a threshold value, and when the approval signal is returned from the issue destination, The YUV image data is read from the SRAM 76b. The selector 78b has two output terminals respectively connected to the data buses A and B, and outputs the read YUV image data from one of the two output terminals.

  The controller 74b refers to the register R4 to identify the issue destination of the write request, and the selector 78b refers to the register R4 to identify the output destination of the YUV image data. In the register R4, identification information of the memory device MD2 is registered corresponding to the moving image display mode, while identification information of the memory device MD1 is registered corresponding to the moving image recording mode. Therefore, under the moving image display mode, a write request is issued toward the memory control circuit 20b constituting the memory device MD2, and the raw image data read from the SRAM 54 is output toward the data bus B. On the other hand, under the moving image recording mode, the write request is issued toward the memory control circuit 20a constituting the memory device MD1, and the raw image data read from the SRAM 54 is output toward the data bus A. .

  The video display circuit 26 is configured as shown in FIG. Similar to the controller 64 shown in FIG. 4, the controller 82 issues a read request to the memory control circuit 20a or 20b each time the amount of data stored in the SRAM 84 falls below the threshold, and an approval signal is returned from the issue destination. Sometimes data is written to the SRAM 84. The YUV image data to be written to the SRAM 84 is a predetermined amount of data output from the read request issuance destination, and is transferred to the data bus A or B. The selector 80 has two input terminals respectively connected to the data buses A and B, and has one output terminal connected to the SRAM 84. The raw image data transferred through the data bus A or B is given to the SRAM 84 through such a selector 80.

  The controller 82 refers to the register R5 to identify the issue destination of the read request, and the selector 80 refers to the register R5 to identify the input source of the YUV image data. Identification information indicating the memory device MD2 is registered in the register R5. Therefore, the read request is issued to the memory control circuit 20b constituting the memory device MD2, and the YUV image data is input to the selector 80 via the data bus B. The encoder 86 performs a predetermined encoding process on the YUV image data stored in the SRAM 84 and outputs the encoded image signal to the LCD monitor 30.

  The video display circuit 26 is configured as shown in FIG. Similar to the controller 82 shown in FIG. 5, the controller 90 issues a read request to the memory control circuit 20a or 20b every time the amount of data stored in the SRAM 92 falls below the threshold, and an approval signal is returned from the issue destination. Sometimes data is written to the SRAM 92. The character code to be written in the SRAM 92 is a predetermined amount of code output from the read request issuing destination, and is transferred to the data bus A or B. Selector 88 has two input terminals connected to data buses A and B, respectively, and has one output terminal connected to SRAM 92. The character code transferred through the data bus A or B is given to the SRAM 92 through such a selector 88.

  The controller 90 refers to the register R6 to identify the issue destination of the read request, and the selector 88 refers to the register R6 to identify the character code input source. Identification information indicating the memory device MD1 (or MD2) is registered in the register R6. Therefore, the read request is issued to the memory control circuit 20a (or 20b) constituting the memory device MD1 (or MD2), and the character code is input to the selector 88 via the data bus A (or B). The character generator 94 creates a character signal corresponding to the character code stored in the SRAM 92 and outputs the created character signal to the LCD monitor 30.

  The H264 encoder 32 is configured as shown in FIG. The controller 98 issues a read request to the memory control circuit 20a or 20b every time the amount of data stored in the SRAM 100 falls below the threshold, and executes data writing to the SRAM 100 when an approval signal is returned from the issue destination. To do. The YUV image data to be written in the SRAM 100 is a predetermined amount of data output from the read request issuance destination, and is transferred through the data bus A or B. Selector 96 has two input terminals respectively connected to data buses A and B, and has one output terminal connected to SRAM 100. The YUV image data transferred through the data bus A or B is given to the SRAM 100 through such a selector 96.

  The moving image compression circuit 102 reads the YUV image data stored in the SRAM 100, performs H264 compression on the read YUV image data, and writes the H264 data in the SRAM 106. The controller 104 issues a write request to the memory control circuit 20a or 20b every time the amount of data stored in the SRAM 106 reaches a threshold value, and outputs a predetermined amount of H264 data when the approval signal is returned from the issue destination. Read from. The selector 108 has two output terminals connected to the data buses A and B, respectively, and outputs the read YUV image data from one of the two output terminals.

  The controller 98 refers to the register R7 to identify the issue destination of the read request, and the selector 96 refers to the register R7 to identify the input destination of the YUV image data. Similarly, the controller 104 refers to the register R8 to identify the issue destination of the write request, and the selector 108 refers to the register R8 to identify the output destination of the H264 data. Identification information indicating the memory device MD2 is registered in each of the registers R7 and R8. Therefore, the read request and the write request are issued toward the memory control circuit 20b configuring the memory device MD2. The YUV image data is input to the selector 96 via the data bus B, and the H264 data read from the SRAM 108 is output toward the data bus B.

  The JPEG encoder 34 is configured as shown in FIG. The controller 112 issues a read request to the memory control circuit 20a or 20b each time the amount of data stored in the SRAM 114 falls below the threshold value, and executes data writing to the SRAM 114 when an approval signal is returned from the issue destination. To do. The YUV image data to be written to the SRAM 114 is a predetermined amount of data output from the read request issuance destination, and is transferred to the data bus A or B. Selector 110 has two input terminals connected to data buses A and B, respectively, and one output terminal connected to SRAM 114. The YUV image data transferred through the data bus A or B is given to the SRAM 114 through such a selector 110.

  The still image compression circuit 116 reads the YUV image data stored in the SRAM 114, performs JPEG compression on the read YUV image data, and writes the JPEG data in the SRAM 120. The controller 118 issues a write request to the memory control circuit 20a or 20b every time the amount of data stored in the SRAM 120 reaches a threshold value, and outputs a predetermined amount of JPEG data to the SRAM 120 when an approval signal is returned from the issue destination. Read from. The selector 122 has two output terminals respectively connected to the data buses A and B, and outputs the read YUV image data from one of the two output terminals.

  The controller 112 refers to the register R9 to identify the issue destination of the read request, and the selector 110 refers to the register R9 to identify the input destination of the YUV image data. Similarly, the controller 118 refers to the register R10 to specify the issue destination of the write request, and the selector 122 refers to the register R10 to specify the output destination of the JPEG data.

  In each of the registers R9 and R10, identification information indicating the memory device MD2 is registered corresponding to the moving image display mode, while identification information indicating the memory device MD1 is registered corresponding to the moving image recording mode. Therefore, in the moving image display mode, the read request and the write request are issued toward the memory control circuit 20b that constitutes the memory device MD2. The YUV image data is input to the selector 110 via the data bus B, and the JPEG data read from the SRAM 120 is output toward the data bus B. On the other hand, in the moving image recording mode, the read request and the write request are issued toward the memory control circuit 20a configuring the memory device MD1. The YUV image data is input to the selector 110 via the data bus A, and the JPEG data read from the SRAM 120 is output toward the data bus A.

  The CPU 40 executes in parallel a plurality of tasks including an imaging task shown in FIG. 9 and a moving image recording task and a character control task (not shown). Note that control programs corresponding to these tasks are stored in the flash memory 44.

  In step S1 shown in FIG. 9, memory allocation is initialized. The memory device MD1 is assigned to the input terminal IN and the character display circuit 28 of the preprocessing circuit 18, the postprocessing circuit 24. The memory device MD2 is assigned to the moving image output terminal M_OUT and the still image output terminal S_OUT, the video display circuit 26, and the JPEG encoder 34 of the post-processing circuit 24. Specifically, the identification information of the memory device MD1 is registered in the registers R1, R2, and R6, and the identification information of the memory device MD2 is registered in the registers R3, R4, R5, R9, and R10.

  Note that the memory allocation to the H264 encoder 32 may be indefinite at this point. Further, the memory device MD2 may be assigned to the character display circuit 28 instead of the memory device MD1.

  In step S3, through image processing is executed. As a result, a through image of the object scene is displayed on the LCD monitor 30. In step S5, it is determined whether or not a moving image recording start operation has been performed. In step S7, it is determined whether or not a still image recording operation has been performed. If YES is determined in the step S7, a still image recording process is executed in a step S9. As a result, the scene image at the time when the still image recording operation is performed is recorded on the recording medium 38 in the file format. When the process of step S9 is completed, the process returns to step S5.

  When the moving image recording start operation is performed, the process proceeds from step S5 to step S11, and a part of memory allocation is changed so as to conform to the moving image recording mode. Specifically, the memory device MD2 is assigned to the H264 encoder 32, and the memory device assigned to the still image output terminal S_OUT of the post-processing circuit 24 and the JPEG encoder 34 is changed from “MD2” to “MD1”. This change process is executed in the vertical blanking period in synchronization with the vertical synchronization signal Vsync. As a result, the identification information of the memory device MD2 is registered in the registers R7 and R8, and the identification information of the memory device MD1 is registered in the registers R4, R9, and R10. When the change of the memory allocation is completed, the moving image recording task is activated in step S13. As a result, a moving image representing the scene is recorded on the recording medium 38 in a file format.

  In step S15, it is determined whether or not a moving image recording end operation has been performed. In step S17, it is determined whether or not a still image recording operation has been performed. If YES is determined in the step S17, a still image recording process similar to the above-described step S9 is executed in a step S19. As a result, the scene image at the time when the still image recording operation is performed is recorded on the recording medium 38 in the file format. When the process of step S19 is completed, the process returns to step S15.

  When the moving image recording end operation is performed, YES is determined in step S15, and the moving image recording task is stopped in step S21. As a result, the recording of the moving image on the recording medium 38 is finished, and the moving image file is completed. In step S23, memory allocation is initialized, and when initialization is completed, the process returns to step S5.

  As can be seen from the above description, the preprocessing circuit 18 repeatedly captures image data representing the object scene. The post-processing circuit 24, the video display circuit 26, and the H264 encoder 32 perform moving image processing (moving image display mode: post-processing and video display) according to a designated mode (moving image display mode or moving image recording mode) on the image data captured by the pre-processing circuit 18. , Moving image recording mode: post-processing, video display and H264 compression). Further, the post-processing circuit 24 and the JPEG encoder 34 perform still image processing (post-processing and JPEG compression) on a part (= 1 frame) of the image data captured by the pre-processing circuit 18. Therefore, the moving image processing amounts of the post-processing circuit 24, the video display circuit 26, and the H264 encoder 32 differ depending on the operation mode.

  The memory control circuits 20a and 20b write and / or write image data (2 million pixel YUV image data or H264 data) related to moving image processing and image data (6 million pixel YUV image data or JPEG data) related to still image processing. Alternatively, the SDRAMs 22a and 22b are respectively accessed for reading. The CPU 40 changes the memory control circuit responsible for the memory access operation of the image data related to the still image processing between the memory control circuits 20a and 20b according to the moving image processing amount (according to the operation mode) (S11, S23). .

  Specifically, the memory access operation of the image data related to the moving image processing is performed by the memory control circuit 20b. However, the H264 encoder 32 is started in the moving image recording mode and stopped in the moving image display mode. That is, the memory access operation for H264 data is executed only in the moving image recording mode. The CPU 40 assigns the memory access operation of the image data related to the still image processing to the memory control circuit 20b corresponding to the moving image display mode and to the memory control circuit 20a corresponding to the moving image recording mode.

  The SDRAMs 22a and 22b store image data related to moving image processing and image data related to still image processing. Since the content of the moving image processing depends on the designated mode, the load applied to the memory access operation of the image data related to the moving image processing differs depending on the mode. Therefore, in this embodiment, the memory control circuit responsible for the memory access operation of the image data related to the still image processing is changed according to the designated mode. This changing operation is realized by updating the identification information registered in the registers R4, R9, and R10. Thereby, the load applied to the memory access operation can be adaptively distributed between the memory control circuits 20a and 20b.

  In this embodiment, a CMOS type imaging device is used, but a CCD type imaging device may be used instead. Furthermore, although a video camera is assumed in this embodiment, the data processing apparatus of the present invention can be applied to apparatuses other than the video camera.

  In this embodiment, memory allocation is performed in the manner shown in Table 1, but the combination of memory allocation is not limited to this. That is, one allocation destination of the memory devices MD1 and MD2 and the other allocation destination of the memory devices MD1 and MD2 may be interchanged with each other, and three or more memory devices and three or more data buses are provided. Also good.

  More specifically, in this embodiment, JPEG data generated in response to a still image recording operation in the moving image display mode is written to the SDRAM 22b, and H264 data generated in response to the moving image recording operation is also written to the SDRAM 22b. I am doing so. However, the JPEG data generated under the moving image display mode and the H264 data generated in response to the moving image recording operation may be written in the SDRAM 22a. In this case, the write destination of JPEG data generated in response to the still image recording operation in the moving image recording mode is the SDRAM 22b.

  In this embodiment, one pixel is represented by 12 bits, but one pixel may be represented by 14 bits.

It is a block diagram which shows an example of a structure of the video camera of this Example. (A) is a timing diagram showing an example of the output operation of the pre-processing circuit, (B) is a timing diagram showing an example of the moving image output operation of the post-processing circuit, and (C) is a still image output of the post-processing circuit. It is a timing diagram which shows an example of operation | movement. It is a block diagram which shows an example of a structure of the pre-processing circuit applied to FIG. 1 Example. It is a block diagram which shows an example of a structure of the post-processing circuit applied to FIG. 1 Example. It is a block diagram which shows an example of a structure of the video display circuit applied to the FIG. 1 Example. It is a block diagram which shows an example of a structure of the character display circuit applied to the FIG. 1 Example. It is a block diagram which shows an example of a structure of the H264 encoder applied to FIG. 1 Example. It is a block diagram which shows an example of a structure of the JPEG encoder applied to the FIG. 1 Example. It is a flowchart which shows a part of operation | movement of CPU applied to the FIG. 1 Example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Video camera 14 ... Imaging device 18 ... Pre-processing circuit 24 ... Post-processing circuit A, B ... Bus 20a, 20b ... Memory control circuit 22a, 22b ... SDRAM
26 ... Video display circuit 32 ... H264 encoder 34 ... JPEG encoder 40 ... CPU

Claims (8)

A plurality of output means each having a plurality of output terminals connected to a plurality of memory devices, each of which executes data output processing for outputting data from a specified output terminal among the plurality of output terminals ;
A plurality of input means each having a plurality of input terminals respectively connected to the plurality of memory devices , each of which executes data input processing for inputting data from a designated input terminal among the plurality of input terminals ;
A plurality of first holding means respectively assigned to the plurality of output means and each holding first identification information for identifying the designated output end;
A plurality of second holding means respectively assigned to the plurality of input means and each holding second identification information for identifying the designated input end; and
Changing means for changing the first identification information held by each of the plurality of first holding means and a part of the second identification information held by each of the plurality of second holding means according to the mode ; Data processing circuit. It further includes a capturing means for capturing desired data,
The data processing circuit according to claim 1, wherein the plurality of output units include a capture data output unit that performs the data output process on the data captured by the capture unit. A first conversion means for performing a first conversion process on the desired data;
3. The data processing circuit according to claim 1, wherein the plurality of input means include first conversion data input means for inputting data to be converted by the first conversion means.   4. The data processing circuit according to claim 3, wherein the plurality of output means include first converted data output means for performing the data output processing on the data converted by the first conversion means. An external output means for outputting desired data to the outside;
5. The data processing circuit according to claim 1, wherein the plurality of input means include external output data input means for inputting data to be output by the external output means. A second conversion means for performing a second conversion process on the desired data;
6. The data processing circuit according to claim 1, wherein the plurality of input means include second conversion data input means for inputting data to be converted by the second conversion means.   7. The data processing circuit according to claim 6, wherein the plurality of output means include second converted data output means for performing the data output processing on the data converted by the second conversion means.   An electronic device comprising the data processing circuit according to claim 1.

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