JP5142103B2 - Circuit board, substrate with built-in electronic device, integrated circuit device, optical waveguide with integrated circuit, and method for assembling substrate with built-in electronic device - Google Patents

Circuit board, substrate with built-in electronic device, integrated circuit device, optical waveguide with integrated circuit, and method for assembling substrate with built-in electronic device Download PDF

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JP5142103B2
JP5142103B2 JP2008066716A JP2008066716A JP5142103B2 JP 5142103 B2 JP5142103 B2 JP 5142103B2 JP 2008066716 A JP2008066716 A JP 2008066716A JP 2008066716 A JP2008066716 A JP 2008066716A JP 5142103 B2 JP5142103 B2 JP 5142103B2
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chip
electronic device
circuit board
substrate
integrated circuit
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JP2009224522A (en
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光正 小柳
徹 田中
誉史 福島
誠 藤原
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Tohoku University NUC
Sumitomo Bakelite Co Ltd
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Tohoku University NUC
Sumitomo Bakelite Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141Disposition
    • H01L2224/1418Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/14181On opposite sides of the body

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  • Optical Couplings Of Light Guides (AREA)
  • Optical Integrated Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of miniaturizing an integrated circuit formed by packaging chip-type electronic devices in a multi-layered board, increasing the number of packaged chip-type electronic devices, and achieving cost reduction. <P>SOLUTION: There are provided a board 1 with built-in electronic devices in which chip-type electronic devices 4 are assembled in device packaging holes 31 formed in a circuit board 3, the circuit board 3 in which terminal portions 34 for energizing connections of the chip-type electronic devices 4 protrude in opening portions of the device packaging holes 31, a method for assembling the board 1 with built-in electronic devices, and an optical waveguide 10 with an integrated circuit using the board 1 with built-in electronic devices. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

本発明は、電子デバイスが実装される回路基板、電子デバイス内蔵基板、集積回路デバイス、集積回路付き光導波路、電子デバイス内蔵基板の組立方法に関する。   The present invention relates to a circuit board on which an electronic device is mounted, an electronic device built-in substrate, an integrated circuit device, an optical waveguide with an integrated circuit, and a method for assembling an electronic device built-in substrate.

従来、光素子、半導体パッケージ等のチップ形電子デバイスの回路基板への実装は、回路基板主面へのフリップチップ実装、ワイヤボンディングが主流である。
ところで、電子機器に組み込まれるLSI等の集積回路デバイスにあっては、電子機器の多機能化、小型化の要求に鑑みて、多層化(多層基板の採用)、これによる小型化、高密度化が進展しつつある。回路基板を複数積層した多層基板へのチップ形電子デバイスの実装は、多層基板の最外層に位置する基板(積層の両端の基板の一方又は両方)が形成する多層基板の端面(デバイス実装面)へのフリップチップ実装、ワイヤボンディングによる実装が一般的である(例えば非特許文献1)。
Sharifi, H.; Tae-Young Choi; Mohammadi, S.:Self-Aligned Wafer-Level Integration Technology With High-Density Interconnects and Embedded Passives,IEEE Transactions on [see also Components, Packaging and Manufacturing Technology, Part B: Advanced Packaging, IEEE Transactions on] Volume: 30, Issue: 1,(2007) Page(s): 11-18
Conventionally, chip-type electronic devices such as optical elements and semiconductor packages are mounted on a circuit board by flip chip mounting or wire bonding on the main surface of the circuit board.
By the way, in the case of integrated circuit devices such as LSIs incorporated in electronic equipment, in view of the demand for multi-functionality and miniaturization of electronic equipment, multilayering (adoption of a multilayer substrate), thereby miniaturization and high density. Is progressing. The chip-type electronic device is mounted on a multilayer substrate in which a plurality of circuit boards are stacked. The end surface of the multilayer substrate (device mounting surface) formed by the substrate (one or both of the substrates on both ends of the stack) located on the outermost layer of the multilayer substrate. Flip chip mounting and wire bonding mounting are generally used (for example, Non-Patent Document 1).
Sharifi, H .; Tae-Young Choi; Mohammadi, S .: Self-Aligned Wafer-Level Integration Technology With High-Density Interconnects and Embedded Passives, IEEE Transactions on [see also Components, Packaging and Manufacturing Technology, Part B: Advanced Packaging , IEEE Transactions on] Volume: 30, Issue: 1, (2007) Page (s): 11-18

しかしながら、上述のように、多層基板の最外層に位置する基板にチップ形電子デバイスを実装する構成では、実装したチップ形電子デバイスが多層基板の外側に突起状に存在することになるため、集積回路デバイスのサイズの小型化には限界がある。また、実装出来るチップ形電子デバイスの数に限界があり実装数の増加が困難であるといった不満があった。また、複雑なパッケージングを必要とし低コスト化が困難、といった問題もあった。   However, as described above, in the configuration in which the chip-type electronic device is mounted on the substrate located on the outermost layer of the multilayer substrate, the mounted chip-type electronic device exists in a protruding shape on the outside of the multilayer substrate. There is a limit to reducing the size of circuit devices. In addition, there was a complaint that the number of chip-type electronic devices that can be mounted is limited and it is difficult to increase the number of mounted electronic devices. In addition, there is a problem that it is difficult to reduce the cost because complicated packaging is required.

本発明は、前記課題に鑑みて、回路基板を複数積層して構成される集積回路デバイスの小型化、チップ形電子デバイスの実装数の増加、低コスト化、を容易に実現できる回路基板、電子デバイス内蔵基板、集積回路デバイス、集積回路付き光導波路、電子デバイス内蔵基板の組立方法の提供を目的としている。   In view of the above problems, the present invention provides a circuit board and an electronic device that can easily realize downsizing of an integrated circuit device formed by stacking a plurality of circuit boards, increasing the number of mounted chip-type electronic devices, and reducing costs. An object of the present invention is to provide an assembly method for a device-embedded substrate, an integrated circuit device, an optical waveguide with an integrated circuit, and an electronic device-embedded substrate.

上記課題を解決するために、本発明では以下の構成を提供する。
本発明は、半導体基板に、該半導体基板の両面の少なくとも一方に形成された配線部と、前記半導体基板に貫設された貫通配線と、前記半導体基板に貫設された貫通孔でありチップ形電子デバイスが組み込まれるデバイス収納孔と、前記半導体基板の両面の内の一方の前記配線部から前記デバイス収納孔の片端の開口部に張り出され、前記チップ形電子デバイスに設けられている電極パッドが電気導通可能に接続される突起状の端子部とが設けられており、前記デバイス収納孔の断面寸法が、前記チップ形電子デバイスの前記デバイス収納孔の軸心に垂直の断面寸法を、前記電極パッドのコンタクト面の寸法の5〜195%だけ大きくした寸法になっており、前記チップ形電子デバイスが角形のチップであり、前記チップ形電子デバイスを収納する断面矩形の前記デバイス収納孔は、その断面外周の互いに平行な2組の辺の内の少なくとも1組の辺の長さが、前記チップ形電子デバイスの対角線寸法よりも短く、前記チップ形電子デバイスは、前記デバイス収納孔内で、前記デバイス収納孔の断面寸法とチップ形電子デバイスの断面寸法との差によって設定・規制されつつ回転移動可能であり、かつ前記デバイス収納孔の軸心を中心とする軸回り方向の前記チップ形電子デバイスの回転移動の全範囲で、前記チップ形電子デバイスの全ての電極パッドのコンタクト面が、それぞれ前記端子部のコンタクト面に平面視において重なった部分を有する回路基板を提供する。
本発明は、前記回路基板の前記デバイス収納孔に前記チップ形電子デバイスが組み込まれ、前記チップ形電子デバイスの前記電極パッドが導電性のボンディング用金属材料によってボンディングして電気導通可能に接続されて電子デバイス内蔵基板を提供する。
本発明は、前記デバイス収納孔内に、前記デバイス収納孔内面と前記チップ形電子デバイスとの間を埋める充填樹脂部を具備することが好ましい。
本発明は、前記デバイス収納孔に、前記チップ形電子デバイスとして発光素子又は受光素子である光素子が組み込まれ、この光素子は、前記端子部にボンディングされた前記電極パッドが設けられている面であるパッド設置面に発光部又は受光部を有することが好ましい。
本発明は、前記デバイス収納孔内に、前記デバイス収納孔内面と前記光素子との間を埋める充填樹脂部を具備し、前記充填樹脂部から連続して前記光素子の前記パッド設置面に形成された透明樹脂層によって前記発光部又は前記受光部が覆われていることが好ましい。
前記回路基板には、前記デバイス収納孔の前記端子部が設けられている開口部を塞ぐ、透明の開口部封止部材が設けられていることが好ましい。
前記回路基板には前記デバイス収納孔が複数形成されており、前記デバイス収納孔に組み込まれた発光素子と、該発光素子が組み込まれたデバイス収納孔とは別のデバイス収納孔に組み込まれた受光素子とを具備することが好ましい。
前記回路基板には前記デバイス収納孔が複数形成されており、発光素子が組み込まれたデバイス収納孔と、前記チップ形電子デバイスとして前記発光素子の駆動用のドライバー素子が組み込まれたデバイス収納孔とを具備し、前記発光素子と前記ドライバー素子とが、前記回路基板に形成されたチップ間接続用配線を介して電気的に接続されていることが好ましい。
前記回路基板には前記デバイス収納孔が複数形成されており、受光素子が組み込まれたデバイス収納孔と、前記チップ形電子デバイスとして前記受光素子の受光信号変換用のレシーバー素子が組み込まれたデバイス収納孔とを具備し、前記受光素子と前記レシーバー素子とが、前記回路基板に形成されたチップ間接続用配線を介して電気的に接続されていることが好ましい。
前記回路基板の両面の少なくとも一方に、電極パッドと、この電極パッドに実装された金属バンプとを具備することが好ましい。
前記チップ形電子デバイスは、前記パッド設置面とは反対の側に第2電極パッドを具備することが好ましい。
前記第2電極パッドに金属バンプが実装されていることが好ましい。
本発明は、前記電子デバイス内蔵基板であるベース回路基板と、このベース回路基板の片面に実装された集積回路部とを具備する集積回路デバイスを提供する。
本発明は、前記集積回路部が、ベース回路基板に多層に積層された集積回路用基板の回路配線を互いに接続して構成され、この集積回路部を構成する複数の集積回路用基板の内の1以上が、前記電子デバイス内蔵基板であることが好ましい。
本発明は、シート形光導波路に、前記電子デバイス内蔵基板であるベース回路基板を具備する前記集積回路デバイスが1又は複数実装され、前記シート形光導波路は、前記集積回路デバイスに組み込まれている発光素子に対応する位置、前記集積回路デバイスに組み込まれている受光素子に対応する位置に、前記発光素子と前記受光素子とを該シート形光導波路を介して光接続する光路形成用のミラー部を具備する集積回路付き光導波路を提供する。
本発明は、さらに、前記シート形光導波路の前記ベース回路基板とは反対の側に積層された第2回路基板を具備し、前記シート形光導波路に貫設されたボンディング材料収納孔に、前記第2回路基板の回路配線と前記集積回路デバイスの前記ベース回路基板に設けられている電極パッドとを電気的に接続したボンディング用金属材料が収納され、前記第2回路基板の回路配線に電気導通可能に接続された複数の前記集積回路デバイスの回路同士が前記第2回路基板の回路配線を介して電気的に接続されていることが好ましい。
本発明は、前記回路基板の前記デバイス収納孔にチップ形電子デバイスを組み込み、このチップ形電子デバイスに設けられている電極パッドに予め実装しておいた金属バンプをリフローして、前記電極パッドを前記端子部にボンディングする電子デバイス内蔵基板の組立方法を提供する。
本発明は、前記電極パッドを前記端子部にボンディングした後に、前記デバイス収納孔内面と前記チップ形電子デバイスとの間を埋める充填樹脂部を形成する充填樹脂部形成工程を具備することが好ましい。
本発明は、前記充填樹脂部形成工程において、前記回路基板の、前記デバイス収納孔の前記端子部が設けられている開口部を、開口部封止部材を用いて塞いだ状態で、前記デバイス収納孔内に液状の樹脂材料を注入して前記充填樹脂部を形成することが好ましい。
本発明は、透明の開口部封止部材を用いることが好ましい。
本発明は、前記チップ形電子デバイスとして、受光素子又は発光素子である光素子を用い、この光素子の受/発光部が設けられている端面に備えられている電極パッドに予め実装しておいた金属バンプをリフローして、前記電極パッドを前記端子部にボンディングすることが好ましい。
本発明は、前記電子デバイス内蔵基板の組立方法に係る前記電子デバイス内蔵基板の組立方法において、前記充填樹脂部形成工程にて、前記充填樹脂部から連続して前記光素子の前記端面を覆う透明樹脂層を形成することが好ましい。
In order to solve the above problems, the present invention provides the following configuration.
The present invention relates to a chip-shaped semiconductor substrate having a wiring portion formed on at least one of both surfaces of the semiconductor substrate, a through wiring penetrating the semiconductor substrate, and a through hole penetrating the semiconductor substrate. A device housing hole into which the electronic device is incorporated, and an electrode pad provided in the chip-type electronic device, which projects from one of the wiring portions on both sides of the semiconductor substrate to an opening at one end of the device housing hole And a projecting terminal portion connected so as to be electrically conductive, and the cross-sectional dimension of the device housing hole is perpendicular to the axis of the device housing hole of the chip-type electronic device, The size is increased by 5 to 195% of the size of the contact surface of the electrode pad, and the chip-type electronic device is a square chip, and the chip-type electronic device is accommodated. Said device receiving holes of rectangular cross section which has a length of at least one pair of sides of the mutually parallel two pairs of sides of the cross-section periphery is shorter than the diagonal dimension of the chip-type electronic device, wherein the chip-type electronic The device is capable of rotating within the device storage hole while being set and regulated by the difference between the cross-sectional dimension of the device storage hole and the cross-sectional dimension of the chip-type electronic device, and is centered on the axis of the device storage hole The contact surfaces of all the electrode pads of the chip type electronic device respectively overlap the contact surfaces of the terminal portions in plan view over the entire range of rotational movement of the chip type electronic device in the direction around the axis. A circuit board is provided.
In the present invention, the chip-type electronic device is incorporated in the device housing hole of the circuit board, and the electrode pads of the chip-type electronic device are bonded with a conductive bonding metal material so as to be electrically conductive. An electronic device embedded substrate is provided.
It is preferable that the present invention includes a filling resin portion that fills a space between the inner surface of the device storage hole and the chip-type electronic device in the device storage hole.
In the present invention, an optical element which is a light emitting element or a light receiving element is incorporated in the device housing hole as the chip-type electronic device, and the optical element is provided with the electrode pad bonded to the terminal portion. It is preferable to have a light emitting part or a light receiving part on the pad installation surface.
The present invention includes a filling resin portion that fills a space between the inner surface of the device accommodation hole and the optical element in the device accommodation hole, and is formed on the pad installation surface of the optical element continuously from the filling resin portion. It is preferable that the light emitting part or the light receiving part is covered with the transparent resin layer.
It is preferable that the circuit board is provided with a transparent opening sealing member that closes an opening provided with the terminal portion of the device housing hole.
The circuit board has a plurality of device housing holes, and a light emitting element incorporated in the device housing hole and a light receiving element incorporated in a device housing hole different from the device housing hole in which the light emitting element is incorporated. It is preferable to comprise an element.
A plurality of the device housing holes are formed in the circuit board, a device housing hole in which a light emitting element is incorporated, and a device housing hole in which a driver element for driving the light emitting element is incorporated as the chip-type electronic device, It is preferable that the light emitting element and the driver element are electrically connected via an inter-chip connection wiring formed on the circuit board.
A plurality of device housing holes are formed in the circuit board, a device housing hole in which a light receiving element is incorporated, and a device housing in which a receiver element for converting a light receiving signal of the light receiving element is incorporated as the chip-type electronic device. It is preferable that the light receiving element and the receiver element are electrically connected via an inter-chip connection wiring formed on the circuit board.
It is preferable that at least one of both surfaces of the circuit board includes an electrode pad and a metal bump mounted on the electrode pad.
The chip-type electronic device preferably includes a second electrode pad on a side opposite to the pad installation surface.
It is preferable that metal bumps are mounted on the second electrode pads.
The present invention provides an integrated circuit device comprising a base circuit board, which is the electronic device built-in substrate, and an integrated circuit portion mounted on one side of the base circuit board.
In the present invention, the integrated circuit portion is configured by connecting circuit wirings of an integrated circuit substrate laminated in multiple layers on a base circuit substrate, and the integrated circuit portion is formed of a plurality of integrated circuit substrates constituting the integrated circuit portion. It is preferable that one or more is the electronic device built-in substrate.
In the present invention, one or a plurality of the integrated circuit devices each including a base circuit board which is the electronic device built-in substrate are mounted on a sheet-shaped optical waveguide, and the sheet-shaped optical waveguide is incorporated in the integrated circuit device. An optical path forming mirror for optically connecting the light emitting element and the light receiving element via the sheet-shaped optical waveguide at a position corresponding to the light emitting element and a position corresponding to the light receiving element incorporated in the integrated circuit device. An optical waveguide with an integrated circuit comprising:
The present invention further includes a second circuit board laminated on the side of the sheet-shaped optical waveguide opposite to the base circuit board, and in the bonding material accommodation hole penetrating the sheet-shaped optical waveguide, A bonding metal material that electrically connects a circuit wiring of the second circuit board and an electrode pad provided on the base circuit board of the integrated circuit device is housed, and is electrically connected to the circuit wiring of the second circuit board. It is preferable that the circuits of the plurality of integrated circuit devices connected to each other are electrically connected to each other via circuit wiring of the second circuit board.
The present invention incorporates a chip-type electronic device into the device housing hole of the circuit board, reflows a metal bump previously mounted on an electrode pad provided in the chip-type electronic device, and Provided is an assembling method of an electronic device built-in substrate to be bonded to the terminal portion.
The present invention preferably includes a filling resin portion forming step of forming a filling resin portion that fills a space between the inner surface of the device housing hole and the chip-type electronic device after the electrode pad is bonded to the terminal portion.
According to the present invention, in the filling resin portion forming step, in the state in which the opening portion of the circuit board in which the terminal portion of the device housing hole is provided is closed using an opening portion sealing member. Preferably, the filling resin portion is formed by injecting a liquid resin material into the hole.
In the present invention, it is preferable to use a transparent opening sealing member.
In the present invention, an optical element that is a light receiving element or a light emitting element is used as the chip-type electronic device, and the chip type electronic device is mounted in advance on an electrode pad provided on an end face provided with a light receiving / emitting part of the optical element. It is preferable to reflow the metal bumps and bond the electrode pads to the terminal portions.
In the method for assembling the electronic device built-in substrate according to the method for assembling the electronic device built-in substrate, in the filling resin portion forming step, the transparent covering the end surface of the optical element continuously from the filled resin portion is provided. It is preferable to form a resin layer.

本発明によれば、チップ形電子デバイスを、回路基板のデバイス収納孔に組み込んで回路基板に実装する構成であるため、実装したチップ形電子デバイスを含む電子デバイス内蔵基板全体のサイズの小型化を容易に実現できる。
複数の集積回路用基板を積層してなる集積回路(集積回路デバイス)を構成する集積回路用基板として、本発明に係る電子デバイス内蔵基板を適用することで、集積回路デバイスの小型化を容易に実現できる。さらに、本発明に係る集積回路デバイスによれば、デバイス内蔵基板の採用によって、集積回路デバイスの内部にチップ形電子デバイスを内蔵した構成となるので、チップ形電子デバイスの実装数の増加も容易に実現できる。ひとつの集積回路デバイスに実装可能なチップ形電子デバイスの数の増加により、チップ形電子デバイスの組み合わせの自由度の向上する。
また、チップ形電子デバイスは、集積回路デバイスを構成する回路基板に内蔵されるため、パッケージングを単純化、あるいは、パッケージングが不要となり、低コスト化を容易に実現できる。
According to the present invention, since the chip-type electronic device is incorporated in the device housing hole of the circuit board and mounted on the circuit board, the overall size of the electronic device built-in substrate including the mounted chip-type electronic device can be reduced. It can be easily realized.
By applying the electronic device built-in substrate according to the present invention as an integrated circuit substrate constituting an integrated circuit (integrated circuit device) formed by laminating a plurality of integrated circuit substrates, the integrated circuit device can be easily downsized. realizable. Furthermore, according to the integrated circuit device of the present invention, the adoption of the device-embedded substrate makes it possible to increase the number of chip-type electronic devices mounted since the chip-type electronic device is built inside the integrated circuit device. realizable. By increasing the number of chip-type electronic devices that can be mounted on one integrated circuit device, the degree of freedom of combination of chip-type electronic devices is improved.
Further, since the chip-type electronic device is built in a circuit board constituting the integrated circuit device, packaging is simplified or packaging is not required, and cost reduction can be easily realized.

以下、本発明を実施した回路基板、電子デバイス内蔵基板、集積回路デバイス、集積回路付き光導波路、電子デバイス内蔵基板の組立方法について、図面を参照して説明する。
図1は本発明に係る電子デバイス内蔵基板1の構造を示す正断面図、図2は図1の電子デバイス内蔵基板1の仮想線で示した領域Aを拡大して示した拡大断面図、図3は回路基板3のデバイス収納孔31(キャビティ部)付近及びデバイス収納孔31に組み込まれるチップ形電子デバイス4を示す図、図4は本発明に係る集積回路デバイス5をシート形光導波路20に実装した集積回路付き光導波路10の構造を示す正断面図、図5は図4の集積回路付き光導波路10の仮想線で示した領域Bを拡大して示した拡大断面図である。
なお、図1〜図4において、説明の便宜上、上側を「上」、下側を「下」として説明する。但し、これは本発明の構成要素の相対関係を簡単に説明するために便宜的に規定したものであり、本発明を実施する場合の製造時や使用時の方向を限定するものではない。
Hereinafter, a method for assembling a circuit board, an electronic device built-in board, an integrated circuit device, an optical waveguide with an integrated circuit, and an electronic device built-in board according to the present invention will be described with reference to the drawings.
1 is a front sectional view showing a structure of an electronic device built-in substrate 1 according to the present invention, and FIG. 2 is an enlarged sectional view showing a region A indicated by a virtual line of the electronic device built-in substrate 1 in FIG. 3 is a view showing the chip-type electronic device 4 in the vicinity of the device housing hole 31 (cavity portion) of the circuit board 3 and the device housing hole 31, and FIG. 4 shows the integrated circuit device 5 according to the present invention in the sheet-type optical waveguide 20. FIG. 5 is an enlarged cross-sectional view showing a region B indicated by a virtual line of the optical waveguide with integrated circuit 10 of FIG. 4 in an enlarged manner.
1 to 4, for convenience of explanation, the upper side is described as “upper” and the lower side is described as “lower”. However, this is defined for convenience in order to simply explain the relative relationship of the constituent elements of the present invention, and does not limit the direction during production or use when the present invention is carried out.

図4、図5に示す集積回路付き光導波路10において、シート形光導波路20に実装された集積回路デバイス5は、本発明に係る電子デバイス内蔵基板1(以下、デバイス内蔵基板、と略称する場合がある)の片面(デバイス実装面1b。上面)に、集積回路用基板51を複数枚積層してなる集積回路部54を実装した構成であり、全体としてチップ形に形成されている。   In the optical waveguide with integrated circuit 10 shown in FIGS. 4 and 5, the integrated circuit device 5 mounted on the sheet-shaped optical waveguide 20 is an electronic device-embedded substrate 1 (hereinafter abbreviated as a device-embedded substrate) according to the present invention. The integrated circuit portion 54 formed by laminating a plurality of integrated circuit substrates 51 is mounted on one surface (device mounting surface 1b, upper surface), and is formed in a chip shape as a whole.

集積回路部54は、集積回路用基板51の回路配線52(導体回路)同士を電気的に接続してなる回路を具備する。図4中、符号53はビア配線であり、集積回路用基板51間にて回路配線52同士の電気的接続を実現する。集積回路デバイス5は、デバイス内蔵基板1の導体回路と、集積回路部54の回路とを電気的に接続して構成されている。以下、この集積回路デバイス5をLSIとも言う。   The integrated circuit portion 54 includes a circuit formed by electrically connecting circuit wirings 52 (conductor circuits) of the integrated circuit substrate 51. In FIG. 4, reference numeral 53 denotes a via wiring, which realizes electrical connection between the circuit wirings 52 between the integrated circuit substrates 51. The integrated circuit device 5 is configured by electrically connecting the conductor circuit of the device-embedded substrate 1 and the circuit of the integrated circuit unit 54. Hereinafter, the integrated circuit device 5 is also referred to as an LSI.

LSI5は、デバイス内蔵基板1の集積回路部54とは反対の側の面(デバイス内蔵基板1においてデバイス実装面1bとは反対側の面。底部側実装面1a。底面)をシート形光導波路20に接合させて、シート形光導波路20に実装されている。
図1、図5に示すように、ここで例示するデバイス内蔵基板1の底部側実装面1aは、回路基板3(詳細には回路基板3の第1主面3a(後述))に被着されたシート状(あるいはプレート状)の開口部封止部材2によって形成される面、詳細には前記開口部封止部材2の回路基板3とは反対側の面である。デバイス内蔵基板1は、前記底部側実装面1aをシート形光導波路20に重ね合わせるようにしてシート形光導波路20に被着されている。
なお、前記開口部封止部材2は透明に形成されている。
The LSI 5 has a surface on the opposite side of the integrated circuit portion 54 of the device-embedded substrate 1 (a surface opposite to the device mounting surface 1b in the device-embedded substrate 1; a bottom-side mounting surface 1a, a bottom surface) on the sheet-type optical waveguide 20. And mounted on the sheet-shaped optical waveguide 20.
As shown in FIGS. 1 and 5, the bottom side mounting surface 1 a of the device-embedded substrate 1 exemplified here is attached to a circuit board 3 (specifically, a first main surface 3 a (described later) of the circuit board 3). The surface formed by the sheet-like (or plate-like) opening sealing member 2, specifically, the surface opposite to the circuit board 3 of the opening sealing member 2. The device-embedded substrate 1 is attached to the sheet-shaped optical waveguide 20 so that the bottom side mounting surface 1 a is superimposed on the sheet-shaped optical waveguide 20.
The opening sealing member 2 is formed transparent.

図4において、LSI5は、シート形光導波路20の複数箇所に実装されている。
デバイス内蔵基板1は、LSI5において、本発明に係るベース回路基板として機能する。
In FIG. 4, the LSI 5 is mounted at a plurality of locations on the sheet-shaped optical waveguide 20.
The device built-in substrate 1 functions as a base circuit substrate according to the present invention in the LSI 5.

図1〜図3に例示したデバイス内蔵基板1は、回路基板3に形成されたデバイス収納孔31内に、チップ形電子デバイス4として光素子を組み込んで実装したものである。
以下、チップ形電子デバイス4が光素子を指す場合は、光素子、と称して説明する場合がある。また、光素子には、図中符号40を付す。
また、チップ形電子デバイスを、以下、単に、チップ、あるいは、チップ形デバイスとも言う。
The device-embedded substrate 1 illustrated in FIGS. 1 to 3 is obtained by mounting an optical element as a chip-type electronic device 4 in a device housing hole 31 formed in the circuit substrate 3.
Hereinafter, when the chip-type electronic device 4 refers to an optical element, it may be referred to as an optical element. Further, reference numeral 40 in the figure is attached to the optical element.
Hereinafter, the chip-type electronic device is also simply referred to as a chip or a chip-type device.

デバイス収納孔31は、回路基板3の複数箇所に形成されている。但し、デバイス収納孔31の形成数は1つだけであっても良い。
ひとつのデバイス収納孔31には、チップ形デバイス4(光素子)として、発光素子41又は受光素子42が組み込まれている。
発光素子41は、例えば、VCSEL(Vertical Cavity Surface Emitting LASER)等の半導体レーザである。受光素子42は、例えばPD(フォトダイオード)である。
The device housing holes 31 are formed at a plurality of locations on the circuit board 3. However, only one device storage hole 31 may be formed.
In one device housing hole 31, a light emitting element 41 or a light receiving element 42 is incorporated as a chip-type device 4 (optical element).
The light emitting element 41 is a semiconductor laser such as a VCSEL (Vertical Cavity Surface Emitting LASER). The light receiving element 42 is, for example, a PD (photodiode).

図4、図5に示すように、各光素子40は、受/発光部401(発光素子41の発光部411又は受光素子42の受光部421)をシート形光導波路20に対面配置させて、デバイス収納孔31に組み込まれている。
シート形光導波路20には、光素子40の受/発光部401に対応する位置に、受/発光部401とシート形光導波路20(詳細には光路H1)との光結合用のミラー部24が形成されている。この集積回路付き光導波路10において、ミラー部24は、シート形光導波路20の光路H1を直角に曲げて、該ミラー部24と光素子40の受/発光部401との間に、シート形光導波路20の光路H1に対して垂直の光路H2を形成する。光素子40の受/発光部401は、ミラー部24を介して、シート形光導波路20の光路H1と光結合される。ミラー部24は、具体的には、前記シート形光導波路20に前記回路基板3とは反対の側から凹むように形成された凹部によって構成されている。このミラー部24は、シート形光導波路20のコア部22の途中に介在するように形成される。
As shown in FIGS. 4 and 5, each optical element 40 has a light receiving / emitting unit 401 (the light emitting unit 411 of the light emitting element 41 or the light receiving unit 421 of the light receiving element 42) facing the sheet-shaped optical waveguide 20. It is incorporated in the device storage hole 31.
In the sheet-shaped optical waveguide 20, a mirror unit 24 for optical coupling between the light-receiving / emitting unit 401 and the sheet-shaped optical waveguide 20 (specifically, the optical path H <b> 1) is located at a position corresponding to the light receiving / emitting unit 401 of the optical element 40. Is formed. In this optical waveguide with integrated circuit 10, the mirror section 24 bends the optical path H 1 of the sheet-shaped optical waveguide 20 at a right angle, and between the mirror section 24 and the light receiving / emitting section 401 of the optical element 40, An optical path H2 perpendicular to the optical path H1 of the waveguide 20 is formed. The light receiving / emitting unit 401 of the optical element 40 is optically coupled to the optical path H <b> 1 of the sheet-shaped optical waveguide 20 through the mirror unit 24. Specifically, the mirror part 24 is configured by a recess formed in the sheet-shaped optical waveguide 20 so as to be recessed from the side opposite to the circuit board 3. The mirror part 24 is formed so as to be interposed in the middle of the core part 22 of the sheet-shaped optical waveguide 20.

ここで説明する集積回路付き光導波路10(図4参照)には、シート形光導波路20(詳細にはシート形光導波路20の光路H1)を介して互いに光接続された発光素子41と受光素子42の対が存在する。
そして、この集積回路付き光導波路10においては、シート形光導波路20を介して光接続された発光素子41と受光素子42の対が構成する信号伝送系によって、発光素子41側の電子回路と受光素子42側の電子回路との間の信号伝送を高速で行える。例えば、シート形光導波路20の複数箇所に実装されている集積回路デバイス5間の信号伝送等に、上述の光素子40の対の信号伝送系を適用して、信号伝送の高速化を図っている。
In the optical waveguide with integrated circuit 10 (see FIG. 4) described here, a light emitting element 41 and a light receiving element that are optically connected to each other via a sheet-shaped optical waveguide 20 (specifically, an optical path H1 of the sheet-shaped optical waveguide 20). There are 42 pairs.
In the optical waveguide with integrated circuit 10, the electronic circuit and the light reception on the light emitting element 41 side are received by a signal transmission system constituted by a pair of the light emitting element 41 and the light receiving element 42 optically connected via the sheet-shaped optical waveguide 20. Signal transmission with the electronic circuit on the element 42 side can be performed at high speed. For example, the signal transmission system of the pair of optical elements 40 described above is applied to signal transmission between the integrated circuit devices 5 mounted at a plurality of locations of the sheet-shaped optical waveguide 20 to increase the speed of signal transmission. Yes.

なお、図4、図5では、シート形光導波路20の複数箇所に形成したミラー部24の形成位置を模式的に示しており、図中の全てのミラー部24を、分岐部を有していない一本のコア部22について形成する構成を意味するものでは無い。シート形光導波路20に3以上のミラー部24が形成された態様は、分岐部を有するコア部22を持つシート形光導波路20、あるいは、複数本のコア部22を持つシート形光導波路20にて実現される。ミラー部24は、発光素子41と受光素子42とをシート形光導波路20のコア部22を介して光接続するために設けられるものであり、シート形光導波路20におけるミラー部24の形成位置は、発光素子41と受光素子42との光接続を実現し得るように設定される。   4 and 5 schematically show the formation positions of the mirror portions 24 formed at a plurality of locations of the sheet-shaped optical waveguide 20, and all the mirror portions 24 in the figure have branch portions. It does not mean the structure formed about the one core part 22 which is not. The aspect in which three or more mirror parts 24 are formed in the sheet-shaped optical waveguide 20 is different from the sheet-shaped optical waveguide 20 having the core part 22 having the branching part or the sheet-shaped optical waveguide 20 having the plurality of core parts 22. Realized. The mirror part 24 is provided to optically connect the light emitting element 41 and the light receiving element 42 via the core part 22 of the sheet-shaped optical waveguide 20, and the formation position of the mirror part 24 in the sheet-shaped optical waveguide 20 is The optical connection between the light emitting element 41 and the light receiving element 42 is set to be realized.

(回路基板、デバイス内蔵基板、デバイス内蔵基板の組立方法)
本発明に係るデバイス内蔵基板1は、回路基板3に形成されたデバイス収納孔31内に、チップ形電子デバイス4を組み込んだ構成になっている。
但し、回路基板3のデバイス収納孔31に組み込むチップ形デバイス4としては、光素子に限定されない。回路基板3に組み込むチップ形デバイス4としては、例えば、光素子以外の半導体素子や、パッケージ化されたICチップ等であっても良い。
なお、1つのデバイス収納孔31には、チップ形デバイス4を1つだけ組み込む。
(Circuit board, device built-in board, device built-in board assembly method)
The device-embedded substrate 1 according to the present invention has a configuration in which a chip-type electronic device 4 is incorporated in a device housing hole 31 formed in the circuit substrate 3.
However, the chip-type device 4 incorporated in the device housing hole 31 of the circuit board 3 is not limited to an optical element. The chip device 4 incorporated in the circuit board 3 may be, for example, a semiconductor element other than an optical element, a packaged IC chip, or the like.
Note that only one chip-type device 4 is incorporated in one device storage hole 31.

図6は、チップ形デバイス4として、発光素子41、該発光素子41の駆動用のドライバー素子46、受光素子42、該受光素子42の受光信号変換用のレシーバー素子47(アンプ)を、回路基板3に組み込んだ構成のデバイス内蔵基板1Aを例示している。
また、図7は、光素子以外のチップ形デバイス4を回路基板に組み込んだデバイス内蔵基板を、集積回路デバイス5の集積回路部54を構成する複数の集積回路用基板51の内の1つに適用した構成を例示する。チップ形デバイス4としては、例えば、既述のドライバー素子46、レシーバー素子47も採用可能である。図7中、集積回路デバイス5に符号5A、集積回路部54に符号54Aを付す。
FIG. 6 shows a chip-type device 4 including a light emitting element 41, a driver element 46 for driving the light emitting element 41, a light receiving element 42, and a receiver element 47 (amplifier) for converting a received light signal of the light receiving element 42. 3A illustrates a device built-in substrate 1A having a configuration incorporated in FIG.
7 shows that a device-embedded substrate in which a chip-type device 4 other than an optical element is incorporated in a circuit substrate is one of a plurality of integrated circuit substrates 51 constituting the integrated circuit portion 54 of the integrated circuit device 5. The applied configuration is illustrated. As the chip-type device 4, for example, the driver element 46 and the receiver element 47 described above can be employed. In FIG. 7, the integrated circuit device 5 is denoted by reference numeral 5A, and the integrated circuit portion 54 is denoted by reference numeral 54A.

回路基板3の前記デバイス収納孔31は、回路基板3を貫通して、回路基板3の両面(両主面。第1主面3a及び第2主面3b)に開口する貫通孔である。
図1〜図3において、符号39は、回路基板3を構成する半導体基板である。前記デバイス収納孔31は、半導体基板39に貫設されている。
The device housing hole 31 of the circuit board 3 is a through hole that penetrates the circuit board 3 and opens on both surfaces (both main surfaces; the first main surface 3a and the second main surface 3b) of the circuit board 3.
1-3, the code | symbol 39 is a semiconductor substrate which comprises the circuit board 3. In FIG. The device housing hole 31 is formed through the semiconductor substrate 39.

回路基板3は、半導体基板39に、デバイス収納孔31と、該半導体基板39の片面に形成された配線部32(導体回路)と、前記半導体基板39に貫設され前記配線部32と電気的に接続された貫通配線33と、前記配線部32が形成された前記半導体基板39の面における前記デバイス収納孔31の開口部に配線部32から張り出された突起状の端子部34とが設けられた構成(デバイス収納孔付き基板)になっている。
端子部34は、配線部32から、回路基板3の第1主面3a(デバイス収納孔31の開口部については、第1主面3aの仮想延長上)に沿って延出している。
The circuit board 3 includes a device housing hole 31 in the semiconductor substrate 39, a wiring portion 32 (conductor circuit) formed on one surface of the semiconductor substrate 39, and an electric connection between the semiconductor substrate 39 and the wiring portion 32. And a protruding terminal portion 34 protruding from the wiring portion 32 at the opening of the device housing hole 31 on the surface of the semiconductor substrate 39 on which the wiring portion 32 is formed. It is the structure (substrate with a device accommodation hole).
The terminal portion 34 extends from the wiring portion 32 along the first main surface 3a of the circuit board 3 (on the virtual extension of the first main surface 3a with respect to the opening of the device housing hole 31).

なお、本明細書においては、回路基板3の両主面3a、3bについて、前記配線部32が形成されている側の面を第1主面3a、これとは反対側の面を第2主面3bとして説明する。   In the present specification, of the two main surfaces 3a and 3b of the circuit board 3, the surface on which the wiring portion 32 is formed is the first main surface 3a, and the opposite surface is the second main surface. The surface 3b will be described.

また、図1に例示したデバイス内蔵基板1は、前記回路基板3(より詳しくは半導体基板39)に貫設された第2貫通配線11を具備している。
また、図1では、回路基板3の第1主面3aに第1金属バンプ12(底部側金属バンプ)が実装され、回路基板3の第2主面3bに第2金属バンプ13、351(デバイス実装側金属バンプ)が実装された構成のデバイス内蔵基板1を例示している。
Further, the device built-in substrate 1 illustrated in FIG. 1 includes a second through wiring 11 penetrating the circuit board 3 (more specifically, the semiconductor substrate 39).
In FIG. 1, the first metal bump 12 (bottom side metal bump) is mounted on the first main surface 3a of the circuit board 3, and the second metal bumps 13 and 351 (devices) are mounted on the second main surface 3b of the circuit board 3. A device-embedded substrate 1 having a configuration in which a mounting-side metal bump) is mounted is illustrated.

金属バンプ(ここでは、第1金属バンプ、第2金属バンプ)は、例えば半田等のボンディング用金属材料で形成されているバンプを指す。   The metal bumps (here, the first metal bump and the second metal bump) refer to bumps formed of a bonding metal material such as solder.

第1金属バンプ12は、回路基板3の第1主面3aに設けられた電極パッド14に実装されており、この電極パッド14を介して第2貫通配線11と電気的に接続されている。
第2金属バンプ13、351の内、符号351の第2金属バンプは、貫通配線33の回路基板3の第2主面3b側の端部に実装されている。符号13の第2金属バンプは、第2貫通配線11の回路基板3の第2主面3b側の端部、に実装されている。
The first metal bump 12 is mounted on an electrode pad 14 provided on the first main surface 3 a of the circuit board 3, and is electrically connected to the second through wiring 11 through the electrode pad 14.
Of the second metal bumps 13 and 351, the second metal bump 351 is mounted on the end of the through wiring 33 on the second main surface 3 b side of the circuit board 3. The second metal bump denoted by reference numeral 13 is mounted on the end of the second through wiring 11 on the second main surface 3 b side of the circuit board 3.

但し、これら金属バンプは、必要に応じて設けられるものであり、省略が可能である。デバイス内蔵基板1にあっては、金属バンプを具備せず、電子部品とのボンディング(ボンディング用金属材料によるボンディング)用の電極パッドのみを具備した構成、回路基板3の両主面3a、3bの内、片方のみに金属バンプが実装された構成も採用可能である。   However, these metal bumps are provided as necessary and can be omitted. The device-embedded substrate 1 has no metal bumps, only electrode pads for bonding with electronic components (bonding using a bonding metal material), and both main surfaces 3a and 3b of the circuit board 3. A configuration in which metal bumps are mounted on only one of them can also be employed.

回路基板3の第1主面3aにおける、第1金属バンプ12及び該第1金属バンプ12の実装用の電極パッド14の設置位置は、必ずしも、第2貫通配線11の第1主面3a側の端部に対応する位置(図1参照)に限定されない。回路基板3の第1主面3aにおいて、第2貫通配線11の第1主面3a側の端部から離隔した位置に設けられた電極パッド14及び第1金属バンプ12を、第1主面3aに形成されている配線部を介して、第2貫通配線11と電気的に接続した構成であっても良い。この場合、回路基板3の第1主面3aには、貫通配線32と端子部34とを電気的に接続する配線部32の他に、電極パッド14及び第1金属バンプ12と第2貫通配線11との接続用の配線部が設けられる。   The installation positions of the first metal bumps 12 and the electrode pads 14 for mounting the first metal bumps 12 on the first main surface 3 a of the circuit board 3 are not necessarily on the first main surface 3 a side of the second through wiring 11. It is not limited to the position (refer FIG. 1) corresponding to an edge part. On the first main surface 3a of the circuit board 3, the electrode pads 14 and the first metal bumps 12 provided at positions separated from the end of the second through wiring 11 on the first main surface 3a side are connected to the first main surface 3a. The structure electrically connected with the 2nd penetration wiring 11 via the wiring part currently formed in this may be sufficient. In this case, on the first main surface 3a of the circuit board 3, in addition to the wiring portion 32 that electrically connects the through wiring 32 and the terminal portion 34, the electrode pad 14, the first metal bump 12, and the second through wiring. 11 is provided.

回路基板3の第2主面3bにおける第2金属バンプ13、351の設置についても、貫通配線33の回路基板3の第2主面3b側の端部、第2貫通配線11の回路基板3の第2主面3b側の端部、に限定されない。第2主面3bにおいて貫通配線33の第2主面3b側の端部から離隔した位置に実装した第2金属バンプ351と貫通配線33とを、第2主面3bに形成した配線部を介して電気的に接続すること、第2主面3bにおいて第2貫通配線11の第2主面3b側の端部から離隔した位置に実装した第2金属バンプ13と第2貫通配線11とを、第2主面3bに形成した配線部を介して電気的に接続すること、も可能である。   Regarding the placement of the second metal bumps 13 and 351 on the second main surface 3 b of the circuit board 3, the end of the through wiring 33 on the second main surface 3 b side of the circuit board 3 and the circuit board 3 of the second through wiring 11 are also provided. It is not limited to the end on the second main surface 3b side. The second metal bump 351 and the through wiring 33 mounted on the second main surface 3b at a position separated from the end of the through wiring 33 on the second main surface 3b side are interposed through the wiring portion formed on the second main surface 3b. The second metal bumps 13 and the second through-wiring 11 mounted at positions separated from the end of the second through-hole wiring 11 on the second main surface 3b side in the second main surface 3b, It is also possible to electrically connect via a wiring portion formed on the second main surface 3b.

前記半導体基板39は、ここでは具体的にはシリコン基板である。
図中符号39aは、半導体基板39の表面に形成された酸化膜(シリコン酸化膜)であり、貫通配線33、配線部32、第2貫通配線11といった、回路基板3に形成された配線と半導体基板39との間の電気絶縁性を確保する。
Here, the semiconductor substrate 39 is specifically a silicon substrate.
Reference numeral 39a in the drawing denotes an oxide film (silicon oxide film) formed on the surface of the semiconductor substrate 39. The wirings formed on the circuit board 3, such as the through wiring 33, the wiring portion 32, and the second through wiring 11, and the semiconductor. Electrical insulation with the substrate 39 is ensured.

このデバイス内蔵基板1の回路基板3に形成された配線(配線部32、貫通配線33、端子部34、第2貫通配線11を含む)は、銅あるいは銅合金等の導体金属によって形成されている。
導体金属としては、例えば、金、アルミニウム等も採用可能である。
また、回路基板3には、配線を形成する導体金属が半導体基板39中に拡散(金属が移行)することを防止する目的で拡散防止膜を設けることができる。拡散防止膜は、配線を形成する導体金属と半導体基板39との間に介在させる。拡散防止膜用の金属としては、Ta、TiN、SiNなどが挙げられる。
The wiring (including the wiring portion 32, the through wiring 33, the terminal portion 34, and the second through wiring 11) formed on the circuit board 3 of the device built-in substrate 1 is formed of a conductive metal such as copper or a copper alloy. .
As the conductor metal, for example, gold, aluminum or the like can be used.
Further, the circuit board 3 can be provided with a diffusion preventing film for the purpose of preventing the conductor metal forming the wiring from diffusing (metal is transferred) into the semiconductor substrate 39. The diffusion prevention film is interposed between the conductor metal forming the wiring and the semiconductor substrate 39. Examples of the metal for the diffusion prevention film include Ta, TiN, SiN and the like.

回路基板3に組み込むチップ形デバイス4としては、外観が直方体状(キュービック状、あるいは、四角板状)のものである。また、このチップ形デバイス4としては、図2、図3、図10等に示すように、6面の外壁面の内の1つが、電極パッド44が設けられたパッド設置面43とされた構成のものを採用できる。前記電極パッド44は、回路基板3の端子部34とボンディング(ボンディング用金属材料によるボンディング)によって電気導通可能に接続されるものである。
また、このチップ形デバイス4としては、ここでは、図3等に示すように、パッド設置面43の電極パッド44に金属バンプ45が実装されたフリップチップタイプのものを採用している。
The chip-type device 4 incorporated in the circuit board 3 has a rectangular parallelepiped appearance (cubic or square plate shape). In addition, as shown in FIGS. 2, 3, 10, etc., the chip type device 4 has a configuration in which one of the six outer wall surfaces is a pad installation surface 43 provided with electrode pads 44. Can be used. The electrode pad 44 is connected to the terminal portion 34 of the circuit board 3 so as to be electrically conductive by bonding (bonding using a bonding metal material).
Further, as the chip-type device 4, here, a flip-chip type device in which metal bumps 45 are mounted on the electrode pads 44 on the pad installation surface 43 is employed as shown in FIG. 3 and the like.

図11等に示すように、デバイス収納孔31は、角穴状(図11において、具体的には、平面視正方形の貫通孔)である。チップ形デバイス4は、パッド設置面43が、回路基板3のデバイス収納孔31の軸心31a(中心軸線)に対して垂直となるようにしてデバイス収納孔31内に組み込まれている。   As shown in FIG. 11 and the like, the device housing hole 31 has a square hole shape (specifically, in FIG. 11, a square through-hole in plan view). The chip-type device 4 is incorporated in the device housing hole 31 so that the pad installation surface 43 is perpendicular to the axis 31 a (center axis) of the device housing hole 31 of the circuit board 3.

図3に示すチップ形デバイス4は、パッド設置面43の電極パッド44に金属バンプ45が実装された構成になっている。
このチップ形デバイス4を回路基板3のデバイス収納孔31内に組み込んで回路基板3に実装するには、回路基板3の第2主面3b側からデバイス収納孔31内に挿入して収納し、チップ形デバイス4の前記金属バンプ45を回路基板3の前記端子部34に接触させ、この状態で金属バンプ45のリフロー、冷却固化することで、電極パッド44を回路基板3の前記端子部34にボンディングする。
The chip-type device 4 shown in FIG. 3 has a configuration in which metal bumps 45 are mounted on the electrode pads 44 on the pad installation surface 43.
In order to incorporate this chip-type device 4 into the device storage hole 31 of the circuit board 3 and mount it on the circuit board 3, the chip-type device 4 is inserted into the device storage hole 31 from the second main surface 3b side of the circuit board 3 and stored. The metal bump 45 of the chip-type device 4 is brought into contact with the terminal portion 34 of the circuit board 3, and in this state, the metal bump 45 is reflowed and cooled and solidified, whereby the electrode pad 44 is attached to the terminal portion 34 of the circuit board 3. Bond.

図2中符号36は、チップ形デバイス4の電極パッド44と回路基板3の前記端子部34とをボンディングして電気的に接続したボンディング金属部である。ボンディング金属部36は、導電性のボンディング用金属材料によって形成されている。
ここでは、前記ボンディング金属部36は、前記金属バンプ45のリフロー、冷却固化によって形成されたものである。但し、チップ形デバイス4の電極パッド44と回路基板3の前記端子部34とのボンディングを実現するための手法としては、これに限定されず、例えば、端子部34上に設置しておいた金属バンプのリフローによって実現することも可能である。
Reference numeral 36 in FIG. 2 denotes a bonding metal portion in which the electrode pad 44 of the chip-type device 4 and the terminal portion 34 of the circuit board 3 are bonded and electrically connected. The bonding metal portion 36 is formed of a conductive bonding metal material.
Here, the bonding metal portion 36 is formed by reflowing and cooling and solidifying the metal bump 45. However, the technique for realizing the bonding between the electrode pad 44 of the chip-type device 4 and the terminal portion 34 of the circuit board 3 is not limited to this, and for example, a metal that has been installed on the terminal portion 34. It can also be realized by reflowing bumps.

ボンディング用金属材料としては例えば半田を用いることができる。半田の場合、金属バンプは半田バンプ、電極パッド44と端子部34とのボンディングは半田付けである。
電極パッド44と端子部34とのボンディング用の金属バンプはボンディング用金属材料によって形成されている。
For example, solder can be used as the bonding metal material. In the case of solder, the metal bumps are solder bumps, and the bonding between the electrode pads 44 and the terminal portions 34 is soldering.
Metal bumps for bonding the electrode pads 44 and the terminal portions 34 are formed of a bonding metal material.

ボンディング用金属材料としては、半田以外に、例えば、Au(金)、InAu合金、その他の低融点合金も採用可能である。ボンディング用金属材料は、全体が導電性の金属(合金を含む)からなるもの、あるいは、金属(合金を含む。導電性を有する)を主成分とするものを指す。後者は、例えばフラックス等の添加物を微量に含有したものである。
電極パッド44と端子部34とのボンディング用の金属バンプを構成するボンディング用金属材料としては、電極パッド44と端子部34とのろう接を実現できるものが好ましい。
As the metal material for bonding, for example, Au (gold), InAu alloy, and other low melting point alloys can be used in addition to solder. The metal material for bonding refers to a material made entirely of a conductive metal (including an alloy) or a material mainly composed of a metal (including an alloy; having conductivity). The latter contains a trace amount of additives such as flux.
As a bonding metal material that forms a metal bump for bonding the electrode pad 44 and the terminal portion 34, a material that can realize brazing between the electrode pad 44 and the terminal portion 34 is preferable.

貫通配線11、33と電子部品(例えば、集積回路部54、半導体パッケージ等の電子デバイス、配線基板等)の回路とを電気的に接続するためのボンディング用の金属バンプ(例えば、符号、12、13、351の金属バンプ)としては、貫通配線11、33と電子部品とのろう接を実現できるものが好ましく、電極パッド44と端子部34とのボンディング用の金属バンプと同様のボンディング用金属材料からなる金属バンプを用いることができる。
例えば、図5等に記載の符号35は、回路基板3の第2主面3bに設けられた電子部品(例えば集積回路部54)と回路基板3の貫通配線とを、電子デバイスあるいは回路基板3に設けられた金属バンプ(ボンディング用金属材料)のリフロー、冷却によってボンディングした、ボンディング金属部である。ボンディング金属部は前記金属バンプのリフロー、冷却によって形成される。
また、図4のボンディング金属部15は、回路基板3の第1主面3aに設けられた電子(例えば第2回路基板9)あるいは回路基板3に設けられた金属バンプ(ボンディング用金属材料)のリフロー、冷却によって形成されるものである。
図5のボンディング金属部36は、チップ形デバイス4あるいは回路基板3の端子部44に設けられた金属バンプのリフロー、冷却によって形成されるものである。
Metal bumps for bonding (for example, reference numerals 12, 12, etc.) for electrically connecting the through wirings 11, 33 and circuits of electronic components (for example, an integrated circuit unit 54, an electronic device such as a semiconductor package, a wiring board, etc.) As the metal bumps 13 and 351, those that can realize brazing between the through wirings 11 and 33 and the electronic component are preferable, and a bonding metal material similar to the metal bump for bonding the electrode pad 44 and the terminal portion 34 is preferable. Metal bumps made of can be used.
For example, reference numeral 35 described in FIG. 5 and the like designates an electronic component (for example, the integrated circuit portion 54) provided on the second main surface 3b of the circuit board 3 and the through wiring of the circuit board 3 as an electronic device or circuit board 3. It is a bonding metal part bonded by reflow and cooling of metal bumps (metal material for bonding) provided on the surface. The bonding metal part is formed by reflow and cooling of the metal bump.
Also, the bonding metal portion 15 in FIG. 4 is formed of electrons (for example, the second circuit board 9) provided on the first main surface 3a of the circuit board 3 or metal bumps (bonding metal material) provided on the circuit board 3. It is formed by reflow and cooling.
The bonding metal portion 36 in FIG. 5 is formed by reflow and cooling of metal bumps provided on the terminal portion 44 of the chip-type device 4 or the circuit board 3.

図2、図11において、符号37は、回路基板3のデバイス収納孔31内に形成された充填樹脂部である。この充填樹脂部37は、前記デバイス収納孔31内面(内周面)と該デバイス収納孔31内に組み込まれた前記チップ形デバイス4(詳細にはチップ形デバイス4の外周面(チップ形デバイス4外壁面の内のパッド設置面43に垂直の面))との間に形成されており、チップ形デバイス4を固定する。   2 and 11, reference numeral 37 denotes a filling resin portion formed in the device housing hole 31 of the circuit board 3. The filled resin portion 37 includes an inner surface (inner peripheral surface) of the device storage hole 31 and the chip-type device 4 (in detail, an outer peripheral surface of the chip-type device 4 (chip-type device 4). The chip-type device 4 is fixed between the outer wall surface and the surface perpendicular to the pad mounting surface 43)).

本発明に係るデバイス内蔵基板1の前記デバイス収納孔31は、その断面寸法(軸心31a(中心軸線)方向に垂直の断面の寸法。以下、デバイス収納孔31の断面寸法、とも言う)が、前記チップ形デバイス4における前記デバイス収納孔31の軸心31aに垂直の断面寸法(以下、チップ形デバイス4の断面寸法、とも言う)よりも若干大きい(第1パッド設置面の電極パッド44のコンタクト面44aの寸法の5〜195%だけ大きくした)寸法になっている。
充填樹脂部37は、デバイス収納孔31の内周面の全周(但し、デバイス収納孔31の内周面に、図11に示すチップ形デバイス4の断面の四隅の頂点のいずれか1以上が接触されている場合(例えば図12参照)は、この接触部分を除く)にわたって形成されている。
なお、デバイス収納孔31の断面寸法と、チップ形デバイス4の電極パッド44のコンタクト面44aとの関係については、後に詳述する。
The device housing hole 31 of the device-embedded substrate 1 according to the present invention has a cross-sectional dimension (a cross-sectional dimension perpendicular to the direction of the axis 31a (center axis). Hereinafter, also referred to as a cross-sectional dimension of the device housing hole 31). The contact of the electrode pad 44 on the first pad mounting surface is slightly larger than the cross-sectional dimension perpendicular to the axis 31a of the device housing hole 31 in the chip-type device 4 (hereinafter also referred to as the cross-sectional dimension of the chip-type device 4). The dimension is increased by 5 to 195% of the dimension of the surface 44a.
The filled resin portion 37 has an entire circumference of the inner circumferential surface of the device housing hole 31 (however, at least one of the apexes of the four corners of the cross section of the chip-shaped device 4 shown in FIG. When it is in contact (for example, see FIG. 12), it is formed over this part.
The relationship between the cross-sectional dimension of the device housing hole 31 and the contact surface 44a of the electrode pad 44 of the chip-type device 4 will be described in detail later.

また、このデバイス内蔵基板1にあっては、回路基板3の前記デバイス収納孔31内に、前記樹脂充填部37の他に、充填樹脂部37から連続して前記チップ形デバイス4の前記パッド設置面43(端子部34とボンディングされた電極パッド44が設置されているパッド設置面43)を覆う延長樹脂層37aも形成されている。
チップ形デバイス4が光素子の場合は、透明樹脂によって延長樹脂層37aを形成して、光素子40のパッド設置面43(受/発光部設置面)を覆う透明樹脂層38として機能させる。
In the device-embedded substrate 1, the pad placement of the chip-type device 4 is continued in the device housing hole 31 of the circuit board 3 from the filling resin portion 37 in addition to the resin filling portion 37. An extended resin layer 37a covering the surface 43 (the pad installation surface 43 on which the electrode pad 44 bonded to the terminal portion 34 is installed) is also formed.
When the chip-type device 4 is an optical element, the extended resin layer 37a is formed of a transparent resin and functions as the transparent resin layer 38 that covers the pad installation surface 43 (receiving / light emitting unit installation surface) of the optical element 40.

図1〜図3において、このデバイス内蔵基板1は、回路基板3の第1主面3aに被着された開口部封止部材2を具備する。この開口部封止部材2は、シート状又はプレート状に形成されており、回路基板3にその第1主面3a側全体を覆うように被着され、回路基板3の第1主面3aにおける前記デバイス収納孔31の開口部を塞いでいる。
この開口部封止部材2は、充填樹脂部37、延長樹脂層37aを形成するための液状の樹脂材料8をデバイス収納孔31に注入する(図15参照)際に、回路基板3の第1主面3aにおける前記デバイス収納孔31の開口部を塞いで、該開口部からの樹脂材料8の漏出を防止する、といった機能を果たす。また、端子部34や、チップ形デバイス4の前記パッド設置面43(第1パッド設置面)を衝突物の衝突等から保護する保護材としても機能する。
1 to 3, the device built-in substrate 1 includes an opening sealing member 2 attached to the first main surface 3 a of the circuit substrate 3. The opening sealing member 2 is formed in a sheet shape or a plate shape, and is attached to the circuit board 3 so as to cover the entire first main surface 3a side, and on the first main surface 3a of the circuit board 3. The opening of the device housing hole 31 is blocked.
The opening sealing member 2 is configured such that when the liquid resin material 8 for forming the filling resin portion 37 and the extended resin layer 37a is injected into the device housing hole 31 (see FIG. 15), the first sealing substrate 2 of the circuit board 3 is used. The function of closing the opening of the device housing hole 31 in the main surface 3a and preventing leakage of the resin material 8 from the opening is achieved. Moreover, it functions also as a protective material which protects the terminal part 34 and the said pad installation surface 43 (1st pad installation surface) of the chip-type device 4 from collision of a collision object.

なお、チップ形デバイス4が光素子の場合は、前記開口部封止部材2として透明の部材を採用して、光素子40のパッド設置面43に設けられている受/発光部401とシート形光導波路20のミラー部24との間の光路H2(図5参照)を形成する。
チップ形デバイス4が光素子以外である場合は、必ずしも透明の開口部封止部材2を採用する必要は無い。
In the case where the chip-type device 4 is an optical element, a transparent member is employed as the opening sealing member 2, and the light receiving / emitting part 401 provided on the pad installation surface 43 of the optical element 40 and the sheet type are used. An optical path H2 (see FIG. 5) between the mirror portion 24 of the optical waveguide 20 is formed.
When the chip-type device 4 is other than an optical element, it is not always necessary to employ the transparent opening sealing member 2.

このデバイス内蔵基板1を組み立てる方法(電子デバイス内蔵基板の組立方法)の一例を説明する。
ここでは、図3に示すように、チップ形デバイス4として、電極パッド44に金属バンプ45が実装されているものを用いる場合を説明する。
また、ここで用いる回路基板3は、図1のように、第1金属バンプ12及び第2金属バンプ13、351を実装した構成のものであるが、第1金属バンプ12及び第2金属バンプ13、351を実装していない回路基板を採用し、回路基板へのチップ形デバイス4の組み込み、実装の完了後に、回路基板に第1金属バンプ12及び第2金属バンプ13、351を実装しても良い。
An example of a method for assembling the device built-in substrate 1 (an assembly method of the electronic device built-in substrate) will be described.
Here, as shown in FIG. 3, a case where a chip-type device 4 in which metal bumps 45 are mounted on electrode pads 44 will be described.
The circuit board 3 used here has a configuration in which the first metal bumps 12 and the second metal bumps 13 and 351 are mounted as shown in FIG. 1, but the first metal bumps 12 and the second metal bumps 13 are mounted. , 351 is employed, and the first metal bump 12 and the second metal bumps 13 and 351 may be mounted on the circuit board after the chip-type device 4 is assembled and mounted on the circuit board. good.

(チップ実装工程)
まず、前記回路基板3のデバイス収納孔31にチップ形デバイス4を組み込み、このチップ形デバイス4の金属バンプ45をリフローして、電極パッド44を回路基板3の前記端子部34にボンディングする(チップ実装工程)。リフローした金属バンプ45の冷却固化によって、チップ形デバイス4の電極パッド44と回路基板3の端子部34とがボンディングされる。
(Chip mounting process)
First, the chip-type device 4 is assembled in the device housing hole 31 of the circuit board 3, the metal bumps 45 of the chip-type device 4 are reflowed, and the electrode pads 44 are bonded to the terminal portions 34 of the circuit board 3 (chips). Mounting process). By cooling and solidifying the reflowed metal bumps 45, the electrode pads 44 of the chip-type device 4 and the terminal portions 34 of the circuit board 3 are bonded.

チップ実装工程においては、金属バンプ45をリフローすることで、溶融状態のバンプ材料(ボンディング用金属材料)の表面張力によって、チップ形デバイス4の複数の電極パッド44のコンタクト面44aと、回路基板3の複数の端子部34上に形成されたコンタクト面34aとが重なり合う(平面視における重なり。図12におけるコンタクト面44a、34a同士の重なり合い)ように、デバイス収納孔31内でのチップ形デバイス4の位置が調整される(リフローしたバンプ材料(ボンディング用金属材料)の表面張力自体によるチップ形デバイス4のセルフアライメント)。   In the chip mounting process, by reflowing the metal bumps 45, the contact surfaces 44a of the plurality of electrode pads 44 of the chip-type device 4 and the circuit board 3 are caused by the surface tension of the molten bump material (bonding metal material). Of the chip-type device 4 in the device housing hole 31 so that the contact surfaces 34a formed on the plurality of terminal portions 34 overlap (overlap in plan view, the contact surfaces 44a and 34a in FIG. 12 overlap). The position is adjusted (self-alignment of the chip-type device 4 by the surface tension itself of the reflowed bump material (bonding metal material)).

既述の通り、本発明に係る回路基板3の前記デバイス収納孔31の断面寸法は、前記チップ形デバイス4の断面寸法に比べて、チップ形デバイス4の前記電極パッド44のコンタクト面44aの寸法の5〜195%だけ大きくした寸法になっている。図11、図12において、具体的には、外観キュービック状のチップ形デバイス4を用いており、このチップ形デバイス4は、前記デバイス収納孔31の軸心31a(中心軸線)に垂直の断面形状が矩形(図11、図12では模式的に正方形の断面形状を図示している)である。デバイス収納孔31の軸心31a(中心軸線)に垂直の断面形状は、チップ形デバイス4の断面形状よりも若干大きい相似形(矩形、さらに詳細には正方形)になっている。
このため、チップ形デバイス4を回路基板3のデバイス収納孔31内に収納した段階(金属バンプ45のリフロー前)では、チップ形デバイス4の断面寸法とデバイス収納孔31の断面寸法との差によって、チップ形デバイス4に、デバイス収納孔31内での可動範囲が確保される。
As described above, the cross-sectional dimension of the device housing hole 31 of the circuit board 3 according to the present invention is larger than the cross-sectional dimension of the chip-type device 4 and the dimension of the contact surface 44 a of the electrode pad 44 of the chip-type device 4. The size is increased by 5 to 195%. 11 and 12, specifically, an external cubic chip device 4 is used, and the chip device 4 has a cross-sectional shape perpendicular to the axis 31a (center axis) of the device housing hole 31. Is a rectangle (FIGS. 11 and 12 schematically show a square cross-sectional shape). The cross-sectional shape perpendicular to the axis 31 a (center axis) of the device housing hole 31 is a similar shape (rectangle, more specifically square) that is slightly larger than the cross-sectional shape of the chip-type device 4.
For this reason, at the stage where the chip-type device 4 is stored in the device storage hole 31 of the circuit board 3 (before the reflow of the metal bump 45), the difference between the cross-sectional dimension of the chip-type device 4 and the cross-sectional dimension of the device storage hole 31 The movable range within the device housing hole 31 is secured in the chip-type device 4.

図10に示す図示例のチップ形デバイス4の複数の電極パッド44のコンタクト面44aは矩形(図示例では正方形)であり、その面積が互いに同じに揃えてある。また、図12に例示した回路基板3の複数の端子部34は、コンタクト面34aの形状、面積が、それぞれチップ形デバイス4の電極パッド44のコンタクト面44aと同じに揃えてある。チップ形デバイス4の電極パッド44は、デバイス収納孔31内でのチップ形デバイス4の位置調整によって、全ての電極パッド44のコンタクト面44aを、一括して、回路基板3の複数の端子部34のコンタクト面34aに重なるように位置合わせできるように配置されている。
前記デバイス収納孔31の断面寸法は、前記チップ形デバイス4の断面寸法に、チップ形デバイス4の電極パッド44のコンタクト面44aの4辺の内の一辺の長さの5〜195%を加えた寸法になっている。
The contact surfaces 44a of the plurality of electrode pads 44 of the chip-type device 4 of the illustrated example shown in FIG. 10 are rectangular (square in the illustrated example), and their areas are aligned with each other. Further, in the plurality of terminal portions 34 of the circuit board 3 illustrated in FIG. 12, the contact surface 34 a has the same shape and area as the contact surface 44 a of the electrode pad 44 of the chip-type device 4. The electrode pads 44 of the chip-type device 4 are formed by collectively adjusting the contact surfaces 44 a of all the electrode pads 44 by adjusting the position of the chip-type device 4 in the device housing hole 31. It arrange | positions so that it can align so that it may overlap with the contact surface 34a.
The cross-sectional dimension of the device housing hole 31 is obtained by adding 5 to 195% of the length of one of the four sides of the contact surface 44 a of the electrode pad 44 of the chip-type device 4 to the cross-sectional dimension of the chip-type device 4. It is a dimension.

なお、チップ形デバイス4の電極パッド44のコンタクト面44aが円形の場合には、デバイス収納孔31の断面寸法は、チップ形デバイス4の電極パッド44のコンタクト面44aの直径の5〜195%を前記チップ形デバイス4の断面寸法に加えた寸法とする。   When the contact surface 44 a of the electrode pad 44 of the chip-type device 4 is circular, the cross-sectional dimension of the device housing hole 31 is 5 to 195% of the diameter of the contact surface 44 a of the electrode pad 44 of the chip-type device 4. The dimensions are in addition to the cross-sectional dimensions of the chip-type device 4.

金属バンプ45をリフローすると、溶融されたバンプ材料(ボンディング用金属材料)の表面張力自体によって、チップ形デバイス4の複数の電極パッド44のコンタクト面44aと、回路基板3の複数の端子部34上のコンタクト面34aとの重なりが合うように、デバイス収納孔31内でのチップ形デバイス4の位置が調整される。ここで、金属バンプ45をリフローしたときの、チップ形デバイス4の複数の電極パッド44のコンタクト面44aと、回路基板3の複数の端子部34のコンタクト面34aとの重なりは、必ずしも、チップ形デバイス4の全ての電極パッド44のコンタクト面44aが、回路基板3の複数の端子部34のコンタクト面34aに完全に重なる(チップ形デバイス4の全ての電極パッド44のコンタクト面44aの全体が端子部34のコンタクト面34a上に位置する)必要はなく、チップ形デバイス4の1以上の電極パッド44に、そのコンタクト面44aが回路基板3の端子部34のコンタクト面34a上に位置していない部分が若干存在していても良い。   When the metal bump 45 is reflowed, the contact surface 44a of the plurality of electrode pads 44 of the chip-type device 4 and the plurality of terminal portions 34 of the circuit board 3 are caused by the surface tension itself of the melted bump material (bonding metal material). The position of the chip-type device 4 in the device housing hole 31 is adjusted so that the contact surface 34a overlaps with the contact surface 34a. Here, when the metal bump 45 is reflowed, the overlap between the contact surfaces 44a of the plurality of electrode pads 44 of the chip-type device 4 and the contact surfaces 34a of the plurality of terminal portions 34 of the circuit board 3 is not necessarily chip-shaped. The contact surfaces 44a of all the electrode pads 44 of the device 4 completely overlap the contact surfaces 34a of the plurality of terminal portions 34 of the circuit board 3 (the entire contact surfaces 44a of all the electrode pads 44 of the chip-type device 4 are terminals). The contact surface 44a is not located on the contact surface 34a of the terminal portion 34 of the circuit board 3 on the one or more electrode pads 44 of the chip-type device 4. Some parts may be present.

回路基板3の複数の端子部34は、コンタクト面34aの形状、面積、設置間隔が、それぞれチップ形デバイス4の電極パッド44のコンタクト面44aと完全に一致している必要は無く、例えば、コンタクト面34aの大きさ(面積)が、チップ形デバイス4の電極パッド44のコンタクト面44aに比べて若干大きい、あるいは、若干小さい構成であっても良い。
また、複数の端子部34のコンタクト面34aの形状、面積は、必ずしも互いに一致している必要は無く、若干のばらつきがあっても構わない。
The plurality of terminal portions 34 of the circuit board 3 do not need to have the shape, area, and installation interval of the contact surface 34a completely coincide with the contact surface 44a of the electrode pad 44 of the chip-type device 4, for example, contact The size (area) of the surface 34 a may be slightly larger or slightly smaller than the contact surface 44 a of the electrode pad 44 of the chip-type device 4.
Further, the shapes and areas of the contact surfaces 34a of the plurality of terminal portions 34 do not necessarily have to coincide with each other, and may vary slightly.

金属バンプ45のリフローによるチップ形デバイス4のセルフアライメントを行うことで、デバイス収納孔31内に収納したチップ形デバイス4の位置が調整され、チップ形デバイス4の全ての電極パッド44のコンタクト面44aが、回路基板3の複数の端子部34のコンタクト面34aに重なった範囲が充分に確保された状態を容易に得ることができる。このため、リフローによる溶融状態のバンプ材料(ボンディング用金属材料)の冷却、固化によって、各電極パッド44と端子部34とのボンディング、電気的接続が確実になされる。   By performing self-alignment of the chip-type device 4 by reflow of the metal bump 45, the position of the chip-type device 4 accommodated in the device accommodation hole 31 is adjusted, and the contact surfaces 44a of all the electrode pads 44 of the chip-type device 4 are adjusted. However, it is possible to easily obtain a state in which the range that overlaps the contact surfaces 34a of the plurality of terminal portions 34 of the circuit board 3 is sufficiently secured. Therefore, the bonding and electrical connection between each electrode pad 44 and the terminal portion 34 are ensured by cooling and solidifying the bump material (bonding metal material) in a molten state by reflow.

金属バンプ45のリフローによるチップ形デバイス4のセルフアライメントが実現されるには、デバイス収納孔31内に収納したチップ形デバイス4の金属バンプ45のリフロー前に、チップ形デバイス4の全ての電極パッド44の金属バンプ45が、回路基板3の端子部34に接触している必要がある。このため、回路基板3の前記デバイス収納孔31の断面寸法は、デバイス収納孔31内に収納したチップ形デバイス4の全ての電極パッド44のコンタクト面44aが、それぞれ、端子部34のコンタクト面34aに重なった部分を有するように調整される。
回路基板3の前記デバイス収納孔31の断面寸法が、前記チップ形デバイス4における前記デバイス収納孔31の軸心31a(中心軸線)に垂直の断面寸法に対して、前記電極パッド44のコンタクト面44aの寸法の5〜195%だけ大きくした寸法であれば、デバイス収納孔31内に収納したチップ形デバイス4の全ての電極パッド44のコンタクト面44aが、それぞれ、端子部34のコンタクト面34aに重なった部分を有する、という関係を実現できる。
In order to realize self-alignment of the chip-type device 4 by reflow of the metal bumps 45, all the electrode pads of the chip-type device 4 before reflow of the metal bumps 45 of the chip-type device 4 housed in the device housing hole 31 are realized. 44 metal bumps 45 need to be in contact with the terminal portions 34 of the circuit board 3. For this reason, the cross-sectional dimensions of the device housing hole 31 of the circuit board 3 are such that the contact surfaces 44a of all the electrode pads 44 of the chip-type device 4 housed in the device housing hole 31 are contact surfaces 34a of the terminal portions 34, respectively. It is adjusted so that it may have a portion that overlaps.
The contact surface 44a of the electrode pad 44 has a cross-sectional dimension of the device housing hole 31 of the circuit board 3 that is perpendicular to the axial center 31a (center axis) of the device housing hole 31 of the chip-type device 4. The contact surfaces 44a of all the electrode pads 44 of the chip-type device 4 housed in the device housing hole 31 overlap the contact surfaces 34a of the terminal portions 34 respectively. It is possible to realize the relationship of having a part.

図12に示すように、金属バンプ45のリフローによるチップ形デバイス4のセルフアライメントが円滑に実現されるには、デバイス収納孔31内に収納したチップ形デバイス4に、金属バンプ45のリフロー時に、デバイス収納孔31の軸心31a(中心軸線)に直交する面に沿った方向の移動、軸心31aを中心とする軸回り方向の回転移動、前記軸心31aに対する傾動(図13参照)が許容されている必要がある。
この点、デバイス収納孔31に対する端子部34の位置は、チップ形デバイス4の全ての電極パッド44のコンタクト面44aの中央部が端子部34のコンタクト面34aの中央部上に重なったとき(コンタクト面44a、34a同士が重なり合った面積が最大のとき。以下、このときの状態を、完全アライメント状態、とも言う)に、チップ形デバイス4の外周(デバイス収納孔31の軸心31aに直交する断面の外周)の全周にわたって、デバイス収納孔31内面との間にギャップが確保されるように設定することが好ましい。本実施形態では、端子部34について、この位置設定を行った構成を例示する。
但し、本発明は、これに限定されるものでは無く、端子部34の位置設定の適宜変更も可能である。
As shown in FIG. 12, in order to smoothly realize the self-alignment of the chip-type device 4 by the reflow of the metal bump 45, the chip-type device 4 stored in the device storage hole 31 is reflowed at the time of the reflow of the metal bump 45. Permits movement of the device housing hole 31 along a plane perpendicular to the axis 31a (center axis), rotational movement about the axis about the axis 31a, and tilting with respect to the axis 31a (see FIG. 13). Need to be.
In this regard, the position of the terminal portion 34 with respect to the device housing hole 31 is determined when the central portion of the contact surface 44a of all the electrode pads 44 of the chip-type device 4 overlaps the central portion of the contact surface 34a of the terminal portion 34 (contact When the area where the surfaces 44a and 34a overlap each other is the maximum, hereinafter, the state at this time is also referred to as a complete alignment state, and the cross section orthogonal to the outer periphery of the chip-type device 4 (the axis 31a of the device housing hole 31). It is preferable to set so that a gap is secured between the inner circumference of the device housing hole 31 and the entire inner circumference. In the present embodiment, a configuration in which this position setting is performed for the terminal portion 34 is illustrated.
However, the present invention is not limited to this, and the position setting of the terminal portion 34 can be appropriately changed.

回路基板3の前記デバイス収納孔31の断面寸法と、前記チップ形デバイス4における前記デバイス収納孔31の軸心31a(中心軸線)に垂直の断面寸法との差が、チップ形デバイス4の電極パッド44のコンタクト面44aの寸法の5%未満であると、デバイス収納孔31の内周面と、このデバイス収納孔31に収納したチップ形デバイス4の外周面との間のギャップが小さすぎ、金属バンプ45のリフローによるチップ形デバイス4のセルフアライメントが円滑に実現されなくなる可能性が大きくなる。また、デバイス収納孔31へのチップ形デバイス4の挿入に手間が掛かるようになってくる。   The difference between the cross-sectional dimension of the device housing hole 31 of the circuit board 3 and the cross-sectional dimension of the chip-shaped device 4 perpendicular to the axis 31a (center axis) of the device housing hole 31 is the electrode pad of the chip-shaped device 4 If the size of the contact surface 44a of 44 is less than 5%, the gap between the inner peripheral surface of the device storage hole 31 and the outer peripheral surface of the chip-type device 4 stored in the device storage hole 31 is too small. There is a high possibility that the self-alignment of the chip-type device 4 due to the reflow of the bumps 45 is not realized smoothly. Further, it takes time to insert the chip-type device 4 into the device storage hole 31.

一方、回路基板3の前記デバイス収納孔31の断面寸法と、前記チップ形デバイス4における前記デバイス収納孔31の軸心31a(中心軸線)に垂直の断面寸法との差が、チップ形デバイス4の電極パッド44のコンタクト面44aの寸法の195%を超えていると、デバイス収納孔31内に収納したチップ形デバイス4の電極パッド44のコンタクト面44aと端子部34のコンタクト面34aとの重なりが極端に小さくなりすぎ、金属バンプ45のリフロー時に、溶融したバンプ材料(ボンディング用金属材料)の表面張力によるセルフアライメントが有効にならなくなるケースが生じやすくなる。この場合は、既述の完全アライメント状態となったとき、チップ形デバイス4の外周とデバイス収納孔31内面との間に、チップ形デバイス4の電極パッド44のコンタクト面44aの寸法の195/2%の大きさのギャップが確保されることとなる。   On the other hand, the difference between the cross-sectional dimension of the device housing hole 31 of the circuit board 3 and the cross-sectional dimension perpendicular to the axis 31a (center axis) of the device housing hole 31 in the chip-shaped device 4 is If it exceeds 195% of the dimension of the contact surface 44 a of the electrode pad 44, the overlap between the contact surface 44 a of the electrode pad 44 of the chip-type device 4 housed in the device housing hole 31 and the contact surface 34 a of the terminal portion 34 will occur. When the metal bump 45 is reflowed, the case where the self-alignment due to the surface tension of the melted bump material (bonding metal material) is not effective is likely to occur. In this case, when the complete alignment state described above is achieved, the dimension of the contact surface 44a of the electrode pad 44 of the chip-type device 4 is 195/2 between the outer periphery of the chip-type device 4 and the inner surface of the device housing hole 31. % Gap will be secured.

また、図12に示すように、回路基板3の断面矩形(図示例では正方形)の前記デバイス収納孔31の断面寸法は、断面4辺の一辺の長さが、チップ形デバイス4のデバイス収納孔31の軸心31a(中心軸線)に垂直の断面(断面形状は矩形。図示例では正方形)の対角線寸法よりも小さいことが好ましい。   Further, as shown in FIG. 12, the cross-sectional dimension of the device storage hole 31 having a rectangular cross section (square in the illustrated example) of the circuit board 3 is such that the length of one side of the four cross sections is the device storage hole of the chip-type device 4. It is preferable that it is smaller than the diagonal dimension of a cross section (cross-sectional shape is rectangular, square in the illustrated example) perpendicular to the axis 31a (center axis) of 31.

デバイス収納孔31の1辺の長さが、チップ形デバイス4の断面の対角線寸法よりも大きいと、デバイス収納孔31内にチップ形デバイス4を収納したときに、チップ形デバイス4を、デバイス収納孔31内面(チップ形デバイス4のデバイス収納孔31内面への当接)によって、軸心31aを中心とする軸回り方向に位置決めする(金属バンプのリフロー前の、コンタクト面44a、34a同士の重なり合いを確保する)ことが難しくなる。また、金属バンプ45のリフロー時に、チップ形デバイス4が、軸心31aを中心とする軸回り方向に自由に回転することで、チップ形デバイス4の各電極パッド44のコンタクト面44aと端子部34のコンタクト面34aとの重なりが非常に小さくなってしまうケースや、重なりが無くなってしまうケースが発生しやすくなる。
互いにボンディングする電極パッド44と端子部34の組の数が多い場合(例えば5組以上)は、金属バンプのサイズ(バンプ材料(ボンディング用金属材料)の量)のばらつき、金属バンプをリフローする工程における金属バンプ45の溶融状況のばらつき、リフローしたバンプ材料を冷却固化させる工程におけるバンプ材料の固化進行のばらつき、などによって、チップ形デバイス4に前記軸回り方向の回転が生じやすくなる。
If the length of one side of the device housing hole 31 is larger than the diagonal dimension of the cross section of the chip device 4, when the chip device 4 is housed in the device housing hole 31, the chip device 4 is stored in the device housing hole 31. Positioning in the direction around the axis centered on the axis 31a by the inner surface of the hole 31 (abutting the inner surface of the device housing hole 31 of the chip-type device 4) (overlap of the contact surfaces 44a and 34a before reflow of the metal bumps) To secure). Further, when the metal bump 45 is reflowed, the chip-type device 4 freely rotates in the direction around the axis centering on the axis 31 a, so that the contact surface 44 a and the terminal portion 34 of each electrode pad 44 of the chip-type device 4. The case where the overlap with the contact surface 34a becomes very small or the case where the overlap disappears easily occurs.
When the number of sets of electrode pads 44 and terminal portions 34 to be bonded to each other is large (for example, 5 sets or more), the process of reflowing metal bumps due to variations in metal bump size (amount of bump material (bonding metal material)) Rotation in the direction around the axis is likely to occur in the chip-type device 4 due to variations in the melting state of the metal bumps 45 and variations in the progress of solidification of the bump material in the step of cooling and solidifying the reflowed bump material.

図12に示すように、デバイス収納孔31の4面の内面の内の対向する組をなす内面間の距離が、チップ形デバイス4の断面の対角線寸法よりも小さく、回路基板3の前記デバイス収納孔31の断面寸法と前記チップ形デバイス4の断面寸法との差によって、金属バンプ45のリフロー時のチップ形デバイス4の前記軸心31aを中心とする軸回り方向の回転範囲が設定されていれば、溶融したバンプ材料(ボンディング用金属材料)の表面張力によるセルフアライメントによって、チップ形デバイス4の各電極パッド44のコンタクト面44aと端子部34のコンタクト面34aとの重なりを充分に大きく確保することをより確実に実現できる。   As shown in FIG. 12, the distance between the opposing inner surfaces of the four inner surfaces of the device housing hole 31 is smaller than the diagonal dimension of the cross section of the chip-type device 4, and the device housing of the circuit board 3. Depending on the difference between the cross-sectional dimension of the hole 31 and the cross-sectional dimension of the chip-type device 4, the rotation range in the direction around the axis about the axis 31a of the chip-type device 4 when the metal bump 45 is reflowed is set. For example, self-alignment due to the surface tension of the melted bump material (bonding metal material) ensures a sufficiently large overlap between the contact surface 44a of each electrode pad 44 of the chip-type device 4 and the contact surface 34a of the terminal portion 34. Can be realized more reliably.

なお、チップ形デバイス4の断面形状、及び、デバイス収納孔31の断面形状は、正方形状に限定されず、長方形状であっても良い。この場合も、デバイス収納孔31の断面形状を、チップ形デバイス4の断面寸法よりも電極パッド44のコンタクト面44aの寸法の5〜195%だけ大きい、チップ形デバイス4断面の相似形とすることは変わりない。また、デバイス収納孔31は、その断面外周の互いに平行な2組の辺の内の少なくとも1組の辺の長さを、前記チップ形デバイス4の対角線寸法よりも短くする。   In addition, the cross-sectional shape of the chip-type device 4 and the cross-sectional shape of the device housing hole 31 are not limited to a square shape, and may be a rectangular shape. Also in this case, the cross-sectional shape of the device housing hole 31 is a similar shape of the cross-section of the chip-type device 4 that is larger than the cross-sectional dimension of the chip-type device 4 by 5 to 195% of the dimension of the contact surface 44a of the electrode pad 44. Will not change. Further, the device housing hole 31 has a length of at least one of the two sets of parallel sides of the outer periphery of the cross section shorter than the diagonal dimension of the chip-type device 4.

この回路基板3では、前記デバイス収納孔31の断面寸法が、前記チップ形デバイス4における前記デバイス収納孔31の軸心31a(中心軸線)に垂直の断面寸法を、前記電極パッド44のコンタクト面44aの寸法の5〜195%だけ大きいため、デバイス収納孔31の内面の精度によってチップ形デバイス4を位置決めする構成(デバイス収納孔31を、チップ形デバイス4の嵌合によって、チップ形デバイス4を位置決めする構成)に比べて、デバイス収納孔31にチップ形デバイス4を挿入して組み込む作業を簡単かつ円滑に行える。また、デバイス収納孔31の内面の精度によってチップ形デバイス4を位置決めする構成(デバイス収納孔31を、チップ形デバイス4の嵌合によって、チップ形デバイス4を位置決めする構成)に比べて、デバイス収納孔31内面の形成精度の要求がかなり低くて済むため、デバイス収納孔31の加工の手間を大幅に低減できるといった利点もある。デバイス収納孔31内面の形成精度が低くても、金属バンプ45をリフローするだけで、溶融したバンプ材料(ボンディング用金属材料)の表面張力によって、チップ形デバイス4のセルフアライメントを実現できる。   In the circuit board 3, the cross-sectional dimension of the device housing hole 31 is perpendicular to the axis 31 a (center axis) of the device housing hole 31 in the chip-type device 4, and the contact surface 44 a of the electrode pad 44 is used. Therefore, the chip-shaped device 4 is positioned by the accuracy of the inner surface of the device housing hole 31 (the chip-shaped device 4 is positioned by fitting the chip-shaped device 4 into the device housing hole 31). Compared to the configuration of the above, the operation of inserting and inserting the chip-type device 4 into the device housing hole 31 can be performed easily and smoothly. Compared to the configuration in which the chip-type device 4 is positioned based on the accuracy of the inner surface of the device storage hole 31 (the configuration in which the chip-type device 4 is positioned by fitting the chip-type device 4 into the device storage hole 31). Since the requirement for the formation accuracy of the inner surface of the hole 31 may be considerably low, there is an advantage that the labor for processing the device housing hole 31 can be greatly reduced. Even if the formation accuracy of the inner surface of the device housing hole 31 is low, the chip-type device 4 can be self-aligned by the surface tension of the melted bump material (bonding metal material) only by reflowing the metal bump 45.

また、金属バンプ351のリフローによってチップ形デバイス4のセルフアライメントを実現できるので、デバイス収納孔31に対するチップ形デバイス4の挿入位置を調整する必要が無く、デバイス収納孔31に対するチップ形デバイス4の挿入作業を非常に簡単に行うことができる。
図14(a)に示すように、回路基板3の複数のデバイス収納孔31にそれぞれ収納したチップ形デバイス4の位置にはばらつきが許容される。そして、金属バンプ351のリフローによって、図14(b)に示すように、複数のチップ形デバイス4を、チップ形デバイス4の複数の電極パッド44のコンタクト面44aと端子部34のコンタクト面34aとの重なりを充分に大きく確保できるように、端子部34に対して位置合わせすることを、一括して、短時間に行うことができる。
In addition, since the self-alignment of the chip-type device 4 can be realized by reflowing the metal bumps 351, it is not necessary to adjust the insertion position of the chip-type device 4 with respect to the device storage hole 31, and the chip-type device 4 is inserted into the device storage hole 31. The work can be done very easily.
As shown in FIG. 14A, variations are allowed in the positions of the chip-type devices 4 respectively housed in the plurality of device housing holes 31 of the circuit board 3. Then, by reflowing the metal bumps 351, as shown in FIG. 14B, the plurality of chip-type devices 4 are connected to the contact surfaces 44a of the plurality of electrode pads 44 of the chip-type device 4 and the contact surfaces 34a of the terminal portions 34. Alignment with respect to the terminal portion 34 can be performed in a short time in a short time so as to ensure a sufficiently large overlap.

(充填樹脂部形成工程)
チップ実装工程が完了したら、前記デバイス収納孔31内面と前記チップ形デバイス4との間を埋める充填樹脂部37を形成する充填樹脂部形成工程を行う。
図15に示すように、この充填樹脂部形成工程は、回路基板3(デバイス収納孔付き基板)の第1主面3aにおける前記デバイス収納孔31の開口部を、開口部封止部材2を用いて塞いだ状態で、前記デバイス収納孔31内に液状の樹脂材料8を注入(デバイス実装面1a側からデバイス収納孔31に注入)して固化させることで前記充填樹脂部37を形成する。
(Filled resin part forming process)
When the chip mounting step is completed, a filling resin portion forming step for forming a filling resin portion 37 that fills the space between the inner surface of the device housing hole 31 and the chip-type device 4 is performed.
As shown in FIG. 15, in this filling resin portion forming step, the opening portion of the device housing hole 31 in the first main surface 3 a of the circuit board 3 (substrate with a device housing hole) is used as the opening sealing member 2. In the closed state, the filling resin portion 37 is formed by injecting the liquid resin material 8 into the device accommodation hole 31 (injecting into the device accommodation hole 31 from the device mounting surface 1a side) and solidifying.

このとき、回路基板3に実装済みのチップ形デバイス4のパッド設置面43と開口部封止部材2との間にギャップを確保し、このギャップにも樹脂材料8を流入させることで、充填樹脂部37とともに、該充填樹脂部37から連続してチップ形デバイス4のパッド設置面43を覆う延長樹脂層37aも形成する。この場合、充填樹脂部37と延長樹脂層37aとは、同じ樹脂材料8によって形成される。
なお、チップ形デバイス4のパッド設置面43と開口部封止部材2との間のギャップは、チップ形デバイス4のパッド設置面43と開口部封止部材2との間に位置する回路基板3の端子部34が、開口部節部材2がデバイス収納孔31内に入り込むことを規制することにより確保できる。また、例えば、別途、ギャップ確保用のスペーサ等を使用することも可能である。
At this time, a gap is ensured between the pad mounting surface 43 of the chip-type device 4 mounted on the circuit board 3 and the opening sealing member 2, and the resin material 8 is allowed to flow into the gap, thereby filling resin. Together with the portion 37, an extended resin layer 37a that covers the pad mounting surface 43 of the chip-type device 4 is also formed continuously from the filled resin portion 37. In this case, the filling resin portion 37 and the extended resin layer 37a are formed of the same resin material 8.
The gap between the pad installation surface 43 of the chip-type device 4 and the opening sealing member 2 is a circuit board 3 positioned between the pad installation surface 43 of the chip-type device 4 and the opening sealing member 2. The terminal portion 34 can be secured by restricting the opening node member 2 from entering the device housing hole 31. In addition, for example, a spacer for securing a gap can be used separately.

チップ形デバイス4が光素子以外の場合、液状の樹脂材料8としては、デバイス収納孔31に注入して固化させることで、チップ実装工程を完了したチップ形デバイス4を固定できるものであれば良く、特に限定は無い。充填樹脂部37、延長樹脂層37aの形成樹脂としては、例えば、エポキシ樹脂、フェノール樹脂、ウレタン樹脂等の熱硬化性樹脂や、エポキシ樹脂、アクリル系樹脂等の紫外線硬化性樹脂、などを採用できる。不透明のものであっても構わない。液状の樹脂材料8は、デバイス収納孔31に注入して固化させることで、充填樹脂部37、延長樹脂層37aを形成するものである。   When the chip-type device 4 is other than an optical element, the liquid resin material 8 may be any material that can fix the chip-type device 4 that has completed the chip mounting process by being injected into the device housing hole 31 and solidified. There is no particular limitation. As the resin for forming the filling resin portion 37 and the extended resin layer 37a, for example, a thermosetting resin such as an epoxy resin, a phenol resin, or a urethane resin, or an ultraviolet curable resin such as an epoxy resin or an acrylic resin can be employed. . It may be opaque. The liquid resin material 8 is injected into the device housing hole 31 and solidified to form the filling resin portion 37 and the extended resin layer 37a.

充填樹脂部37、延長樹脂層37aの形成樹脂が紫外線硬化性樹脂の場合は、開口部封止部材2として、デバイス収納孔31内に注入した液状の樹脂材料8の硬化用の紫外線を透過可能な透明のものを採用することが好ましい。これにより、開口部封止部材2を介して回路基板3とは反対の側から、デバイス収納孔31内の樹脂材料8への紫外線照射が可能となる。
この場合、透明のシート状(あるいはプレート状)の開口部封止部材2の形成材料としては、例えば、ポリイミド、ポリノルボルネン(PNB)、ベンゾシクロブテン(BCB)等が好適である。
チップ形デバイス4が光素子の場合は、シート形光導波路10のミラー部24と、光素子40の受/発光部401との間の光路H2(図5参照)を形成するために、透明の開口部封止部材2の採用が必須となる。
When the resin for forming the filling resin portion 37 and the extended resin layer 37a is an ultraviolet curable resin, the opening sealing member 2 can transmit ultraviolet rays for curing the liquid resin material 8 injected into the device housing hole 31. It is preferable to use a transparent material. Thereby, it is possible to irradiate the resin material 8 in the device housing hole 31 with ultraviolet rays from the side opposite to the circuit board 3 through the opening sealing member 2.
In this case, for example, polyimide, polynorbornene (PNB), benzocyclobutene (BCB), or the like is preferable as a material for forming the transparent sheet-like (or plate-like) opening sealing member 2.
When the chip-type device 4 is an optical element, a transparent optical path H2 (see FIG. 5) is formed between the mirror part 24 of the sheet-type optical waveguide 10 and the light receiving / emitting part 401 of the optical element 40. Adoption of the opening sealing member 2 is essential.

また、透明の開口部封止部材2の採用は、充填樹脂部形成工程において、開口部封止部材2が回路基板3の第1主面3aに被着された状態において、充填樹脂部37及び透明樹脂層38を形成するための樹脂材料8がデバイス収納孔31に注入されることとなり、デバイス内蔵基板1の底部側実装面1aの側から、開口部封止部材2を介して、デバイス収納孔31内への樹脂材料8の充填状況を観察することができる。   In addition, the transparent opening portion sealing member 2 is used in the filling resin portion forming step in the state where the opening portion sealing member 2 is attached to the first main surface 3a of the circuit board 3 and The resin material 8 for forming the transparent resin layer 38 is injected into the device accommodation hole 31, and the device accommodation is performed from the bottom side mounting surface 1 a side of the device built-in substrate 1 through the opening sealing member 2. The filling state of the resin material 8 into the holes 31 can be observed.

充填樹脂部形成工程が完了することで、充填樹脂部37、延長樹脂層37aを具備するデバイス内蔵基板1が得られる。   By completing the filling resin portion forming step, the device-embedded substrate 1 including the filling resin portion 37 and the extended resin layer 37a is obtained.

図1に例示したデバイス内蔵基板1は、回路基板3の第1主面3aに実装された第1金属バンプ12、第2主面3bに実装された第2金属バンプ13、351を利用して、電子部品(例えば、半導体パッケージ等の電子デバイス、配線基板等)の回路との電気的接続(ボンディング)を行える。
第1金属バンプ12は、開口部封止部材2を貫通して、デバイス内蔵基板1の底部側実装面1aから突出されており、デバイス内蔵基板1の底部側実装面1a側に配置される電子部品との電気的接続に利用できる。
The device-embedded substrate 1 illustrated in FIG. 1 uses the first metal bumps 12 mounted on the first main surface 3a of the circuit board 3 and the second metal bumps 13 and 351 mounted on the second main surface 3b. Electrical connection (bonding) with a circuit of an electronic component (for example, an electronic device such as a semiconductor package, a wiring board, etc.) can be performed.
The first metal bump 12 penetrates the opening sealing member 2 and protrudes from the bottom side mounting surface 1a of the device built-in substrate 1, and is arranged on the bottom side mounting surface 1a side of the device built-in substrate 1. It can be used for electrical connection with parts.

図7に示す集積回路デバイス5Aの集積回路部54Aでは、該集積回路部54Aを構成する複数(ここでは3以上)の集積回路用基板51の内、両端の集積回路基板51の間に位置する中間層の集積回路基板51の1つとして前記デバイス内蔵基板1を用いた構成を例示している。
図示例の集積回路部54Aでは、デバイス内蔵基板1の第1、第2金属バンプ12、13を利用して、デバイス内蔵基板1の回路配線とデバイス内蔵基板1の底部側実装面1aの側に積層されている集積回路基板51の回路配線とのボンディングによる電気的接続、デバイス内蔵基板1の回路配線とデバイス内蔵基板1のデバイス実装面1bの側に積層されている集積回路基板51の回路配線とのボンディング、電気的接続を行っている。
また、集積回路部としては、例えば、集積回路用基板51(集積回路用基板51として採用したデバイス内蔵基板を含む)として、その片面(例えば、図7において、各集積回路用基板51の下側の面)のみに金属バンプを具備したものを積層した構成等も採用可能である。
In the integrated circuit portion 54A of the integrated circuit device 5A shown in FIG. 7, the integrated circuit portion 54A is located between the integrated circuit substrates 51 at both ends among a plurality (three or more in this case) of integrated circuit substrates 51 constituting the integrated circuit portion 54A. A configuration in which the device-embedded substrate 1 is used as one of the intermediate circuit substrates 51 is illustrated.
In the illustrated integrated circuit portion 54A, the first and second metal bumps 12 and 13 of the device built-in substrate 1 are used to connect the circuit wiring of the device built-in substrate 1 and the bottom side mounting surface 1a of the device built-in substrate 1 to the side. Electrical connection by bonding with circuit wiring of the laminated integrated circuit board 51, circuit wiring of the device built-in board 1 and circuit wiring of the integrated circuit board 51 laminated on the device mounting surface 1b side of the device built-in board 1 Bonding and electrical connection.
Further, as the integrated circuit section, for example, as an integrated circuit substrate 51 (including a device built-in substrate adopted as the integrated circuit substrate 51), one side thereof (for example, the lower side of each integrated circuit substrate 51 in FIG. 7) It is also possible to adopt a configuration in which metal bumps provided only on the surface are laminated.

なお、集積回路部54としては、中間層の集積回路用基板51に本発明に係るデバイス内蔵基板を適用した構成に限定されず、集積回路部54を構成する複数の集積回路用基板51の内、両端の集積回路基板51の一方又は両方に、本発明に係るデバイス内蔵基板1を適用することも可能である。また、集積回路部を構成する複数の集積回路用基板51の内の2以上が、本発明に係るデバイス内蔵基板1であっても良い。   The integrated circuit portion 54 is not limited to the configuration in which the device-embedded substrate according to the present invention is applied to the intermediate-layer integrated circuit substrate 51, and the integrated circuit portion 54 is not limited to the plurality of integrated circuit substrates 51 constituting the integrated circuit portion 54. The device-embedded substrate 1 according to the present invention can be applied to one or both of the integrated circuit substrates 51 at both ends. Further, two or more of the plurality of integrated circuit substrates 51 constituting the integrated circuit portion may be the device-embedded substrate 1 according to the present invention.

図8は、デバイス内蔵基板1のデバイス実装面1bに、集積回路部として、パッケージ化されたLSIチップ54Bを実装して組み立てた集積回路デバイス5Bを例示する。
この集積回路デバイス5Bでは、デバイス内蔵基板1の第2金属バンプ13、351を、LSIチップ54Bの電極パッド(図示略)と、デバイス内蔵基板1の回路配線(図8においては、具体的には貫通配線33及び第2貫通配線11)とのボンディング、電気的接続に利用している。
但し、本発明では、これに限定されず、例えば、金属バンプを具備するフリップチップタイプのLSIチップを採用し、このLSIチップの金属バンプを利用して、LSIチップの本発明に係るデバイス内蔵基板(但し、第2金属バンプ13、351を具備していないもの)に対するボンディングに利用して、LSIチップをデバイス内蔵基板のデバイス実装面に実装することも可能である。
FIG. 8 illustrates an integrated circuit device 5B assembled by mounting a packaged LSI chip 54B as an integrated circuit portion on the device mounting surface 1b of the device-embedded substrate 1.
In this integrated circuit device 5B, the second metal bumps 13 and 351 of the device built-in substrate 1 are connected to the electrode pads (not shown) of the LSI chip 54B and the circuit wiring (specifically in FIG. 8). It is used for bonding and electrical connection with the through wiring 33 and the second through wiring 11).
However, the present invention is not limited to this. For example, a flip chip type LSI chip provided with metal bumps is adopted, and the LSI built-in device substrate according to the present invention using the metal bumps of the LSI chip. It is also possible to mount the LSI chip on the device mounting surface of the device built-in substrate by using it for bonding to (which does not include the second metal bumps 13 and 351).

図9(a)、(b)は、チップ形デバイス4として、前記パッド設置面43とは反対の側にも、電極パッド441(第2電極パッド)が設けられたパッド設置面431(第2パッド設置面)を具備するもの(チップ形デバイス4A)を採用した構成を例示する。
図示例のチップ形デバイス4Aでは両方のパッド設置面43、431の電極パッド44、441に金属バンプを実装した構成となっている。図中、符号451は、第2電極パッド電極パッド441に実装された金属バンプである。
但し、これに限定されず、片方のパッド設置面の電極パッドのみに金属バンプを実装した構成、両面に金属バンプを具備せず、電極パッド44、441のみが設けられている構成も採用できる。
FIGS. 9A and 9B show, as the chip-type device 4, a pad installation surface 431 (second electrode) in which an electrode pad 441 (second electrode pad) is provided on the side opposite to the pad installation surface 43. The structure which employ | adopted the thing (chip-type device 4A) which comprises a pad installation surface) is illustrated.
The chip type device 4A of the illustrated example has a configuration in which metal bumps are mounted on the electrode pads 44, 441 of both pad mounting surfaces 43, 431. In the figure, reference numeral 451 denotes a metal bump mounted on the second electrode pad electrode pad 441.
However, the present invention is not limited to this, and a configuration in which metal bumps are mounted only on the electrode pads on one of the pad mounting surfaces, or a configuration in which only the electrode pads 44 and 441 are provided without providing metal bumps on both sides can be employed.

図9(a)、(b)に示すように、回路基板3のデバイス収納孔31に組み込むチップとして、このチップ形デバイス4Aを採用して組み立てたデバイス内蔵基板は、そのデバイス実装面1b側に、第2金属バンプ13、351と、チップ形デバイス4Aの第2設置面431に実装されている金属バンプ451とを具備する構造となる。
この場合、金属バンプ451を利用することで、チップ形デバイス4Aと、デバイス内蔵基板のデバイス実装面側に設けられる電子部品6(例えば、図4に例示した集積回路部54、図7に例示した集積回路部54A、図8に例示したLSIチップ54Bを含む)とを直接的に接続(電気的接続)できる。
As shown in FIGS. 9A and 9B, a device-embedded board that is assembled using the chip-type device 4A as a chip to be incorporated in the device housing hole 31 of the circuit board 3 is disposed on the device mounting surface 1b side. The second metal bumps 13 and 351 and the metal bumps 451 mounted on the second installation surface 431 of the chip-type device 4A are provided.
In this case, by using the metal bump 451, the chip-type device 4A and the electronic component 6 provided on the device mounting surface side of the device-embedded substrate (for example, the integrated circuit unit 54 illustrated in FIG. 4 and illustrated in FIG. 7). The integrated circuit portion 54A and the LSI chip 54B illustrated in FIG. 8) can be directly connected (electrically connected).

図4、図7、図8に例示した構成は、デバイス内蔵基板1のデバイス実装面1b側の電子部品6(図示例では集積回路部54B)とチップ形デバイス4とを、デバイス内蔵基板の貫通配線33、配線部32、端子部34を経由して接続する構成である。
これとの対比で、図9(a)、(b)に示す構成の場合は、チップ形デバイス4Aと電子デバイスとの間を接続する接続配線長の短縮が可能である。
4, 7, and 8, the electronic component 6 (integrated circuit portion 54 </ b> B in the illustrated example) and the chip-type device 4 on the device mounting surface 1 b side of the device-embedded substrate 1 pass through the device-embedded substrate. In this configuration, the wiring 33, the wiring part 32, and the terminal part 34 are connected.
In contrast to this, in the case of the configuration shown in FIGS. 9A and 9B, the length of the connection wiring connecting the chip-type device 4A and the electronic device can be shortened.

電子デバイス間の接続配線長の短縮は、電子デバイス間の高周波の信号特性の確保を容易にする。このため、電子デバイス間の信号伝送の高速化、伝送量増大を図ることができる。   The shortening of the connection wiring length between the electronic devices facilitates ensuring high-frequency signal characteristics between the electronic devices. For this reason, it is possible to increase the speed of signal transmission between electronic devices and increase the transmission amount.

次に、チップ形デバイス4として光素子を用いる場合について説明する。
図1、図4、図5等に示すように、ここで採用される光素子40は、パッド設置面43に受/発光部401を具備するものである。本実施形態では、図10に示すように、パッド設置面43において、その中央部に受/発光部401が設置され、電極パッド44が、受/発光部401の周囲の複数箇所に設けられているものを例示している。
なお、発光素子41においては、電極パッド44は、発光素子41への駆動用電気信号の入力端子として機能する。発光素子42においては、電極パッド44は、受光素子42から受光信号(電気信号)を出力するための出力端子として機能する。
Next, a case where an optical element is used as the chip type device 4 will be described.
As shown in FIGS. 1, 4, 5, and the like, the optical element 40 employed here includes a light receiving / emitting unit 401 on a pad installation surface 43. In the present embodiment, as shown in FIG. 10, on the pad installation surface 43, the light receiving / emitting unit 401 is installed at the center, and the electrode pads 44 are provided at a plurality of locations around the receiving / emitting unit 401. This is an example.
In the light emitting element 41, the electrode pad 44 functions as an input terminal for an electric signal for driving to the light emitting element 41. In the light emitting element 42, the electrode pad 44 functions as an output terminal for outputting a light receiving signal (electric signal) from the light receiving element 42.

光素子40において、パッド設置面43は、受/発光部設置面として機能する。光素子40について、パッド設置面43を、以下、受/発光部設置面とも言う。
受/発光部設置面43は、光素子40において、シート形光導波路20に対面する端面である。
なお、受/発光部設置面43における受/発光部401の位置は、必ずしも受/発光部設置面43の中央部である必要は無い。受/発光部設置面43の中央部からずれた位置であっても良い。
また、受/発光部設置面43に設けられる受/発光部401の数は、ひとつだけの場合に限定されず、複数であっても良い(一例として図20(a)〜(c)を参照)。
In the optical element 40, the pad installation surface 43 functions as a light receiving / light emitting unit installation surface. In the optical element 40, the pad installation surface 43 is hereinafter also referred to as a light receiving / emitting unit installation surface.
The light receiving / emitting part installation surface 43 is an end surface of the optical element 40 that faces the sheet-shaped optical waveguide 20.
Note that the position of the light receiving / light emitting unit 401 on the light receiving / light emitting unit installation surface 43 is not necessarily the center of the light receiving / light emitting unit installation surface 43. The position may be shifted from the center of the light receiving / light emitting unit installation surface 43.
Further, the number of light receiving / light emitting portions 401 provided on the light receiving / light emitting portion installation surface 43 is not limited to one, and may be plural (see FIGS. 20A to 20C as an example). ).

光素子40を回路基板3のデバイス収納孔31に組み込んで実装した構成のデバイス内蔵基板については、既述のように、チップ実装工程の完了後の充填樹脂部形成工程にて、透明の開口部封止部材2を用い、透明の合成樹脂からなる充填樹脂部37及び延長樹脂層37a(以下、透明樹脂層38とも言う)を形成する。これにより、デバイス内蔵基板1の底部側実装面1a側の光部品(例えば図4、図5のシート形光導波路)と、光素子40の受/発光部401との光結合を可能とする。
図4、図5に示す集積回路付き光導波路10においては、透明樹脂層38及び開口部封止部材2を介して、シート形光導波路20のミラー部24と光素子40の受/発光部401との間の光伝送(つまり、光路H2の確保)がなされる。
For the device-embedded substrate having the structure in which the optical element 40 is mounted in the device housing hole 31 of the circuit board 3, as described above, in the filling resin portion forming step after the completion of the chip mounting step, the transparent opening Using the sealing member 2, a filling resin portion 37 and an extended resin layer 37a (hereinafter also referred to as a transparent resin layer 38) made of a transparent synthetic resin are formed. This enables optical coupling between the optical component (for example, the sheet-shaped optical waveguide in FIGS. 4 and 5) on the bottom side mounting surface 1 a side of the device-embedded substrate 1 and the light receiving / emitting unit 401 of the optical element 40.
In the optical waveguide with integrated circuit 10 shown in FIGS. 4 and 5, the mirror part 24 of the sheet-shaped optical waveguide 20 and the light receiving / emitting part 401 of the optical element 40 through the transparent resin layer 38 and the opening sealing member 2. Is transmitted (that is, the optical path H2 is secured).

透明の開口部封止部材2の採用は、既述のように、充填樹脂部37及び透明樹脂層38を形成する合成樹脂として紫外線硬化性樹脂を用いて、充填樹脂部37及び延長樹脂層37aを簡単に短時間で形成する、といったことを可能にする。
なお、充填樹脂部37及び透明樹脂層38を形成する合成樹脂としては、既述の熱硬化性樹脂を採用することも可能である。但し、熱硬化性樹脂としては、光路H1、H2の確保に鑑みて透明のものを採用する。
As described above, the transparent opening portion sealing member 2 uses an ultraviolet curable resin as a synthetic resin for forming the filling resin portion 37 and the transparent resin layer 38, and uses the filling resin portion 37 and the extension resin layer 37a. Can be formed easily in a short time.
In addition, as a synthetic resin which forms the filling resin part 37 and the transparent resin layer 38, it is also possible to employ | adopt the thermosetting resin as stated above. However, as the thermosetting resin, a transparent resin is adopted in view of securing the optical paths H1 and H2.

また、図4、図5に示す集積回路付き光導波路10において、透明樹脂層38は、光素子40の受/発光部401とシート形光導波路20との間に空気層が介在することを防止して、空気層の存在に起因する伝送光の散乱による損失の低下に有効に寄与する。   4 and 5, the transparent resin layer 38 prevents the air layer from interposing between the light receiving / emitting part 401 of the optical element 40 and the sheet-shaped optical waveguide 20. Thus, it effectively contributes to a reduction in loss due to scattering of transmitted light due to the presence of the air layer.

集積回路付き光導波路10について説明する。
図4、図5に示すように、集積回路付き光導波路10は、デバイス内蔵基板1に集積回路部を実装(デバイス内蔵基板1のデバイス実装面1bに実装する)してなる集積回路デバイスをシート形光導波路20に実装することで組み立てることができる。
The optical waveguide with integrated circuit 10 will be described.
As shown in FIGS. 4 and 5, the optical waveguide with integrated circuit 10 is a sheet of an integrated circuit device formed by mounting an integrated circuit portion on the device-embedded substrate 1 (mounting on the device mounting surface 1b of the device-embedded substrate 1). It can be assembled by mounting on the optical waveguide 20.

シート形光導波路20のミラー部24は、シート形光導波路20に集積回路付き光導波路10のデバイス内蔵基板1が接合(底部側実装面1aを接合)された状態において、図4、図5に示すように、シート形光導波路20(および開口部封止部材2,透明樹脂層38)を介して回路基板3(デバイス内蔵基板1)とは反対の側から透視できる光素子40の受/発光部401に位置を合わせて、シート形光導波路20に、その回路基板3とは反対の側からV字形の凹部であるミラー部24を形成する。ミラー部24の形成は、例えば、シート形光導波路20のレーザー加工、機械加工等によって行う。
あるいは、ミラー部24を形成済みのシート形光導波路20に、集積回路付き光導波路10を実装して、デバイス内蔵基板1を接合(底部側実装面1aを接合)しても良い。
The mirror portion 24 of the sheet-shaped optical waveguide 20 is shown in FIGS. 4 and 5 in a state where the device-embedded substrate 1 of the optical waveguide with integrated circuit 10 is bonded to the sheet-shaped optical waveguide 20 (the bottom side mounting surface 1a is bonded). As shown, the optical element 40 can receive and emit light through the sheet-shaped optical waveguide 20 (and the opening sealing member 2 and the transparent resin layer 38) from the side opposite to the circuit board 3 (device-embedded substrate 1). The mirror part 24 which is a V-shaped concave part is formed on the sheet-shaped optical waveguide 20 from the side opposite to the circuit board 3 in alignment with the part 401. The mirror portion 24 is formed by, for example, laser processing or machining of the sheet-shaped optical waveguide 20.
Alternatively, the optical waveguide with integrated circuit 10 may be mounted on the sheet-shaped optical waveguide 20 in which the mirror portion 24 has been formed, and the device-embedded substrate 1 may be bonded (the bottom-side mounting surface 1a is bonded).

(シート形光導波路)
シート形光導波路20について説明する。
図16はシート形光導波路20の構造を示す斜視図である。
図16に示すように、シート形光導波路20は、シート状のクラッド部21内に線状のコア部22を有する構造になっている。線状のコア部22の周囲はクラッド部21によって覆われている。
コア部22は直線状である必要はなく、クラッド部21内で湾曲していても良い。また、コア部22には分岐部が存在していても良く、これにより、コア部22を回路状に構成していても良い。
(Sheet type optical waveguide)
The sheet type optical waveguide 20 will be described.
FIG. 16 is a perspective view showing the structure of the sheet-shaped optical waveguide 20.
As shown in FIG. 16, the sheet-shaped optical waveguide 20 has a structure having a linear core portion 22 in a sheet-like clad portion 21. The periphery of the linear core portion 22 is covered with a clad portion 21.
The core part 22 does not need to be linear, and may be curved in the clad part 21. Moreover, the core part 22 may have a branch part, and thereby the core part 22 may be configured in a circuit shape.

前記シート形光導波路20の製造方法としては、例えば、以下の(a)、(b)を採り得る。
(a) 図17(a)に示すように、コア部形成用の樹脂層であるコア層231の両面に、クラッド層232(クラッド部21の一部を形成するための樹脂層)が設けられた3層構造の光導波路形成体23を作成し、この光導波路形成体23に活性エネルギー線を照射してコア部22を形成する(図17(b))。
活性エネルギー線の照射によって、コア層231の一部がコア部22となり、コア層231のコア部22以外の部分と、コア層231の両側のクラッド層232とが、クラッド部21を構成する。
この製造方法の場合は、断面四角形(長方形。但し正方形を含む)のコア部22が得られる。
For example, the following (a) and (b) can be adopted as a method of manufacturing the sheet-shaped optical waveguide 20.
(A) As shown to Fig.17 (a), the clad layer 232 (resin layer for forming a part of clad part 21) is provided in both surfaces of the core layer 231 which is a resin layer for core part formation. An optical waveguide forming body 23 having a three-layer structure is prepared, and the optical waveguide forming body 23 is irradiated with active energy rays to form the core portion 22 (FIG. 17B).
By irradiation with active energy rays, a part of the core layer 231 becomes the core part 22, and a part other than the core part 22 of the core layer 231 and the clad layers 232 on both sides of the core layer 231 constitute the clad part 21.
In the case of this manufacturing method, the core part 22 having a quadrangular cross section (rectangle, but including a square) is obtained.

コア層231を形成する材料としては、例えば、アクリル系樹脂、エポキシ系樹脂、ポリイミド系樹脂、ベンゾシクロブテン系樹脂、ノルボルネン系樹脂等の環状オレフィン系樹脂、といった樹脂材料が挙げられる。ベンゾシクロブテン系樹脂、ノルボルネン系樹脂等の環状オレフィン系樹脂を主材料とする樹脂組成物が好適であり、ノルボルネン系樹脂の付加重合体を主材料とする樹脂組成物が特に好ましい。
コア部22の形成のための活性エネルギー線としては、可視光、紫外光、赤外光、レーザー光等の活性エネルギー光線や、電子線、X線等が挙げられる。電子線は、例えば50〜200KGy程度の照射量で照射することができる。
クラッド層を構成する材料としては、コア層を構成する材料よりも屈折率が低いものであれば特に限定されない。具体的には、アクリル系樹脂、エポキシ系樹脂、ポリイミド系樹脂、ベンゾシクロブテン系樹脂、ノルボルネン系樹脂等の環状オレフィン系樹脂、といった樹脂材料が挙げられる。これらの中でも、ノルボルネン系樹脂の付加重合体を主材料とする樹脂組成物が特に好ましい。
コア層、クラッド層の形成材料としてノルボルネン系樹脂の付加重合体を主材料とする樹脂組成物を採用した場合は、透明性、絶縁性、柔軟性及び耐熱性が充分に得られる。また、他の樹脂を用いた場合との比較で、吸湿性を低くできる。また、ノルボルネン系樹脂の付加重合体を主材料とする樹脂組成物の場合、ノルボルネン系樹脂の付加重合体の側鎖の種類等によって、屈折率を調整することができる利点がある。
Examples of the material for forming the core layer 231 include resin materials such as acrylic resins, epoxy resins, polyimide resins, benzocyclobutene resins, and cyclic olefin resins such as norbornene resins. A resin composition mainly containing a cyclic olefin resin such as a benzocyclobutene resin or a norbornene resin is preferred, and a resin composition mainly containing an addition polymer of a norbornene resin is particularly preferred.
Examples of the active energy rays for forming the core portion 22 include active energy rays such as visible light, ultraviolet light, infrared light, and laser light, electron beams, and X-rays. An electron beam can be irradiated with an irradiation dose of, for example, about 50 to 200 KGy.
The material constituting the cladding layer is not particularly limited as long as the refractive index is lower than that of the material constituting the core layer. Specific examples include resin materials such as acrylic resins, epoxy resins, polyimide resins, benzocyclobutene resins, and cyclic olefin resins such as norbornene resins. Among these, a resin composition mainly comprising an addition polymer of norbornene resin is particularly preferable.
When a resin composition mainly composed of an addition polymer of norbornene-based resin is adopted as a material for forming the core layer and the clad layer, transparency, insulation, flexibility and heat resistance can be sufficiently obtained. In addition, the hygroscopicity can be reduced as compared with the case where other resins are used. In the case of a resin composition mainly composed of an addition polymer of norbornene resin, there is an advantage that the refractive index can be adjusted depending on the type of side chain of the addition polymer of norbornene resin.

3層構造の光導波路形成体23は、例えば、シート状あるいはプレート状の基材に、該光導波路形成体23の個々の層を形成する樹脂材料を含むワニスを塗布して、3層の各層を順次形成していくことで、得ることができる。この場合、例えば、回路基板3自体を基材として用いることも可能である。
集積回路付き光導波路10としては、シート形光導波路20の一方の面に回路基板3、他方の面に3層構造の光導波路形成体23をその個々の層を形成する樹脂材料を含むワニスの塗布によって順次形成する際に用いる基材が設けられた構成であっても良い。
The optical waveguide forming body 23 having a three-layer structure is formed by, for example, applying a varnish containing a resin material for forming individual layers of the optical waveguide forming body 23 to a sheet-like or plate-like base material. Can be obtained by sequentially forming. In this case, for example, the circuit board 3 itself can be used as a base material.
The optical waveguide with integrated circuit 10 is made of a varnish containing a resin material that forms the individual layers of the circuit board 3 on one surface of the sheet-shaped optical waveguide 20 and the optical waveguide forming body 23 having a three-layer structure on the other surface. The structure provided with the base material used when forming in order by application | coating may be sufficient.

(b)予め形成しておいたコア部の周囲をクラッド材(クラッド部)で覆う。
この製造方法の場合は、コア部22の断面形状は自由となる。
(B) The periphery of the core part formed in advance is covered with a clad material (clad part).
In the case of this manufacturing method, the cross-sectional shape of the core part 22 becomes free.

また、集積回路付き光導波路10としては、シート形光導波路20の一方の面に回路基板3、他方の面にシート状あるいはプレート状の基材が被着された構成であっても良い。
前記基材は、例えば、既述の3層構造の光導波路形成体23の個々の層を形成する樹脂材料を含むワニスの塗布によって順次形成する際に用いる基材であっても良い。
但し、基材は、シート形光導波路20へのミラー部24の形成の障害とならないようにする必要がある。このために、例えば、シート形光導波路20から剥離可能なものを採用する、ミラー部24の形成予定位置を避けた箇所のみ設ける、ミラー部24の形成後にシート形光導波路20に被着する、といった対策を採る。
Further, the optical waveguide with integrated circuit 10 may have a configuration in which the circuit board 3 is attached to one surface of the sheet-shaped optical waveguide 20 and a sheet-like or plate-like base material is attached to the other surface.
The base material may be, for example, a base material used when sequentially forming by applying a varnish containing a resin material for forming each layer of the optical waveguide forming body 23 having the three-layer structure described above.
However, it is necessary that the base material does not become an obstacle to the formation of the mirror portion 24 on the sheet-shaped optical waveguide 20. For this purpose, for example, a material that can be peeled off from the sheet-shaped optical waveguide 20 is employed, provided only at a location that avoids the planned formation position of the mirror portion 24, and is attached to the sheet-shaped optical waveguide 20 after the formation of the mirror portion 24. Take the following measures.

図4に例示したLSI5は、集積回路部54が、発光素子41の駆動制御用のドライバー回路及び受光素子42用のレシーバー回路(アンプ)を具備する。集積回路部54の回路は、回路基板3の貫通配線33、配線部32を介して、発光素子41及び受光素子42に電気的に接続されており、
なお、回路基板3に実装する集積回路部54としては、発光素子41のドライバー回路、及び、受光素子42のレシーバー回路の内、一方のみを具備する構成であっても良い。
In the LSI 5 illustrated in FIG. 4, the integrated circuit unit 54 includes a driver circuit for driving control of the light emitting element 41 and a receiver circuit (amplifier) for the light receiving element 42. The circuit of the integrated circuit portion 54 is electrically connected to the light emitting element 41 and the light receiving element 42 via the through wiring 33 and the wiring portion 32 of the circuit board 3.
The integrated circuit unit 54 mounted on the circuit board 3 may be configured to include only one of the driver circuit of the light emitting element 41 and the receiver circuit of the light receiving element 42.

図4に示すように、シート形光導波路20には、デバイス内蔵基板1と、シート形光導波路20を介して前記デバイス内蔵基板1とは反対の側に設けられた電子部品9(例えば、回路基板(第2回路基板)、半導体パッケージ等)とを導電性のボンディング用金属材料によって電気導通可能に接続したボンディング金属部15を収納するためのボンディング材料収納孔25が貫設されている。   As shown in FIG. 4, the sheet-shaped optical waveguide 20 includes a device-embedded substrate 1 and an electronic component 9 (for example, a circuit) provided on the opposite side of the device-embedded substrate 1 via the sheet-shaped optical waveguide 20. A bonding material storage hole 25 is provided through which a bonding metal portion 15 that connects a substrate (second circuit board), a semiconductor package, etc.) with a conductive bonding metal material so as to be electrically conductive can be provided.

ここでは、デバイス内蔵基板1の底部側実装面1a側に突設されている金属バンプ12(図1参照)を、デバイス内蔵基板1と電子部品9とのボンディング、電気的接続に用いている。
電子部品9とのボンディング前のデバイス内蔵基板1の金属バンプ12は、前記ボンディング材料収納孔25に収納されることで、前記シート形光導波路20を介してデバイス内蔵基板1とは反対の側に突出されるため、電子部品9とのボンディングに用いることができる。
Here, the metal bumps 12 (see FIG. 1) protruding from the bottom side mounting surface 1a side of the device built-in substrate 1 are used for bonding and electrical connection between the device built-in substrate 1 and the electronic component 9.
The metal bumps 12 of the device built-in substrate 1 before bonding to the electronic component 9 are housed in the bonding material housing hole 25, so that they are on the side opposite to the device built-in substrate 1 through the sheet-shaped optical waveguide 20. Since it protrudes, it can be used for bonding with the electronic component 9.

また、デバイス内蔵基板1の金属バンプ12を省略して、電子部品9に突設した金属バンプを、デバイス内蔵基板1と電子部品9とのボンディングに用いることも可能である。この場合は、電子部品9に突設した金属バンプとして、該金属バンプをボンディング材料収納孔25に挿入したときに、デバイス内蔵基板1(詳細には電極パッド14)に当接させることができるサイズのものを採用する。   It is also possible to omit the metal bump 12 of the device built-in substrate 1 and use the metal bump protruding from the electronic component 9 for bonding the device built-in substrate 1 and the electronic component 9. In this case, as a metal bump protruding from the electronic component 9, the metal bump can be brought into contact with the device-embedded substrate 1 (specifically, the electrode pad 14) when the metal bump is inserted into the bonding material storage hole 25. Adopt one.

なお、シート形光導波路20にボンディング材料収納孔25を加工(形成)する手法としては、例えば、エキシマレーザーを用いたレーザー加工が好適である。この他、反応性イオンエッチング(Reactive Ion Etching;RIE)を用いる方法や、感光性を有するシート形光導波路20の露光、現像による加工等も採用可能である。
レーザー加工では、ステンシルマスクの使用等によって、所望の大きさのボンディング材料収納孔25を容易に加工できる。反応性イオンエッチング、感光性を有するシート形光導波路20の露光、現像では、フィルム状のマスクや、レジスト樹脂の使用等によって、所望の大きさのボンディング材料収納孔25を容易に加工できる。
As a method for processing (forming) the bonding material accommodation hole 25 in the sheet-shaped optical waveguide 20, for example, laser processing using an excimer laser is suitable. In addition, a method using reactive ion etching (RIE), exposure of the sheet-shaped optical waveguide 20 having photosensitivity, and processing by development can be employed.
In laser processing, the bonding material accommodation hole 25 having a desired size can be easily processed by using a stencil mask or the like. In the exposure and development of the reactive ion etching and the photosensitive sheet-shaped optical waveguide 20, the bonding material accommodation hole 25 having a desired size can be easily processed by using a film-like mask or a resist resin.

図4等に示す図示例の集積回路付き光導波路10では、デバイス内蔵基板1のデバイス実装面1b側に設けられた集積回路部54の回路が、ボンディング用金属材料を用いたボンディングによってデバイス内蔵基板1の第2貫通配線11に電気導通可能に接続され、シート形光導波路20を介してデバイス内蔵基板1とは反対の側に設けられた電子部品9がボンディング金属部15を介してデバイス内蔵基板1の第2貫通配線11にボンディングされ、集積回路デバイス5の回路と電子部品9の回路とが、第2貫通配線11を介して電気的に接続されている。
デバイス内蔵基板1の第2貫通配線11は、デバイス内蔵基板1のデバイス実装面1b側に設けられた集積回路部54と、デバイス内蔵基板1とボンディングした電子部品9とを、電気的に接続するための接続配線として機能する。
In the optical waveguide with integrated circuit 10 illustrated in FIG. 4 and the like, the circuit of the integrated circuit portion 54 provided on the device mounting surface 1b side of the device-embedded substrate 1 is bonded to the device-embedded substrate by bonding using a bonding metal material. An electronic component 9 that is connected to one second through wiring 11 so as to be electrically conductive and is provided on the side opposite to the device-embedded substrate 1 via the sheet-shaped optical waveguide 20 is connected to the device-embedded substrate via the bonding metal portion 15. Bonded to one second through wiring 11, the circuit of the integrated circuit device 5 and the circuit of the electronic component 9 are electrically connected via the second through wiring 11.
The second through wiring 11 of the device built-in substrate 1 electrically connects the integrated circuit portion 54 provided on the device mounting surface 1b side of the device built-in substrate 1 and the electronic component 9 bonded to the device built-in substrate 1. Function as connection wiring.

図4においては、前記電子部品9として、回路基板(以下、符号9を付して、第2回路基板とも言う)を採用した構成を例示している。
この第2回路基板9は、シート形光導波路20に沿って延在されており、シート形光導波路20に積層して被着されている。この第2回路基板9は、集積回路付き光導波路10の集積回路デバイス5間を電気的に接続する集積回路間接続用基板として機能する。
In FIG. 4, a configuration in which a circuit board (hereinafter referred to as a reference numeral 9 and also referred to as a second circuit board) is employed as the electronic component 9 is illustrated.
The second circuit board 9 extends along the sheet-shaped optical waveguide 20 and is laminated and attached to the sheet-shaped optical waveguide 20. The second circuit board 9 functions as an inter-integrated circuit connecting board that electrically connects the integrated circuit devices 5 of the optical waveguide with integrated circuit 10.

第2回路基板9は、シート形光導波路20に臨む接合面91に、集積回路デバイス5間の接続用の回路配線92(集積回路間接続用配線)を有している。この回路配線92には、ボンディング金属部15を介して、集積回路付き光導波路10の集積回路部54の回路が電気導通可能に接続されている。この第2回路基板9の回路配線92を介して、互いに離隔させてシート形光導波路20に設けられている複数の集積回路デバイス5の回路同士を電気的に接続できる。   The second circuit board 9 has circuit wirings 92 for connecting between the integrated circuit devices 5 (interconnecting circuits for connecting integrated circuits) on the joint surface 91 facing the sheet-shaped optical waveguide 20. The circuit wiring 92 is connected to the circuit of the integrated circuit portion 54 of the optical waveguide with integrated circuit 10 through the bonding metal portion 15 so as to be electrically conductive. The circuits of the plurality of integrated circuit devices 5 provided in the sheet-shaped optical waveguide 20 can be electrically connected to each other through the circuit wiring 92 of the second circuit board 9 so as to be separated from each other.

(混載形デバイス内蔵基板)
図6は、既述のように、デバイス収納孔31を複数(ここでは4以上)有する1つの回路基板3に、チップ形デバイス4として、発光素子41、該発光素子41の駆動用のドライバー素子46、受光素子42、該受光素子42の受光信号変換用のレシーバー素子47(アンプ)を組み込んだ構成のデバイス内蔵基板1A(混載形デバイス内蔵基板)を例示している。なお、図示を略すが、各チップ形デバイス4(発光素子41、ドライバー素子46、受光素子42、レシーバー素子47)は、いずれも、デバイス収納孔31内に形成された充填樹脂部37、延長樹脂層37aによって固定されている。
このデバイス内蔵基板1Aは、回路基板3の第1主面3aに、貫通配線33と端子部34との間の接続用の配線部32の他に、回路基板3に組み込まれているチップ形デバイス4間の接続用の配線321(以下、チップ間接続用配線とも言う)を具備する。
(Built-in hybrid device board)
As described above, FIG. 6 shows a light emitting element 41 and a driver element for driving the light emitting element 41 as a chip-type device 4 on one circuit board 3 having a plurality of device housing holes 31 (four or more in this case). 46, a light receiving element 42 and a device built-in substrate 1A (mixed device built-in substrate) configured to incorporate a light receiving signal converting receiver element 47 (amplifier) of the light receiving element 42 are illustrated. Although not shown, each of the chip-type devices 4 (the light emitting element 41, the driver element 46, the light receiving element 42, and the receiver element 47) has a filling resin portion 37 and an extension resin formed in the device housing hole 31. It is fixed by the layer 37a.
The device-embedded substrate 1A is a chip-type device incorporated in the circuit board 3 on the first main surface 3a of the circuit board 3 in addition to the wiring part 32 for connection between the through wiring 33 and the terminal part 34. 4 is provided with a wiring 321 for connection between the four (hereinafter also referred to as inter-chip connection wiring).

チップ間接続用配線321は、回路基板3のデバイス収納孔31間に形成されており、回路基板3の互いに異なる位置のデバイス収納孔31にそれぞれ突設されている端子部34と電気的に接続されている。
このデバイス内蔵基板1Aでは、デバイス収納孔31に組み込んで実装されたチップ形デバイス4の回路同士を、チップ間接続用配線321を介して電気的に接続できる。
The interchip connection wiring 321 is formed between the device storage holes 31 of the circuit board 3 and is electrically connected to the terminal portions 34 respectively protruding from the device storage holes 31 at different positions of the circuit board 3. Has been.
In this device built-in substrate 1 </ b> A, the circuits of the chip-type device 4 mounted in the device housing hole 31 can be electrically connected via the inter-chip connection wiring 321.

チップ間接続用配線321は、2つのチップ形デバイス4の回路同士の接続に対応するべく、2つのデバイス収納孔31間に形成しても良いが、3以上のチップ形デバイス4の回路同士の接続に対応するべく、3以上のデバイス収納孔31のそれぞれに突設されている端子部34と電気的に接続した構成としても良い。   The interchip connection wiring 321 may be formed between the two device housing holes 31 so as to correspond to the connection between the circuits of the two chip type devices 4, but between the circuits of the three or more chip type devices 4. In order to correspond to the connection, it may be configured to be electrically connected to the terminal portion 34 protruding from each of the three or more device storage holes 31.

図6に例示したデバイス内蔵基板1Aでは、発光素子41とドライバー素子46、受光素子42とレシーバー素子47とを、それぞれチップ間接続用配線321を介して電気的に接続している。
このため、このデバイス内蔵基板1Aにあっては、例えば、発光素子41、受光素子42を、デバイス内蔵基板1の貫通配線33、配線部32、端子部34を経由して、デバイス内蔵基板1A上に実装した集積回路部54の回路と電気的に接続する構成に比べて、発光素子41とドライバー素子46との間、受光素子42とレシーバー素子47との間を接続する接続配線長は短くて済み、接続配線長を短縮できる。
チップ形デバイス4間の接続配線長の短縮は、チップ形デバイス4間の高周波の信号特性の確保を容易にする。このため、電子デバイス間の信号伝送の高速化、伝送量増大を図ることができる。
In the device-embedded substrate 1A illustrated in FIG. 6, the light emitting element 41 and the driver element 46, and the light receiving element 42 and the receiver element 47 are electrically connected to each other via an interchip connection wiring 321.
For this reason, in the device built-in substrate 1A, for example, the light emitting element 41 and the light receiving element 42 are connected to the device built-in substrate 1A via the through wiring 33, the wiring unit 32, and the terminal unit 34 of the device built-in substrate 1. The connection wiring length connecting the light emitting element 41 and the driver element 46 and between the light receiving element 42 and the receiver element 47 is shorter than the configuration in which the circuit is electrically connected to the circuit of the integrated circuit unit 54 mounted in FIG. The connection wiring length can be shortened.
The shortening of the connection wiring length between the chip-type devices 4 facilitates ensuring high-frequency signal characteristics between the chip-type devices 4. For this reason, it is possible to increase the speed of signal transmission between electronic devices and increase the transmission amount.

(集積回路付き光導波路の別態様)
図18は、開口部封止部材2を有していないデバイス内蔵基板1Bを具備する集積回路デバイス5Bを、シート形光導波路20に被着した構成の集積回路付き光導波路10Aを示す。
この集積回路付き光導波路10Aにあっては、回路基板3の第1主面3aが、直接、シート形光導波路20に接合される。
(Another aspect of optical waveguide with integrated circuit)
FIG. 18 shows an optical waveguide with integrated circuit 10 </ b> A in which an integrated circuit device 5 </ b> B having a device-embedded substrate 1 </ b> B that does not have the opening sealing member 2 is attached to a sheet-shaped optical waveguide 20.
In the optical waveguide with integrated circuit 10 </ b> A, the first main surface 3 a of the circuit board 3 is directly bonded to the sheet-shaped optical waveguide 20.

開口部封止部材2を有していないデバイス内蔵基板1Bは、例えば、既述の開口部封止部材2付きのデバイス内蔵基板1から開口部封止部材2を除去する、充填樹脂部形成工程を、回路基板3に対して接離自在の封止プレート等を使用してデバイス収納孔31の開口部を塞いだ状態で行う(充填樹脂部形成工程の完了後に、封止プレートを回路基板3から離隔させる)、ことによって得ることができる。   For example, the device-embedded substrate 1B that does not have the opening sealing member 2 removes the opening sealing member 2 from the device-embedded substrate 1 with the opening sealing member 2 described above. Is performed in a state in which the opening of the device housing hole 31 is closed using a sealing plate or the like that can be moved toward and away from the circuit board 3 (after the filling resin portion forming step is completed, the sealing plate is attached to the circuit board 3). Can be obtained by

この集積回路付き光導波路10Aの場合は、回路基板3とシート形光導波路20との間に開口部封止部材2が介在しないため、図4、図5に例示した集積回路付き光導波路10に比べて、光素子40の受/発光部401とミラー部24との間の距離が短い。また、光素子40の受/発光部401とミラー部24との間に存在する樹脂層の数(換言すれば光路H2が通る樹脂層の数)が少ないため、層間の界面での伝送光の散乱が抑えられ、シート形光導波路20と光素子40の受/発光部401との間での光損失を小さくすることができる。つまり、シート形光導波路20と光素子40の受/発光部401との間の結合損失の低減、発光素子41からシート形光導波路20への送入光の挿入損失の低減を容易に実現できる。   In the case of this optical waveguide with integrated circuit 10A, since the opening sealing member 2 is not interposed between the circuit board 3 and the sheet-shaped optical waveguide 20, the optical waveguide with integrated circuit 10 illustrated in FIGS. In comparison, the distance between the light receiving / emitting unit 401 of the optical element 40 and the mirror unit 24 is short. Further, since the number of resin layers (in other words, the number of resin layers through which the optical path H2 passes) between the light receiving / emitting section 401 and the mirror section 24 of the optical element 40 is small, the transmission light at the interface between the layers is reduced. Scattering is suppressed, and light loss between the sheet-shaped optical waveguide 20 and the light receiving / emitting unit 401 of the optical element 40 can be reduced. That is, it is possible to easily realize a reduction in coupling loss between the sheet-shaped optical waveguide 20 and the light receiving / emitting section 401 of the optical element 40 and a reduction in insertion loss of light transmitted from the light-emitting element 41 to the sheet-shaped optical waveguide 20. .

(電子デバイス内蔵基板の組立方法(集積回路付き光導波路)の組立方法の別態様)
図18に示す集積回路付き光導波路10Aは、例えば、図19に示すように、回路基板3に直接被着(具体的には第1主面3aに被着)したシート形光導波路20自体を開口部封止部材として充填樹脂部形成工程を行って得ることもできる。
チップ実装工程は、充填樹脂部形成工程の前に行う。シート形光導波路20は、チップ実装工程の完了後に行うことが好ましい。
(Another method of assembling the electronic device-embedded substrate (optical waveguide with integrated circuit))
An optical waveguide with integrated circuit 10A shown in FIG. 18 includes, for example, a sheet-type optical waveguide 20 itself directly attached to the circuit board 3 (specifically, attached to the first main surface 3a) as shown in FIG. It can also obtain by performing a filling resin part formation process as an opening part sealing member.
The chip mounting process is performed before the filling resin portion forming process. The sheet-shaped optical waveguide 20 is preferably performed after the completion of the chip mounting process.

(受/発光部を複数持つ光素子の採用)
本発明に係るデバイス内蔵基板に適用される光素子40としては、既述のように、受/発光部設置面43に受/発光部401が複数設けられているものも採用可能である。
但し、金属バンプのリフローによる、光素子40の回路基板3に対するセルフアライメントを出来るだけ有効に機能させる点で、例えば図20(a)〜(c)に示すように、受/発光部設置面43において、受/発光部401を介して両側に電極パッド44が設けられている構成のものを採用することが好ましい。
図20(a)〜(c)の光素子40に、区別のため、符号40A、40B、40Cを付す。
(Adopting optical elements with multiple light receiving / emitting sections)
As described above, the optical element 40 applied to the device-embedded substrate according to the present invention may be one in which a plurality of light receiving / light emitting portions 401 are provided on the light receiving / light emitting portion installation surface 43.
However, as shown in FIGS. 20A to 20C, for example, as shown in FIGS. 20A to 20C, the light receiving / light emitting portion installation surface 43 is provided so that self-alignment of the optical element 40 with respect to the circuit board 3 can be performed as much as possible by reflowing metal bumps. In this case, it is preferable to adopt a configuration in which the electrode pads 44 are provided on both sides via the light receiving / emitting unit 401.
Reference numerals 40A, 40B, and 40C are attached to the optical elements 40 in FIGS.

図20(a)〜(c)に示す例では、光素子40は、長方形の受/発光部設置面43を有する外観直方体状のチップである。
図20(a)、(c)に示す光素子40A、40Cは、長方形の受/発光部設置面43の幅方向中央部(長方形の受/発光部設置面43の短辺に沿った方向の中央部)に、複数の受/発光部401が、長方形の受/発光部設置面43の長手方向に沿って一列に配列設置され、この複数の受/発光部401が配列されてなる受/発光部設置列401Lを介して両側の複数箇所に、それぞれ、電極パッド44が設置された構成になっている。
In the example shown in FIGS. 20A to 20C, the optical element 40 is a chip having a rectangular parallelepiped shape having a rectangular light receiving / emitting part installation surface 43.
Optical elements 40A and 40C shown in FIGS. 20 (a) and 20 (c) have a central portion in the width direction of the rectangular light receiving / light emitting portion installation surface 43 (in the direction along the short side of the rectangular light receiving / light emitting portion installation surface 43). A plurality of light receiving / light emitting portions 401 are arranged and arranged in a line along the longitudinal direction of the rectangular light receiving / light emitting portion installation surface 43 in the center portion, and the plurality of light receiving / light emitting portions 401 are arranged. The electrode pads 44 are installed at a plurality of locations on both sides via the light emitting unit installation row 401L.

仮に、電極パッド44が、受/発光部設置列401Lを介して両側の内の片側のみに設けられている構成の場合は、デバイス収納孔31内に光素子を収納して、各電極パッド44に実装しておいた金属バンプを端子部34のコンタクト面34aに当接させたときに、光素子40が傾いてしまい、金属バンプをリフローしても、光素子40の回路基板3に対するセルフアライメントが有効に機能しない可能性が出てくる。これに対して、図20(a)、(c)に示す光素子40A、40Cのように、受/発光部設置列401Lを介して両側の複数箇所に電極パッド44が設置された構成であれば、デバイス収納孔31内に光素子を収納して、各電極パッド44に実装しておいた金属バンプを端子部34のコンタクト面34aに当接させたときに、光素子40に無用な傾きを与えることを防ぐことができ、金属バンプのリフローによって、光素子40の回路基板3に対するセルフアライメントを確実に行うことができる。   If the electrode pad 44 is provided on only one side of the both sides via the light receiving / emitting unit installation row 401L, the optical element is accommodated in the device accommodation hole 31, and each electrode pad 44 is accommodated. The optical element 40 tilts when the metal bump mounted on the contact portion 34a is brought into contact with the contact surface 34a of the terminal portion 34, and the self-alignment of the optical element 40 with respect to the circuit board 3 even if the metal bump is reflowed. May not work effectively. On the other hand, as in the optical elements 40A and 40C shown in FIGS. 20A and 20C, the electrode pads 44 may be installed at a plurality of positions on both sides via the light receiving / emitting section installation row 401L. For example, when the optical element is stored in the device storage hole 31 and the metal bump mounted on each electrode pad 44 is brought into contact with the contact surface 34a of the terminal portion 34, the optical element 40 is tilted unnecessarily. And the self-alignment of the optical element 40 with respect to the circuit board 3 can be reliably performed by reflowing the metal bumps.

長方形の受/発光部設置面43を有する光素子40において、金属バンプのリフローによって、光素子40の回路基板3に対するセルフアライメントを有効に機能させる点では、電極パッド44が、長方形の受/発光部設置面43の幅方向両側のそれぞれにて受/発光部設置面43の長手方向に沿う複数箇所に設けられている構成であることが好ましい。この点、受/発光部401は、必ずしも、受/発光部設置列401Lを形成する配置である必要はない。例えば、受/発光部401を、受/発光部設置面43の幅方向両側の、電極パッド44が設置されている領域内に設置し、受/発光部設置面43の幅方向中央部には設置しない、構成等を排除するものでは無い。   In the optical element 40 having the rectangular light receiving / emitting part installation surface 43, the electrode pad 44 is rectangular in light receiving / emitting light in that the self-alignment of the optical element 40 with respect to the circuit board 3 effectively functions by reflowing the metal bumps. It is preferable that the configuration is provided at a plurality of locations along the longitudinal direction of the light receiving / light emitting unit installation surface 43 on each of both sides in the width direction of the unit installation surface 43. In this regard, the light receiving / light emitting unit 401 is not necessarily arranged to form the light receiving / light emitting unit installation row 401L. For example, the light receiving / light emitting unit 401 is installed in the region where the electrode pad 44 is installed on both sides in the width direction of the light receiving / light emitting unit installation surface 43, and at the center in the width direction of the light receiving / light emitting unit installation surface 43. It does not exclude the configuration, etc. that are not installed.

図20(b)の光素子40Bは、受/発光部401と電極パッド44とを、長方形の受/発光部設置面43の長手方向に沿って一列に配列設置した構成になっている。
この場合、デバイス収納孔31内に光素子を収納して、各電極パッド44に実装しておいた金属バンプを端子部34のコンタクト面34aに当接させたときには、図20(a)、(c)に示す光素子40A、40Cに比べて光素子の姿勢安定性が劣るが、金属バンプのリフローによる光素子40の回路基板3に対するセルフアライメントは問題なく実現できる。
The optical element 40B of FIG. 20B has a configuration in which the light receiving / emitting section 401 and the electrode pad 44 are arranged in a line along the longitudinal direction of the rectangular receiving / light emitting section installation surface 43.
In this case, when the optical element is housed in the device housing hole 31 and the metal bump mounted on each electrode pad 44 is brought into contact with the contact surface 34a of the terminal portion 34, FIG. Although the posture stability of the optical element is inferior to the optical elements 40A and 40C shown in c), self-alignment of the optical element 40 with respect to the circuit board 3 by reflow of metal bumps can be realized without any problem.

なお、長方形の受/発光部設置面43を有する外観直方体状のチップに形成された光素子40を採用した場合でも、デバイス収納孔31の軸心31aに垂直の断面を、前記光素子4における前記デバイス収納孔31の軸心31aに垂直の断面寸法よりも若干大きい(前記電極パッド44のコンタクト面44aの寸法の5〜195%だけ大きくした)寸法の長方形とすることは、正方形の受/発光部設置面43を有する光素子の場合と同様である。
また、断面長方形のデバイス収納孔31は、その断面長辺寸法を、光素子40のデバイス収納孔31の軸心31a(中心軸線)に垂直の断面(断面形状は矩形。図示例では正方形)の対角線寸法よりも小さくする。
Even when the optical element 40 formed on the rectangular parallelepiped chip having the rectangular light receiving / emitting portion installation surface 43 is employed, a cross section perpendicular to the axis 31 a of the device housing hole 31 is taken as the optical element 4. A rectangular shape having a dimension slightly larger than the cross-sectional dimension perpendicular to the axis 31a of the device housing hole 31 (enlarged by 5 to 195% of the dimension of the contact surface 44a of the electrode pad 44) This is the same as the case of the optical element having the light emitting portion installation surface 43.
Further, the device housing hole 31 having a rectangular cross section has a long side dimension of the cross section perpendicular to the axis 31a (center axis) of the device housing hole 31 of the optical element 40 (the cross sectional shape is rectangular. In the illustrated example, the square shape). Make it smaller than the diagonal dimension.

長方形の受/発光部設置面43の長手方向に沿った複数箇所に受/発光部401が設けられている構成の光素子40を採用した場合、シート形導波路20として、光素子40の複数の受/発光部401に対応する本数(あるいは受/発光部401の数よりも多くても良い)のコア部22を具備するものを採用する。また、光素子40の各受/発光部401に対応する位置にミラー部24を設けて、該ミラー部24を介して、シート形導波路20のコア部22毎に対応する光路と受/発光部401とを1対1に光結合させる。   When the optical element 40 having a configuration in which the light receiving / emitting parts 401 are provided at a plurality of locations along the longitudinal direction of the rectangular light receiving / emitting part installation surface 43, a plurality of the optical elements 40 are used as the sheet-shaped waveguide 20. The number of core portions 22 corresponding to the number of the light receiving / light emitting portions 401 (or the number of the light receiving / light emitting portions 401 may be larger) is adopted. In addition, a mirror part 24 is provided at a position corresponding to each light receiving / emitting part 401 of the optical element 40, and an optical path and light receiving / emitting light corresponding to each core part 22 of the sheet-shaped waveguide 20 via the mirror part 24. The unit 401 is optically coupled on a one-to-one basis.

現在、市販されている、受/発光部401を複数持つタイプの光素子40は、長方形の受/発光部設置面43の長手方向における受/発光部401の設置間隔が250μmであることが一般的である。これに対応するには、シート形光導波路20にて、光素子40の複数の受/発光部401に対応して並列に形成されるコア部22の配列間隔も250μmとする。   The optical element 40 of the type having a plurality of light receiving / light emitting portions 401 that is currently on the market generally has an installation interval of the light receiving / light emitting portions 401 in the longitudinal direction of the rectangular light receiving / light emitting portion installation surface 43 of 250 μm. Is. In order to cope with this, the arrangement interval of the core portions 22 formed in parallel corresponding to the plurality of light receiving / emitting portions 401 of the optical element 40 in the sheet-shaped optical waveguide 20 is also set to 250 μm.

シート形光導波路20に並列に形成されるコア部22の配列間隔は、光素子40における長方形の受/発光部設置面43の長手方向における受/発光部401の設置間隔と揃えるが、受/発光部401の設置間隔は250μmに限定されない。250μm以外(例えば、125μm)の場合は、これに応じて、コア部22の配列間隔も、受/発光部401の設置間隔と揃える。   The arrangement interval of the core portions 22 formed in parallel with the sheet-shaped optical waveguide 20 is aligned with the installation interval of the light receiving / light emitting portions 401 in the longitudinal direction of the rectangular light receiving / light emitting portion installation surface 43 in the optical element 40. The installation interval of the light emitting units 401 is not limited to 250 μm. In the case of other than 250 μm (for example, 125 μm), the arrangement interval of the core portions 22 is also aligned with the installation interval of the light receiving / emitting portions 401 accordingly.

本発明に係るデバイス内蔵基板、回路基板3によれば、チップ形電子デバイス4を、回路基板3のデバイス収納孔31に組み込んで回路基板3に実装する構成であるため、実装したチップ形電子デバイス4を含むデバイス内蔵基板全体のサイズの小型化を容易に実現できる。
複数の集積回路用基板を積層してなる集積回路(集積回路デバイス)を構成する集積回路用基板として、本発明に係るデバイス内蔵基板1を適用することで、集積回路デバイスの小型化を容易に実現できる。
According to the device-embedded substrate and the circuit board 3 according to the present invention, the chip-type electronic device 4 is built in the device housing hole 31 of the circuit board 3 and mounted on the circuit board 3. 4 can easily be reduced in size of the entire device-embedded substrate including 4.
By applying the device-embedded substrate 1 according to the present invention as an integrated circuit substrate constituting an integrated circuit (integrated circuit device) formed by stacking a plurality of integrated circuit substrates, it is possible to easily reduce the size of the integrated circuit device. realizable.

集積回路デバイスを構成する複数の集積回路用基板の1つ以上として、チップ形デバイス4を回路基板3のデバイス収納孔31に組み込んだデバイス内蔵基板を用いることで、集積回路デバイスの製造上、複数の集積回路用基板を積層してなる多層基板上にチップ形デバイスをワイヤボンディング等によって実装する工程を無くす(あるいは、ワイヤボンディング等によって実装するチップ形デバイスの数を減少)ことができ、集積回路デバイスの組み立てを効率良く行える。また、複数の集積回路用基板を積層して集積回路デバイスを組み立てる工程は、周知、既存の技術を適用可能であり、生産性の確保の点で有利である。   By using a device-embedded substrate in which the chip-type device 4 is incorporated in the device housing hole 31 of the circuit substrate 3 as one or more of the plurality of integrated circuit substrates constituting the integrated circuit device, a plurality of integrated circuit devices are manufactured. It is possible to eliminate the step of mounting a chip-type device by wire bonding or the like on a multilayer substrate formed by stacking integrated circuit substrates (or to reduce the number of chip-type devices to be mounted by wire bonding or the like). The device can be assembled efficiently. In addition, a known and existing technique can be applied to the process of assembling an integrated circuit device by stacking a plurality of integrated circuit substrates, which is advantageous in terms of ensuring productivity.

上述のデバイス内蔵基板を組み立てるにあたり、チップ形デバイスの位置決め、実装は、回路基板3のデバイス収納孔31内に収納したチップ形デバイス4の金属バンプをリフローするだけで、セルフアライメントによって、簡単に行える。回路基板3に対するチップ形デバイスの位置決め、実装は、複数の集積回路用基板を積層して組み立てた多層基板上にワイヤボンディング等によってチップ形デバイスを実装する技術に比べて、簡単に効率良く行える。   In assembling the above-described device-embedded substrate, the positioning and mounting of the chip-type device can be easily performed by self-alignment simply by reflowing the metal bumps of the chip-type device 4 housed in the device housing hole 31 of the circuit board 3. . The positioning and mounting of the chip-type device with respect to the circuit board 3 can be performed simply and efficiently as compared with the technique of mounting the chip-type device by wire bonding or the like on a multilayer substrate assembled by stacking a plurality of integrated circuit substrates.

さらに、本発明に係る集積回路デバイスによれば、デバイス内蔵基板の採用によって、集積回路デバイスの内部にチップ形デバイス4を内蔵した構成となるので、チップ形電子デバイス4の実装数の増加も容易に実現できる。
また、チップ形電子デバイス4は、集積回路デバイスを構成する回路基板に内蔵されているため、パッケージングを単純化、あるいは、パッケージングが不要となり、低コスト化を容易に実現できる。
Further, according to the integrated circuit device of the present invention, since the chip-type device 4 is built in the integrated circuit device by adopting the device-embedded substrate, the number of mounted chip-type electronic devices 4 can be easily increased. Can be realized.
Further, since the chip-type electronic device 4 is built in a circuit board constituting the integrated circuit device, packaging is simplified or packaging is not required, and cost reduction can be easily realized.

本発明では、回路基板3に形成するデバイス収納孔31のサイズによって、チップ形デバイス4のサイズ(パッド設置面43に沿った方向のサイズ)に対応できる。
また、チップ形デバイス4の位置決めに、金属バンプのリフローによるセルフアライメントを採用することで、チップ形デバイス4の外周面とデバイス収納孔31の内周面との間に確保するギャップの範囲で、デバイス収納孔31に、チップ形デバイス4のサイズ(パッド設置面43に沿った方向のサイズ)に対する若干の汎用性を確保できる。
In the present invention, the size of the chip-type device 4 (the size in the direction along the pad installation surface 43) can be accommodated by the size of the device housing hole 31 formed in the circuit board 3.
In addition, by adopting self-alignment by reflow of metal bumps for positioning of the chip-shaped device 4, in the range of the gap secured between the outer peripheral surface of the chip-shaped device 4 and the inner peripheral surface of the device housing hole 31, In the device housing hole 31, some versatility can be ensured with respect to the size of the chip-type device 4 (size in the direction along the pad installation surface 43).

また、図21(a)、(b)に示すように、本発明では、チップ形デバイス4の高さ寸法h(パッド設置面43に垂直の方向の寸法)に幅広く対応するために、回路基板3として、その厚さ寸法t及びデバイス収納孔31の軸方向寸法dが、チップ形デバイス4の高さ寸法h1、h2に比べて充分に大きいもの(図中、符号3A)を採用し、この回路基板3Aのデバイス収納孔31にチップ形デバイス4を組み込んで実装した後(充填樹脂部形成工程の完了後)に、得られたデバイス内蔵基板1Cのデバイス実装面1b側からの研磨等によって、デバイス内蔵基板1Cの厚みを薄くことも可能である。
チップ形デバイス4の実装後にデバイス内蔵基板1Cを薄くすることで、デバイス内蔵基板1C、回路基板3Aの厚さ寸法を、チップ形デバイス4の高さ寸法h1、h2に対応して適宜調整できる。また、デバイス内蔵基板1Cの厚さ寸法の縮小によって、該デバイス内蔵基板1Cを用いて構成される集積回路デバイスの小型化等を実現できる。
なお、デバイス内蔵基板1Cの厚みをデバイス実装面1b側から薄くしていくため手法としては、研磨に限定されない。例えば、レーザー等を用いた切断、機械的切削、切断、あるいは、これらの内のいずれかと研磨との併用等、を挙げることができる。
In addition, as shown in FIGS. 21A and 21B, in the present invention, in order to widely correspond to the height dimension h (dimension in the direction perpendicular to the pad installation surface 43) of the chip-type device 4, a circuit board is used. 3 in which the thickness dimension t and the axial dimension d of the device housing hole 31 are sufficiently larger than the height dimensions h1 and h2 of the chip-type device 4 (reference numeral 3A in the figure). After the chip-type device 4 is assembled and mounted in the device housing hole 31 of the circuit board 3A (after completion of the filling resin portion forming step), by polishing from the device mounting surface 1b side of the obtained device built-in substrate 1C, etc. It is also possible to reduce the thickness of the device built-in substrate 1C.
By reducing the thickness of the device-embedded substrate 1C after the chip-type device 4 is mounted, the thickness dimensions of the device-embedded substrate 1C and the circuit board 3A can be appropriately adjusted according to the height dimensions h1 and h2 of the chip-type device 4. Further, by reducing the thickness dimension of the device-embedded substrate 1C, it is possible to reduce the size of an integrated circuit device configured using the device-embedded substrate 1C.
The method for reducing the thickness of the device-embedded substrate 1C from the device mounting surface 1b side is not limited to polishing. For example, cutting using a laser or the like, mechanical cutting, cutting, or a combination of any of these and polishing may be used.

チップ形デバイス4が光素子の場合は、光素子40を組み込んだデバイス内蔵基板をシート形光導波路に被着することで、例えばシート形光導波路上に被着した基板上に実装した光素子をシート形光導波路と光結合させる構成に比べて、光素子40の受/発光部401をシート形光導波路20に近接配置することが容易であり、これにより、光素子40とシート形光導波路20との間の結合損失の低減、発光素子41からシート形光導波路20への送入光の挿入損失の低減を容易に実現できる。   When the chip-type device 4 is an optical element, an optical element mounted on a substrate deposited on the sheet-shaped optical waveguide, for example, by attaching a device-embedded substrate incorporating the optical element 40 to the sheet-shaped optical waveguide. Compared with the configuration in which optical coupling is performed with the sheet-shaped optical waveguide, the light receiving / emitting portion 401 of the optical element 40 can be easily disposed close to the sheet-shaped optical waveguide 20. And the insertion loss of light transmitted from the light emitting element 41 to the sheet-shaped optical waveguide 20 can be easily realized.

なお、本発明は、上述の実施の形態に限定されず、適宜変更が可能である。
(a)本発明は、充填樹脂部37、透明樹脂層38を具備していない構成のデバイス内蔵基板、充填樹脂部37、透明樹脂層38の内、充填樹脂部のみを具備した構成のデバイス内蔵基板を含む。また、デバイス内蔵基板の組立方法については、充填樹脂部形成工程を具備していない構成も含む。
(b)図6に例示した、チップ間接続用配線を具備するデバイス内蔵基板は、発光素子41、ドライバー素子46、受光素子42、レシーバー素子47を内蔵した構成に限定されず、デバイス内蔵基板に設けられた複数のチップ形デバイス同士の電気的接続、光素子以外のチップ形デバイス同士の電気的接続にも広く応用できる。チップ間接続用配線を具備するデバイス内蔵基板の回路基板に組み込まれる複数のチップ形デバイスとして、光素子が含まれない構成であっても良い。
(c)回路基板としては、半導体基板にデバイス収納孔を形成したものに限定されない。例えば、電気絶縁性の絶縁樹脂板にデバイス収納孔、配線部、端子部、貫通配線を設けたもの等も採用可能である。
In addition, this invention is not limited to the above-mentioned embodiment, It can change suitably.
(A) The present invention includes a device-embedded substrate that does not include the filling resin portion 37 and the transparent resin layer 38, and a device that includes only the filling resin portion among the filling resin portion 37 and the transparent resin layer 38. Includes substrate. In addition, the method for assembling the device-embedded substrate includes a configuration that does not include the filling resin portion forming step.
(B) The device-embedded substrate having the inter-chip connection wiring illustrated in FIG. 6 is not limited to the configuration in which the light-emitting element 41, the driver element 46, the light-receiving element 42, and the receiver element 47 are built-in. The present invention can be widely applied to electrical connection between a plurality of provided chip-type devices and electrical connection between chip-type devices other than optical elements. The plurality of chip-type devices incorporated in the circuit board of the device-embedded board having the inter-chip connection wiring may be configured such that no optical element is included.
(C) As a circuit board, it is not limited to what formed the device accommodation hole in the semiconductor substrate. For example, a device in which a device housing hole, a wiring portion, a terminal portion, and a through wiring are provided on an electrically insulating insulating resin plate can be employed.

本発明に係る実施形態のデバイス内蔵基板、回路基板の構造を示す正断面図である。It is a front sectional view showing the structure of a device built-in substrate and a circuit board according to an embodiment of the present invention. 図1のデバイス内蔵基板の仮想線で示した領域Aを拡大して示した拡大断面図である。It is the expanded sectional view which expanded and showed the area | region A shown with the virtual line of the device built-in board | substrate of FIG. 回路基板のデバイス収納孔に組み込む前のチップ形電子デバイスを示す図である。It is a figure which shows the chip-type electronic device before incorporating in the device accommodation hole of a circuit board. 本発明に係る実施形態の集積回路付き光導波路の構造を示す全体正面図である。1 is an overall front view showing a structure of an optical waveguide with an integrated circuit according to an embodiment of the present invention. 図4の集積回路付き光導波路の仮想線で示した領域Bを拡大して示した拡大断面図である。FIG. 5 is an enlarged cross-sectional view showing a region B indicated by an imaginary line of the optical waveguide with an integrated circuit in FIG. 4 in an enlarged manner. 発光素子、ドライバー素子、受光素子、レシーバー素子を回路基板のデバイス収納孔に組み込んだ構成の混載形デバイス内蔵基板、これを用いて構成された集積回路付き光導波路の構造を示す正断面図である。FIG. 3 is a front sectional view showing a structure of a mixed device built-in substrate having a configuration in which a light emitting element, a driver element, a light receiving element, and a receiver element are incorporated in a device housing hole of a circuit board, and a structure of an optical waveguide with an integrated circuit configured using the substrate . 本発明に係る集積回路デバイスの別態様を示す正断面図である。It is a front sectional view showing another embodiment of the integrated circuit device according to the present invention. パッケージ化されたLSIチップを集積回路部としてデバイス内蔵基板に実装した構成の集積回路デバイスを示す断面図である。It is sectional drawing which shows the integrated circuit device of the structure which mounted the packaged LSI chip on the device built-in board | substrate as an integrated circuit part. 両面に電極パッド及び金属バンプを具備するチップ形電子デバイス、それを回路基板のデバイス収納孔に組み込んだ構成のデバイス内蔵基板を説明する正断面図であって、(a)はチップ形電子デバイスの組み込み前、(b)は組み込み後を示す。BRIEF DESCRIPTION OF THE DRAWINGS It is front sectional drawing explaining the chip-type electronic device which comprises an electrode pad and a metal bump on both surfaces, and the device built-in board | substrate of the structure which incorporated it in the device accommodation hole of a circuit board, (a) is a chip-type electronic device Before installation, (b) shows after installation. チップ形電子デバイスのパッド設置面(光素子の受/発光部設置面)を示す図である。It is a figure which shows the pad installation surface (receiving / light-emitting part installation surface of an optical element) of a chip-type electronic device. チップ形電子デバイスの複数の電極パッド(詳細には電極パッドのコンタクト面)が、それぞれ、回路基板の端子部(詳細には端子部のコンタクト面)と重なった状態を示す平面図である。It is a top view which shows the state which the several electrode pad (specifically contact surface of an electrode pad) of a chip-type electronic device overlapped with the terminal part (specifically contact surface of a terminal part) of a circuit board, respectively. 回路基板のデバイス収納孔の断面寸法と、チップ形電子デバイスの断面寸法(特に、矩形断面の対角線寸法)との関係を示す平面図である。It is a top view which shows the relationship between the cross-sectional dimension of the device storage hole of a circuit board, and the cross-sectional dimension (especially diagonal dimension of a rectangular cross section) of a chip-type electronic device. チップ形電子デバイスの金属バンプのリフローによる、回路基板のデバイス収納孔内でのチップ形電子デバイスの傾動を説明する正断面図である。It is a front sectional view explaining inclination of a chip type electronic device in a device accommodation hole of a circuit board by reflow of a metal bump of a chip type electronic device. (a)、(b)は、回路基板の複数のデバイス収納孔におけるチップ形電子デバイスのセルフアライメントを説明する図(平面図)であり、(a)はチップ形電子デバイスの金属バンプのリフロー前、(b)はチップ形電子デバイスの金属バンプのリフロー後を示す。(A), (b) is a figure (plan view) explaining the self-alignment of the chip-type electronic device in a plurality of device housing holes of the circuit board, (a) before reflow of the metal bumps of the chip-type electronic device (B) shows after reflow of the metal bump of the chip-type electronic device. 本発明に係るデバイス内蔵基板の組立方法における充填樹脂部形成工程を説明する図であって、回路基板の接合面におけるデバイス収納孔の開口部を開口部封止部材を用いて塞いだ状態でデバイス収納孔内に液状の樹脂材料を注入する工程を説明する図である。It is a figure explaining the filling resin part formation process in the assembly method of the device built-in board concerning the present invention, Comprising: It is a device in the state where the opening part of the device accommodation hole in the joint surface of a circuit board was plugged up using the opening part sealing member It is a figure explaining the process of inject | pouring a liquid resin material in a storage hole. 本発明に係る集積回路付き光導波路のシート形光導波路の構造を示す斜視図である。It is a perspective view which shows the structure of the sheet-like optical waveguide of the optical waveguide with an integrated circuit which concerns on this invention. 図16のシート形光導波路の製造方法の一例を説明する図であって、(a)は3層の光導波路形成体を示す斜視図、(b)は図17(a)の光導波路形成体への活性エネルギーの照射によってコア部を形成した状態を示す斜視図である。It is a figure explaining an example of the manufacturing method of the sheet | seat type optical waveguide of FIG. 16, (a) is a perspective view which shows the optical waveguide formation body of 3 layers, (b) is an optical waveguide formation body of FIG. It is a perspective view which shows the state which formed the core part by irradiation of active energy to. 本発明に係る集積回路付き光導波路の別態様を説明する図であって、シート形光導波路自体を開口部封止部材として用いた構成の集積回路付き光導波路の構造を示す正断面図である。It is a figure explaining another aspect of the optical waveguide with an integrated circuit which concerns on this invention, Comprising: It is a front sectional view which shows the structure of the optical waveguide with an integrated circuit of the structure which used the sheet | seat type optical waveguide itself as an opening part sealing member . 電子デバイス内蔵基板の組立方法(集積回路付き光導波路)の組立方法の別態様を説明する図である。It is a figure explaining another aspect of the assembly method (optical waveguide with an integrated circuit) of the assembly method of a board | substrate with a built-in electronic device. (a)〜(c)は、受/発光部を複数具備する光素子の例を示す図である。(A)-(c) is a figure which shows the example of the optical element which comprises multiple light receiving / light-emitting parts. デバイス内蔵基板を、チップ形デバイスの高さ寸法hに比べて、厚さ寸法t及びデバイス収納孔の軸方向寸法dが充分に大きい回路基板を用いて組み立てる場合を説明する図であって、(a)は回路基板のデバイス収納孔にチップ形デバイスを組み込んだ状態を模式的に示す図、(b)は図21(a)の後に回路基板の厚さを薄くした状態を模式的に示す図である。It is a figure explaining the case where a device built-in board is assembled using a circuit board in which thickness dimension t and axial direction dimension d of a device accommodation hole are large enough compared with height dimension h of a chip type device, FIG. 21A is a diagram schematically showing a state in which a chip-type device is incorporated in a device housing hole of a circuit board, and FIG. 21B is a diagram schematically showing a state in which the thickness of the circuit board is reduced after FIG. It is.

符号の説明Explanation of symbols

1、1A、1B、1C…電子デバイス内蔵基板(光素子内蔵基板)、1a…底部側実装面、1b…デバイス実装面、11…第2貫通配線、12…金属バンプ(第1金属バンプ)、13…金属バンプ(第2金属バンプ)、14…電極パッド、15…ボンディング金属部、2…開口部封止部材、3、3A…回路基板、3a…第1主面、3b…第2主面、31…デバイス収納孔、31a…軸心、32…配線部、321…チップ間接続用配線、33…貫通配線、34…端子部、34a…コンタクト面、35…ボンディング金属部、351…金属バンプ(第2金属バンプ)、36…ボンディング金属部、37…充填樹脂部、37a…延長樹脂層、38…透明樹脂層、39…半導体基板(シリコン基板)、39a…酸化膜、4、4A…チップ形電子デバイス、40、40A、40B、40C…光素子、401…受/発光部、41…発光素子、411…発光部、42…受光素子、421…受光部、43…パッド設置面(受/発光部設置面)、431…パッド設置面(第2パッド設置面)、44…電極パッド、44a…コンタクト面、441…電極パッド(第2電極パッド)、45…金属バンプ、451…金属バンプ、46…ドライバー素子、47…レシーバー素子、5、5A、5B…集積回路デバイス(LSI)、5a…下面、51…基板、52…電子回路、53…ビア配線、54、54A…集積回路部、54B…集積回路部(LSIチップ)、6…電子部品、8…(液状の)樹脂材料、9…電子部品(第2回路基板)、91…接合面、92…回路配線(集積回路間接続配線)、10、10A…集積回路付き光導波路、20…シート形光導波路、21…クラッド部、22…コア部、23…光導波路形成体、231…コア層、232…クラッド層、25…ボンディング材料収納孔。   DESCRIPTION OF SYMBOLS 1, 1A, 1B, 1C ... Electronic device built-in board | substrate (optical element built-in board | substrate), 1a ... Bottom part side mounting surface, 1b ... Device mounting surface, 11 ... 2nd penetration wiring, 12 ... Metal bump (1st metal bump), DESCRIPTION OF SYMBOLS 13 ... Metal bump (2nd metal bump), 14 ... Electrode pad, 15 ... Bonding metal part, 2 ... Opening part sealing member 3, 3A ... Circuit board, 3a ... 1st main surface, 3b ... 2nd main surface 31 ... Device housing hole, 31a ... Axis center, 32 ... Wiring portion, 321 ... Inter-chip connection wiring, 33 ... Through wiring, 34 ... Terminal portion, 34a ... Contact surface, 35 ... Bonding metal portion, 351 ... Metal bump (Second metal bump), 36 ... bonding metal part, 37 ... filling resin part, 37a ... extended resin layer, 38 ... transparent resin layer, 39 ... semiconductor substrate (silicon substrate), 39a ... oxide film, 4, 4A ... chip Electronic device , 40, 40A, 40B, 40C ... optical element, 401 ... light receiving / emitting part, 41 ... light emitting element, 411 ... light emitting part, 42 ... light receiving element, 421 ... light receiving part, 43 ... pad installation surface (light receiving / light emitting part installation) Surface), 431 ... pad mounting surface (second pad mounting surface), 44 ... electrode pad, 44a ... contact surface, 441 ... electrode pad (second electrode pad), 45 ... metal bump, 451 ... metal bump, 46 ... driver Element, 47 ... Receiver element, 5, 5A, 5B ... Integrated circuit device (LSI), 5a ... Bottom surface, 51 ... Substrate, 52 ... Electronic circuit, 53 ... Via wiring, 54, 54A ... Integrated circuit section, 54B ... Integrated circuit Part (LSI chip), 6 ... electronic component, 8 ... (liquid) resin material, 9 ... electronic component (second circuit board), 91 ... bonding surface, 92 ... circuit wiring (connection wiring between integrated circuits), 10, 10A ... Circuit-equipped optical waveguide, 20 ... sheet type optical waveguide, 21 ... clad portion, 22 ... core part, 23 ... optical waveguide forming body, 231 ... core layer, 232 ... clad layer, 25 ... bonding material accommodating hole.

Claims (22)

半導体基板に、該半導体基板の両面の少なくとも一方に形成された配線部と、前記半導体基板に貫設された貫通配線と、前記半導体基板に貫設された貫通孔でありチップ形電子デバイスが組み込まれるデバイス収納孔と、前記半導体基板の両面の内の一方の前記配線部から前記デバイス収納孔の片端の開口部に張り出され、前記チップ形電子デバイスに設けられている電極パッドが電気導通可能に接続される突起状の端子部とが設けられており、
前記デバイス収納孔の断面寸法が、前記チップ形電子デバイスの前記デバイス収納孔の軸心に垂直の断面寸法を、前記電極パッドのコンタクト面の寸法の5〜195%だけ大きくした寸法になっており、
前記チップ形電子デバイスが角形のチップであり、前記チップ形電子デバイスを収納する断面矩形の前記デバイス収納孔は、その断面外周の互いに平行な2組の辺の内の少なくとも1組の辺の長さが、前記チップ形電子デバイスの対角線寸法よりも短く、
前記チップ形電子デバイスは、前記デバイス収納孔内で、前記デバイス収納孔の断面寸法とチップ形電子デバイスの断面寸法との差によって設定・規制されつつ回転移動可能であり、かつ前記デバイス収納孔の軸心を中心とする軸回り方向の前記チップ形電子デバイスの回転移動の全範囲で、前記チップ形電子デバイスの全ての電極パッドのコンタクト面が、それぞれ前記端子部のコンタクト面に平面視において重なった部分を有することを特徴とする回路基板。
A semiconductor substrate incorporates a wiring portion formed on at least one of both surfaces of the semiconductor substrate, a through-wiring penetrating the semiconductor substrate, and a through-hole penetrating the semiconductor substrate and incorporating a chip-type electronic device. The device storage hole and the electrode pad provided on the chip-type electronic device are electrically connected to each other by extending from one of the wiring portions on both sides of the semiconductor substrate to the opening at one end of the device storage hole. And a protruding terminal portion connected to the
The cross-sectional dimension of the device housing hole is a dimension obtained by increasing the cross-sectional dimension perpendicular to the axis of the device housing hole of the chip-type electronic device by 5 to 195% of the dimension of the contact surface of the electrode pad. ,
The chip-type electronic device is a square chip, and the device storage hole having a rectangular cross section for storing the chip-type electronic device has a length of at least one of the two sets of parallel sides of the outer periphery of the cross section. Is shorter than the diagonal dimension of the chip-type electronic device,
The chip-type electronic device is capable of rotating and moving within the device storage hole while being set and regulated by a difference between a cross-sectional dimension of the device storage hole and a cross-sectional dimension of the chip-type electronic device, and The contact surfaces of all the electrode pads of the chip-type electronic device overlap the contact surfaces of the terminal portions in plan view over the entire range of rotational movement of the chip-type electronic device around the axis centered on the axis. A circuit board characterized by having a portion.
請求項に記載の回路基板の前記デバイス収納孔に前記チップ形電子デバイスが組み込まれ、前記チップ形電子デバイスの前記電極パッドが導電性のボンディング用金属材料によってボンディングして電気導通可能に接続されていることを特徴とする電子デバイス内蔵基板。 The chip-type electronic device is incorporated in the device housing hole of the circuit board according to claim 1, and the electrode pads of the chip-type electronic device are bonded with a conductive bonding metal material so as to be electrically conductive. An electronic device-embedded substrate characterized by comprising: 前記デバイス収納孔内に、前記デバイス収納孔内面と前記チップ形電子デバイスとの間を埋める充填樹脂部を具備することを特徴とする請求項記載の電子デバイス内蔵基板。 3. The electronic device built-in substrate according to claim 2 , further comprising: a filling resin portion that fills a space between the inner surface of the device storage hole and the chip-type electronic device in the device storage hole. 前記デバイス収納孔に、前記チップ形電子デバイスとして発光素子又は受光素子である光素子が組み込まれ、この光素子は、前記端子部にボンディングされた前記電極パッドが設けられている面であるパッド設置面に発光部又は受光部を有することを特徴とする請求項2又は3記載の電子デバイス内蔵基板。 An optical element that is a light-emitting element or a light-receiving element as the chip-type electronic device is incorporated in the device housing hole, and this optical element is a surface on which the electrode pad bonded to the terminal portion is provided. 4. The electronic device built-in substrate according to claim 2 , further comprising a light emitting portion or a light receiving portion on a surface. 前記デバイス収納孔内に、前記デバイス収納孔内面と前記光素子との間を埋める充填樹脂部を具備し、前記充填樹脂部から連続して前記光素子の前記パッド設置面に形成された透明樹脂層によって前記発光部又は前記受光部が覆われていることを特徴とする請求項記載の電子デバイス内蔵基板。 A transparent resin formed on the pad mounting surface of the optical element continuously from the filling resin part, comprising a filling resin part filling the space between the inner surface of the device storage hole and the optical element in the device storage hole The electronic device-embedded substrate according to claim 4 , wherein the light emitting unit or the light receiving unit is covered with a layer. 前記回路基板に、前記デバイス収納孔の前記端子部が設けられている開口部を塞ぐ、透明の開口部封止部材が設けられていることを特徴とする請求項4又は5記載の電子デバイス内蔵基板。 6. The electronic device built-in according to claim 4 , wherein the circuit board is provided with a transparent opening sealing member that closes the opening provided with the terminal portion of the device housing hole. substrate. 前記回路基板には前記デバイス収納孔が複数形成されており、前記デバイス収納孔に組み込まれた発光素子と、該発光素子が組み込まれたデバイス収納孔とは別のデバイス収納孔に組み込まれた受光素子とを具備することを特徴とする請求項4〜6のいずれかに記載の電子デバイス内蔵基板。 The circuit board has a plurality of device housing holes, and a light emitting element incorporated in the device housing hole and a light receiving element incorporated in a device housing hole different from the device housing hole in which the light emitting element is incorporated. The board | substrate with a built-in electronic device in any one of Claims 4-6 characterized by including an element. 前記回路基板には前記デバイス収納孔が複数形成されており、発光素子が組み込まれたデバイス収納孔と、前記チップ形電子デバイスとして前記発光素子の駆動用のドライバー素子が組み込まれたデバイス収納孔とを具備し、前記発光素子と前記ドライバー素子とが、前記回路基板に形成されたチップ間接続用配線を介して電気的に接続されていることを特徴とする請求項4〜7のいずれかに記載の電子デバイス内蔵基板。 A plurality of the device housing holes are formed in the circuit board, a device housing hole in which a light emitting element is incorporated, and a device housing hole in which a driver element for driving the light emitting element is incorporated as the chip-type electronic device, comprising a, the light emitting element and the driver element is, in any one of claims 4-7, characterized in that said are electrically connected through a circuit board formed wiring chip connection The board | substrate with a built-in electronic device of description. 前記回路基板には前記デバイス収納孔が複数形成されており、受光素子が組み込まれたデバイス収納孔と、前記チップ形電子デバイスとして前記受光素子の受光信号変換用のレシーバー素子が組み込まれたデバイス収納孔とを具備し、前記受光素子と前記レシーバー素子とが、前記回路基板に形成されたチップ間接続用配線を介して電気的に接続されていることを特徴とする請求項4〜8のいずれかに記載の電子デバイス内蔵基板。 A plurality of device housing holes are formed in the circuit board, a device housing hole in which a light receiving element is incorporated, and a device housing in which a receiver element for converting a light receiving signal of the light receiving element is incorporated as the chip-type electronic device. ; and a hole, and the light receiving element and the receiver element, any claim 4-8, characterized in that said are electrically connected through a circuit board formed wiring chip connection An electronic device-embedded substrate according to claim 1. 前記回路基板の両面の少なくとも一方に、電極パッドと、この電極パッドに実装された金属バンプとを具備することを特徴とする請求項2〜9のいずれかに記載の電子デバイス内蔵基板。 The electronic device-embedded substrate according to claim 2 , further comprising an electrode pad and a metal bump mounted on the electrode pad on at least one of both surfaces of the circuit board. 前記チップ形電子デバイスは、前記パッド設置面とは反対の側に第2電極パッドを具備することを特徴とする請求項2〜10のいずれかに記載の電子デバイス内蔵基板。 11. The electronic device-embedded substrate according to claim 2 , wherein the chip-type electronic device includes a second electrode pad on a side opposite to the pad mounting surface. 前記第2電極パッドに金属バンプが実装されていることを特徴とする請求項11記載の電子デバイス内蔵基板。 12. The electronic device built-in substrate according to claim 11, wherein metal bumps are mounted on the second electrode pads. 請求項2〜12のいずれかに記載の電子デバイス内蔵基板であるベース回路基板と、このベース回路基板の片面に実装された集積回路部とを具備することを特徴とする集積回路デバイス。 13. An integrated circuit device comprising: a base circuit board that is an electronic device built-in substrate according to claim 2 ; and an integrated circuit portion mounted on one surface of the base circuit board. 前記集積回路部が、ベース回路基板に多層に積層された集積回路用基板の回路配線を互いに接続して構成され、この集積回路部を構成する複数の集積回路用基板の内の1以上が、請求項2又は3記載の電子デバイス内蔵基板であることを特徴とする請求項13記載の集積回路デバイス。 The integrated circuit portion is configured by connecting circuit wirings of an integrated circuit substrate laminated in multiple layers on a base circuit substrate, and one or more of the plurality of integrated circuit substrates constituting the integrated circuit portion are: 14. The integrated circuit device according to claim 13 , wherein the integrated circuit device is a substrate with a built-in electronic device according to claim 2 or 3 . シート形光導波路に、請求項3〜9のいずれかに記載の電子デバイス内蔵基板であるベース回路基板を具備する請求項13又は14記載の集積回路デバイスが1又は複数実装され、
前記シート形光導波路は、前記集積回路デバイスに組み込まれている発光素子に対応する位置、前記集積回路デバイスに組み込まれている受光素子に対応する位置に、前記発光素子と前記受光素子とを該シート形光導波路を介して光接続する光路形成用のミラー部を具備することを特徴とする集積回路付き光導波路。
One or a plurality of integrated circuit devices according to claim 13 or 14 are mounted on the sheet-shaped optical waveguide, the base circuit substrate being the electronic device built-in substrate according to any one of claims 3 to 9 ,
The sheet-shaped optical waveguide has the light emitting element and the light receiving element at positions corresponding to light emitting elements incorporated in the integrated circuit device and positions corresponding to light receiving elements incorporated in the integrated circuit device. An optical waveguide with an integrated circuit, comprising a mirror portion for forming an optical path that is optically connected through a sheet-shaped optical waveguide.
さらに、前記シート形光導波路の前記ベース回路基板とは反対の側に積層された第2回路基板を具備し、
前記シート形光導波路に貫設されたボンディング材料収納孔に、前記第2回路基板の回路配線と前記集積回路デバイスの前記ベース回路基板に設けられている電極パッドとを電気的に接続したボンディング用金属材料が収納され、前記第2回路基板の回路配線に電気導通可能に接続された複数の前記集積回路デバイスの回路同士が前記第2回路基板の回路配線を介して電気的に接続されていることを特徴とする請求項15記載の集積回路付き光導波路。
And a second circuit board laminated on the opposite side of the sheet-shaped optical waveguide from the base circuit board,
For bonding, the circuit wiring of the second circuit board and the electrode pads provided on the base circuit board of the integrated circuit device are electrically connected to the bonding material accommodation holes penetrating the sheet-shaped optical waveguide. A plurality of the integrated circuit devices in which a metal material is stored and connected to the circuit wiring of the second circuit board so as to be electrically conductive are electrically connected to each other via the circuit wiring of the second circuit board. The optical waveguide with an integrated circuit according to claim 15 .
請求項に記載の回路基板の前記デバイス収納孔にチップ形電子デバイスを組み込み、このチップ形電子デバイスに設けられている電極パッドに予め実装しておいた金属バンプをリフローして、前記電極パッドを前記端子部にボンディングすることを特徴とする電子デバイス内蔵基板の組立方法。 A chip-type electronic device is incorporated in the device housing hole of the circuit board according to claim 1, and a metal bump previously mounted on an electrode pad provided in the chip-type electronic device is reflowed to form the electrode pad. An electronic device built-in substrate assembling method, wherein: 前記電極パッドを前記端子部にボンディングした後に、前記デバイス収納孔内面と前記チップ形電子デバイスとの間を埋める充填樹脂部を形成する充填樹脂部形成工程を具備することを特徴とする請求項17記載の電子デバイス内蔵基板の組立方法。 Claim 17, characterized in that said electrode pad after bonding to the terminal part comprises a filled resin portion forming step of forming a filled resin portion filling the space between the said chip-type electronic device and the device receiving hole inner surface A method for assembling the electronic device-embedded substrate as described. 前記充填樹脂部形成工程において、前記回路基板の、前記デバイス収納孔の前記端子部が設けられている開口部を、開口部封止部材を用いて塞いだ状態で、前記デバイス収納孔内に液状の樹脂材料を注入して前記充填樹脂部を形成することを特徴とする請求項18記載の電子デバイス内蔵基板の組立方法。 In the filling resin portion forming step, the circuit board has a liquid in the device housing hole in a state in which the opening of the device housing hole provided with the terminal portion is closed with an opening sealing member. 19. The method of assembling an electronic device built-in substrate according to claim 18, wherein the resin material is injected to form the filled resin portion. 透明の開口部封止部材を用いることを特徴とする請求項19記載の電子デバイス内蔵基板の組立方法。 20. The method of assembling a substrate with a built-in electronic device according to claim 19 , wherein a transparent opening sealing member is used. 前記チップ形電子デバイスとして、受光素子又は発光素子である光素子を用い、この光素子の受/発光部が設けられている端面に備えられている電極パッドに予め実装しておいた金属バンプをリフローして、前記電極パッドを前記端子部にボンディングすることを特徴とする請求項17〜20のいずれかに記載の電子デバイス内蔵基板の組立方法。 As the chip-type electronic device, an optical element that is a light-receiving element or a light-emitting element is used, and metal bumps that are mounted in advance on electrode pads provided on the end face where the light-receiving / light-emitting portion of the optical element is provided. 21. The method of assembling an electronic device built-in substrate according to claim 17 , wherein the electrode pad is bonded to the terminal portion by reflow. 請求項19又は20記載の電子デバイス内蔵基板の組立方法に係る請求項21記載の電子デバイス内蔵基板の組立方法において、
前記充填樹脂部形成工程にて、前記充填樹脂部から連続して前記光素子の前記端面を覆う透明樹脂層を形成することを特徴とする電子デバイス内蔵基板の組立方法。
The method for assembling an electronic device built-in substrate according to claim 21, wherein the electronic device built-in substrate according to claim 19 or 20 is assembled.
A method of assembling a substrate with a built-in electronic device, wherein in the filling resin portion forming step, a transparent resin layer covering the end face of the optical element is formed continuously from the filling resin portion.
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