JP5103894B2 - Symbol processing apparatus and method - Google Patents

Description

  The present invention relates to a symbol processing apparatus and method equipped in, for example, a receiving unit of a portable wireless communication device.

  Patent Document 1 discloses a receiver that divides each symbol period into m (m is an integer of 3 or more), sets each division point as a sampling timing, and detects a symbol from a digital modulation signal at each sampling timing. . In the receiver, the first sampling timing is corrected based on the symbol value at each sampling timing so that the central sampling timing in the arrangement order of the m sampling timings becomes the symbol timing (see FIG. 6 steps 66, 67).

  Patent Document 1 also introduces Patent Document 2 as a prior art. In Patent Document 2, in the case of quaternary FSK modulation, the first and second time points in each symbol period are selected, and the first and second detection signals at the first and second time points are selected. The direction of the symbol clock shift is detected based on the difference between the reference value obtained from the shift amount, for example, the average value, and the first shift amount (FIG. 2 of Patent Document 2), so that the shift is eliminated. In addition, the timing of the symbol clock is corrected (VFO in FIG. 1 of Patent Document 2).

  The conventional portable wireless communication device 100 shown in FIGS. Parts common to FIGS. 1 to 8 according to the present invention to be described later are designated by the same reference numerals as those in the drawings, and description thereof is omitted. Hereinafter, only the main points of the portable wireless communication device 100 will be described.

  FIG. 11 is a schematic configuration diagram of a receiving system of the portable wireless communication device 100. The portable wireless communication device 100 includes a DSP (digital signal processor) 101. The detection signal is A / D converted by an A / D (analog / digital) converter 11 and then supplied to the DSP 101. The clock recovery unit 102 recovers the symbol clock based on the input signal from the A / D converter 11 and supplies the symbol clock to the symbol detection unit 20. The symbol detector 20 extracts a symbol value from the input signal from the A / D converter 11 at the symbol timing based on the symbol clock. The extracted symbol value is output as sound from the speaker 14 via the vocoder 22 and the D / A (digital / analog) converter 13.

  FIG. 12 is an explanatory diagram of symbol rate control processing in the DSP 101. The symbol rate control process is executed by the clock recovery unit 102 of the DSP 101. One symbol period is equally divided into N (N = 5 in this example), and symbol values are extracted using the central time of each time segment as a sampling timing. The Nyquist point is in the time division of the 1st to Nth center numbers (in this example, 3rd), the central time of the time division is the symbol timing, and the sampling value at the symbol timing is the symbol value.

  FIG. 13 is an explanatory diagram of symbol rate correction processing in the DSP 101. Symbol rate correction processing is also executed in the clock recovery unit 102 of the DSP 101. In FIG. 13, it is assumed that the symbol timing in the DSP 101 is shifted to the negative side (delay side) with respect to the Nyquist point.

  After setting N to the decrement counter, the DSP 101 performs symbol timing detection processing, and starts symbol timing correction processing as it detects a shift. If the symbol timing is shifted to the negative side with respect to the Nyquist point, N-1 smaller than N is replaced with the measurement count value of the decrement counter in place of the default value N in the next measurement count value setting process of the decrement counter. Set as a value. In the example of FIG. 13, N−1 = 4.

Thereby, since the next measurement cycle of the decrement counter becomes measurement count value = N−1, the start of the next next measurement cycle is advanced. As a result, the symbol timing shift with respect to the Nyquist point decreases.
JP 2006-74089 A JP 2003-333113 A

  FIG. 14 is an explanatory diagram of the relationship between the mode switching of the DSP 101 and the symbol timing. The portable wireless communication device 100 is appropriately switched from the normal operation mode to the power-down mode in order to save power, thereby suppressing the power consumption of the battery. In the power down mode, the DSP 101 is stopped from power supply from the battery and is in a non-operational state except for some functions (eg, external interrupt). In FIG. 14, it is assumed that the portable wireless communication device 100 is first in the normal operation mode, then in the power down mode, receives a predetermined interrupt signal, and returns to the normal operation mode again. Yes.

  In the normal operation mode before entering the power-down mode, the DSP 101 operates the decrement counter (received data sample number counter) to capture the symbol timing. However, as the DSP 101 enters the power-down mode, the decrement counter Stops working. After that, the DSP 101 receives a predetermined external interrupt signal and returns to the normal operation mode. However, since the symbol timing is lost at the time of return, the DSP 101 synchronizes the operation of the decrement counter with the symbol timing (Nyquist point). A return process is required when returning to the normal operation mode, which takes a considerable amount of time. Note that the timing of the external interrupt signal for returning the DSP 101 to the normal operation mode is shifted from the symbol timing, and it is difficult to reduce the recovery time for synchronization by synchronizing the decrement counter with the interrupt timing. .

  FIG. 15 is an explanatory diagram of problems during processing of the decrement counter in the DSP 101. The decrement counter sets the measurement count value of each cycle to the number N of symbol value samplings during the symbol period, and sets the measurement count value prior to the start of each cycle. However, among the three N settings in FIG. 15, when another process overlaps at the start of the cycle and the other process is given priority as in the second N setting from the left, the measurement count The value setting process may be delayed. Also, among the three N settings in FIG. 15, the measurement count value setting process itself may take a long time, as in the rightmost N setting. In such a case, the setting of the measurement count value in the decrement counter is not in time for the next data reception, and an error occurs in the reception serial port of the DSP 101, or the count number of the reception data is shifted.

  The symbol processing apparatus of Patent Document 1 divides a symbol period into a plurality of equal parts, sets a sampling timing in association with each section, and detects a sampling timing corresponding to the center of the eye pattern from a symbol value at each sampling timing. The sampling timing is merely adjusted so as to be the symbol timing. The symbol processing apparatus disclosed in Patent Document 1 does not use a timer counter to detect symbol timing, but when the symbol timing calculated based on the timer counter deviates from the Nyquist point, the measured count value of the timer counter It is not intended to eliminate the deviation.

  The symbol processing device of Patent Document 2 corrects the symbol clock so that it matches the Nyquist point, but does not use a timer counter, and solves the problems inherent to the timer counter as pointed out in FIG. There is no mention of any means to do it.

  An object of the present invention is to provide a symbol processing apparatus and method that can smoothly set a measurement count value of a timer counter for generating a symbol timing.

  Another object of the present invention is to provide a symbol processing apparatus and method capable of quickly obtaining appropriate symbol timing when a digital signal processor returns to a normal operation mode.

According to the present invention, the timer counter that generates the symbol clock that is the basis of the reception side symbol timing is installed in an external device outside the DSP, not in the DSP (digital signal processor). The DSP is supplied with a symbol clock from the timer counter as an external interrupt, and extracts a symbol value at a receiving symbol timing related to the external interrupt. The DSP also detects information related to the shift of the receiver symbol timing with respect to the Nyquist point as the transmitter symbol timing based on the digital modulation signal, and externally issues a command for correcting the timing of the external interrupt in the direction of decreasing the shift. Issue to the device.

Preferably, when the DSP returns from the power saving mode to the normal operation mode, the external processing from the timer counter of the external device to the DSP is used for detection of the reception side symbol timing to rationalize the return processing.

  That is, the symbol processing apparatus of the present invention includes a digital signal processor and an external device provided outside the digital signal processor. The external device is equipped with a timer counter. The timer counter repeats a cycle for measuring a set time and supplies an external interrupt to the digital signal processor at the end of each cycle.

The digital signal processor further includes symbol value acquisition means and command issue means. The symbol value acquisition means acquires a symbol value at the reception-side symbol timing based on the external interrupt supply timing. The command issuing means detects information related to the deviation of the reception side symbol timing with respect to the Nyquist point as the transmission side symbol timing based on the digital modulation signal extracted from the reception signal, and shifts the supply timing of the external interrupt in the direction of reducing the deviation. Issue a command to the external device.

The symbol processing method of the present invention includes the following steps.
A step of controlling the digital signal processor, which is a receiver side symbol based on a supply timing of an external interrupt from a timer counter external to the digital signal processor from a digital modulation signal extracted from the received signal and supplied to the digital signal processor Obtaining a symbol value at timing,
This is a step to control the digital signal processor, which detects information related to the shift of the receiver symbol timing with respect to the Nyquist point as the transmitter symbol timing based on the digital modulation signal, and shifts the supply timing of the external interrupt in the direction of reducing the shift A step of issuing a command to the external device, and a step of controlling the timer counter, setting a measurement count value of the timer counter based on a command from the digital signal processor to the timer counter, and measuring the measurement count value in the timer counter Supplying an external interrupt from the timer counter to the digital signal processor at the end of the measurement cycle by repeating the cycle.

  According to the present invention, the timer counter is provided in an external device outside the DSP, and the DSP does not need to set the measurement count value that the timer counter measures in each cycle one by one. It is only necessary to issue a command for correcting the measurement count value of the counter to the external device. Therefore, the DSP takes time to perform another process, the measurement count value setting process in the timer counter is delayed due to other priority processes, or the measurement count value setting process in the timer counter itself is prolonged, and the timer It is possible to avoid a situation where the setting completion of the measurement count value in the counter is delayed.

  FIG. 1 is a schematic configuration diagram of a main part of a reception system of the portable radio communication device 10. The portable wireless communication device 10 includes an A / D converter 11, a DSP 12, a D / A converter 13, a speaker 14, and a timer logic 15. Radio waves from a portable radio communication device or a base station on the other side are captured by an antenna (not shown) of the portable radio communication device 10 and then extracted and detected by a front end and a detector (both not shown). Then, it is input to the A / D converter 11 as a detection signal (baseband signal). In this case, the detection signal is a digital modulation signal. The digital modulation signal is analog-digital converted by the A / D converter 11 and supplied to the DSP 12.

  The DSP 12 includes a symbol detection unit 20, a clock reproduction unit 21, and a vocoder 22. The clock recovery unit 21 calculates symbol timing based on the symbol clock from the timer logic 15 and sends the symbol timing to the symbol detection unit 20. The clock recovery unit 21 also detects a Nyquist point based on the digital modulation signal from the A / D converter 11, detects a shift in symbol timing with respect to the Nyquist point, and sends a command for canceling the shift to the timer logic 15.

  The symbol detector 20 extracts a symbol value from the digital modulation signal at each symbol timing, and sends it to the vocoder 22. The vocoder 22 generates a digital audio signal from the symbol value from the symbol detector 20 and sends it to the D / A converter 13.

  The D / A converter 13 generates an analog audio signal from the digital audio signal from the vocoder 22. The speaker 14 converts the analog audio signal into audio and outputs it.

  FIG. 2 is an explanatory diagram of mode switching of the portable wireless communication device 10. The portable wireless communication device 10 is appropriately switched between the normal operation mode and the power-down mode during the power-on period. In the power-down mode, power supply to most of the elements of the DSP 12 other than the trigger generation relationship for accepting external interrupts and starting a return process to the normal operation mode is stopped, and power saving of the portable wireless communication device 10 is achieved. Is planned.

Switching control example of the normal operation mode and power-down mode is as follows.

(A) The detection circuit (analog or logic circuit) measures the electric field strength at regular intervals, and the control IC (eg, an external control IC 65 in FIG. 7 described later) monitors the measured value, and the electric field during the normal operation mode period. If the intensity level is less than the threshold value, it is determined that there is no appropriate signal, and the control IC performs switching control from the normal operation mode to the power down mode.

(B) When the detection circuit measures the electric field strength at regular intervals, the control IC monitors the measured value, and the electric field strength level is equal to or higher than the threshold value during the power down mode, and an appropriate signal is output. When it is determined, the control IC performs switching control from the power down mode to the normal operation mode.

(C) The received and demodulated digital data includes timing information to be received (eg, channel information (mainly TDMA) and frame information). In accordance with the information, the control IC switches the mode so that the period during which reception is not necessary is set to the power-down mode, and the mode returns to the normal operation mode immediately before the timing to receive.

(D) The user manually switches between the normal operation mode and the power down mode.

  FIG. 3 is a detailed configuration diagram of the main parts of the DSP 12 and the timer logic 15. Hereinafter, the “default count value” and the “adjustment count value” may be abbreviated as appropriate and referred to as “default value” and “adjustment value”, respectively. The DSP 12 includes a symbol timing control unit 27, and the symbol timing control unit 27 includes a symbol rate setting unit 28 and a symbol timing correction processing unit 29. The symbol timing control unit 27 basically has two commands to be sent to the timer logic 15.

  The symbol rate setting unit 28 issues the first command, and the symbol timing correction processing unit 29 issues the second command. As for the command issued by the symbol rate setting unit 28, the symbol rate setting unit 28 calculates a symbol rate based on the digital modulation signal, and a default value of a measurement count value corresponding to the symbol rate (for example, default value = in FIG. 12). The described N) is notified to the timer logic 15. The command issued by the symbol timing correction processing unit 29 is determined by the symbol timing correction processing unit 29 to determine whether or not the timing of the external interrupt from the timer logic 15 needs to be corrected based on the digital modulation signal. Such an adjustment value (for example, adjustment value = N−1 or N + 1) is notified to the timer logic 15.

  The timer logic 15 includes a decrement counter 33, a default count value storage unit 34, an adjustment count value storage unit 35, and a switching unit 36. The decrement counter 33 is set with a measurement count value prior to the start of the decrement cycle, and decrements the count value by one each time a predetermined clock pulse is input after the cycle starts. The decrement counter 33 issues a measurement count value load request to the default count value storage unit 34 and the adjustment count value storage unit 35 every time the count value becomes 0, that is, at the end of each measurement cycle. In response to the load request from the decrement counter 33, the default count value storage unit 34 and the adjustment count value storage unit 35 output a default value and an adjustment value, respectively.

  The switching unit 36 connects the decrement counter 33 to the default count value storage unit 34 or the adjustment count value storage unit 35 based on an instruction from the adjustment count value storage unit 35. When the adjustment count value storage unit 35 receives a command from the symbol timing correction processing unit 29, the adjustment count value storage unit 35 stores the adjustment value in the decrement counter 33 as the measurement count value only for one measurement cycle. The adjustment count value storage unit 35 is instructed to be connected to the decrement counter 33. When the adjustment count value storage unit 35 does not accept a command from the symbol timing correction processing unit 29, the adjustment count value storage unit 35 causes the switching unit 36 to hold the position where the default count value storage unit 34 is connected to the decrement counter 33. The timer logic 15 sends an external interrupt signal to the DSP 12 every time the count value of the decrement counter 33 becomes 0, that is, every time each measurement cycle ends. The external interrupt signal is the basis of symbol timing detection as a symbol clock in the DSP 12.

  FIG. 4 is an operation flowchart in the DSP 12 and the timer logic 15. Among the processes described in FIG. 4, the processes performed by the DSP 12 are S41, S42, and S43, and the other processes are performed by the timer logic 15. In S41, the DSP 12 calculates a symbol rate based on the digital modulation signal as the detection signal of the portable wireless communication device 10, calculates a default value corresponding to the symbol rate, and gives this to the timer logic 15 with a predetermined command. . On the other hand, the timer logic 15 sets the default value given by the command to the default value variable Def_num in S47. Thereafter, the decrement counter in the timer logic 15 receives the start trigger and starts operating.

  In S42, the DSP 12 determines the situation relating to the time difference between the Nyquist point detected based on the digital modulation signal (the Nyquist point will be described in detail later in FIG. 5) and the symbol timing based on the external interrupt timing from the timer logic 15, for example, the former. To determine whether the latter is moving forward or behind. If it is determined that the external interrupt timing needs to be adjusted, the command related to the adjustment, specifically, the decrement counter 33 of the timer logic 15 is set to the default count N. On the other hand, the timer logic 15 is instructed to change the adjustment value to N + 1 or N−1 which is larger or smaller by one. On the other hand, in S48, the timer logic 15 is notified of the adjustment value notified by the command.

  In S50, it is determined whether or not the timer logic 15 has received an adjustment value notification command from the DSP 12. If the determination is negative, the process proceeds to S51, and if positive, the process proceeds to S52. In S51, the default value received from the DSP 12 in S47 is loaded into the decrement counter 33. That is, the default value is set to the measurement count value of the decrement counter 33 in the next measurement cycle. Specifically, the value of the variable Def_num is substituted into the variable Dec_count. Dec_count is the decrement counter 33 configured by software. In S52, the adjustment value received from the DSP 12 in S48 is substituted into a variable Dec_count (= decrement counter 33).

  S57 is executed when a predetermined clock pulse is input. In S57, the count value of the decrement counter 33 is decremented by one. Specifically, the value of Dec_count is subtracted by 1. In S58, it is determined whether Dec_count = 0. If the determination is positive, the process proceeds to S59, and if not, the process returns to S57.

  In S59, the timer logic 15 issues an external interrupt to the DSP 12. The DSP 12 receives an external interrupt from the timer logic 15 in S43.

  FIG. 5 is a timing chart of the DSP 12 and the timer logic 15 in the initial operation of the decrement counter 33. The DSP 12 sets a default value N as a measurement count value in the decrement counter 33 of the timer logic 15 prior to the start of operation (time t1) of the decrement counter 33 (denoted as a symbol timing timer in FIG. 5). Since the default value N is determined by the symbol rate of the digital modulation signal input to the DSP 12, and the symbol rate is determined by the standard, the DSP 12 defaults to a predetermined value without detecting it one by one from the input digital modulation. It is also possible to store the value N in a memory, read the default value N from the memory, and notify the timer logic 15 with a command.

  The decrement counter 33 of the timer logic 15 starts to operate from time t1. A cycle from when the decrement counter 33 starts measuring the count value until the count value of the decrement counter 33 becomes 0, that is, until the measurement of the count value is finished, is defined as one cycle. The DSP 12 finishes the measurement of the external interrupt timing from the timer logic 15, that is, the decrement counter 33 so that the substantially central time (time t 2, t 4, t 6) of each cycle coincides with the symbol timing on the transmission side, that is, the Nyquist point. The time is adjusted by a command to the timer logic 15 (details will be described later with reference to FIG. 6). The DSP 12 acquires a symbol value from the digital modulation signal at each symbol timing (time t2, t4, t6). There are various known methods for detecting the Nyquist point. For example, refer to the flowchart of FIG. The sampling timing corresponding to the minimum buffer number in FIG. 6 of Patent Document 1 is the Nyquist point.

  The decrement counter 33 of the timer logic 15 decrements the count value by 1 every time a clock pulse having a predetermined period is input, and issues an external interrupt to the DSP 12 every time the count value becomes 0 (time t3, t5). When the decrement counter 33 has not received a command from the DSP 12 in each cycle, the decrement counter 33 sets the measurement count value of the next cycle to the default value N and then starts the next measurement cycle.

  FIG. 6 is a timing diagram of the DSP 12 and the timer logic 15 in a situation where the DSP 12 determines that correction of the external interrupt timing from the timer logic 15 is necessary. The DSP 12 performs a symbol timing detection process based on the external interrupt accompanying the external interrupt from the timer logic 15 at time t11. For this detection process, for example, the method described in FIGS. 3 and 4 of Patent Document 1 (a method of detecting the center timing of the eye pattern and using the center timing as the symbol timing) can be employed.

  If the DSP 12 determines that the external interrupt timing needs to be corrected after completion of the symbol timing detection processing, the DSP 12 subsequently performs symbol timing correction processing. Specifically, the measurement count value of the decrement counter 33 is set to an adjustment value N + 1 or N−1 that is larger or smaller by 1 than the default value N. When the symbol timing calculated from the external interrupt is delayed with respect to the Nyquist point, the adjustment value is set to N−1, the cycle of the decrement counter 33 is shortened, and the end of the measurement cycle is accelerated. When the symbol timing calculated from the external interrupt is advanced with respect to the Nyquist point, the adjustment value is set to N + 1, the cycle of the decrement counter 33 is lengthened, and the end of the measurement cycle is delayed.

  The DSP 12 sends a command to inform the adjustment value thus determined to the timer logic 15 before time t12 when the next cycle of the decrement counter 33 starts. When there is an adjustment value command from the DSP 12, the timer logic 15 sets the adjustment value to the measurement count value instead of the default value, and starts a cycle from time t12. In the example of FIG. 6, the external interrupt is delayed with respect to the Nyquist point. Therefore, the time length Na of the time t12-t13 is shorter than the time length Nd of the cycle (t11-t12, t13-t14) in which the default value is set by an amount corresponding to the count value 1 of the decrement counter 33. (Na <Nd).

  Accordingly, the end time t13 of the cycle (t12-t13) for measuring the adjustment value N-1 is advanced. In addition, the measurement count value in the cycle from time t13 is returned to the default value N because the command from the DSP 12 is not accepted between t12 and t13. As a result, in the cycle from t13 to t14, the DSP 12 can adjust the symbol timing calculated based on the external interrupt signal at time t13 to the Nyquist point.

  FIG. 7 is a timing chart of the DSP 12 and the timer logic 15 when the portable radio communication device 10 is switched to the power-down mode for a predetermined time and then returned to the normal operation mode. The external control IC 65 can also serve as the timer logic 15.

  After receiving an external interrupt from the timer logic 15 at time t21, the DSP 12 completes preparation for switching to the power-down mode before time t22. At t22, upon receiving an external interrupt from the timer logic 15, the DSP 12 notifies the external control IC 65 of the entry into the power down mode and then enters the power down mode. The external control IC 65 masks interrupts during the power-down mode of the DSP 12 (the interrupt process is not performed even if an interrupt signal is received from the outside).

  As a specific method of the external mask, there is a method in which the external interrupt of the timer logic 15 and the output of the external mask are input to the AND circuit and the output of the AND circuit is output to the external interrupt input unit of the DSP 12. The AND circuit may be provided inside the DSP 12 or outside the DSP 12. If the output of the external mask is maintained at “0”, the external interrupt “1” of the timer logic 15 is prevented from reaching the external interrupt input unit of the DSP 12.

  When the DSP 12 receives an external interrupt to the external interrupt input unit during power down, the DSP 12 immediately returns from the power down mode to the normal operation mode. Further, the decrement counter 33 of the timer logic 15 repeats the cycle for measuring the default value N during the power-down mode of the DSP 12, and continues to issue an external interrupt to the DSP 12 at the end of each cycle. . However, the mask prevents the external interrupt from the timer logic 15 from reaching the external interrupt input unit, and the DSP 12 maintains the power-down mode.

  If the external control IC 65 determines that it is time to switch the DSP 12 to the normal operation mode, the external control IC 65 cancels the interrupt mask of the DSP 12. Alternatively, another interrupt that is not masked is applied to the DSP 12, so that the DSP 12 cancels the interrupt mask in the interrupt processing.

  At time t23 after the interrupt mask is released, the DSP 12 receives an external interrupt from the timer logic 15, immediately returns to the normal operation mode, and calculates a symbol timing based on the external interrupt.

  The timer logic 15 repeats the measurement cycle of the default value N without taking a rest from t22 to t23, that is, in the power-down mode period of the DSP 12, and as a result, an external interrupt from the timer logic 15 to the DSP 12 at t23 is Even during the power down mode, synchronization with the Nyquist point is almost maintained. Therefore, the DSP 12 can omit the symbol clock detection process at the time of return, and immediately detect the symbol timing based on the timing of the external interrupt at time t23, and can quickly obtain an appropriate symbol value.

  FIG. 8 is a timing diagram of the DSP 12 and the timer logic 15 in the process of returning from the power down mode to the normal operation mode of the DSP 12 by an external interrupt of the timer logic 15 without using a mask. Also in the case of FIG. 8, when the DSP 12 receives an external interrupt from the timer logic 15 during the power-down mode, the DSP 12 returns to the normal operation mode using it as a trigger. In the case of FIG. 8, the external control IC 65 in FIG. 7 is unnecessary.

  The DSP 12 accepts an external interrupt from the timer logic 15 at time t31, and then completes preparation for switching to the power-down mode before time t32. For this preparation, the time in the current power-down mode, that is, the time from the next external interrupt reception time t32 to the time t33 when the DSP 12 returns to the power-down mode again is calculated. Here, the power-down mode time (time t32-t33) calculated by the DSP 12 is u times (u is an integer of 2 or more) the count time Nd (Nd is shown in FIG. 6) of the default value N by the timer logic 15. Set. Thus, the command of the adjustment value u · N corresponding to the power down mode time u · Nd is notified from the DSP 12 to the timer logic 15 before time t32.

  The decrement counter 33 uses the adjustment value u · N corresponding to the power down mode period as the measurement count value before the time t32, and starts measuring the adjustment value u · N from the time t32. The measurement of the adjustment value u · N ends at time t33 when the time u · Nd has elapsed from time t32. Therefore, the decrement counter 33 sends an external interrupt to the DSP 12 at time t33.

  When the DSP 12 receives an external interrupt from the timer logic 15 during power-down, the DSP 12 immediately returns from the power-down mode to the normal operation mode. As a result, after time t33, the DSP 12 returns to the normal operation mode.

  Since the time u · Nd from t32 to t33 is an integral multiple of the count time Nd of the default value N by the timer logic 15, t33 is substantially synchronized with the Nyquist point. Therefore, the DSP 12 can omit the symbol clock detection process at the time of return, and immediately detect the symbol timing based on the timing of the external interrupt at t33, and can quickly obtain an appropriate symbol value.

  FIG. 9 is a block diagram of the symbol processing device 70. The symbol processing device 70 includes a DSP (digital signal processor) 71 and an external device 78. The symbol processing device 70 is installed in, for example, the portable wireless communication device 10 (FIG. 1), but a communication device other than the portable wireless communication device 10, such as an in-vehicle communication device, a stationary communication device, You may equip with the communication apparatus only for reception.

  The external device 78 is provided outside the DSP 71 and includes a timer counter 79. The timer counter 79 repeats a cycle for measuring the set time and supplies an external interrupt to the DSP 71 at the end of each cycle. Specific examples of the DSP 71 and the external device 78 are the DSP 12 and the timer logic 15, respectively.

  The timer counter 79 is, for example, a decrement counter 33 (FIG. 3), and typically exists on software. The timer counter 79 may be an increment counter. The decrement counter 33 (FIG. 3) of the timer logic 15 measures a measurement count value as a numerical value, but actually measures a time such as a symbol period.

  The DSP 71 includes symbol value acquisition means 72 and command issue means 73. The symbol value acquisition unit 72 acquires a symbol value at a symbol timing based on an external interrupt supply timing. The command issuing means 73 detects information related to the symbol timing deviation with respect to the Nyquist point based on the digital modulation signal extracted from the received signal, and sends a command for shifting the supply timing of the external interrupt to the external device 78 in the direction of decreasing deviation. Issue.

  In this way, the DSP 71 has its own timer counter and is released from the management of setting the measurement count value for each cycle in the timer counter. The DSP 71 only needs to issue a command related to the measurement count value to the external device 78 and receive an external interrupt related to the symbol clock. Therefore, in the symbol processing device 70, the DSP 71 delays the process of setting the measurement count value to the timer counter for other priority processes, or takes time for the process of setting the measurement count value to the timer counter itself. It is possible to avoid problems that occur.

  The set time of the timer counter 79 corresponding to the cycle of the Nyquist point is defined as “default time”. Preferably, the timer counter 79 is kept in an active state even during the power saving mode of the DSP 71 and repeats the measurement cycle of the default time. On the other hand, when the DSP 71 returns from the power saving mode to the normal operation mode, the symbol value acquisition unit 72 obtains the symbol timing using the external interrupt from the timer counter 79 at that time as a symbol clock.

  As a result, when the DSP 71 returns from the power saving mode to the normal operation mode, the process of newly detecting the symbol clock from the input detection signal can be omitted, and appropriate symbol timing can be quickly captured.

  Preferably, the symbol processing device 70 includes a mask means 76. The mask means 76 masks an external interrupt from the external device 78 to the DSP 71 while the timer counter 79 is in the power saving mode. A specific example of the mask means 76 is an external control IC 65 (FIG. 7). The power saving mode of the timer counter 79 is, for example, the power down mode of FIG. For example, the external control IC 65 maintains the other input side of the AND circuit to which an external interrupt from the mask means 76 is input on one input side, at “0” during the power saving mode. These configurations correspond to the description of FIG. 7 described above.

  For example, before the digital signal processor 71 shifts to the power saving mode, the command issuing means 73 sets the adjustment time that is an integral multiple of the default time as the period of the current power saving mode, and sets the adjustment time to the timer counter 79. A command for instructing time is issued to the external device 78. In addition, when the DSP 71 is supplied with an external interrupt from the external device 78 during the power saving mode, the DSP 71 returns to the normal operation mode. When the DSP 71 returns from the power saving mode to the normal operation mode, the symbol value acquisition means 72 obtains the symbol timing using the external interrupt from the timer counter 79 at that time as a symbol clock.

  A configuration in which the adjustment time is set to an integral multiple of the default time to set the timer counter 79 corresponds to the description of FIG. 8 described above. For the adjustment time and the set time, the adjustment count value and the measurement count value of those subordinate concepts are used in the description of FIG.

  Typically, the command for shifting the timing of the symbol clock in the decreasing direction of the shift instructs the external device 78 to set the time increased or decreased by a predetermined amount from the default time as the set time of the timer counter 79. There is a command to do. The command corresponds to a command instructed by the DSP 12 to use the timer logic 15 as an adjustment value instead of a default value as a count value.

  Typically, the DSP 71 issues a command for notifying the external device 78 of the default time when the external device 78 starts operating. When the external device 78 does not accept a command from the DSP 71, the external device 78 sets the default time as the set time in the next measurement cycle.

  FIG. 10 is a flowchart of the symbol processing method 86. The symbol processing method 86 is applied to the symbol processing device 70 and includes S88, S89, and S92. S88 and S89 relate to the control of the DSP 71, and S92 relates to the control of the external device 78.

  In S88, a symbol value is acquired from the digital modulation signal extracted from the received signal and supplied to the DSP 71 at a symbol timing based on the supply timing of the external interrupt from the timer counter 79 outside the DSP 71.

  In S89, information related to the symbol timing deviation with respect to the Nyquist point is detected based on the digital modulation signal, and a command for shifting the supply timing of the external interrupt in the direction of the deviation reduction is issued to the external device 78.

  In S92, the measurement count value of the timer counter 79 is set based on a command from the DSP 71 to the timer counter 79, and the timer counter 79 repeats a cycle for measuring the measurement count value, and from the timer counter 79 to the DSP 71 every time the measurement cycle ends. Supply an external interrupt to

  The processes of S88 and S89 correspond to the functions of the symbol value acquisition means 72 and the command issue means 73, respectively. The specific functions described above for the symbol value acquisition means 72 and the command issue means 73 are the specific processes of S88 and S89. Can also be applied. Similarly, the process of S92 corresponds to the function of the external device 78, and each specific function described above for the external device 78 can be applied as the specific process of S92.

  Although the present invention has been described with respect to the best mode, it is needless to say that the present invention is not limited to this and can be implemented in various forms within the scope of the gist.

It is a principal part schematic block diagram of the receiving system of a portable radio | wireless communication apparatus. It is mode switching explanatory drawing of a portable radio | wireless communication apparatus. It is a detailed block diagram of the principal part of DSP and timer logic. It is an operation | movement flowchart in DSP and timer logic. It is a timing diagram of DSP and timer logic at the initial stage of operation of the decrement counter.

FIG. 5 is a timing diagram of the DSP and timer logic in a situation where the DSP determines that external interrupt timing correction from the timer logic is necessary. It is a timing diagram of DSP and timer logic when the portable wireless communication device is switched to the power-down mode for a predetermined time and then returned to the normal operation mode. FIG. 10 is a timing diagram of a DSP and timer logic in a process in which a DSP returns from a power-down mode to a normal operation mode by an external interrupt of the timer logic without using a mask. It is a block diagram of a symbol processing device. It is a flowchart of a symbol processing method.

It is a schematic block diagram of the receiving system of the conventional portable radio | wireless communication apparatus. It is explanatory drawing of the symbol rate control process in DSP of the conventional portable radio | wireless communication apparatus. It is explanatory drawing of the symbol rate correction process in DSP of the conventional portable radio | wireless communication apparatus. It is explanatory drawing about the relationship between the mode switching of DSP of a conventional portable radio | wireless communication apparatus, and symbol timing. It is explanatory drawing about the problem at the time of the process of the decrement counter in DSP of the conventional portable radio | wireless communication apparatus.

Explanation of symbols

70: Symbol processing device, 71: Digital signal processor, 72: Symbol value acquisition means, 73: Command issuing means, 76: Mask means, 78: External device, 79: Timer counter, 86: Symbol processing method.

Claims (7)

A digital signal processor, and an external device that is external to the digital signal processor and includes a timer counter, and the timer counter repeats a cycle for measuring a set time and supplies an external interrupt to the digital signal processor at the end of each cycle ,
With
The digital signal processor is:
A symbol value acquisition means for acquiring a symbol value at a reception-side symbol timing based on the supply timing of the external interrupt; and
A command for detecting information related to a shift in the reception side symbol timing with respect to the Nyquist point as a transmission side symbol timing based on a digital modulation signal extracted from the reception signal and shifting the supply timing of the external interrupt in the direction of reducing the shift Command issuing means to issue to external device,
A symbol processing apparatus comprising: The set time of the timer counter corresponding to the period of the Nyquist point is defined as the default time,
The timer counter is kept active during the power saving mode of the digital signal processor and repeats the default time measurement cycle,
When the digital signal processor returns from the power saving mode to the normal operation mode, the symbol value acquisition means obtains the receiving side symbol timing by using an external interrupt from the timer counter at that time as a symbol clock. The symbol processing apparatus according to claim 1.   3. The symbol processing apparatus according to claim 2, further comprising a masking means for masking an external interrupt from the external apparatus to the digital signal processor during the power saving mode of the timer counter. The set time of the timer counter corresponding to the period of the Nyquist point is defined as the default time,
Prior to the digital signal processor shifting to the power saving mode, the command issuing means sets an adjustment time that is an integral multiple of a default time as a period of the current power saving mode, and sets the adjustment time as a set time of the timer counter. Issue a command to instruct the external device to
When the digital signal processor is supplied with an external interrupt from the external device during the power saving mode, the digital signal processor returns to the normal operation mode,
When the digital signal processor returns from the power saving mode to the normal operation mode, the symbol value acquisition means obtains the receiving side symbol timing by using an external interrupt from the timer counter at that time as a symbol clock. The symbol processing apparatus according to claim 1. The set time of the timer counter corresponding to the period of the Nyquist point is defined as the default time,
The command to shift the timing of the symbol clock in the direction of decreasing deviation is a command for instructing the external device to set a time increased or decreased by a predetermined amount with respect to the default time as the set time of the timer counter. The symbol processing apparatus according to claim 1, wherein: The digital signal processor issues a command for notifying the external device of a default time at the start of operation of the external device,
6. The symbol processing apparatus according to claim 5, wherein when the external device does not accept a command from the digital signal processor, a default time is set as a set time in a next measurement cycle. A step of controlling a digital signal processor, wherein a symbol based on a supply timing of an external interrupt from a timer counter external to the digital signal processor from a digital modulation signal extracted from a received signal and supplied to the digital signal processor Obtaining a symbol value at timing,
A step of controlling the digital signal processor, wherein information relating to a deviation of a receiving side symbol timing with respect to a Nyquist point as a transmitting side symbol timing is detected based on the digital modulation signal, and the external interrupt is supplied in a direction of reducing the deviation Issuing a command for shifting the timing to an external device; and controlling the timer counter, setting a measured count value of the timer counter based on a command from the digital signal processor to the timer counter, and the timer Supplying the external interrupt from the timer counter to the digital signal processor at the end of the measurement cycle by causing the counter to repeat the cycle of measuring the measurement count value;
A symbol processing method comprising:

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