JP2002252661A - Communication apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a compact communication apparatus capable of conducting high-speed start-stop synchronization communication. SOLUTION: This invention comprises an input capture circuit, which detects an input capture value of leading and trailing edges of a prescribed signal based on a clock signal inputted from a timer counter and resets the timer counter during leading and trailing edges of the prescribed signal, an output compare circuit, which inputs a counter value from the timer counter and outputs an interrupt signal when the inputted counter value is larger than a prescribed data length included in the prescribed input signal, and a data generation means, which generates data based on the detected input capture value, and detects a data end by the interrupt signal from the output compare circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication device for start-stop synchronous communication, and more particularly to a communication device capable of high-speed communication.

[0002]

2. Description of the Related Art Conventionally, a communication apparatus relating to start-stop synchronous communication detects a state in which a stop signal is changed to a start signal, thereby knowing the beginning of a character for each data unit and starting to synchronize so that each character is synchronized. It is configured to receive, detect a stop signal following each character to know the end, and suspend synchronization.

When the asynchronous communication is performed by a single-chip microcomputer, the communication is processed by a communication module built in the single-chip microcomputer.

[0004]

However, a communication device that performs start-stop synchronous communication with a communication module built in the above-mentioned conventional single-chip microcomputer has a high speed because the communication module uses a timer built in the single-chip microcomputer. There was a drawback that processing could not be performed. In order to solve such a drawback, when high-speed processing is to be performed, a communication processing circuit must be added separately to a single-chip microcomputer, and there is a drawback that the apparatus becomes large. In particular, in a device such as a non-contact automatic ticket gate that has already been mounted in a highly confidential manner, the emergence of a communication device that is reduced in size and capable of high-speed processing has been awaited.

The present invention has been made in order to solve the above-mentioned drawbacks, and an object of the present invention is to provide a communication device which is capable of high-speed start-stop synchronous communication and is downsized. is there.

[0006]

In order to achieve the above object, a communication apparatus according to the present invention, based on a clock signal input from a timer counter, detects a falling or rising input capture value of a predetermined input signal. An input capture circuit for detecting and resetting the timer counter when the predetermined input signal falls or rises, and a counter value from the timer counter is input, and the input counter value is applied to the predetermined input signal. An output compare circuit that outputs an interrupt signal when the data length becomes longer than a predetermined data length included therein, and generates data based on the detected input capture value, and outputs an interrupt signal from the output compare circuit. Data generation means for detecting the end of data.

[0007]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic configuration diagram of a communication device according to an embodiment, and is a block diagram of a timer module 2 included in a CPU 1 as a single-chip microcomputer.

The timer module 2 includes an input capture circuit 3 for inputting serial data (refer to an input signal in FIG. 2 to be described later) transmitted from a higher-level device (not shown) which is higher than the CPU 1, and a timer for generating a timer signal. It includes a counter 4 and an output compare circuit 5 that stores the count value of the timer counter 4 and outputs a signal (interrupt signal) when the count value reaches a predetermined count value.

In FIG. 1, reference numeral 6 denotes an MPU configured to read received data based on an input capture value from the input capture circuit 3 and an interrupt signal from the output compare circuit 5. I have.

The control operation will be described below with reference to the time chart of FIG. 2 and the flowchart of FIG. Now, a higher-level device not shown in the input capture circuit 3 (when the present communication device is incorporated in a non-contact automatic ticket gate, a CPU that controls the main body of the non-contact automatic ticket gate is mainly configured. It is assumed that serial data shown as an input signal in FIG. 2 is input from the controller). This input signal includes 8-bit data (character) between a 1-bit start bit and a 1-bit stop bit, as shown in an enlarged manner at the bottom of FIG. Note that no parity bit is included.

When the input capture circuit 1 detects a start bit for detecting the fall of the signal, the input capture circuit 1 reads the counter value from the timer counter 4 at that time (see the time chart of the sawtooth timer in FIG. 2). The value at the falling position is stored and an interrupt signal is given to the timer counter 4 (see FIGS. 2 and 3A). The timer counter 4 is reset when receiving an interrupt signal from the input capture circuit 3, and starts counting again. The count value stored in the input capture circuit 3, that is, the capture value is
6 is sent.

The input capture circuit 3 detects a capture value each time a rising edge or a falling edge of an input signal is detected and sends it to the MPU 6, and also provides an interrupt signal to the timer counter 4 each time (FIG. 3 (b) )reference).

The MPU 6 has an input capture circuit 3
Generates data "00, 12,..." As shown in FIG. 2 on the basis of the capture value input from the device, and transmits the generated data to a device not shown (for example, a reader / writer of a contactless automatic ticket gate). Output to

A counter value is input to the input compare circuit 5 in the same manner as the input capture circuit 3. The input counter value is a counter value (data bit and data bit) preset in the output compare circuit 5. This is compared with a counter value slightly larger than the total start bit (9 bits), for example, a counter value equivalent to 10 bits. Then, the output compare circuit 5 sends an interrupt signal to the MPU 6 when the input counter value exceeds a preset counter value (see FIG. 2). That is, if the input signal input to the input capture circuit 3 does not rise or fall, and the timer counter 4 is not reset even after reaching a predetermined counter value (10 bits in the above example), it is determined that the data has ended. (See FIG. 3C).

As described above, the communication device according to the present invention
Since the input capture value can be detected using the input capture circuit 3 and the output compare circuit 5 included in the built-in module of the single-chip microcomputer, it is possible to efficiently read an input signal input at high speed. Also, since the device can be downsized, for example,
It can be made suitable as a communication device for a non-contact automatic ticket gate.

[0016]

The communication device according to the present invention detects the falling and rising input capture values of a predetermined input signal based on a clock signal input from a timer counter, and detects the falling of the predetermined input signal. An input capture circuit for resetting the timer counter at the time of rising, and a counter value from the timer counter, and when the input counter value becomes larger than a predetermined data length included in the predetermined input signal. An output compare circuit for outputting an interrupt signal, and data generating means for generating data based on the detected input capture value and detecting the end of the data based on the interrupt signal from the output compare circuit. Therefore, high-speed communication is possible, and the size of the device can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a schematic configuration of a communication device according to an embodiment of the present invention.

FIG. 2 is an example of a time chart.

FIG. 3 is a flowchart showing a control operation.

[Explanation of symbols]

 1 Single-chip microcomputer (CPU) 2 Timer module 3 Input capture circuit 4 Timer counter 5 Output compare circuit 6 MPU

Claims (1)

[Claims] An input capture value of a predetermined input signal falling and rising is detected based on a clock signal input from a timer counter, and the timer counter is reset when the predetermined input signal falls and rises. An input capture circuit for inputting a counter value from the timer counter, and outputting an interrupt signal when the input counter value becomes larger than a predetermined data length included in the predetermined input signal. A communication circuit, comprising: a compare circuit; and data generating means for generating data based on the detected input capture value and detecting the end of the data by an interrupt signal from the output compare circuit. .