JP5090440B2 - Semiconductor device - Google Patents

Description

The present invention, with respect to MOS transistor circuits, relates to a semiconductor equipment comprising a substrate control circuit.

  The term “MOS” has been used in the past for metal / oxide / semiconductor stacked structures and is an acronym for Metal-Oxide-Semiconductor. However, in particular, in a field effect transistor having a MOS structure (hereinafter simply referred to as “MOS transistor”), the material of the gate insulating film and the gate electrode is improved from the viewpoint of recent integration and improvement of the manufacturing process.

  For example, in a MOS transistor, polycrystalline silicon has been adopted instead of metal as a material for a gate electrode mainly from the viewpoint of forming a source / drain in a self-aligned manner. From the viewpoint of improving electrical characteristics, a high dielectric constant material is used as a material for the gate insulating film, but the material is not necessarily limited to an oxide.

  Therefore, the term “MOS” is not necessarily limited to the metal / oxide / semiconductor laminated structure, and is not presumed in this specification. That is, in view of technical common sense, here, “MOS” has not only an abbreviation derived from the word source but also a broad meaning including a laminated structure of a conductor / insulator / semiconductor.

  In the MOS transistor, when a substrate voltage (substrate bias) is applied, the threshold voltage Vth and the drain current Id change due to the substrate bias effect. The drain current Id also changes depending on the value of the power supply voltage.

  In the MOS transistor, the threshold voltage Vth and the drain current Id vary due to manufacturing variations. Therefore, a method for suppressing variations in MOS transistors by controlling the substrate voltage and the power supply voltage has been proposed.

  In Non-Patent Document 1, an appropriate power supply voltage is determined by monitoring the delay time value of the delay detection circuit as needed and performing feedback control of the result.

  In Non-Patent Document 2, drain current and threshold voltage are monitored as needed instead of delay time, and feedback control is performed using them as substrate bias control values.

  In Non-Patent Document 3, a circuit delay is measured with a ring oscillator when power is turned on, and a substrate bias value corresponding to device variations caused by a manufacturing process is determined. The relationship between the oscillation frequency and the bias value is determined by a table lookup method with reference to a table. Thereafter, the bias value is changed in accordance with the temperature change. The relationship between the change temperature and the bias value is determined by a table lookup method.

S. Akui et al., “Dynamic Voltage and Frequency Management for a Low-Power Embedded Microprocessor”, ISSCC Digest of Technical Papers, pp. 64-65, 2004. M. Sumita et al., “Mixed Body-Bias Techniques with Fixed Vt and Ids Generation Circuits”, ISSCC Digest of Technical Papers, pp. 158-159, 2004. H. Okano et al., “Supply Voltage Adjustment Technique for Low Power Consumptions and its application to SOCs with Multiple Threshold Voltage CMOS”, Symp. On VLSI Circuits Digest of Technical Papers, 2006.

  In the substrate control methods of Non-Patent Document 1 and Non-Patent Document 2, since the power supply voltage and the substrate voltage are changed while monitoring at any time during operation, there are innumerable operating states. In other words, in order to guarantee operation, it is necessary to confirm normal operation in a myriad of states, and a test of each chip on the wafer (hereinafter referred to as a chip test) is performed after dicing the wafer and before dicing. It becomes difficult.

  In the substrate control method of Non-Patent Document 3, the number of states is limited by table lookup, but it is necessary to determine a table entry every time the power is turned on.

  As described above, in the chip test using the conventional substrate control method, it is necessary to perform operation state monitoring and table entry each time the chip test is turned on, and the chip test is complicated.

  Therefore, an object of the present invention is to provide a control mechanism for the substrate voltage and the power supply voltage, corresponding to the suppression of device variations of MOS transistors, by simple means.

  According to one embodiment of the present invention, at the time of chip test, drain current and operation speed when the MOS transistor is off are first tested to check device variations of each MOS transistor to be controlled, and the device A fuse is programmed so as to select a ROM in which the relationship between the value of the power supply voltage and the value of the substrate voltage is set according to the state of variation. In the subsequent chip test, the optimum substrate voltage is determined by looking up the ROM table in accordance with the value of the power supply voltage input from the outside.

  According to the above embodiment, the substrate voltage can be controlled according to the contents of the ROM table selected by the programmed fuse. Therefore, after the fuse program, the chip state is fixed, and the subsequent chip test can be simplified.

  The objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description and the accompanying drawings.

FIG. 3 is a schematic diagram of a substrate control circuit according to the first embodiment. 3 is a flowchart of substrate voltage control in the first embodiment. It is a figure which shows the combination of an address address, a power supply voltage, and a 1st board | substrate voltage set to the 1st read-only memory. It is a figure which shows the combination of an address address, a power supply voltage, and a 1st board | substrate voltage set to the 2nd read-only memory. It is a figure which shows the combination of an address address, a power supply voltage, and a 1st board | substrate voltage set to the 3rd read-only memory. It is a figure which shows the combination of an address address, a power supply voltage, and a 1st board | substrate voltage set to the 4th read-only memory. It is a figure which shows the combination of an address address, a power supply voltage, and a 2nd board | substrate voltage set to the 5th read-only memory. It is a figure which shows the combination of an address address, a power supply voltage, and a 2nd board | substrate voltage set to the 6th read-only memory. It is a figure which shows the combination of an address address, a power supply voltage, and a 2nd board | substrate voltage set to the 7th read-only memory. It is a figure which shows the combination of an address address, a power supply voltage, and a 2nd board | substrate voltage set to the 8th read-only memory. It is the schematic of the test regarding drain current. It is the schematic of the test regarding operation speed. It is a figure which shows the correspondence of 1st-4th read-only memory, a 1st address, and each of 5th-8th read-only memory, and a 2nd address. It is a figure which shows the correspondence of a power supply voltage and an information code. It is a figure which shows the correspondence of an information code and a 3rd address. It is the schematic of an address converter. It is the schematic of a 1st voltage conversion circuit. FIG. 7 is a schematic diagram of a substrate control circuit according to a second embodiment. It is a figure which shows the combination of an information code and a 3rd address. It is a figure which shows the correspondence of a 3rd address and a 1st board | substrate voltage. It is a figure which shows the example of a change of the corresponding relationship between the information code shown in FIG. 19, and a 3rd address. It is a figure which shows the example of a change of the correspondence of the 3rd address shown in FIG. 20, and a 1st board | substrate voltage. FIG. 7 is a schematic diagram of a substrate control circuit according to a third embodiment. It is a figure which shows a 4th address. It is a figure which shows a 5th address. It is a figure which shows the correspondence of an address address and a 1st board | substrate voltage. It is a figure which shows the correspondence of an address address and a 2nd board | substrate voltage. FIG. 10 is a schematic diagram of a substrate control circuit according to a fourth embodiment. It is a figure which shows a 6th address. It is a figure which shows the correspondence of a 6th address, a 1st board | substrate voltage, and a 2nd board | substrate voltage. It is a figure which shows the modification of the board | substrate control circuit according to Embodiment 4. FIG. FIG. 10 shows a characteristic test circuit according to a fifth embodiment. It is a figure which shows the inverter which comprises a 1st ring oscillator. It is a figure which shows the inverter which comprises a 2nd ring oscillator. It is a figure which shows the inverter which comprises a 3rd ring oscillator. It is a figure which shows an example of the oscillation frequency of each ring oscillator.

[Embodiment 1]
In this embodiment, at the beginning of the chip test, a drain current when the MOS transistor is in an off state and an operation speed are tested (hereinafter, a drain current when the MOS transistor is in an off state and an operation speed test are characterized. The relationship between the power supply voltage and the substrate voltage (difference between the power supply voltage and the substrate voltage) is determined in accordance with the operation state. In the subsequent chip test, the substrate voltage is determined according to the value of the power supply voltage input for each item of the chip test.

  FIG. 1 is a schematic diagram of a substrate control circuit BCC according to the first embodiment. The substrate control circuit BCC in the present embodiment includes a voltage selection circuit BSC that selects an optimum voltage, voltage conversion circuits VC0 to VC1 that generate a substrate voltage selected by the voltage selection circuit BSC, and a control target block that is a control target. The variable power supply circuit VS supplies the power supply voltage VDD to the control target block CB.

  The voltage selection circuit BSC is a read-only memory ROM0-ROM3 that sets a combination of values of the power supply voltage VDD and the first substrate voltage VBP in advance, and a read-only memory ROM4 that sets a combination of the power supply voltage VDD and the second substrate voltage VBN. -ROM7. The substrate voltage generation circuit BSC also selects fuses for selecting the optimum values of the first substrate voltage VBP and the second substrate voltage VBN from the combinations set in the read-only memories ROM0 to ROM7. Circuits FU0 to FU1, selector circuits SC0 to SC1, and an address converter AT are further provided.

  Read-only memories ROM0-ROM3, fuse circuit FU0, selector circuit SC0, voltage conversion circuit VC0 provides the first substrate voltage VBP, read-only memory ROM4-ROM7, fuse circuit FU1, selector circuit SC1, voltage conversion circuit VC1 provides the second A substrate voltage VBN is generated respectively.

  In the control target circuit block CB, an inverter circuit IC is shown as a circuit to be controlled. The inverter circuit IC has a configuration in which a P-channel MOS transistor PT and an N-channel MOS transistor NT are connected in series. A common gate of the P-channel MOS transistor PT and the N-channel MOS transistor NT is an input terminal IN, and a common drain is output. Terminal OUT.

  The source of the P-channel MOS transistor PT is connected to the power supply node VH, and the power supply node VH is supplied with the power supply voltage VDD from the variable power supply circuit VS. The substrate voltage of the P-channel MOS transistor is supplied with the first substrate voltage VBP from the first voltage conversion circuit VC0 via the power supply node VP. The source of the N channel MOS transistor NT is connected to the reference node VL, and the reference voltage VSS is supplied to the reference node VL. The substrate voltage of N channel MOS transistor NT is supplied with second substrate voltage VBN from second voltage conversion circuit VC1 via power supply node VN.

  FIG. 2 shows a flowchart of substrate voltage control in the present embodiment. Hereinafter, the present embodiment will be described along the flow FC1-FC12 shown in this flowchart.

  The flowchart of substrate voltage control in the present embodiment is roughly divided into three steps. The three steps are steps for performing the characteristic test, programming the fuse circuit, and performing the remaining items of the chip test.

  First, in step 1, some items of the chip test are performed. As the items to be implemented, the MOS transistors to be controlled are evaluated by limiting only to the minimum necessary chip test mainly on device variations. Based on the test result, a combination of the power supply voltage VDD and the substrate voltage that can obtain the substrate bias effect that cancels the device variation is determined. Specific contents will be described using the flows FC1 to FC3.

  (FC1) In the read-only memories ROM0 to ROM3, a combination of the power supply voltage VDD and the first substrate voltage VBP is set for each address address BN. Similarly, a combination of the power supply voltage VDD and the second substrate voltage VBN is set for each address address BN in the read-only memory ROM4-ROM7.

  For example, if the ROM is a mask ROM, the combination is set during the manufacturing process related to the manufacture of the semiconductor device. Further, an electrically programmable ROM can be set in a timely manner after the manufacturing process is completed. That is, the combination can be set after the characteristic test.

  3 to 6 show combinations of the address address BN, the power supply voltage VDD, and the first substrate voltage VBP, which are set in the read-only memories ROM0 to ROM3, respectively. For each read-only memory, the difference between the power supply voltage VDD and the second substrate voltage VBP is set in a certain combination. In the case of the read-only memory ROM0 shown in FIG. 3, the difference between the power supply voltage VDD and the first substrate voltage VBP is 0V, and in the read-only memory ROM1 shown in FIG. 4, the difference between the source voltage VDD and the first substrate voltage VBP is If the read-only memory ROM2 shown in FIG. 5 is 0.3V, the difference between the power supply voltage VDD and the first substrate voltage VBP is 0.6V. If the read-only memory ROM3 shown in FIG. The difference between the substrate voltages VBP is 0.9V and constant. Depending on the device variation of the P-channel MOS transistor PT, one of the read-only memories is selected in the flow FC3 described later.

  Next, FIGS. 7 to 10 show combinations of the address address BN, the reference voltage VSS, and the second substrate voltage VNP, which are set in the read-only memories ROM4-ROM7, respectively. The reference voltage VSS is 0.0V. For each read-only memory, the difference between the reference voltage VSS and the second substrate voltage VBN is set in a certain combination. In the case of the read-only memory ROM4 shown in FIG. 7, the difference between the reference voltage VSS and the second substrate voltage VBN is 0V, and in the read-only memory ROM5 shown in FIG. 8, the difference between the source voltage VDD and the first substrate voltage is 0. .3V, if the read-only memory ROM 6 shown in FIG. 9 is used, the difference between the reference voltage VSS and the second substrate voltage VBN is 0.6V. If the read-only memory ROM 7 shown in FIG. The voltage difference is constant at 0.9V. Depending on the device variation of the N channel MOS transistor NT, one of the read-only memories is selected in a flow FC3 described later.

  That is, by setting different combinations of the power supply voltage VDD and the substrate voltage for each of the read-only memories ROM0 to ROM7, the threshold voltage Vth and the drain current Id are uniformly set for each of the read-only memories ROM0 to ROM7 due to the substrate bias effect. Keep it changing. The variation is controlled by balancing the change in threshold voltage Vth and drain current Id due to the substrate bias effect and the change in threshold voltage Vth and drain current Id due to device variation.

  Here, the power supply voltage VDD means an operating voltage of the semiconductor chip. In this example, 0.9 [V] to 1.2 [V] can be referred to as an operating range. Do not consider operating the semiconductor chip for reasons such as poor operating characteristics. However, it may be used beyond this operating range on the user's side, and in that case, the manufacturer can change the range of VDD.

  (FC2) Next, a characteristic test of each MOS transistor in the control target block CB is performed. The characteristic test is performed for the control target block CB with respect to two items, that is, the drain current when the MOS transistor is off and the operation speed. At this stage, only a chip test for evaluating device variations and a minimum operation (for example, a very basic operation test of whether or not an overcurrent flows) is performed.

  For P channel MOS transistor PT, there are four combinations of power supply voltage VDD and first substrate voltage VBP as shown in FIGS. 3 to 6, and for N channel MOS transistor NT, as shown in FIGS. There are four types of combinations of the reference voltage VSS and the second substrate voltage VBN. In the characteristic test, the test is performed on 16 kinds of voltage conditions obtained by combining the respective voltage conditions.

  From the value of the drain current when the MOS transistor is off, which is obtained from the test for each voltage condition, the state of device variation with respect to each voltage condition is confirmed to determine whether it is good or bad. Also, regarding the operating speed, whether the voltage is good or bad is determined from the test results. FIG. 11 shows an example of the drain current test result in the off state, and FIG. 12 shows an example of the operation speed test result. In the figure, “◯” indicates a good test result and “×” indicates a defective test result.

  (FC3) The voltage difference between the power supply voltage VDD and the first substrate voltage VBP and the voltage difference between the reference voltage VSS and the second substrate voltage VBN are determined according to the result of device variation obtained by the characteristic test of the flow FC2. Select the corresponding read-only memory.

  As the voltage condition, a condition that has obtained a good result in a specific test is selected. For example, in the case of the results of FIGS. 11 and 12, the P-channel MOS transistor has the voltage condition of FIG. 4, and the N-channel MOS transistor has the voltage condition of FIG. If there are a plurality of voltage conditions that give good results for both items in the characteristic test, one of them is selected. If there is no voltage condition that results in good results, the circuit is a defective circuit and is excluded from subsequent chip tests.

  A read-only memory corresponding to the selected voltage condition is selected. 11 and FIG. 12, the read-only memory ROM 1 in which the voltage condition of FIG. 4 is set and the read-only memory ROM 7 in which the voltage condition of FIG. 10 is set.

  Next, step 2 will be described. In step 2, the fuse circuits FU0-FU1 are programmed so that the read-only memory determined in step 1 is fixed in the subsequent chip test. Specific contents will be described using the flow FC4.

  (FC4) The first selector circuit SC0 is set so as to select the read-only memory determined in the flow FC3 and for which the voltage condition is set. Specifically, the first fuse circuit FU0 is programmed and set to output the first address AP to the first selector circuit SC0. For example, AP = 01 is programmed. Then, according to the first address AP, the first selector circuit SC0 selects a desired read-only memory (in this example, the output of the ROM 1).

  Similarly, the second substrate voltage VBN is set so that the second selector circuit SC1 selects the read-only memory determined in the flow FC3 and for which the voltage condition is set. Specifically, the second fuse circuit FU1 is programmed and set to output the second address AN to the second selector circuit SC1. According to the second address AN, the second selector circuit SC1 selects a desired read-only memory.

  FIG. 15 shows the correspondence between the read-only memories ROM0-ROM3 and the first address AP, and the read-only memories ROM4-ROM7 and the second address AN. Each fuse circuit FU0-FU1 is programmed to output the first address AP and the second address AN according to the read-only memory selected in the flow FC3. 11 and FIG. 12, the fuse circuits FU0-FU1 may be programmed so that the first address AP is “01” and the second address AN is “11”.

  As shown in step 1 (flows FC1 to FC3), the drain current when the MOS transistor is off is measured in the characteristic test, and the state of variation in each voltage condition is evaluated. In step 2 (flow FC4), the optimum voltage condition is selected according to the evaluation in step 1, and the fuse circuits FU0-FU1 are programmed to select the corresponding read-only memory. As a result, in the remaining tests performed in step 3 (flows FC5 to FC12), each substrate voltage can be automatically supplied from the power supply voltage information code VDDC using the substrate control circuit BCC, and variation control is performed. Can be implemented.

  That is, if the characteristic test is performed and the fuse circuits FU0 to FU1 are programmed based on the result, the flow for setting the substrate voltage of each MOS transistor to be controlled in the remaining chip test can be greatly reduced.

  Finally, the operation of the substrate control circuit BCC in the remaining chip test in step 3 will be described. Specific contents will be described using the flow FC5-FC12.

  (FC5) The information code VDDC of the power supply voltage VDD is input from the external input EI. FIG. 14 shows the correspondence between the power supply voltage VDD and the information code VDDC. At this time, the power supply voltage VDD is set to a value within the range of the power supply voltage VDD set in the read-only memories ROM0 to ROM7.

  (FC6) The information code VDDC is converted into the third address AV by the address converter AT. FIG. 15 shows an example of the relationship between the information code VDDC and the third address AV. The third address AV is input to the read-only memories ROM0 to ROM7.

  (FC7) The third address AV corresponds to the address address BN shown in FIGS. In accordance with the third address AV, the value of the substrate voltage at the corresponding address address BN of the read-only memories ROM0 to ROM7 is selected. Information on the value of the first substrate voltage VBP selected by the read-only memories ROM0 to ROM3 is input to the selector circuit SC0. Information on the value of the second substrate voltage VBN selected by the read-only memory ROM4-ROM7 is input to the selector circuit SC1, respectively.

  (FC8) The first address AP is input from the first fuse circuit FU0 to the first selector circuit SC0 in accordance with the contents programmed in advance in the first fuse circuit FU0 in the flow FC4. Similarly, the second address AP is input from the second fuse circuit FU1 to the second selector circuit SC1 in accordance with the contents programmed in advance in the second fuse circuit FU1 in the flow FC4. Each of the first address AP and the second address AN is a 2-bit signal.

  (FC09) FIG. 13 shows the relationship between the read memory ROM0-ROM3 and the first address AP, and the read-only memory ROM4-ROM7 and the second address AN. The first selector circuit SC0 selects the read-only memory corresponding to the first address AP from the read-only memories ROM0 to ROM3. The second selector circuit SC1 selects the read-only memory corresponding to the second address AP from the read-only memories ROM4-ROM7.

  In the results of FIGS. 11 and 12, since the first address AP is “01”, the second read-only memory ROM1 is selected, and the second address AN is “11”. Read-only circuit ROM7 is selected.

  (FC10) By the flow FC6-FC7, the address address BN of the read-only memories ROM0-ROM3 is selected, and the information on the optimum substrate voltage VBP is input to the first selector circuit SC0 for each read-only memory ROM0-ROM3. The In addition, the first address AP is input to the first selector SC0 by the flow FC7-FC8. From the information input in these flows, the first selector circuit SC0 selects one optimum value of the first substrate voltage VBP. Information VBPC on the value of the selected first substrate voltage VBP is input from the first selector SC0 to the first voltage conversion circuit VC0.

  Similarly, the second selector circuit SC1 selects one optimum value of the second substrate voltage VBN from information input from the read-only memory ROM4-ROM7 and the second fuse circuit FU1. The information VBNC on the value of the second substrate voltage VBN to be selected is input from the second selector SC1 to the second voltage conversion circuit VC1.

  In this step, the value of each substrate voltage is determined. Since each address input from the fuse circuits FU0 to FU1 is constant depending on the program, it is fixed to the read-only memory selected in this step in the subsequent chip test. Further, since the information code VDDC is changed according to the value of the power supply voltage VDD, each substrate voltage in the subsequent chip test is influenced only by the value of the power supply voltage. That is, thereafter, if only the value of the chip test power supply voltage VDD is determined, the value of the substrate voltage is automatically determined, and it is not necessary to perform the test under a plurality of voltage conditions as in the characteristic test, and the chip test becomes easy. .

  (FC11) In the flow FC10, the first substrate voltage VBP is generated by the first voltage conversion circuit VC0 according to the value of the first substrate voltage VBP selected by the first selector circuit SC0. Similarly, the second substrate voltage VBP is generated by the second voltage conversion circuit VC1 according to the value of the second substrate voltage VBN selected by the second selector circuit SC1. Each generated substrate voltage is supplied to the control target circuit block.

  (FC12) Each substrate potential generated by the voltage conversion circuits VC0 to VC1 is supplied to the control target block CB and becomes the substrate voltage of each MOS transistor. In the inverter circuit IC, the first substrate voltage VBP is supplied via the power supply node VP to the substrate voltage of the P channel MOS transistor PT, and the second substrate voltage VBN is supplied via the power supply node VN to the N channel MOS transistor NT. Is supplied as a substrate voltage.

  After performing the flow FC5-FC12, when performing other chip test items, the flow returns to the flow FC5 and the flow FC5-FC12 is performed again. If all necessary items are implemented, the chip test is completed.

  By the flow FC5-FC12, each substrate voltage is generated in the substrate control circuit BCC and supplied as the substrate voltage of each MOS transistor in the control target circuit CB. The influence of device variations is suppressed by the substrate device effect generated by the substrate voltage.

  In the chip test, various tests are performed according to the function and configuration of the control target circuit CB in addition to the test items of the drain current in which the MOS transistor is off and the operation speed of the circuit performed in the flow FC2. . In the chip test after the specific test is performed and the fuse is programmed in the flow FC4, each substrate voltage is supplied by the flow FC5-FC12.

  That is, in the substrate control circuit BCC of the present embodiment, it is performed under a plurality of voltage conditions only at the time of a specific test, and at the time of the remaining chip test, as long as the power supply voltage information code VDDC corresponding to each item is input, 1 It is determined by one voltage condition, and the chip test is simplified.

  Hereinafter, the operation of step 3 (flows FC5 to FC12) will be described with specific numerical values.

  For example, when the value of the power supply voltage VDD is set to “1.0”, “5” is input as the information code VDDC from the relationship of FIG. Receiving the information code VDDC, the address converter AT converts the information code VDDC “5” into the third address AV “2” from the relationship of FIG. According to the third address AV “2”, “2” is selected as the address address BN of the read-only memories ROM0 to ROM7, and information on the voltage set in the address address BN2 is input to the selector circuits SC0 to SC1, respectively. The

  At this time, from FIG. 11 and FIG. 12, since the first fuse circuit FU0 “11” is set, the first address AP becomes “11” and is input to the first selector circuit SC0. The first selector circuit SC0 selects the read-only memory ROM3 from the correspondence relationship of FIG. Further, since the second fuse circuit FU1 is set to “00”, the second address AN is “00” and is input to the second selector circuit SC1. The second selector circuit SC1 selects the read-only memory ROM4 from the correspondence relationship of FIG.

  The value of the first substrate voltage VBP is “2.0” from the second address of the read-only memory ROM3. Information VBPC on the value of the first substrate voltage VBP is input from the first selector circuit SC0 to the first voltage conversion circuit VC0. Based on the value information VBPC of the first substrate voltage VBP, the first voltage conversion circuit VC0 generates the first substrate voltage VBP and supplies it to the control target block CB.

  The value of the second substrate voltage VBN is “0.0” from the second address of the read-only memory ROM4. Information VBNC on the value of the second substrate voltage VBN is input from the second selector circuit SC1 to the second voltage conversion circuit VC1. Based on the value information VBNC of the second substrate voltage VBN, the second voltage conversion circuit VC1 generates the second substrate voltage VBN and supplies it to the controlled block CB.

  Thus, the optimum combination of the power supply voltage VDD, the first substrate voltage VBP, and the second substrate voltage VBN is selected, and each MOS transistor in the control target block CB is controlled.

  In the read-only memories ROM0 to ROM7, desired values are shown in an address mapped state. Although voltage values are used for explanation, they are coded in the same manner as the information code VDDC.

  Further, the power supply voltage VDD is generated by the variable power supply circuit VS according to the information code VDDC. The variable power supply circuit VS includes an external voltage EX. VDD is supplied, and this external voltage EX. A power supply voltage VDD is generated based on VDD. The power supply voltage VDD is supplied to a power supply node in the control target block CB, for example, a power supply node VH of a P-channel MOS transistor in the inverter circuit. The reference voltage VSS is also supplied from the variable power supply circuit VS to the power supply node in the control target block CB, for example, the power supply node VN of the N-channel MOS transistor in the inverter circuit.

  In this embodiment, the read-only memory ROM is used as a storage device for setting a combination of the power supply voltage VDD and the first substrate voltage VBP or the second substrate voltage VBN. However, the storage device is limited to the ROM. There is no need to be done.

  The number of read-only memory ROMs shown in this embodiment is an example, and the number may be increased or decreased as necessary. Further, the number of combinations of the power supply voltage, VDD, and the first substrate voltage VBP or the second substrate voltage VNP set in the read-only memories ROM0 to ROM7 may be increased or decreased as necessary.

  In the measurement of characteristics in the present embodiment, in addition to the method of measuring each MOS transistor to be controlled, there is also a method of installing a test circuit separately and performing a characteristic test on the test circuit.

  FIG. 16 shows a schematic diagram of the address converter AT in FIG. The address converter AT is composed of a 6 bit × 64 word ROM as shown in FIG. A third address AV (post-conversion address) corresponding to the information code VDDC (pre-conversion address) is set in the 6-bit × 64 word ROM, and the corresponding third address AV is output according to the input information code VDDC. To be.

  As the fuse circuits FU0 to FU1 in FIG. 1, a fuse program circuit disclosed in Japanese Patent Laid-Open No. 2002-74979 is used. Since the outputs of the fuse circuits FU0 to FU1 in this embodiment each require a 2-bit signal, the fuse program circuit disclosed in Japanese Patent Laid-Open No. 2002-74979 is configured to use two circuits each.

  In FIG. 1, the variable power supply circuit VS has an external voltage EXT. A desired power supply voltage VDD is supplied to the target circuit block CB based on VDD. Voltage conversion circuits VC0-VC1 are also connected to external voltage EXT. Based on VDD, a first substrate voltage VBP and a second substrate voltage VBN are generated, respectively.

  The configuration of the first voltage conversion circuit VC0 has an external voltage EXT. It is determined by the relationship between VDD and the first substrate voltage VBP. That is, the external voltage EXT. When the value of VDD is higher than the desired value of the first substrate voltage VBP, the first voltage conversion circuit VC0 connects the step-down circuit to the external voltage EXT. When the value of VDD is lower than the desired value of the first substrate voltage VBP, the first voltage conversion circuit VC0 is configured to include a booster circuit. The step-down circuit and the step-up circuit used here may be circuits used for a general memory internal power supply. Here, a case where the value of the external voltage is lower than the value of the substrate voltage will be described.

  FIG. 17 shows the configuration of the first voltage conversion circuit VC0. The first voltage conversion circuit VC0 includes a digital-analog converter DAC, a voltage comparator VC, and a booster circuit BC. The first substrate voltage information VBPC input from the first selector circuit SC0 to the first voltage conversion circuit VC0 is a digital value. This digital value is converted into an analog value VBPA by a digital-analog converter DAC. The converted analog value VBPA is compared with the voltage value VBPT generated by the booster circuit BC. While the analog value VBPA is smaller than the voltage value VBPT, the boosting circuit BC repeats boosting. When the analog value VBPA is equal to or higher than the voltage value VBPT, the boosting operation is terminated, and the voltage value VBPT at that time is supplied to the control target circuit CB as the first substrate voltage VBP.

  The second voltage conversion circuit VC1 can also be realized with the same configuration as the first voltage conversion circuit VC0. However, as shown in FIGS. 8 to 10, the second substrate voltage VBN is required to be lower than the GND level voltage (in this case, 0.0 V). Therefore, the booster circuit BC used in the second voltage conversion circuit VC1 is configured to invert the polarities of various signals of the booster circuit BC used in the first voltage conversion circuit VC0.

[Embodiment 2]
FIG. 18 shows a schematic diagram of the substrate control circuit BCC of the present embodiment. In the present embodiment, the address converter AT is omitted from the circuit configuration of the first embodiment by devising the address mapping of the information code VDDC and the read-only memories ROM0 to ROM7. In FIG. 18, parts corresponding to those in the configuration shown in FIG.

  FIG. 19 shows an example of a combination of the information code VDDC and the third address AV. FIG. 20 shows the relationship between the third address AV and the first substrate voltage VBP in the read-only memory ROM2. 19 and 20, the information code VDDC and the third address AV used in the first embodiment are expressed in binary numbers.

  Further, FIG. 21 shows a changed correspondence between the information code VDDC and the third address AV in FIG. FIG. 22 shows a modification of the correspondence between the third address AV and the first substrate voltage VBP of FIG. As shown in FIGS. 21 and 22, even if the correspondence is changed, it is logically equivalent to the data shown in FIGS.

  In place of the combination of FIGS. 19 and 18 shown in the first embodiment, the combination of FIGS. 21 and 20 is set so that the lower 2 bits of the information code VDDC correspond to the lower 2 bits of the third address AV. By doing so, the lower two bits of the information code VDDC can be handled as they are as the third address AV. As a result, the address converter AT for generating the third address AV from the information code VDDC becomes unnecessary, and the circuit scale can be reduced compared to the circuit configuration of FIG.

[Embodiment 3]
FIG. 23 shows a schematic diagram of the substrate control circuit BCC of the present embodiment. In FIG. 23, a read-only memory ROM_P is used instead of the read-only memories ROM0 to ROM3 shown in FIG. Further, instead of the read-only memory ROM4-ROM7 shown in FIG. 1, a read-only memory ROM_N is used. In the read-only memories ROM_P and ROM_N, as shown later, addressed substrate voltage data is stored. In FIG. 23, parts corresponding to those shown in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted.

  In the present embodiment, a fourth address APV, which is a combination of the first address AP and the third address AV, and a fifth address ANV, which is a combination of the second address AN and the third address AV, are used. Thus, a circuit configuration in which the selector circuits SC0 to SC1 are omitted from the first embodiment is realized.

  FIG. 24 shows the fourth address APV. The fourth address APV is simply a concatenation of the first address AP and the third address AV.

  FIG. 25 shows the fifth address ANV. The fifth address ANV is simply a concatenation of the second address AN and the third address AV.

  The fourth address APV is represented by 4-bit data. The fourth address APV is input to the read-only memory ROM_P, and the address address BNP corresponding to the fourth address APV is selected in the read-only memory ROM_P. The data stored in the selected address address BNP is input to the first voltage conversion circuit VC0.

  Similarly, the fifth address ANV is represented by 4-bit data. The fifth address ANV is input to the read-only memory ROM_N, and the address address BNN corresponding to the fifth address ANV is selected in the read-only memory ROM_N. The data stored in the selected address address BNN is input to the second voltage conversion circuit VC1.

  FIG. 26 shows the relationship between the address address BNP and the first substrate voltage VBP set in the read-only memory ROM_P. FIG. 27 shows the relationship between the address address BNN and the second substrate voltage VBN set in the read-only memory ROM_N. Next, the operation will be described.

  For example, it is assumed that the first address AP is “01”, the second address AN is “11”, and the third address AV is “10”. At this time, the address APV is “0110” and the address ANV is “1110”.

  If the address APV “0110” is expressed in decimal notation, it is 6 (address), so the first substrate voltage VBP is “1.3” from the relationship of FIG. Since the address ANV is “1110”, that is, “14” (address) in decimal notation, the second substrate voltage VBN is “−0.9” from the relationship of FIG.

  In this way, by using the fourth address APV, which is a combination of the first address AP and the third address AV, and the fifth address ANV, which is a combination of the second address AN and the third address AV. Therefore, the selector circuits SC0 to SC1 are unnecessary, and the circuit scale can be reduced.

  The address converter AT in the present embodiment can be omitted as in the second embodiment.

[Embodiment 4]
FIG. 28 shows a schematic diagram of the substrate control circuit BCC of the present embodiment. In FIG. 28, a read-only memory ROM_C is used instead of the read-only memories ROM0 to ROM7 shown in FIG. In FIG. 28, parts corresponding to those shown in FIG. 1 are given the same reference numerals, and detailed descriptions thereof are omitted.

  In the present embodiment, the selector circuit SC0-SC1 is changed from the circuit configuration of the first embodiment by using the sixth address APNV connecting the first address AP, the second address AN, and the third address AV. Omitted, the read-only memory can be combined into one.

  FIG. 29 shows a sixth address APNV based on the first address AP, the second address AN, and the third address AV.

  The sixth address APNV is represented by 6-bit data. The sixth address APNV is input to the read-only memory ROM_C, and the address address BNPN corresponding to the sixth address APNV is selected in the read-only memory ROM_C. Data related to the first substrate voltage VBP stored in the selected address address BNP is input to the first voltage conversion circuit VC0, and data related to the second substrate voltage VBN is input to the second voltage conversion circuit VC1, respectively. .

  FIG. 30 shows a correspondence relationship between the sixth address APNV, the first substrate voltage VBP, and the second substrate voltage VBN. Next, the operation will be described.

  For example, if the first address AP is entered as “01”, the second address AN as “11”, and the third address AV as “10”, the sixth address APNV becomes “011110”.

  Since the address APNV “011110” is “30” (address) in decimal notation, the first substrate voltage VBP is “1.3” and the second substrate voltage VBN is “−0.9” from the relationship of FIG. "

  In this way, by using the sixth address APNV that connects the first address AP, the second address AN, and the third address AV, the selector circuits SC0-SC1 become unnecessary, and the circuit scale can be reduced. Can do. Also, since the read-only memories can be combined into one, layout design is facilitated.

  The address converter AT in the present embodiment can be omitted as in the second embodiment.

  FIG. 31 shows a modification of the board control circuit according to the fourth embodiment. The configuration shown in FIG. 31 can be realized when a plurality of functions are packed in one chip by SOC (SOC: System On a Chip) or the like, and a read-only memory prepared for another purpose is provided in another function portion. In the configuration of FIG. 31, the read-only memory of the substrate control circuit can be shared with the memory unit having other functions, so that the area of the entire SOC can be reduced. In this embodiment, the read-only memory prepared in FIG. 31 is an on-chip flash memory FM.

  The on-chip flash memory FM is connected via a circuit MCIF related to memory control and interface for shared control with other blocks and interface arbitration. In general, since the on-chip flash memory FM is shared by a plurality of blocks, the circuit MCIF related to memory control and intermediate frequency can also be shared, and is shared with other blocks also in this configuration.

  With the circuit configuration shown in FIG. 31, the area of the read-only memory portion can be reduced as compared with the circuit configuration of FIG. Further, when the on-chip flash memory FM is used only for other purposes, if the on-chip flash memory has a free capacity, it is possible to use the capacity to carry out overhead as a whole configuration including external circuits. Can be small.

  In each of the embodiments described so far, after the fuse program, the substrate voltage is controlled based on the fluctuation of the power supply voltage VDD. However, the substrate voltage can also be controlled in accordance with the temperature change. . In FIG. 1, a substrate voltage value corresponding to a temperature change is previously added to the read-only memories ROM0 to ROM7, and a signal corresponding to the temperature change is input to the read-only memories ROM0 to ROM7. An optimum substrate voltage value is selected from the voltage information code VDDC.

  Further, in each of the embodiments described so far, the configuration in which two types of substrate voltages, the first substrate voltage VBP and the second substrate voltage VBN2, are generated is shown. However, depending on the configuration of the control target block CB, May be configured to generate any one type of substrate voltage.

[Embodiment 5]
In the present embodiment, an example of a characteristic test performed in the flow FC2 shown in FIG. 2 is shown.

  FIG. 32 shows a characteristic test circuit TC in the present embodiment. This characteristic test circuit TC is mounted on the same chip as the substrate control circuit shown in FIG. 1, and has the same variation (finish) as the transistors in the control target block CB. The characteristic test circuit TC includes a first ring oscillator RING_N, a second ring oscillator RING_P, and a third ring oscillator RING_C. Signals are input from the common input terminal RING_EN to the first to third ring oscillators.

  The first ring oscillator RING_N connects the NAND circuit NAND_N and the inverter circuit INV_N including even-numbered inverters INV_N1 to INV_Nm (also referred to as INV_Nm) in series, and returns the output of the final stage to the input of the NAND circuit NAND_N of the first stage. Self-oscillate and output from the output terminal N_OUT via the buffer BUF_N. Similarly, the second ring oscillator includes a NAND circuit NAND_P and an inverter circuit INV_P each including an even number of inverters INV_P1 to INV_Pm (also referred to as INV_Pm) connected in series, and the output of the final stage is connected to the NAND circuit NAND_P of the first stage. It returns to the input and self-oscillates and outputs from the output terminal P_OUT via the buffer BUF_P. Similarly, the third ring oscillator RING_C includes a NAND circuit NAND_C and an inverter circuit INV_C each including an even number of inverters INV_C0 to INV_Cm (also referred to as INV_Cm) connected in series, and the output of the final stage is connected to the first stage NAND circuit. It returns to the input of the NAND_C and self-oscillates and outputs from the output terminal C_OUT via the buffer BUF_C. Note that the transistor sizes of the inverter circuits constituting the first to third ring oscillators are different for each ring oscillator.

  FIG. 33 shows an example of the inverter INV_Nm that constitutes the first ring oscillator RING_N, FIG. 34 shows an example of the inverter INV_Pm that constitutes the second ring oscillator RING_P, and FIG. 35 shows an example of the inverter INV_Cm that constitutes the third ring oscillator RING_C.

  The inverter INV_Nm is configured such that the P-channel MOS transistor PT_N and the N-channel MOS transistor NT_N are connected between the power supply voltage VDD and the reference voltage VSS. A first substrate voltage VBP is supplied to the P channel MOS transistor PT_N, and a second substrate voltage VBN is supplied to the N channel MOS transistor NT_N.

  Here, the transistor size of the N channel MOS transistor NT_N is designed to be smaller than the transistor size of the P channel MOS transistor PT_N. As an example, in FIG. 33, the transistor length pl of the P-channel MOS transistor PT_N is 0.1 μm, the transistor width pw = 32 μm, the transistor length nl = 0.1 μm of the N-channel MOS transistor NT_N, and the transistor width nw = 1 μm.

  The inverter INV_Pm is configured such that the P-channel MOS transistor PT_P and the N-channel MOS transistor NT_P are connected between the power supply voltage VDD and the reference voltage VSS. A first substrate voltage VBP is supplied to the P channel MOS transistor PT_P, and a second substrate voltage VBN is supplied to the N channel MOS transistor NT_P.

  Here, the transistor size of the P-channel MOS transistor PT_P is designed to be smaller than the transistor size of the N-channel MOS transistor NT_P. For example, in FIG. 34, the transistor length pl of the P-channel MOS transistor PT_N is 0.1 μm, the transistor width pw = 1 μm, the transistor length nl of the N-channel MOS transistor NT_N is 0.1 μm, and the transistor width nw = 32 μm.

  The inverter INV_Cm is configured such that the P-channel MOS transistor PT_C and the N-channel MOS transistor NT_C are connected between the power supply voltage VDD and the reference voltage VSS. A first substrate voltage VBP is supplied to the P channel MOS transistor PT_C, and a second substrate voltage VBN is supplied to the N channel MOS transistor NT_C.

  Here, the transistor size of the P channel MOS transistor PT_C and the transistor size of the N channel MOS transistor NT_C are designed to be equal. For example, in FIG. 35, the transistor length pl of the P-channel MOS transistor PT_N is 0.1 μm, the transistor width pw = 1 μm, the transistor length nl of the N-channel MOS transistor NT_N is 0.1 μm, and the transistor width nw = 1 μm.

  By designing the inverter in this way, the oscillation frequency of the first ring oscillator RING_N is greatly affected by the fluctuation of the drain current of the N-channel MOS transistor NT_N, that is, the second substrate voltage VBN. In addition, the oscillation frequency of the second ring oscillator RING_P is greatly affected by the fluctuation of the drain current of the P-channel MOS transistor PT_P, that is, the first substrate voltage VBP. Since the third ring oscillator RING_C is designed to have a balanced transistor size, the third ring oscillator RING_C does not have high sensitivity to either the first substrate voltage VBP or the second substrate voltage VBN.

  An example of the measurement results of the oscillation frequencies of the first to third ring oscillators is shown in FIG. Since the dependency of the first to third ring oscillators on the first substrate voltage VBP and the dependency on the second substrate voltage VBN are different depending on the finished state of the P-channel MOS transistor and the N-channel MOS transistor, each oscillation frequency The result is characteristic. Based on this feature, the fuse program is determined.

  TT, FF, SS, FS, and SF shown on the horizontal axis in FIG. 36 indicate the finished states of the transistors. The TT finish means that the drain current of the P channel MOS transistor and the N channel MOS transistor is a median finish. The FF finish means that the drain current of the P-channel MOS transistor and the N-channel MOS transistor is greatly finished. The SS finish means that the P channel MOS transistor and the N channel MOS transistor are finished with a small drain current. The FS finish means that the drain current of the N channel MOS transistor is large and the drain current of the P channel MOS transistor is small. SF finish means that the drain current of the N-channel MOS transistor is small and the drain current of the P-channel MOS transistor is large.

  Each of 0.00, 0.60, and 1.20 indicated on the horizontal axis of FIG. 36 is the substrate voltage (bias value) of the first substrate voltage VBP (or the second substrate voltage VBN). The symbols N, P, and B indicate the types of transistors in which the bias value is changed. Specifically, N is a bias value of the N channel MOS transistor (second substrate voltage VBN), P is a bias value of the P channel MOS transistor (first substrate voltage VBP), and B is a bias value of the N channel MOS transistor. The second substrate voltage VBN and the bias value of the P-channel MOS transistor (first substrate voltage VBP) are changed (0.00 V, 0.60 V, 1.20 V), respectively. The vertical axis represents each oscillation frequency (the oscillation frequency of the first ring oscillator RING_N: Freq_N, the oscillation frequency of the second ring oscillator RING_P: Freq_P, and the oscillation frequency of the third ring oscillator RING_C: Freq_C).

  In this measurement result, for example, in the case of SF finish, the drain current of the N-channel MOS transistor is weak, so the sensitivity of the first ring oscillator RING_N to the bias value of the second substrate voltage VBN is increased, and the second The substrate voltage VBN dependency and the amount of change when both the first substrate voltage VBP and the second substrate voltage VBN are changed are large.

  Further, for example, in the case of FF finish, since both the P-channel MOS transistor and the N-channel MOS transistor drain have a large current and are balanced, there is no difference in either dependency.

  In this way, characteristics of each oscillation frequency are obtained from the characteristics of the transistor obtained by the characteristic test circuit TC. Therefore, the characteristics of the transistors of the control target block CB having the same finish as the transistors constituting the characteristic test circuit TC are also found. Therefore, the fuse circuit can be programmed according to the characteristics of the transistor based on this result.

  For example, a simple method for measuring a threshold voltage of a transistor requires a dedicated external input / output pin to measure an analog value, and a measurement tester accurately measures current. Therefore, analog characteristics are required. However, by digitizing the measurement value viewed from the tester as in this embodiment, measurement with an inexpensive tester becomes possible. Further, if it is a digital value, multiplexing with other pins is possible, and the chip manufacturing cost can be reduced.

  The chip test of the present invention is not necessarily limited to the test performed before dicing. However, a chip test may be performed after dicing, but the test becomes complicated, and therefore the chip test is a test before dicing in the present invention.

  Although the present invention has been described in detail, the above description is illustrative in all aspects, and the present invention is not limited thereto. It is understood that countless variations that are not illustrated can be envisaged without departing from the scope of the present invention.

Claims (11)

First storage circuitry having a first data about the first voltage and the second voltage,
The first in the memory circuits, a first signal supply circuits for inputting the first issue signal specifying the desired data from said first data,
Based on signals input external or al, second is signal is input to the first storage circuits,
Said first storage circuits, from among the first data, the specific data corresponding to said first signal contact and the second issue signal inputted to the first memory circuitry A semiconductor device that selects and outputs a third signal corresponding to the specific data. The semiconductor device according to claim 1, characterized in that it comprises further a first voltage generating circuits for generating the second voltage based on said third signal. MOS transistor further comprising a motor, a semiconductor device according to claim 1, characterized by using the second voltage to the substrate voltage of the MOS transistor data. First storage circuitry having a first data about the first voltage and the second voltage,
The first in the memory circuits, a first signal supply circuits for inputting the first issue signal specifying the desired data from said first data,
Second storage circuits having a second data related to said first voltage and the third voltage,
The second in the memory circuits, the second signal supply circuits for inputting the second issue signal specifying the desired data from said second data,
With
Based on signals input external or al, third issue signal is input said first storage circuits to said second storage circuits,
Said first storage circuits, from among the first data, the data corresponding to the signal of said first storage times the input to the path first signal contact and said third fourth Output as
Said second storage circuits, from among the second data, the data corresponding to the signal of the second storage times the input to the path the second signal contact and said third fifth A semiconductor device characterized by output as a signal. First voltage generating circuits for generating the second voltage based on said fourth signal,
Second voltage generating circuits for generating the third voltage based on the fifth signal,
The semiconductor device according to claim 4, further comprising: Memory circuits having data relating to the first voltage and the second voltage and the third voltage,
The first signal supply circuits for inputting the first issue signals to the memory circuit,
Second signal supply circuits for inputting the second issue signals to the memory circuit,
With
Based on signals input external or al, third issue signal is input to the storage circuits,
Wherein the storage circuitry selects the data corresponding to the first said and signal of the second signal contact and the third issue signal, wherein based on the corresponding data, the fourth signal and the fifth A semiconductor device which outputs a signal. First voltage generating circuits for generating the second voltage based on said fourth signal,
The semiconductor device according to claim 6, characterized in that it comprises further a second voltage generating circuits for generating the third voltage based on the fifth signal. The semiconductor device further includes a plurality of MOS transistors data,
Wherein each second and third voltage is characterized by being used as the substrate potential of said plurality of MOS transistors motor, the semiconductor device according to any one of claims 4 or claim 6. Wherein the plurality of MOS transistors comprises a MOS transistor capacitor and the MOS transistor capacitor of the second polarity of the first polarity,
Using the second voltage to the substrate potential of the MOS transistor capacitor of the first polarity,
The semiconductor device according to claim 8, wherein the use of the third voltage to the substrate potential of the MOS transistor capacitor of the second polarity. Further comprises an address converter,
7. The semiconductor device according to claim 1, wherein a signal input from the outside is converted into a desired signal through the address converter. Wherein the signal input from the external device is a signal relating to the value of the first voltage, the semiconductor device according to any one of claims 1 or claim 4 or claim 6.

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