WO2008133167A1 - Semiconductor device and method for manufacturing semiconductor device - Google Patents

Semiconductor device and method for manufacturing semiconductor device Download PDF

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Publication number
WO2008133167A1
WO2008133167A1 PCT/JP2008/057487 JP2008057487W WO2008133167A1 WO 2008133167 A1 WO2008133167 A1 WO 2008133167A1 JP 2008057487 W JP2008057487 W JP 2008057487W WO 2008133167 A1 WO2008133167 A1 WO 2008133167A1
Authority
WO
WIPO (PCT)
Prior art keywords
power supply
supply voltage
rom
semiconductor device
substrate
Prior art date
Application number
PCT/JP2008/057487
Other languages
French (fr)
Japanese (ja)
Inventor
Hiroaki Suzuki
Original Assignee
Renesas Technology Corp.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp. filed Critical Renesas Technology Corp.
Priority to JP2009511840A priority Critical patent/JP5090440B2/en
Publication of WO2008133167A1 publication Critical patent/WO2008133167A1/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
    • H03K19/00384—Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits

Abstract

To provide a mechanism for controlling a substrate voltage and a power supply voltage for suppressing MOS transistor device fluctuation by a simple means and to simplify a testing step. Combinations of a plurality of power supply voltage values (VDD) and substrate voltage values (VBP, VBN) are set in ROMs (ROM1- ROM 7). At the time of performing chip test, drain current and operation speed tests are performed at first to MOS transistors (PT, NT) to be controlled, while the transistors are turned off, and device fluctuation is confirmed. Fuse circuits (FU0-FU1) program to select an ROM having an optimum combination of the power supply voltage value (VDD) and the substrate voltage values (VBP, VBN), corresponding to the status of device fluctuation. In the subsequent chip tests, optimum substrate voltages are determined by looking up an ROM table corresponding to a power supply voltage value inputted from the external.
PCT/JP2008/057487 2007-04-23 2008-04-17 Semiconductor device and method for manufacturing semiconductor device WO2008133167A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009511840A JP5090440B2 (en) 2007-04-23 2008-04-17 Semiconductor device

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2007112767 2007-04-23
JP2007-112767 2007-04-23
JP2007-336241 2007-12-27
JP2007336241 2007-12-27

Publications (1)

Publication Number Publication Date
WO2008133167A1 true WO2008133167A1 (en) 2008-11-06

Family

ID=39925623

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/057487 WO2008133167A1 (en) 2007-04-23 2008-04-17 Semiconductor device and method for manufacturing semiconductor device

Country Status (2)

Country Link
JP (1) JP5090440B2 (en)
WO (1) WO2008133167A1 (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001345693A (en) * 2000-05-30 2001-12-14 Hitachi Ltd Semiconductor integrated circuit device
JP2002041160A (en) * 2000-07-24 2002-02-08 Univ Tokyo Power controller and power control method and recording medium with power control program recorded
JP2003142598A (en) * 2001-11-01 2003-05-16 Hitachi Ltd Semiconductor integrated circuit device
JP2004228417A (en) * 2003-01-24 2004-08-12 Renesas Technology Corp Semiconductor integrated circuit apparatus
JP2005136322A (en) * 2003-10-31 2005-05-26 Toshiba Corp Semiconductor integrated circuit and power-supply-voltage/substrate-bias control circuit

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001345693A (en) * 2000-05-30 2001-12-14 Hitachi Ltd Semiconductor integrated circuit device
JP2002041160A (en) * 2000-07-24 2002-02-08 Univ Tokyo Power controller and power control method and recording medium with power control program recorded
JP2003142598A (en) * 2001-11-01 2003-05-16 Hitachi Ltd Semiconductor integrated circuit device
JP2004228417A (en) * 2003-01-24 2004-08-12 Renesas Technology Corp Semiconductor integrated circuit apparatus
JP2005136322A (en) * 2003-10-31 2005-05-26 Toshiba Corp Semiconductor integrated circuit and power-supply-voltage/substrate-bias control circuit

Also Published As

Publication number Publication date
JP5090440B2 (en) 2012-12-05
JPWO2008133167A1 (en) 2010-07-22

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