JP5078290B2 - Power semiconductor module - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a power semiconductor module which is capable of restraining heat released from semiconductor elements from causing thermal damage to a low heat-resistant member, such as a bonding material etc, in a case where a current applied to a power semiconductor element is comparatively large and amounts to 50A/cm<SP>2</SP>or above. <P>SOLUTION: The power module is equipped with a board where power semiconductor unit elements are mounted on its one surface with a first bonding material and a board supporting member to which the above board is bonded with a second bonding material. Provided that a maximum current supplied to per unit area of the unit element is represented by (a), the resistance value of the unit element is represented by Ron, the area ratio of the unit element to an insulating board is represented by (r), the allowable rising temperature of the first bonding member is represented by &Delta;T, and the area of the unit element is represented by (s); (s) is so set as to satisfy two Formulas, &Delta;T&ge;Ron a<SP>2</SP>(9.9s+64.2r+8.8)&times;10<SP>-2</SP>and 0.25&ge;s&ge;0.1, and the power semiconductor module is constituted so as to satisfy Formula, N=A/s, wherein N is the parallel number of the unit elements, and A denotes a current to be supplied. <P>COPYRIGHT: (C)2008,JPO&amp;INPIT

Description

  The present invention relates to a power semiconductor module in which a substrate having a power semiconductor element bonded to one surface via a first bonding material is bonded to a substrate support member via a second bonding material.

  A power semiconductor module is used for a power supply module circuit that controls a driving device such as a motor (see, for example, Patent Document 1). A schematic explanatory view showing an example of the structure of such a conventional power semiconductor module is shown in FIG.

  As shown in FIG. 20, the power semiconductor module 101 is mounted (or bonded) to a substantially flat insulating substrate 111 and one surface (upper surface in the drawing) of the insulating substrate 111 via a first bonding material 112. In addition, the power semiconductor element 113 and the other surface (the lower surface in the drawing) of the insulating substrate 111 are configured to include a substantially flat base plate 115 bonded through a second bonding material 114. . Although not shown in FIG. 20, the circuit is formed in the power semiconductor element 113 by connecting a plurality of wirings by wire bonding or the like. For example, lead-free solder is used as the first bonding material 112.

  In general, in such a power semiconductor module 101, the power semiconductor element 113 itself generates heat in accordance with the amount of current applied, but the power semiconductor element 113 itself and the first bonding material 112 are different from other members. By being a weak heat-resistant member having a low heat resistance, it is necessary to prevent the heat generated by the heat generation from causing thermal damage to these weak heat-resistant members. Therefore, in the conventional power semiconductor module 101, heat sink is promoted by providing a heat sink (not shown) on the back surface of the base plate 115, or by causing the base plate 115 itself to function as a heat sink. The first bonding material 112 is prevented from being thermally damaged.

  In the field of such a power semiconductor module, a module that can cope with higher output is strongly desired. As such a module, the power semiconductor element 113 includes a Si (silicon) bipolar device (Si-IGBT element). ) Is used. In such a Si-IGBT element, if a parallel connection structure of a plurality of elements is adopted, current may be biased in some elements and non-uniform operation may occur, so that current capacity can be secured and high output can be supported. In addition, there is a tendency to use a module whose element size is increased within a range in consideration of securing the yield.

JP 2003-37241 A

  In recent years, power semiconductor elements (SiC elements) using SiC (silicon carbide) instead of conventional Si elements used in such power semiconductor modules are attracting attention. This SiC element has superior heat resistance compared to conventional Si elements, and also has a large amount of current that can be input per unit area, and is expected as an important device responsible for miniaturization and high output of power semiconductor modules. Yes.

Specifically, the Si element has a dielectric breakdown electric field of 0.3 MV / cm. For example, in order to ensure a withstand voltage of about 1000 V, the electric resistance value Ron depending on the doping concentration and thickness of the drift layer is expressed in terms of area. Normalized to approximately several hundred mΩ · cm ² . On the other hand, in the SiC element, the dielectric breakdown electric field is 3 MV / cm, which is one digit higher than that of the Si element. Similarly, in order to ensure a withstand voltage of 1000 V, the electric resistance value Ron is two or more orders of magnitude smaller than that of the Si element. . Therefore, when it is assumed that the same heat generation amount is allowed in the element, the amount of current that can be supplied to the power semiconductor element is larger in the SiC element having a smaller electric resistance value, that is, a current that is one digit or more larger than that in the Si element. Density will be allowed. In addition, since such a SiC element has a wide band gap, it has high heat resistance that can maintain its semiconductor characteristics even at a relatively high temperature, and the allowable amount of heat generation is much higher than that of the Si element. large. Therefore, it is possible to further enhance the current density. For example, the Si element needs to suppress the temperature rise of the element to about 150 ° C. or less due to its heat resistance, whereas the SiC element can be operated as a semiconductor element at about 400 ° C. or higher. In addition, in the Si element, the input current amount per unit area is suppressed to less than 50 A / cm ² and the calorific value per unit area is used between 40 to 80 W / cm ² , whereas the SiC element is used. The element is expected to be used in a region where the input current amount per unit area is 50 A / cm ² or more and the heat generation amount per unit area is 80 W / cm ² or more.

  However, even if the current density can be increased and the power semiconductor element itself has high heat resistance, the first bonding material for bonding the SiC element to the insulating substrate is as follows. There is no change in the use of weak heat-resistant members such as lead-free solder materials, and it is necessary to suppress the occurrence of thermal damage to these weak heat-resistant members. For example, it is necessary to suppress the temperature rise of lead-free solder materials to about 125 ° C or less. In a high-power module, simply devising heat dissipation such as a heat sink can sufficiently increase the temperature of weak heat-resistant members. In some cases, it cannot be suppressed. Under such circumstances, there is a problem that development of a power semiconductor device with high output is hindered by effectively utilizing the high heat resistance characteristics of the SiC element.

Therefore, an object of the present invention is to solve the above-described problem, and when the input current amount per unit area of the power semiconductor element is relatively large as 50 A / cm ² or more, the heat generated in the semiconductor element is used. An object of the present invention is to provide a power semiconductor module in which the occurrence of thermal damage to a weak heat-resistant member such as a bonding material is suppressed.

  In order to achieve the above object, the present invention is configured as follows.

According to a first aspect of the present invention, an insulating substrate;
A power semiconductor element group configured by electrically connecting a plurality of power semiconductor unit elements having the same shape bonded to one surface of the insulating substrate via a first bonding material in parallel;
A base member that is bonded to the other surface of the insulating substrate via a second bonding material and supports the insulating substrate;
A cooling block in which the base member is disposed via silicon grease,
Here, when the area of the power semiconductor unit element is an area in plan view when the power semiconductor unit element is disposed on one surface of the insulating substrate,
Maximum amount of current is charged per unit area of the power semiconductor unit devices a (A / cm ^2), the power resistance value per unit area of the semiconductor unit devices Ron (Ω · cm ^2), the power for the insulating substrate The area ratio r of the semiconductor unit elements, the allowable increase temperature ΔT (° C.) of the first bonding material, and the area s (cm ² ) per one power semiconductor unit element are in a range satisfying Formula 11. Each power semiconductor unit element is formed,
The total area S1 (cm ²⁾ of the plurality of power semiconductor unit devices, characterized in that the parallel number N of the respective power semiconductor unit elements, the power semiconductor element group so as to satisfy the equation 12 is constituted A power semiconductor module is provided.
ΔT ≧ Ron · a ² (9.9s + 64.2r + 8.8) × 10 ⁻² (Equation 11)
N = S1 / s (Equation 12)

According to a second aspect of the present invention, there is provided the power semiconductor module according to the first aspect, wherein the maximum amount of current input per unit area of each of the power semiconductor unit elements is 50 A / cm ² or more.

  According to a third aspect of the present invention, there is provided the power semiconductor module according to the first aspect or the second aspect, wherein each of the power semiconductor unit elements is a SiC semiconductor element formed of SiC.

According to a fourth aspect of the present invention, there is provided the power semiconductor module according to any one of the first to third aspects, wherein the first bonding material is formed of a lead-free solder material.

According to a fifth aspect of the present invention, the upper Symbol respective power semiconductor unit element is arranged in a staggered pattern on said one surface of the insulating substrate, said power semiconductor element group is configured A power semiconductor module according to any one of the first to third aspects is provided.

  According to the present invention, it is possible to employ a parallel connection configuration in which a power semiconductor element is divided into a plurality of power semiconductor unit elements in accordance with the amount of heat generated. Even in cases where the total amount of heat generated from the unit is large, the amount of generated heat can be effectively distributed to individual unit elements to reduce the peak value, and the weak heat resistance existing in the module. It is possible to reliably prevent thermal damage to the member.

  Embodiments according to the present invention will be described below in detail with reference to the drawings.

  FIG. 1 is a schematic perspective view showing an external structure of a power semiconductor module 1 which is an example of a power semiconductor module according to an embodiment of the present invention. As shown in FIG. 1, the power semiconductor module 1 includes an insulating base 11 that is an example of a substantially flat substrate (circuit board), and a first bonding material on one surface (upper surface in the drawing) of the insulating substrate 11. And a plurality of power semiconductor unit elements 13 joined (mounted) via 12. Further, the other surface (the lower surface in the drawing) of the insulating substrate 11 is bonded to a substantially flat base plate 15 which is an example of a substrate support member via a second bonding material 14, thereby configuring the power semiconductor module 1. Has been.

  As the insulating substrate 11, for example, a ceramic material having a high insulation rate and thermal conductivity such as aluminum nitride is used. As the first bonding material 12 and the second bonding material 14, a solder material, for example, a lead-free solder material is used. Further, as the base plate 15, in the present embodiment, for example, a metal plate made of an alloy containing copper is used.

  Further, as shown in FIG. 1, each power semiconductor unit element 13 is an element formed of SiC (silicon carbide), and is the same as a unipolar device (SiC element) such as a SiC-MOSFET, for example. It is formed to have a shape. Further, the power semiconductor elements 13 are electrically connected to each other in parallel, and thereby, a power semiconductor element group 16 is configured.

  Further, the SiC-MOSFET element (that is, the power semiconductor unit element) 13 used in the power semiconductor module 1 of the present embodiment is different from a conventional Si element, for example, an Si-IGBT element, and each unit element 13 is replaced with each other. The power semiconductor module 1 has a characteristic that non-uniform operation hardly occurs even when electrically connected in parallel. In the power semiconductor module 1, one large semiconductor element is used, or a plurality of small power semiconductor elements (unit elements). It is possible to realize a highly flexible design that can be used in parallel connection.

  On the other hand, the power semiconductor module 1 having such a configuration has heat resistance of the power semiconductor element 13 and deterioration or damage (thermal damage) characteristics due to heat of the solder material that is a bonding material in the environment where the product is applied. In addition, from the viewpoint of the reliability of joints at each joint resulting from thermal deformation of the entire module, the amount of current that is input is limited so that the temperature rise from room temperature does not exceed a certain temperature Therefore, it is necessary to suppress the occurrence of thermal damage to the weak heat-resistant member present in the module.

  The power semiconductor module 1 according to the present embodiment includes a plurality of power semiconductors having a power semiconductor element having a size required for the module as means for suppressing the occurrence of thermal damage to the weak heat-resistant member. By dividing the unit element 13 and adopting a structure in which the individual unit elements 13 are electrically connected in parallel, the amount of heat generated in the power semiconductor element is distributed to the individual power semiconductor unit elements 13. Thus, the temperature rise of the weak heat resistant member represented by the first bonding material 12 can be suppressed.

Here, a parameter relational expression indicating a structural condition of the power semiconductor module 1 of the present embodiment is shown. A maximum current amount a (A / cm ² ) input per unit area of the power semiconductor unit element 13, a resistance value Ron (Ω · cm ² ) per unit area of the power semiconductor unit element 13, The area ratio r with the insulating substrate 11, the allowable temperature rise ΔT (° C.) of the weak heat-resistant member (for example, the first bonding material 12), and the area s (cm ² ) of each power semiconductor unit element 13 is several 1 The power semiconductor module 1 is configured to satisfy a range that satisfies the above. In the present embodiment, the area (or unit area) of the unit element means an area in plan view in a state where the semiconductor element is arranged.
ΔT ≧ Ron · a ² (9.9s + 64.2r + 8.8) × 10 ⁻² (Equation 1)

However, in the power semiconductor module 1, a plurality of wires, for example, aluminum wires, are connected to each power semiconductor unit element 13 by bonding. From such a wire diameter and wire bonding accuracy, at least a lower limit value of the area of the unit element 13 to be secured, that is, a minimum allowable area s _min (cm ² ) for wire bonding is determined. Further, in the process of manufacturing each power semiconductor unit element 13, in order to ensure a sufficient yield from the mixing ratio of voids and the like generated per one semiconductor wafer, the area per unit element 13 is increased. A maximum allowable area s _max (cm ² ) is determined. That is, the area s per power semiconductor unit element 13 needs to satisfy the above formula 1 and also the formula 2. Note that the minimum allowable area s _min and the maximum allowable area s _max of the area of such unit elements are values that change with the progress of semiconductor element manufacturing techniques and mounting techniques such as wire bonding. In the SiC element, for example, the minimum allowable area s _min = 0.1 cm ² and the maximum allowable area s _max = 0.25 cm ² , but with the advancement of technology, the minimum allowable area s _min becomes a smaller value and the maximum allowable area It is conceivable that s _max becomes a larger value.
s _max ≧ s ≧ s _min (Expression 2)

Thus, using the power semiconductor unit elements 13 having the area s satisfying Equations 1 and 2, the parallel number N of the respective semiconductor unit elements 13 constituting the power semiconductor element group 16 is determined by Equation 3 . it is Ru can be. Thereby, the power semiconductor module 1 in which the power semiconductor element group 16 is configured can be provided. S1 is the total area of the power semiconductor unit elements 13 constituting the power semiconductor element group 16.
N = S1 / s (Equation 3)

  In such a power semiconductor module 1, while adopting a SiC element as the power semiconductor element 13, the temperature rise in the weak heat-resistant member, for example, the first bonding material 12, can be suppressed to ΔT (° C.) or less, The power semiconductor module 1 in which thermal damage to the weak heat resistant member is suppressed can be configured.

  Each of these mathematical expressions, that is, parameter relational expressions, can be represented on the graph shown in FIG. In FIG. 2, the horizontal axis indicates the input current amount a per unit area of the power semiconductor unit element 13, that is, the current density, and the vertical axis indicates the area s per unit of the power semiconductor unit element 13. Yes. In such a graph, the allowable rise temperature ΔT of the first bonding material 12 is plotted as an isotherm according to Equation 1. Further, the conditions shown in Equation 2 are also plotted in the graph of FIG.

  Here, the power semiconductor module 1 having a structure determined from Equations 1 to 3 and the graph of FIG. 2 will be described with specific numerical examples. For example, it is assumed that the predetermined amount of current input to the product, that is, the maximum amount of current required when an excessive load is applied to the product is 174A. Further, as a result of the temperature rise due to heat transfer inside the power semiconductor module 1, even if the connection portion of the first bonding material 12 is thermally damaged, the first bonding material 12 is also caused by the overall thermal deformation. Even if mechanical damage is given to the connection portion, the allowable rise temperature ΔT is set to 20 ° C. as a restriction necessary for sufficiently satisfying the connection life. Then, in the example of the present description, the temperature increase of the first bonding material 12, that is, the solder bonding portion does not exceed 20 ° C. with respect to the amount of current 174 A input to the power semiconductor module 1, that is, the power semiconductor element group 16. It is necessary to design such a structure.

Moreover, since a SiC element is used as the power semiconductor unit element 13, Ron which is the resistance characteristic of the semiconductor unit element itself is, for example, 0.01 Ω · cm ² . Further, in consideration of the size restriction required for the power semiconductor module 1 (that is, a module that is too large actually has more usage restrictions), the total area of each power semiconductor unit element 13 is not limited. The insulating substrate 11 having an area 10 times larger is used, and the area ratio r is 0.1.

Looking at the correspondence between the various conditions so far and the graph of FIG. 2, the range indicated by the oblique lines in the figure is the designable range D of the power semiconductor module 1. That is, the range that is below the isotherm of the allowable rise temperature ΔT = 20 ° C. determined by Equation 1 and that satisfies the manufacturing or mounting conditions of the unit element 13 shown by Equation 2 is designed. This is a possible range D. In the designable range D, the lower limit of the current density is 50 A / cm ² in order to utilize the advantage of using the SiC element as the unit element. The current density in the conventional Si element is less than 50 A / cm ² .

In order to satisfy the designable range D determined by Equations 1 and 2, for example, the current amount a input per one power semiconductor unit element 13 is 110 A / cm ² , and the power semiconductor unit element 13 is 0.1 cm ^2, and the amount of current input to the power semiconductor module 1 is 174 A, the total area of the power semiconductor unit elements 13 is 174 ÷ 110≈1.6 cm ² . Further, since the area s per unit element 13 is 0.1 cm ² , the number N of parallel arrangements can be determined as N = 1.6 ÷ 0.1 = 16. Each power semiconductor unit element 13 determined in this way is arranged on the insulating substrate 11 through the first bonding material 12 in, for example, a matrix shape (or a lattice shape or a matrix shape) in 4 rows × 4 columns. Thus, the temperature increase of the first bonding material 12 can be reduced to 20 ° C. or less, and thus the power semiconductor module 1 in which the occurrence of thermal influence on the bonding material 12 is suppressed can be configured.

(About the principle to suppress the temperature rise due to the division into unit elements)
Next, the principle of suppressing the temperature rise by dividing the power semiconductor element into a plurality of unit elements 13 will be described below. In such description, as a comparative example of the present embodiment, a schematic explanatory diagram of a power semiconductor module when the power semiconductor element is formed as one element is shown in FIG. Or the graph which shows distribution of the temperature rise value in a 1st joining material) is shown to FIG. 3 (B). For this comparative example, a schematic explanatory diagram when a power semiconductor module is formed using a plurality of power semiconductor unit elements as in this embodiment is shown in FIG. Or the graph which shows distribution of the temperature rise value in a 1st joining material) is shown in FIG.4 (B). In addition, the schematic explanatory diagram of the module shown in FIGS. 3A and 4A and the position of the insulating substrate surface shown on the horizontal axis in the temperature distribution graphs of FIGS. 3B and 4B are: They are shown as corresponding to each other. The power semiconductor element 213 in the module 201 of the comparative example and the power semiconductor unit element 13 in the module 1 of the present embodiment are both formed as SiC elements, and the total area of each element is the same. The insulating substrate 11 and the first bonding material 12 are also formed of the same material. In addition, the number of divisions into the respective unit elements 13 in the module 1 of the present embodiment is set to, for example, 3 for the sake of easy understanding of the following description.

3 and 4, assuming that the input current amount I (A) to the modules 201 and 1 is the same, the heat generation amount W ₂₁₃ of the power semiconductor element 213 in the module 201 of the comparative example of FIG. be able to.
W ₂₁₃ = R × I ² = (Ron / S1) × I ² = (Ron · I ² ) / S1
... (Equation 4)
Meanwhile, the heating value W ₁₃ of one power semiconductor unit devices 13 in the module 1 of this embodiment can be represented by the number 5.
W ₁₃ = R × (I / N) ² = {Ron / (S1 / N)} × (I / N) ²
= (Ron · I ² ) / (S1 · N) (Equation 5)
Note that R is the resistance value of one element, S1 is the total area of the elements, N is the number of divisions into unit elements 13, and in this description, N = 3.

As is apparent from the calorific values W ₂₁₃ and W ₁₃ expressed by the equations 4 and 5, the calorific value of one element, that is, a single element, is inversely proportional to the number of divided unit elements 13 (or the number of parallel elements). It turns out that it becomes small.

As shown in FIGS. 3A and 3B, in the module 201 of the comparative example, the temperature rise ΔT gradually increases as the semiconductor element 213 is approached from the respective end portions of the insulating substrate 11. A local maximum value ΔT ₁₀ of the temperature increase ΔT is generated at a position P 10 at the substantially center of the element 213. On the other hand, referring to FIGS. 4A and 4B, in the module 1 of this embodiment, the temperature gradually increases from the respective end portions of the insulating substrate 11 toward the unit elements 13 located at both ends. The rise ΔT is increased, and peaks ΔT ₁ and ΔT _{3 of the} temperature rise ΔT are generated at the central positions P1 and P3 of the respective unit elements 13 at both ends. The temperature rises gradually as the center unit element 13 is further approached. [Delta] T is lowered, the maximum value [Delta] T ₂ of the temperature rise [Delta] T is generated at the center position P2 at the center of the unit element 13 again. However, the maximum value [Delta] T ₂ in module 1, and the peak [Delta] T _1, [Delta] T ₂ has a sufficiently low value as compared with the maximum value [Delta] T ₁₀ in module 201 of the comparative example.

  The reason can be considered as follows. In a single element, even if substantially uniform heat generation occurs regardless of the end portion or the center of the element, direct heat transfer occurs inside the element, so that a maximum point of temperature rise ΔT occurs in the center of the element. Become. On the other hand, by dividing the element into a plurality of unit elements, it becomes possible to substantially divide the direct heat transfer between the unit elements, and the maximum point of the temperature rise ΔT occurs for each unit element. The absolute value can be reduced in inverse proportion to the number of divisions. However, although it is sufficiently small compared with the direct heat transfer in the element, the indirect heat transfer through the insulating substrate and the like remains even after the above-mentioned division, so the unit arranged in the center The maximum value of the element 13 is slightly higher than the maximum value of the unit element 13 disposed on the end side. Therefore, by adopting the parallel arrangement structure to the plurality of unit elements 13 in this way, it is possible to suppress the temperature rise ΔT according to the division number N.

Here, by dividing such a semiconductor element into a plurality of unit elements, the effect of suppressing the temperature rise with respect to the weak heat-resistant member is that the area of the unit element (cm ² ) and the number N of element divisions (number ) And the temperature rise ΔT (° C.) of the weak heat-resistant member, an example of the relationship is shown in the graph of FIG. As shown in FIG. 14, by dividing the area of the semiconductor element from, for example, 1.44 cm ² and reducing the size, the temperature rise ΔT can be reduced. It can be seen that the temperature rise ΔT can be reduced to about 20 ° C. by downsizing to about 2 cm ² , that is, dividing into 10 or more unit elements.

(Influence of heat transfer to adjacent unit elements)
Further, as a graph showing the number of divided semiconductor elements and the influence of heat transfer from one unit element to an adjacent unit element, the relationship between the distance d from the center of the unit element and the substrate internal temperature T is expressed as follows: FIG. 15 shows a graph shown for each (for example, the number of divisions of 2, 10, and 16). As shown in FIG. 15, when the number of element divisions is two, the substrate internal temperature T = T ₂ at the element center (d = 0) decreases as the distance increases. It can be seen that d ₂ decreases to T ₀ , which is a sufficiently lower temperature than temperature T ₂ . Further, when the number of element divisions is 10, the temperature at the element center can be reduced to T ₁₀ <T _2, and the distance for reducing the temperature to T ₀ can be reduced to d ₁₀ <d _2. . Furthermore, when the number of element divisions is increased to 16, the substrate internal temperature can be reduced to T ₁₆ <T ₁₀ , and the distance for reducing the temperature to T ₀ can be further shortened to d ₁₆ <d _10. I understand that. Note that such a temperature T ₀ can be said to be a temperature at which the thermal influence due to heat transfer to adjacent unit elements is sufficiently reduced with respect to the allowable temperature increase ΔT, for example.

(Circuit configuration of power semiconductor module)
Here, an example of a circuit configuration in the power semiconductor module of the present embodiment will be described below with reference to schematic circuit configuration diagrams shown in FIGS. 16, 17, and 18.

  First, FIG. 16 and FIG. 17 are schematic circuit configuration diagrams showing the concept of the circuit configuration in the present embodiment, and FIG. 16 shows a conventional power semiconductor module 101 in the case where the semiconductor element 113 configured as a transistor is taken as an example. FIG. 17 is a diagram illustrating a circuit configuration in the power semiconductor module 1 of the present embodiment when a plurality of unit elements 13 that are also configured as transistors are taken as an example. As shown in FIG. 16, a transistor is generally provided with three electrodes, that is, a drain electrode 101d, a source electrode 101s, and a gate electrode 101g. The power semiconductor module 1 of this embodiment is configured by dividing such a conventional transistor into a plurality of parts and electrically connecting them in parallel. Specifically, as shown in FIG. 17, the power semiconductor module 1 forms an assembly of transistors by connecting individual transistors configured by a plurality of unit elements 13 in parallel. As a whole, a common drain electrode 1d, source electrode 1s, and gate electrode 1g are provided. That is, in the present embodiment, for example, the power semiconductor module 1 is configured by electrically dividing one transistor function physically and performing electrical connection in parallel.

  As shown in FIG. 17, for example, a circuit for driving a motor according to the example of the present embodiment as shown in FIG. 18 is configured by using the transistor circuit including the plurality of unit elements of the present embodiment. Can do. The circuit 80 shown in FIG. 18 boosts the DC voltage (for example, 200 to 300 V) of the battery 81 by the converter 82 (for example, boosts to 600 to 700 V), and then converts it to three-phase AC by the inverter 83, The circuit configuration is such that the AC motor 84 is driven. The converter 82 is configured by the power semiconductor module of the present embodiment, and is configured by, for example, two transistors 13A that are unit elements. The inverter 83 is also configured by the power semiconductor module of the present embodiment, and is configured by, for example, six transistors 13B that are unit elements. As shown in FIG. 18, a smoothing capacitor 85 and a reactor 86 are provided between the battery 81 and the converter 82, and a filter capacitor 87 is provided between the converter 82 and the inverter 83. Is provided. In the circuit 80 for driving the AC motor 84 configured as described above, it is possible to suppress the occurrence of a thermal influence on a weak heat-resistant member such as a bonding material while using a power semiconductor element, and a higher output motor. It becomes possible to realize the drive.

(About the derivation method of number 1 by thermal fluid analysis)
Next, a derivation method of Equation 1, which is a parameter relational expression between the area s of each power semiconductor unit element 13 and the allowable temperature rise ΔT of the weak heat resistant member, will be described below. In the present invention, as a method for deriving such a parameter relational expression, a method of performing thermal fluid analysis by a finite volume method using a steady thermal fluid model (three-dimensional model) is used.

  First, as for the analysis model of the power semiconductor module used as the steady thermal fluid model, a schematic external perspective view of the analysis model 10 is shown in FIG. 5, and a schematic partial sectional view thereof is shown in FIG. It should be noted that each constituent member in the analysis model 10 of the power semiconductor module 1 is given the same reference numeral as each constituent member of the power semiconductor module 1 in order to facilitate understanding thereof. As shown in FIGS. 5 and 6, the analysis model 10 includes a plurality of power semiconductor unit elements 13 (that is, a power semiconductor element group) and these semiconductor unit elements 13 bonded together via a first bonding material 12. The insulating substrate 11 includes a base plate 15 to which the insulating substrate 11 is bonded via a second bonding material 14, and a cooling block 18 in which the base plate 15 is disposed via silicon grease 17. In this analysis model 10, the base plate 15 has a function as a heat sink. Further, as shown in FIG. 5, a silicon gel 19 is disposed so as to cover the entire exposed surface (upper surface in the drawing) of the insulating substrate 11 and each power semiconductor unit element 13. In FIG. 6, illustration of the silicon gel 19 is omitted.

  As shown in FIG. 6, the insulating substrate 11 has, for example, a three-layer structure, and is composed of an electrode layer 11a, a substrate layer 11b, and an aluminum layer 11c from the upper surface in the drawing. The thickness t of each member is, for example, semiconductor unit element 13: 0.037 cm, first bonding material 12: 0.01 cm, electrode layer 11a: 0.04 cm, substrate layer 11b: 0.064 cm, aluminum layer : 0.04 cm, second bonding material 14: 0.025 cm, base plate 15: 0.3 cm, and silicon grease 17: 0.005 cm. Further, in such an analysis model 10, in order to evaluate the influence on the temperature rise for each design parameter represented by the size and number of the power semiconductor unit elements 13 and the size of the insulating substrate 11, these Design parameters are assumed to be variable. In addition, each unit element 13 arrange | positioned on the insulated substrate 12 shall be arrange | positioned at equal distribution according to the parallel number (division | segmentation number).

  In such an analysis model 10, the heat generation amount (W / piece) per unit element is set as the first condition, and the cooling block 18 is set as a fixed temperature, for example, cooling water as the second condition. A temperature (° C.) was set, and a fixed temperature (° C.) was set around the analysis model 10 as a third condition. Detailed conditions, that is, design parameters and the like will be described later. Further, as an evaluation point, the temperature of the first bonding material 12 arranged on the lower surface of the power semiconductor unit element 13 was obtained by analysis. In addition, analysis calculation is continued until each temperature will be in an equilibrium state, and the said temperature is calculated. Regarding the calculation environment, “finite volume method” was adopted as an analysis technique, “thermal fluid analysis software (Flotherm Ver. 5.1)” was used as a solver, and the number of elements was about 200,000.

Here, the design parameters and analysis experiment levels in this thermal fluid analysis will be specifically described. First, as design parameters that can be varied in this analysis, the total current (total current) A input to each power semiconductor unit element 13, the cooling water temperature T 0 in the cooling block 18, the power semiconductor unit elements 13 The total area (total area of all elements) S1, the parallel number N of unit elements 13, and the total area S2 of the insulating substrate 11 are used. Further, with respect to these design parameters, as shown in the table of FIG. 7, an analysis experiment was performed by combining a plurality of experimental levels. Specifically, three experimental levels of 45A, 146A, and 174A are applied as the total current A input to the unit element, and the unit element total area S1 is 3 of 1 cm ² , 2 cm ² , and 3 cm ² . The three experimental levels of 1, 10, and 16 are applied as the parallel number N of unit elements, and the total area S2 of the insulating substrate is 3.240 cm ² , 8. Three experimental levels of 820 cm ² and 14.440 cm ² were applied, and ^two experimental levels of 65 ° C. and 110 ° C. were applied as the cooling water temperature T0.

  A part of the results of the thermal fluid analysis for all 162 cases, which are all combinations of these design parameters, are shown in the table of FIG. As shown in FIG. 1, for each design parameter, the unit element total area S1 = 1, the parallel number N = 2, the substrate total area S2 = 3.24, the total current A = 45.00, and the cooling water temperature T0 = 65.00. And an analysis calculation was performed to obtain an analysis result indicating that the temperature T of the first bonding material 12 was 71.76 ° C. Thereafter, data No. In 2 and later, the combination of design parameter experimental levels was changed, and the analysis results were calculated for all 162 cases, that is, multivariate analysis was performed.

Using this analysis result, a temperature prediction formula for predicting the temperature T of the first bonding material 12 using each design parameter can be derived as shown in Equation 6.
T = T0 +
A ² · {(8.8 / S1) + (9.9 / N) + (64.2 / S2)} × 10 ⁻⁴
... (Equation 6)

In the temperature prediction formula shown in Formula 6, when the on-resistance value Ron of the unit element is taken into consideration, it can be converted into the formula shown in Formula 7. The temperature increase value ΔT of the first bonding material can be expressed by ΔT = T−T0.
ΔT = (Ron / S1) · A ² ×
{(8.8 / S1) + (9.9 / N) + (64.2 / S2)} × 10 ⁻⁴
... (Equation 7)

Further, the mathematical formula shown in Equation 7 is modified as shown in Equation 8.
ΔT = (Ron / S1 ² ) · A ² ×
{8.8+ (9.9 · S1 / N) + (64.2 · S1 / S2)} × 10 ⁻⁴
... (Equation 8)
Then, when the current density a = A / S1 in the unit element, the area s = S1 / N of one unit element, and the area ratio r = S1 / S2 between the unit element and the insulating substrate are substituted into the mathematical expression of Expression 8, The following mathematical formula can be derived.
ΔT = Ron · a ² · (9.9s + 64.2r + 8.8) × 10 ⁻² (Equation 9)
Furthermore, in Equation 9, the parameter relational expression of the present invention shown in Equation 1 can be derived by setting ΔT as the temperature rise allowable value of the first bonding material. In the temperature prediction formula of Equation 9 derived by the analysis calculation in this way, the temperature prediction could be performed within a range of ± several degrees with respect to the temperature calculated by the thermal fluid analysis.

(Difference between the conventional Si element and the SiC element of this embodiment)
Here, the difference between the Si element used in the conventional power semiconductor module and the SiC element used in the power semiconductor module of the present embodiment will be described in more detail.

Although the conventional Si element and the SiC element of this embodiment are semiconductor elements that are also used in the power semiconductor module, they are elements having completely different characteristics. Specifically, a module using an SiC element can operate at a higher current density, for example, 50 A / cm ² or more than a module using a conventional Si element. It can be said that the characteristics are different. The reason is as follows.

  For example, the doping concentration and thickness of the drift region in the device are designed so that a high voltage can be withstood when the power semiconductor module is in an off state. The electric field distribution in the drift region is determined by the concentration and thickness in this case. The electric field in the depleted drift region increases with a slope determined by the doping concentration, and takes a maximum value at the p / n junction interface. Since the integrated value of the electric field distribution in the drift region determines the breakdown voltage of the power semiconductor module, it is necessary to design the concentration and thickness of the drift region so as to ensure a desired breakdown voltage. In such a design, the withstand voltage of the power semiconductor module is guaranteed by setting the electric field generated at the p / n junction interface where the electric field is greatest to be equal to or less than the dielectric breakdown electric field which is a physical property value of Si. can do. Here, the electrical resistance value Ron when the module is turned on is determined by the designed concentration and thickness.

For example, in the case of a Si element, since the dielectric breakdown electric field is 0.3 MV / cm, a drift region having a thickness of about 100 μm is required at a doping concentration of about 1 × 10 14 in order to ensure a breakdown voltage of about 1000 V. The electrical resistance value Ron determined by the doping concentration and thickness of the drift layer that guarantees a breakdown voltage of 1000 V is normalized by the area and is about several hundred mΩ · cm ² .

  On the other hand, in the case of the SiC element, the dielectric breakdown electric field is 3 MV / cm or more, which is an order of magnitude higher than that of the Si element. An order of magnitude higher doping concentration and an order of magnitude thinner will suffice. For this reason, the power semiconductor module formed of the SiC element has an electric resistance value Ron that is two digits or more smaller than that of the power semiconductor module formed of the Si element.

  Such contents apply to unipolar devices such as MOSFETs, and SiC-MOSFETs are expected to have electrical resistance values Ron that are two orders of magnitude smaller than Si-MOSFETs. On the other hand, a bipolar device (IGBT or the like) is widely used as the Si element instead of the unipolar device described above, but this IGBT or the like uses the injection of minority carriers of the bipolar device to increase the electric resistance value Ron even with the same breakdown voltage. It can be lowered by one digit or more. Even when the SiC-MOSFET is compared with such a Si-IGBT, the magnitude of the electrical resistance value Ron in the power semiconductor module having a 1000V breakdown voltage can be made smaller by one digit in the SiC-MOSFET.

Such an electric resistance value Ron becomes a loss when a current flows through the element, and generates heat W proportional to the square value of the flowing current (W = Ron × I ² ). That is, when the same calorific value is allowed in the element, the current (current per unit area, that is, current density) that can be passed through the SiC element increases. For example, if a SiC-MOSFET is compared with a Si-MOSFET, the SiC-MOSFET is allowed to have a current density that is an order of magnitude greater.

  Furthermore, since the SiC element has a wide band gap, the semiconductor characteristics can be maintained even at high temperatures. In the case of an Si element, the temperature needs to be kept at about 150 ° C. or lower. However, an SiC element can be operated as a semiconductor element even at 400 ° C. or higher. By taking advantage of such high-temperature operation, the SiC element can be used as a power semiconductor element even if the current density is further increased and the element temperature rises due to an increase in heat generation. From the opposite view of such characteristics, the SiC element has a characteristic that the current density can be increased, so that the element area can be reduced when the same current flows. I can say that.

  Further, the difference in characteristics between the Si element and the SiC element from another viewpoint will be described. In a Si-IGBT having characteristics that it can cope with relatively large power (high withstand voltage, large current) among Si elements, each element can be configured by electrically connecting a plurality of Si-IGBT elements in parallel. There may be a non-uniform operation in which current flows biased to some elements due to a difference in characteristics between them. In order to secure a larger current capacity while suppressing the occurrence of such non-uniform operation, it is desirable to increase the size of the Si element. That is, in order to suppress the occurrence of such non-uniform operation in the Si element, the element is increased in size within a range in which the yield of the element can be secured without parallelization to a plurality of elements. .

  On the other hand, the SiC-MOSFET element does not have the problem that non-uniform operation occurs as in the Si-IGBT element. This is because the Si-IGBT element has a temperature characteristic that the electric resistance decreases as the temperature rises, and the temperature of the element rises due to a large current flowing unbalanced, and the resistance decreases accordingly. This is because the current is further increased and the non-uniform operation is amplified. On the other hand, since the SiC-MOSFET element has a characteristic that the electrical resistance increases conversely with a temperature rise, the non-uniform operation is hardly amplified.

  Considering such a difference in characteristics between the two elements, in the conventional Si element, as a structural design for dealing with high power, while avoiding the above-described non-uniform operation, avoiding a parallel configuration of a plurality of elements. It is considered that there is a design philosophy of actively increasing the element size. On the other hand, in the SiC element (SiC-MOSFET) of the present invention, any structure such as a parallel configuration of a plurality of elements or an increase in element size can be adopted in the structural design. Therefore, it can be said that the element has completely different characteristics from the conventional Si element.

(About weak heat-resistant members and allowable temperature rise)
In the description of the above-described embodiment, the case where the weak heat-resistant member is, for example, the first bonding material has been described. However, the present invention is not limited only to such a case. In this specification, the “weak heat-resistant member” is a member having a relatively low heat resistance among the respective members constituting the power semiconductor module, and is thermally caused by the heat generated by the power semiconductor unit element. It is a member that is likely to be adversely affected, and that it is difficult to maintain the function of the member due to such a thermal adverse effect, or the risk that it is likely to be difficult. It is the “allowable temperature rise ΔT” that is set so as not to adversely affect the weak heat-resistant member. Examples of such a weak heat-resistant member include a first bonding material and a second bonding material in which a solder material is used. In addition, a wire material (for example, for electrically connecting unit elements) Aluminum wire: heat resistant temperature of about 200 to 250 ° C., insulating substrate itself (for example, ceramic substrate: heat resistant temperature of 125 to 250 ° C.), molded resin material (heat resistant temperature of 175 ° C. or lower), and the like. For example, when the weak heat-resistant member is a first bonding material using lead-free solder (heat-resistant temperature of about 125 ° C.), for example, the allowable temperature rise ΔT is set to 20 ° C. be able to. When the power semiconductor module is cooled at a cooling temperature of 85 ° C. through the cooling block, the allowable increase temperature ΔT is 20 ° C. considering the heat-resistant temperature of lead-free solder of 125 ° C. and a margin of 20 ° C. It can be determined from the fact that it must be kept within ° C.

(Example of unit element mounting form)
Here, an example of a specific mounting form in the power semiconductor module having such characteristics will be described with reference to a schematic configuration diagram (schematic cross-sectional view) of the power semiconductor module 301 shown in FIG. As shown in FIG. 19, a plurality of unit elements 313 are mounted on a metal electrode 317 via solder 312 on the upper surface of an insulating substrate 311 formed of ceramics. In addition, the insulating substrate 311 is joined to the heat radiating plate 315 as the base plate via the metal electrode 318 and the solder 314 on the lower surface in the drawing. The heat radiating plate 315 is connected to a case member 321 formed of, for example, a molding resin having a hollow container shape, and the power semiconductor module 301 is disposed inside the case member 321. As shown in FIG. 19, the case member 321 is formed with a plurality of metal bodies (for example, conductor wirings) 320 so that the external space and the internal space are in electrical communication. One end of a wire 319 formed of a conductive material such as aluminum is connected to the end of the metal body 320 on the inner space side of the case member 321. The wire 319 is connected to the upper surface of each unit element 313 in the drawing. So-called wire bonding is performed so that the formed device electrodes 313a are electrically connected in parallel. A wire 319 is also connected by wire bonding between the metal electrode 317 disposed on the upper surface of the insulating substrate 311 and the metal body 320. A control circuit board 322 mounted with a plurality of electronic components 323 is fixed above the power semiconductor module 301 in the internal space of the case member 321. The control circuit board 322 is electrically connected to the metal body 320. It is connected to the. Thus, by connecting each unit element 313 in the power semiconductor module 301 to the metal body 320 that is an external terminal by using wire bonding as its mounting form, various effects according to the present embodiment can be obtained. An electric circuit including a power semiconductor module can be configured.

(Modification example of arrangement of power semiconductor unit elements)
Next, a modified example of the arrangement configuration of each power semiconductor unit element 13 in the power semiconductor module 1 of the present embodiment will be described. In the above description, as shown in FIG. 1, for example, 16 power semiconductor unit elements 13 are arranged in 4 × 4 for the purpose of equally dividing the heat radiation amount from each power semiconductor unit element 13 to the insulating substrate 11. However, the arrangement configuration of the unit elements 13 is not limited only to such a case.

  Instead of such a matrix-like arrangement configuration, for example, as shown in FIG. 9, a configuration in which 16 unit elements 13 are arranged in a staggered pattern may be employed. Specifically, as shown in FIG. 9, a total of 16 power semiconductor unit elements 13 are arranged in four rows on the insulating substrate 11 in the power semiconductor module 21 according to this modification. The unit elements 13 in adjacent columns are arranged in a staggered pattern so that the distance between the unit elements 13 is maximum. That is, an arrangement configuration is employed in which the unit elements 13 arranged in a certain column are not adjacent to and adjacent to other unit elements arranged in the adjacent column. By adopting such an arrangement, the distance between the unit elements 13 can be maximized without increasing the area of the insulating substrate 11, and the thermal influence between the unit elements 13 can be minimized. It is possible to suppress the temperature rise ΔT of the first bonding material 12 more effectively.

(About power semiconductor module design method)
Next, a method for specifically designing a power semiconductor module in which a temperature increase with respect to the first bonding material 12 is suppressed using the relational expression of Formula 1 that determines the structure of the power semiconductor module 1 of the present embodiment. An example will be described below.

First, as a first step, in the relational expression of Equation 1, it is assumed that the area s = 0 of each power semiconductor unit element 13 and the area ratio r = 0 between the unit element 13 and the insulating substrate 11 are as follows. Is considered to be divided into the smallest and the area of the insulating substrate 11 is maximized. Then, the relationship between the current density a and the resistance value Ron per unit area of the unit element when the area of the unit element 13 and the area of the insulating substrate 11 are in the best state with respect to the heat dissipation performance is shown in the graph of FIG. Can be derived as follows. In FIG. 10, the vertical axis indicates the resistance value Ron (mΩ · cm ² ) per unit area of the unit element, the horizontal axis indicates the current density a (A / cm ² ), and the first An allowable temperature rise ΔT (° C.) of the bonding material 12 is indicated by an isotherm.

As shown in the graph of FIG. 10, for example, when it is intended to realize a power semiconductor module in which the allowable temperature rise ΔT is 20 ° C. or less at a current density a of 150 (A / cm ² ) or more, It can be seen that the resistance value Ron must be 10 (mΩ · cm ² ) or less. In the conventional Si element, since the resistance value Ron per unit area exceeds 10 (mΩ · cm ² ), a module having such a specification cannot be realized. Therefore, it can be seen that in order to realize this module, it is necessary to use a SiC element having such a characteristic that Ron is 10 (mΩ · cm ² ) or less.

Next, as a second step, when the condition that the resistance value per unit area is Ron = 2 (mΩ · cm ² ) is set, the unit element area s = 0 is assumed in the relational expression (1). Consider the case where the unit element is in the best condition for heat dissipation performance. Then, the relationship between the current density a and the area ratio r between the unit element and the insulating substrate can be derived as shown in the graph of FIG. In FIG. 11, the vertical axis represents the area ratio r between the unit element and the insulating substrate, the horizontal axis represents the current density a (A / cm ² ), and the allowable rise temperature of the first bonding material 12. ΔT (° C.) is indicated by an isotherm.

Using the graph of FIG. 11, when a predetermined current density a is applied, an area ratio r that can realize ΔT ≦ 20 ° C. of the allowable increase temperature of the first bonding material 12 is determined. For example, when the current density is a = 200 (A / cm ² ), the area ratio needs to be set to r ≦ 0.25 (that is, the area of the insulating substrate is not more than 4 times the total area of the unit elements). I understand that. If the current density is a = 300 (A / cm ² ), the area ratio must be set to r ≦ 0.03. Actually, when the area ratio r is smaller than 0.1, for example, the area of the insulating substrate 11 becomes too large. Therefore, the area ratio is preferably set to r ≧ 0.1 or more from this viewpoint. It can be seen that the current density is preferably a ≦ 250 (A / cm ² ).

Finally, as a third step, when the resistance value per unit area is set to Ron = 2 (mΩ · cm ² ) and the area ratio between the unit element and the insulating substrate is set to r = 0.1, Using the relational expression of Equation 1, the relationship of the area s of one unit element to the current density a is derived as shown in the graph of FIG. In the graph of FIG. 12, the vertical axis indicates the area s (cm ² ) of the unit element, the horizontal axis indicates the current density a (A / cm ² ), and further, the tolerance of the first bonding material 12. The rise temperature ΔT (° C.) is indicated by an isotherm.

Using the graph shown in FIG. 12, the current density a and the unit element area s at which the allowable increase temperature of the first bonding material 12 can realize ΔT ≦ 20 (° C.) are determined. For example, when the current density is a = 200 (A / cm ² ), the area of one unit element needs to be s ≦ 1.0 (cm ² ), and a = 250 (A / cm ² ). cm ²⁾ and when the one unit of area elements it can be seen that it is necessary to make the s ≦ 0.1 (cm ^2).

By performing such first to third steps, it is possible to design and manufacture a power semiconductor module having a structure capable of suppressing the occurrence of a thermal adverse effect on the first bonding material 12. It becomes possible. Note that the order of these steps is not limited to the order as described above, and can be performed in other orders. An example of combinations of design parameters in the power semiconductor module determined using such a design technique is shown in the table shown in FIG. In the table shown in FIG. 13, in the design condition that the amount of current applied to the power semiconductor module is 174 A and the allowable temperature rise of the first bonding material 12 is ΔT = 20 ° C., Equations 1 and 2 , And combinations of design parameters derived using Equation (3). For example, under the conditions of the resistance value Ron = 10 (mΩ · cm ² ), the area ratio r = 0.1, and the current density a = 110 (A / cm ² ), the total area S1 = 1.58 ( cm ² ), the insulating substrate area S2 = 15.82 (cm ² ), and the unit number N = 16 of the unit elements having the area s = 0.1 (cm ² ) is arranged, or the area s = 0.15. It is possible to employ a configuration of a power semiconductor module in which (cm ² ) unit elements are arranged in a parallel number N = 11.

  According to the above-described embodiment, it is possible to reliably suppress a thermal adverse effect on the weak heat-resistant member such as the first bonding material existing in the module by using the SiC element that can correspond to the high power specification. A configuration of a power semiconductor module that can be realized can be realized. In particular, by applying the concept of positively parallel (divided) arrangement that does not exist in the Si elements used in conventional power semiconductor modules to the SiC element of the present invention, a plurality of SiC unit elements are arranged in parallel. The power semiconductor module can be configured by the arrangement, and the peak value of the heat generation temperature generated in each unit element can be reduced to effectively suppress the adverse thermal effect on the weak heat resistant member. Moreover, when determining the structure of such a power semiconductor module, the structural design can be facilitated by applying the parameter relational expressions of Equation 1, Equation 2, and Equation 3. Therefore, by manufacturing a power semiconductor module having a structure that satisfies such a relational expression of Equations 1 to 3, it can meet high power specifications while suppressing the thermal influence on the weak heat resistant member. It is possible to provide a module that can be used.

  It is to be noted that, by appropriately combining arbitrary embodiments of the various embodiments described above, the effects possessed by them can be produced.

  In the power semiconductor module of the present invention, when the heat generation amount per unit area of the semiconductor element is relatively large, the heat amount is efficiently dispersed according to the heat generation amount, and the semiconductor element and the semiconductor element are bonded with the smallest possible area. The temperature rise of the weak heat resistant member such as the bonding material to be reduced can be reduced. Therefore, it is possible to make effective use of characteristics that can be applied to a high power specification such as a SiC element, which is useful for increasing the power of the power semiconductor module.

The schematic perspective view which shows the structure of the power semiconductor module concerning one Embodiment of this invention. The power semiconductor module of the said embodiment WHEREIN: The graph which shows the relationship between the area S per unit element, and the injection current amount per unit area to a unit element. In the power semiconductor module (one element) concerning the comparative example of the said embodiment, it is a figure which shows distribution of a temperature rise, Comprising: (A) is a schematic cross section of the module of the said comparative example, (B) is a temperature rise. The graph which shows distribution of. In the power semiconductor module of the above embodiment (divided into three unit elements), it is a diagram showing the distribution of temperature rise, (A) is a schematic cross-sectional view of the module of the above embodiment, (B) is a temperature rise A graph showing the distribution. FIG. 4 is a schematic perspective view of an analysis model in thermal fluid analysis for deriving a relational expression that determines the configuration of the power semiconductor module of the embodiment. FIG. 3 is a schematic partial cross-sectional view of an analysis model in the thermal fluid analysis. The table format figure which shows the design parameter and analysis experiment level in the said thermal fluid analysis. The table format figure which shows a part of result of the said thermal fluid analysis. It is a model perspective view of the power semiconductor module concerning the modification of the said embodiment, Comprising: The figure of the structure by which the unit element was arranged in the zigzag form. The graph which shows the relationship between resistance value Ron per unit area of a unit element, and the current density a in the Example which designs a module using the relational expression of the power semiconductor module of the said embodiment. The graph which shows the relationship between the area ratio r of a unit element and an insulating substrate, and the current density a in the Example which designs a module using the relational expression of the power semiconductor module of the said embodiment. The graph which shows the relationship between the area s per unit element, and the current density a in the Example which performs module design using the relational expression of the power semiconductor module of the said embodiment. The figure of a table format which shows the combination of the parameter determined by the Example of the said module design. In the said embodiment, the graph which shows the effect which can reduce the temperature rise of a weak heat resistant member by dividing | segmenting into a several unit element. In the said embodiment, the graph which shows the relationship between the distance from the center of a unit element, and board | substrate internal temperature. The schematic circuit diagram which shows the circuit example of the conventional power semiconductor element. The schematic circuit diagram which shows the circuit example of the power semiconductor element of the said embodiment. The schematic circuit diagram which shows the example of the circuit for AC motor drive comprised by the power semiconductor element of the said embodiment formation. In the said embodiment, the schematic cross section which shows the mounting form of the power semiconductor module by wire bonding. The model perspective view which shows the structure of the conventional power semiconductor module.

Explanation of symbols

1 power semiconductor module 10 analysis model 11 insulating substrate 11a electrode layer 11b substrate layer 11c aluminum layer 12 first bonding material 13 power semiconductor unit element 14 second bonding material 15 base plate 16 power semiconductor element group 17 silicon grease 18 cooling block 19 Silicon gel S1 Total area of power semiconductor unit element S2 Area of insulating substrate s Area per power semiconductor unit element N Number of parallel (divided) power semiconductor unit elements A Maximum amount of current input to power semiconductor module a Power Maximum current amount Ron input per unit area to semiconductor unit element Ron Electric resistance value ΔT of power semiconductor element Allowable temperature rise of weak heat resistant member r Area ratio of power semiconductor unit element to insulating substrate

Claims (5)

An insulating substrate;
A power semiconductor element group configured by electrically connecting a plurality of power semiconductor unit elements having the same shape bonded to one surface of the insulating substrate via a first bonding material in parallel;
A base member that is bonded to the other surface of the insulating substrate via a second bonding material and supports the insulating substrate;
A cooling block in which the base member is disposed via silicon grease,
Here, when the area of the power semiconductor unit element is an area in plan view when the power semiconductor unit element is disposed on one surface of the insulating substrate,
Maximum amount of current is charged per unit area of the power semiconductor unit devices a (A / cm ^2), the power resistance value per unit area of the semiconductor unit devices Ron (Ω · cm ^2), the power for the insulating substrate The area ratio r of the semiconductor unit elements, the allowable increase temperature ΔT (° C.) of the first bonding material, and the area s (cm ² ) per one power semiconductor unit element are in a range satisfying Formula 11. Each power semiconductor unit element is formed,
The total area S1 (cm ²⁾ of the plurality of power semiconductor unit devices, characterized in that the parallel number N of the respective power semiconductor unit elements, the power semiconductor element group so as to satisfy the equation 12 is constituted Power semiconductor module.
ΔT ≧ Ron · a ² (9.9s + 64.2r + 8.8) × 10 ⁻² (Equation 11)
N = S1 / s (Equation 12) ^2. The power semiconductor module according to claim 1, wherein the maximum amount of current input per unit area of each of the power semiconductor unit elements is 50 A / cm ² or more.   The power semiconductor module according to claim 1, wherein each of the power semiconductor unit elements is a SiC semiconductor element formed of SiC.   The power semiconductor module according to claim 1, wherein the first bonding material is formed of a lead-free solder material. On SL respective power semiconductor unit element is arranged in a staggered pattern on said one surface of the insulating substrate, in any one of claims 1-3 in which the power semiconductor element group is configured The power semiconductor module described.

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