JP5076088B2 - Sn plated copper substrate, manufacturing method of Sn plated copper substrate, lead frame and connector terminal using the same - Google Patents

Description

  The present invention relates to a Sn-plated copper substrate used for a semiconductor lead frame or a connector terminal of an electronic component, a method of manufacturing a Sn-plated copper substrate, and a lead frame and a connector terminal using the same.

  Usually, semiconductor lead frames and connector terminals of electronic devices are plated with Sn—Pb alloy in order to improve solderability. However, in recent years, Sn plating that does not use Pb is required due to environmental problems. .

  However, whisker made of Sn single crystal spontaneously occurs in a needle shape from the Sn plating surface. Whisker has a diameter of several μm, and a length of several μm to a long one can be several mm, which may cause a short circuit. Such whiskers are various, such as those that occur quickly within a few days after plating, and those that occur slowly within a few months after plating.

Although the whisker growth mechanism is not completely understood, it is said that when compressive stress is applied to the Sn plating layer, this acts as a driving force to induce movement and concentration of Sn atoms, and whisker grows.
Here, as the compressive stress applied to the Sn plating layer, plating residual compressive stress generated by plating, or an alloy phase of Sn and Cu (Cu ₃ Sn or Cu at the interface between the plating and the Cu substrate reacting with Cu of the substrate after plating) Compressive stress due to the formation of ₆ Sn ₅ ), compressive stress generated by bending after plating, and the like can be considered.

Therefore, one of the measures for preventing the occurrence of Sn whiskers is to prevent the Sn plating layer from being subjected to compressive stress.
As a method of reducing the compressive stress and preventing whisker generation, (1) reducing plating residual stress by examining plating conditions and plating methods; (2) Sn and Cu alloy phase at the interface between the substrate and the plating In order to prevent this, it is conceivable to perform base plating on a copper or copper alloy substrate, or (3) relieve residual stress by performing a heat treatment after Sn plating.

  As a method of (1), for example, as shown in Patent Document 1, there is a method of relaxing internal stress of Sn plating by performing pulse plating.

  As a method of (2), for example, as reported in Non-Patent Document 1, generation of compressive stress is suppressed by forming an alloy phase of Cu and Sn by performing base plating with Ni or Ag on a Cu substrate. Thus, it is described that the generation of whiskers can be suppressed.

  As a method of (3), for example, as shown in Patent Document 2, a Sn plating material is heat-treated in the range of 180 ° C. to a melting point temperature, or as shown in Patent Document 3, Sn—Cu alloy plating is performed. There is a method of performing a heat treatment at 227 ° C. or higher and 270 ° C. or lower for 15 minutes or less. In these methods, an alloy phase is rapidly formed at the interface between the substrate and the plating by heat treatment, but since it is in a heated state, the generated compressive stress is rapidly relieved, and once the alloy phase is formed, the alloy phase is formed. Since the diffusion rate of Sn and Cu in the phase becomes very slow, the growth of the alloy phase is suppressed when the temperature is returned to room temperature, and the generation of new compressive stress is suppressed. In addition, after the compression stress is relaxed by heating, a tensile stress is generated due to a difference in thermal expansion coefficient between Sn and Cu due to cooling after heating, so that the generation of whiskers is suppressed.

  In addition to the reduction of compressive stress, a method for preventing whisker generation by Sn alloy plating has been reported. For example, Patent Document 4 includes Sn—Bi alloy plating, Patent Document 5 includes Sn—Zn alloy plating, Patent Document 6 includes Sn—Cu alloy plating, and Patent Document 7 includes Sn—Ag alloy plating. Have been described.

  About Sn-Cu alloy plating, although the reason for suppression of whisker is not specified, it is described that Sn or Bi alloy plating or Sn-Zn alloy plating suppresses diffusion of Sn by Bi or Zn. Moreover, about Sn-Ag alloy plating, since the alloy phase of Ag is formed in a Sn plating layer, generation | occurrence | production of a whisker is suppressed.

JP 2003-129276 A JP-A-57-126992 JP 2003-193289 A JP 2004-169073 A JP 2003-253470 A JP 2000-87204 A JP 2002-220682 A Tin Whisker Formation-Results, Test Methods and Countermeasures, IEEE (2003), pp822-826

However, in the method described in Patent Document 1, even if the initial plating residual stress is reduced, Sn and the copper of the substrate gradually react after plating to form an alloy phase of Sn and copper at the interface. Since the compressive stress is generated by the whisker, there is a problem that whisker is generated.
In the method described in Non-Patent Document 1, whiskers are generated if there is residual compressive stress after plating. Therefore, for example, a combination with Patent Document 1 is required, but when processing is performed after plating, there is a problem that whiskers are generated because compressive stress is generated.

Further, the method described in Patent Document 2 has a problem that whisker is generated when external compressive stress is generated by processing.
And in the alloy plating of patent documents 4-7, since management of a plating bath composition is difficult, there exists a problem that it is difficult to form stably the plating layer suitable for suppression of generation | occurrence | production of a whisker. In addition, these alloy platings also have a problem that whiskers are generated when compressive stress is applied from the outside. Therefore, it is difficult to completely suppress the generation of whiskers even by these methods.

  The present invention has been made in view of the above-described problems, and can stably form a plating layer in which whisker is not easily generated even when an external stress such as bending is applied. An object of the present invention is to provide an Sn-plated copper substrate that does not contain Pb, has excellent solderability when used for a terminal, a method for manufacturing the Sn-plated copper substrate, and a lead frame and a connector terminal using the same. To do.

Whisker is said to grow by gathering Sn atoms at locations where whiskers are diffused from locations far from the whisker, as well as from locations far away from the whisker. In addition, when the present inventors observed a cross section at the root of the generated whisker, the core of the whisker is the Sn plating crystal grain of the Sn plating surface layer portion existing at a depth of about 1 μm from the Sn plating surface. I found out that it was growing. Therefore, in order to suppress the growth of whiskers, the present inventors at least Sn surface layer portion from the Sn plating surface to a depth of about 1 μm by Sn-Cu alloy phase or Cu plating layer that Sn hardly diffuses. It was considered that the generation of whiskers can be suppressed by dividing the crystal grains into a size smaller than the distance at which Sn atoms diffuse.
Under such an idea, the present inventors paid attention to the diffusion of Sn atoms, and as a result of intensive studies, formed an alloy phase or a metal layer in which the diffusion rate of Sn atoms is slowed during Sn plating to form Sn. It has been found that the generation of whiskers is suppressed by dividing the crystal grains, and the present invention has been completed.

[1] An Sn-plated copper substrate according to the present invention comprises an Sn-plated layer serving as an intermediate layer and a Cu-plated layer on any one of a pure copper plate, a copper alloy plate, and a copper-plated metal plate. The plating film layer formed in this order is provided with at least one film layer with a layer thickness of 1.5 μm or more, and becomes an outermost layer with a layer thickness of 0.2 μm or more and 1.5 μm or less on the plating film layer. The Sn plating layer is provided with a total thickness of 3 μm or more with the plating film layer, at least the grain boundary of each Sn plating layer serving as the intermediate layer and the outermost layer, the Sn plating layer serving as the outermost layer, and the Cu plating layer interface, and the intermediate layer become Sn plated layer and the Cu interface with the plating layer, the Cu plating layer and to diffuse the Cu derived from at least one of said metal substrate formed by Sn-Cu to any of the Has alloy phase It is characterized in that.
[2] In the Sn plated copper substrate of the present invention, Cu derived from at least one of the Cu plated layer and the metal substrate is diffused at the interface between the Sn plated layer as the intermediate layer and the metal substrate. It preferably has a Sn—Cu alloy phase.

  The Sn-plated copper substrate according to the present invention includes a Sn-plated layer and a Cu-plated layer having such a specific layer thickness, and further, Sn-Cu formed by Cu atoms diffusing into grain boundaries and grains of the Sn-plated layer. The alloy phase is formed at the Cu plating layer, the interface between the metal substrate and the Sn plating layer, and the grain boundary of the Sn plating layer. In particular, the Sn plating layer that is the outermost layer is an Sn-Cu alloy phase that continues from the lower Cu plating layer to the surface of the Sn plating layer that is the outermost layer within the grain boundaries and grains of the Sn plating layer that is the outermost layer. Therefore, the Sn plating layer as the outermost layer is divided at the crystal grain level. That is, by the Sn—Cu alloy phase, the Sn plating layer serving as the outermost layer including at least the crystal grains serving as the nuclei for whisker generation is formed in a direction parallel to and perpendicular to the Sn plating layer serving as the outermost layer. Since it is divided at the level, it is possible to make it difficult to collect Sn atoms, thereby suppressing the generation of whiskers.

  In addition, the Sn plated copper substrate according to the present invention includes a Sn plated layer and a Cu plated layer, and a thick Sn plated layer. Therefore, even if the surface layer of the plated film layer is scraped by bending or the like, the plated film The layer can remain. Therefore, even in such a case, solderability and corrosion resistance can be maintained. Moreover, since the layer thicknesses of the Sn plating layer and the Cu plating layer serving as the intermediate layer are appropriately adjusted, the Sn plating layer serving as the intermediate layer is also divided by the Sn-Cu alloy phase, so that the remaining plating film layer In addition, since the Sn plating layer remains divided in the Cu or Sn—Cu alloy phase, there is no possibility that whiskers are generated from the bent portion. Further, since the outermost layer is a Sn plating layer, the solderability is excellent.

[ 3 ] In the Sn-plated copper substrate of the present invention, at least one of the Cu plating layer and the Sn—Cu alloy phase is formed with a Kirkendall void formed by diffusion of the Cu. It is preferable that the average crystal grain size of the Sn plating layer, which is the outermost layer formed above, is 5 μm or less.
Thus, it becomes possible to more reliably divide the Sn plating layer by setting the average of the crystal grain size of the Sn plating layer formed above the Kirkendall void to a specific value or less. . Therefore, it is possible to make it difficult to collect Sn atoms, and it is possible to further suppress the generation of whiskers.

[ 4 ] In the Sn-plated copper substrate of the present invention, the Sn-plated copper substrate occupies a vertical cross-sectional area above a line formed by connecting the Kirkendall void formed in the Cu plating layer immediately below the Sn plating layer as the outermost layer. The cross-sectional area ratio of the Cu alloy phase and the Cu plating layer is preferably 30% or more and 90% or less.
Thus, if the Sn—Cu alloy phase and the Cu plating layer cross-sectional area ratio occupying the vertical cross-sectional area above the Kirkendall void are within a specific range, a sufficient amount of crystal grains of the Sn plating layer can be secured. Whisker generation can be suppressed while ensuring good solderability.

  In the Sn-plated copper substrate of the present invention, a Cu plating layer and Sn as a lower intermediate layer from a line connecting the Kirkendall voids formed in the Cu plating layer immediately below the Sn plating layer as the outermost layer. The total thickness of the plating layers is 2 μm or more, and the thickness of each Sn plating layer that is an intermediate layer is 0.5 μm or more and 3 μm or less, and is formed on the Cu plating layer immediately below the Sn plating layer that is the outermost layer The total thickness of the upper Cu plating layer and the outermost Sn plating layer from the line connecting the Kirkendall voids is preferably 0.2 μm or more and 1.5 μm or less.

  Thus, if the total thickness of the Cu plating layer and the Sn plating layer below the line connecting the Kirkendall voids is within the specific range described above, the Sn plating layer is sufficiently thick, so The fear that the entire plating film layer is scraped off by processing or the like can be eliminated. Moreover, if the thickness of each Sn plating layer that is an intermediate layer below the line connecting the Kirkendall voids is set to the specific range described above, the remaining Sn plating layer also depends on the Cu plating layer or the Sn—Cu alloy phase. Since it is divided at the crystal grain level in a direction parallel to and perpendicular to the Sn plating layer, it is possible to ensure solderability while preventing whisker generation. And if the layer thickness of each Sn plating layer used as an intermediate | middle layer above the line | wire which connects a Kirkendall void is made into the above-mentioned specific range, even if it carries out a bending process, it can make it difficult to expose a metal substrate.

[ 5 ] The method for producing an Sn-plated copper substrate according to the present invention includes an Sn plating layer serving as an intermediate layer and a Cu plating on a pure copper plate, a copper alloy plate, or a copper-plated metal plate. At least one film layer is laminated so that the layer thickness is 1.5 μm or more, and further, 0.2 μm or more and 1.5 μm or less is formed on the plating film layer. A lamination step of laminating an Sn plating layer that is an outermost layer of the layer thickness so that a total thickness of the plating film layer is 3 μm or more, and at least grain boundaries of each Sn plating layer that is the intermediate layer and the outermost layer the between the Sn-plated layer as the outermost layer the Cu plating layer interface, and between the intermediate layer and formed of the Sn plating layer and the Cu plated layer interface of the Cu plating layer and the metal substrate in any Derived from at least one By diffusing Cu is characterized by comprising an alloy phase forming step of forming a Sn-Cu alloy phase, a.

  The manufacturing method of the Sn-plated copper substrate according to the present invention is such that Cu atoms are diffused into the grain boundaries and grains of the Sn plating layer by laminating the Sn plating layer and the Cu plating layer with such a specific layer thickness. It becomes easy to do. In particular, the Sn plating layer that is the outermost layer is an Sn-Cu alloy phase that continues from the lower Cu plating layer to the surface of the Sn plating layer that is the outermost layer within the grain boundaries and grains of the Sn plating layer that is the outermost layer. Therefore, the Sn plating layer as the outermost layer is divided at the crystal grain level. In other words, the Sn plating layer which is the outermost layer including at least crystal grains serving as nuclei for whisker generation is divided at the crystal grain level in the direction parallel to and perpendicular to the Sn plating layer by the Sn—Cu alloy phase. , Sn atoms can be made difficult to collect, and thus whisker generation can be suppressed.

  Moreover, since the manufacturing method of the Sn plating copper substrate which concerns on this invention has laminated | stacked Sn plating layer and Cu plating layer and made Sn plating layer thick, even if the surface layer of a plating film layer is scraped off by bending etc. The plating film layer can remain. Therefore, even in such a case, solderability and corrosion resistance can be maintained. Moreover, since the layer thicknesses of the Sn plating layer and the Cu plating layer serving as the intermediate layer are appropriately adjusted, the Sn plating layer serving as the intermediate layer is also divided by the Sn-Cu alloy phase, so that the remaining plating film layer In addition, since the Sn plating layer remains divided in the Cu or Sn—Cu alloy phase, there is no possibility that whiskers are generated from the bent portion. Further, since the outermost layer is a Sn plating layer, the solderability is excellent.

[ 6 ] In the method for producing a Sn-plated copper substrate of the present invention, in the laminating step, the Cu plating layer formed immediately below the Sn plating layer as the outermost layer has a thickness of 0.05 μm to 1 μm. It is preferable to do this.
If the Cu plating layer formed immediately below the outermost Sn plating layer is provided with such a layer thickness, the grain boundary and the inside of the outermost Sn plating layer are sufficiently divided by the Sn-Cu alloy phase. Therefore, it is possible to suppress the generation of whiskers.

[ 7 ] In the manufacturing method of the Sn plated copper substrate of the present invention, in the stacking step, two or more plated film layers are stacked, and each Sn plated layer serving as the intermediate layer constituting the plated film layer is formed. It is preferable to laminate with a layer thickness of 0.5 μm to 3 μm.
If the Sn plating layer serving as the intermediate layer is laminated with such a layer thickness, the Sn plating layer is sufficiently thick. Therefore, the Sn plating layer serving as the outermost layer has been scraped off by bending. However, it is possible to make it difficult to expose the metal substrate. That is, good solderability can be maintained even in such a case. Further, when the Sn plating layer serving as the intermediate layer is laminated at this layer thickness, the Sn plating layer serving as the intermediate layer is also parallel to and perpendicular to the Sn plating layer by the Sn-Cu alloy phase and / or the Cu plating layer. Divided at the grain level. Therefore, even if the Sn plating layer which is the outermost layer is scraped off by bending, the remaining plating film layer is also divided into the Cu plating layer and the Sn-Cu alloy phase. Therefore, there is no possibility that whiskers are generated from the bent portion.

[ 8 ] In the method for producing a Sn-plated copper substrate of the present invention, in the stacking step, when two or more plated film layers are stacked, between the Sn plated layers serving as the intermediate layer and the intermediate layer The thickness of each Cu plating layer sandwiched between the Sn plating layer to be the outermost Sn plating layer and the Sn plating layer having any thicker thickness among the Sn plating layers sandwiching the Cu plating layer The layers are preferably laminated with a layer thickness of 1/10 to 1 μm.
When the Cu plating layer is provided with such a layer thickness, the amount of Cu atoms to be diffused from the Cu plating layer into the grain boundaries and grains of the Sn plating layer becomes appropriate. An Sn-Cu alloy phase that forms an Sn—Cu alloy phase in the boundaries and grains can also be divided at the crystal grain level, and good solderability can be ensured.

[9] In the method for producing a Sn-plated copper substrate according to the present invention, at least one of the Cu plating layer and the metal substrate is formed at the interface between the Sn plating layer serving as the intermediate layer and the metal substrate by the alloy phase forming step. It is preferable to form an Sn—Cu alloy phase formed by diffusing Cu originating from one side.
[ 10 ] In the method for producing a Sn-plated copper substrate of the present invention, it is preferable that a Kirkendall void formed by diffusion of Cu is formed in the Cu plating layer by the alloy phase forming step.
If the Kirkendall void is formed, Cu atoms are sufficiently and moderately diffused in the grains and grain boundaries of the Sn plating layer to form a Sn—Cu alloy phase. Therefore, it is possible to obtain an Sn-plated copper substrate in which the Sn plating layer can be surely divided in the in-plane direction and the thickness direction by the Sn—Cu alloy phase.

[ 11 ] The lead frame of the present invention is a lead frame using the Sn-plated copper substrate according to the present invention described above, wherein the Sn-plated copper substrate is formed in a strip shape, and a plurality of lead portions and A continuous bonding pad is formed by punching or etching.
In this way, since the Sn-plated copper substrate described above is used, it is possible to obtain a lead frame that hardly generates whiskers while ensuring good solderability.

[1 2 ] A lead frame according to the present invention is a lead frame in which a plurality of lead portions and a bonding pad continuous therewith are formed using the Sn plated copper substrate according to the present invention, and the Sn plated copper substrate The metal substrate used in is characterized in that the plurality of lead portions and the bonding pads are formed in advance.

  In this case, since the Sn plating is also applied to the punched end surface of the lead frame, the metal substrate is not exposed, and corrosion resistance and solderability can be ensured. Moreover, although the plating compression stress becomes high at the edge portion and the corner portion between the surface of the lead frame and the punched end surface, the lead frame of the present invention has a plating layer film and an Sn plating layer that is the outermost layer laminated thereon. And the Sn—Cu alloy phase is formed at the interfaces and grain boundaries of these layers, thereby dividing at the crystal grain level in the direction parallel to and perpendicular to the Sn plating layer as the outermost layer. , Whisker can be made difficult to occur.

[1 3 ] The lead frame of the present invention is characterized in that the lead portion is press-bended.
In this way, since the plating layer film and the outermost Sn plating layer are provided, it is possible to provide a lead frame that is less likely to generate whiskers while ensuring good solderability.

[1 4 ] The connector terminal of the present invention is a connector terminal using the Sn-plated copper substrate according to the present invention, and the Sn-plated copper substrate is formed into a thin plate and pressed into a predetermined shape. It is characterized by that.
In this way, since the Sn-plated copper substrate described above is used, it is possible to obtain a connector terminal that is less likely to generate whiskers while ensuring good solderability.

  According to the Sn-plated copper substrate of the present invention, whisker is generated even when an external stress such as bending is applied by forming a Sn plating layer and a Sn-Cu alloy phase that can include a Cu plating layer. It can be suppressed and has excellent solderability required when used for lead frames and connector terminals. Moreover, since this plating film layer does not contain Pb, there is little environmental load.

  According to the manufacturing method of the Sn-plated copper substrate of the present invention, it is possible to stably form a plating film layer that is less likely to generate whiskers even when an external stress such as bending is applied. It is possible to produce a Sn-plated copper substrate that does not contain Pb and has excellent solderability required when used in the above.

  According to the lead frame and connector terminal of the present invention, whisker is hardly generated even when an external stress such as bending is applied, so that the possibility of short-circuiting can be reduced and the solderability is excellent.

  Next, the Sn plated copper substrate, the method for producing the Sn plated copper substrate, the lead frame and the connector terminal using the same will be described in detail.

  First, the Sn plating copper substrate 1 which concerns on this invention is demonstrated with reference to FIG. 1 and FIG. 1 is a cross-sectional view illustrating a configuration example of the Sn-plated copper substrate of the present invention, and FIG. 2 is a cross-sectional view illustrating another configuration of the Sn-plated copper substrate of the present invention.

  As shown in FIG. 1 and FIG. 2, an Sn-plated copper substrate 1 according to the present invention is Sn as an intermediate layer on a metal substrate 2 of any one of a pure copper plate, a copper alloy plate, and a copper-plated metal plate. A plating film layer 5 formed by laminating a plating layer 3 (hereinafter referred to as “intermediate Sn plating layer 3IL”) and a Cu plating layer 4 in this order for the convenience of explanation is at least 1.5 μm thick. 1 film layer (that is, a layer composed of a set of intermediate Sn plating layer 3IL and Cu plating layer 4) or more and a thickness of 0.2 μm or more and 1.5 μm or less on this plating film layer 5 The outermost Sn plating layer 3 (hereinafter referred to as “outermost Sn plating layer 3OL” for convenience of explanation) and the plating film layer 5 have a total thickness (referred to as a total layer thickness) of 3 μm or more. It is prepared to become.

The Sn-plated copper substrate 1 includes at least the intermediate Sn plating layer 3IL and the grain boundary 3g of the outermost Sn plating layer 3OL, the interface 34o between the outermost Sn plating layer 3OL and the Cu plating layer 4, and the intermediate Sn plating. interface 34i of the layer 3IL and Cu plating layer 4, in any of a Sn-Cu alloy phase 6 obtained by diffusing the Cu atoms derived from at least one of Cu plating layer 4 and the metal substrate 2 and the Yes. In addition, it is preferable to have Sn—Cu alloy phase 6 formed by diffusing Cu derived from at least one of Cu plating layer 4 and metal substrate 2 at interface 32 between intermediate Sn plating layer 3IL and metal substrate 2.
Due to the Sn—Cu alloy phase 6, the outermost Sn plating layer 3OL effective for whisker generation is divided at the crystal grain level, and the movement and concentration of Sn atoms can be suppressed.

  Here, it is the outermost Sn plating that the plating film layer 5 formed by laminating the intermediate Sn plating layer 3IL and the Cu plating layer 4 in this order has at least one film layer with a layer thickness of 1.5 μm or more. Although there is a relationship with the layer 3OL, it is for preventing the metal substrate 2 from being exposed when it is bent or the like, and the solderability being deteriorated. The plating film layer 5 is more preferably 2 μm or more.

  On the other hand, when the intermediate Sn plating layer 3IL is thickened, depending on the thickness of the Cu plating layer 4, the Cu plating layer 4 or one of the intermediate Sn plating layers 3IL is sandwiched from the metal substrate 2 sandwiching the intermediate Sn plating layer 3IL. The grain boundary 3g of the intermediate Sn plating layer 3IL cannot be divided by the Sn—Cu alloy phase 6 continuing from the Cu plating layer 4 to the other Cu plating layer 4. When the bending process is not performed after Sn plating, or when the bending process is performed, the outermost Sn plating layer 3OL is not scraped off, or the outermost Sn plating layer 3OL is scraped off by the bending process. However, when the part scraped off by soldering is completely covered with solder, if only the outermost Sn plating layer 3OL is divided at the crystal grain level, the generation of whiskers can be suppressed. However, when the outermost Sn plating layer 3OL is scraped off by bending and the intermediate Sn plating layer 3IL is exposed, the whisker has to be separated if the intermediate Sn plating layer 3IL is not divided by the Sn—Cu alloy phase at the crystal grain level. May occur. In order to divide the intermediate Sn plating layer 3IL at the crystal grain level, the thickness of the intermediate Sn plating layer 3IL needs to be 0.5 μm or more and 3 μm or less. Further, the thickness of the Cu plating layer 4 at this time is 1/10 of the Sn plating layer 4 having a thicker thickness among the Sn plating layers 4 and 4 (see FIG. 2) sandwiching the Cu plating layer 4. It is good to set it as 1 micrometer or less.

  The outermost Sn plating layer 3OL is provided with a layer thickness in the range of 0.2 μm or more and 1.5 μm or less so that the total thickness with the plating film layer 5 is 3 μm or more. Good solderability This is because sufficient Cu atoms are diffused to obtain the desired effect of the present invention toward the grain boundary 3g and the grain interior 3c of the outermost Sn plating layer 3OL. Thereby, it is alloyed with Sn at the grain boundary 3g and the interface 34o of the outermost Sn plating layer 3OL to form the Sn-Cu alloy phase 6, and the outermost Sn plating layer 3OL can be divided at the crystal grain level. As a result, the movement and concentration of Sn atoms can be suppressed and the generation of whiskers can be prevented.

  When the outermost Sn plating layer 3OL is less than 0.2 μm, Cu atoms are excessively diffused to the surface of the outermost Sn plating layer 3OL, so that the formation ratio of the surface Sn—Cu alloy phase 6 becomes excessively high. End up. For this reason, the solderability is deteriorated. The outermost Sn plating layer 3OL is more preferably 0.3 μm or more, and further preferably 0.4 μm or more.

  On the other hand, if the outermost Sn plating layer 3OL exceeds 1.5 μm, Cu atoms hardly diffuse to the surface of the outermost Sn plating layer 3OL, so that the outermost Sn plating layer 3OL is sufficiently divided at the crystal grain level. Will not be able to occur, and whiskers are likely to occur. That is, if the outermost Sn plating layer 3OL cannot be sufficiently divided at the crystal grain level, the diffusion of Sn atoms is activated by the compressive stress induced when the Sn—Cu alloy phase 6 is formed. However, whiskers are more likely to occur. The outermost Sn plating layer 3OL is more preferably 1.2 μm or less, and further preferably 1 μm or less.

  As shown in FIG. 2, the intermediate Sn plating layer 3IL has a thickness of each intermediate Sn plating layer 3IL for the same reason as described above even when two or more plating film layers 5 are stacked. The layers are preferably laminated with a layer thickness of 0.5 μm or more and 3 μm or less.

  The total thickness of the intermediate Sn plating layer 3IL, the Cu plating layer 4 and the outermost Sn plating layer 3OL is set to 3 μm or more because all plating (intermediate Sn plating layer 3IL) is performed by bending or the like. , Cu plating layer 4 and outermost Sn plating layer 3OL) are prevented from being scraped off. The total thickness of the intermediate Sn plating layer 3IL, the Cu plating layer 4, and the outermost Sn plating layer 3OL is more preferably 5 μm or more.

  In the Sn-plated copper substrate 1 of the present invention, at least one of the Cu plating layer 4 and the Sn—Cu alloy phase 6 is formed with a Kirkendall void K formed by diffusion of Cu atoms. The average grain size of the outermost Sn plating layer 3OL formed above K is preferably 5 μm or less.

  Here, Kirkendall void K refers to a cavity formed in a metal layer that diffuses quickly when a diffusion pair in which metal layers of different types of diffusion coefficients are in contact with each other is formed. The Kirkendall void K is formed by appropriately controlling the layer thickness of the Sn plating layer 3 (intermediate Sn plating layer 3IL and outermost Sn plating layer 3OL) and the Cu plating layer 4, as will be described later. . Note that the Kirkendall void K is formed because Cu atoms in the Cu plating layer 4 are sufficiently diffused into the grain boundaries 3g and the intragranular 3c of the Sn plating layer 3 (particularly, the outermost Sn plating layer 3OL). This is because it is considered that the Sn—Cu alloy phase 6 is formed, and the generation of whiskers can be more reliably suppressed. The Kirkendall void K is preferably formed on all the Cu plating layers 4 when two or more Cu plating layers 4 are laminated. This is because each Sn plating layer 3 can be divided at the crystal grain level.

  Further, when the Kirkendall void K is formed, the position of the original Cu plating layer 4 is known from the position of the Kirkendall void K, and the outermost Sn plating layer 3OL and the intermediate Sn plating layer 3IL, Also, the approximate layer thickness of the intermediate Sn plating layer 3IL below this can be seen. That is, when a line connecting the Kirkendall voids K is drawn, the upper part is the outermost Sn plating layer 3OL or the intermediate Sn plating layer 3IL above it, and the lower part is the intermediate Sn plating below it. It can be said that it is layer 3IL. If Cu atoms are evenly diffused in the Sn plating layer 3 sandwiching the Cu plating layer 4 at the top and bottom, it is considered that the Kirkendall void K can be formed at the center of the original Cu plating layer 4. By subtracting half the thickness of the Cu plating layer 4 from the thickness of the outermost Sn plating layer 3OL above the void K, the layer thickness of the original Sn plating layer 3 can be obtained. The same applies to the thickness of the Sn plating layer 3 below the Kirkendall void K.

The average of the crystal grain size of the outermost Sn plating layer 3OL is, for example, the outermost Sn plating layer 3OL divided by the Sn—Cu alloy phase 6 using an image taken by a FIB (Focused Ion Beam) apparatus. For a plurality of (for example, seven) crystal grains, the length between the points where the boundary between the Sn—Cu alloy phase 6 and the outermost Sn plating layer 3OL and the line on the plating surface intersect is measured, and the average It can be obtained by calculating the value as the size of the crystal grain.
If the average grain size of the outermost Sn plating layer 3OL obtained in this way is larger than 5 μm, the outermost Sn plating layer 3OL is not sufficiently divided at the crystal grain level, so whiskers are generated. It becomes easy to do. The average of the crystal grain size of the outermost Sn plating layer 3OL is more preferably 3 μm or less.

  In addition, in the Sn plated copper substrate 1 of the present invention, Sn—Cu occupies a vertical cross-sectional area above the line formed by connecting the Kirkendall void K formed on the Cu plated layer 4 immediately below the outermost Sn plated layer 3OL. The cross-sectional area ratio of the alloy phase 6 and the Cu plating layer 4 is preferably 30% or more and 90% or less. Here, the line formed by connecting the Kirkendall void K means that the entire Kirkendall void K formed in the same Cu plating layer 4 is continuous in the plate width direction in the cross section in the plate thickness direction of the Sn plated copper substrate 1. A line that is assumed to be connected.

When the cross-sectional area ratio of the Sn—Cu alloy phase 6 and the Cu plating layer 4 occupying the longitudinal cross-sectional area above the Kirkendall void K exceeds 90%, the Sn—Cu alloy existing in the surface layer of the outermost Sn plating layer 3OL Since the formation ratio of the phase 6 is increased, the solderability is deteriorated.
On the other hand, when the cross-sectional area ratio of the Sn—Cu alloy phase 6 and the Cu plating layer 4 occupying the vertical cross-sectional area above the Kirkendall void K is less than 30%, the outermost Sn plating layer 3OL is sufficiently divided at the crystal grain level. Since this is not done, whiskers are likely to occur.

  In addition, the upper limit of the cross-sectional area ratio of the Sn—Cu alloy phase 6 and the Cu plating layer 4 in the vertical cross-sectional area above the Kirkendall void K is more preferably 80% or less, and 70% or less. Further preferred. Further, the lower limit of the cross-sectional area ratio of the Sn—Cu alloy phase 6 and the Cu plating layer 4 occupying the vertical cross-sectional area above the Kirkendall void K is more preferably 35% or more, and more preferably 40% or more. Further preferred.

  In the present invention, the total thickness of the lower Cu plating layer 4 and the intermediate Sn plating layer 3IL from the line connecting the Kirkendall voids K formed on the Cu plating layer 4 immediately below the outermost Sn plating layer 3OL. Is 2 μm or more, and the thickness of each Sn plating layer (each intermediate Sn plating layer 3IL) as an intermediate layer is 0.5 μm or more and 3 μm or less, and is formed on the Cu plating layer 4 immediately below the outermost Sn plating layer 3OL. It is preferable that the total thickness of the Cu plating layer 4 and the outermost Sn plating layer 3OL above the line formed by connecting the Kirkendall void K is 0.2 μm or more and 1.5 μm or less.

  When the total layer thickness of the lower Cu plating layer 4 and the intermediate Sn plating layer 3IL from the line formed by connecting the Kirkendall void K formed on the Cu plating layer 4 immediately below the outermost Sn plating layer 3OL is less than 2 μm, When bending is performed, the outermost Sn plating layer 3OL, the Cu plating layer 4 and the like are scraped off to expose the metal substrate 2, which may impair solderability and corrosion resistance. The total thickness of the Cu plating layer 4 and the Sn plating layer 3 below the line connecting the Kirkendall voids K formed on the Cu plating layer 4 immediately below the outermost Sn plating layer 3OL is 3 μm or more. More preferably, it is more preferably 5 μm or more.

  Further, the total thickness of the upper Cu plating layer 4 and the outermost Sn plating layer 3OL from the line connecting the Kirkendall void K formed on the Cu plating layer 4 immediately below the outermost Sn plating layer 3OL is 0.2 μm. If it is less than this, since the outermost Sn plating layer 3OL is almost entirely made of a Sn—Cu alloy, whisker is not generated but solderability is deteriorated. The total thickness of the Cu plating layer 4 and the outermost Sn plating layer 3OL above the line connecting the Kirkendall void K is more preferably 0.3 μm or more, and further preferably 0.4 μm or more. preferable.

  On the other hand, the total thickness of the upper Cu plating layer 4 and the outermost Sn plating layer 3OL from the line connecting the Kirkendall voids K formed on the Cu plating layer 4 immediately below the outermost Sn plating layer 3OL is 1.5 μm. When the Cu content exceeds 3, the ratio of reaching the surface decreases even if Cu atoms diffuse into the grain boundaries 3g and the intragranular 3c of the outermost Sn plating layer 3OL, and the outermost Sn plating layer 3OL cannot be sufficiently divided at the crystal grain level. Therefore, it becomes easy to generate whiskers. In addition, when the outermost Sn plating layer 3OL is not sufficiently divided at the crystal grain level, Sn atoms are diffused more actively by the compressive stress induced by the formation of the Sn—Cu alloy phase 6. However, whiskers are likely to occur. The total thickness of the Cu plating layer 4 and the outermost Sn plating layer 3OL above the line connecting the Kirkendall voids K formed on the Cu plating layer 4 immediately below the outermost Sn plating layer 3OL is 1.2 μm or less. More preferably, it is more preferably 1 μm or less.

Next, with reference to FIG. 3, the manufacturing method of the Sn plating copper substrate based on this invention is demonstrated. In addition, FIG. 3 is a figure which shows the flow of the manufacturing method of the Sn plating copper substrate of this invention.
As shown in FIG. 3, the manufacturing method of the Sn plating copper substrate which concerns on this invention comprises lamination | stacking process S1 and alloy phase formation process S2.

In addition, the critical significance that the layer thickness of the plating film layer 5 is 1.5 μm or more, the critical significance that the layer thickness of the outermost Sn plating layer 3OL is 0.2 μm or more and 1.5 μm or less, and 0.2 μm or more The reason why each layer thickness is defined in a specific range, such as the critical significance of setting the outermost Sn plating layer 3OL having a layer thickness of 1.5 μm or less to a total thickness of 3 μm or more with respect to the plating film layer 5, is as follows. Since it is as described in the description of the plated copper substrate, the description thereof is omitted.
Further, at least the significance of having the Sn—Cu alloy phase 6 at the grain boundary 3g and the interfaces 34i, 34o of the intermediate Sn plating layer 3IL and the outermost Sn plating layer 3OL, the Cu plating layer 4 and the Sn—Cu alloy The preferred embodiment of the Sn-plated copper substrate of the present invention, such as the point that it is preferable to form Kirkendall void K on at least one of the phases 6, the reason for doing so, etc. Therefore, the description thereof is omitted.

  When the Sn-plated copper substrate 1 is used for a lead frame or a connector terminal, these parts are often bent after the alloy phase forming step S2, so that if the plated film layer 5 is too thin, it is rubbed with the processing jig. The plated surface layer of the portion is scraped off to expose the metal substrate 2, and the solderability and corrosion resistance of that portion are significantly reduced. In order to prevent this, in the present invention, Cu is diffused and alloyed in the grain boundaries 3g of the Sn plating layer 3 and in the grains 3c of the Sn plating layer 3, and the grain boundaries 3g of the Sn plating layer 3 and the Cu plating are formed. The Sn plating layer 3 is divided at the crystal grain level at the interfaces 34o, 34i, 32 between the layer 4 and the metal substrate 2 and the Sn plating layer 3, thereby suppressing the movement and concentration of Sn atoms and preventing the generation of whiskers. I am trying. However, since the diffusion distance of Cu atoms to the grain boundary 3g is about 1 to 2 μm, in order to divide the Sn plating layer 3 by such a method, as described above, at least the outermost Sn plating layer 3OL. Since the Cu atoms cannot be diffused to the surface unless the layer thickness is 1 to 2 μm or less, the outermost Sn plating layer 3OL cannot be divided at the crystal grain level. That is, if the outermost Sn plating layer 3OL is too thick, Cu atoms cannot be sufficiently diffused, so that whisker generation cannot be prevented.

In the present invention, in consideration of this, the lamination step S1 is performed under the following conditions.
[Lamination process]
The lamination step S1 is a plating formed by laminating an intermediate Sn plating layer 3IL and a Cu plating layer 4 in this order on a metal substrate 2 which is a pure copper plate, a copper alloy plate, or a copper-plated metal plate. At least one film layer is laminated so that the film thickness 5 is 1.5 μm or more, and the outermost Sn plating layer 3OL having a layer thickness of 0.2 μm or more and 1.5 μm or less is further formed on the plating film layer 5. Are laminated so that the total thickness with the plating film layer 5 is 3 μm or more.
As a result, the Sn-plated copper substrate 1 ′ (see FIGS. 1 and 2) in a state before the outermost Sn plating layer 3 OL is divided by the Sn—Cu alloy phase 6 at the crystal grain level as described later is obtained. Can do.

  The thickness of the Sn plating layer 3 (intermediate Sn plating layer 3IL and outermost Sn plating layer 3OL) is such that Sn plating is performed on the metal substrate in advance for various times, and the Sn plating layer formed on the metal substrate is attached. The plating adhesion amount per unit area is obtained from the amount and the plating area, and by dividing the theoretical density of Sn by this value, the formation rate of the Sn plating layer is obtained, and a predetermined layer thickness is plated based on this formation rate. By determining the plating time necessary for this, the layer thickness of the Sn plating layer 3 can be controlled. The same applies to the control of the layer thickness of the Cu plating layer 4.

  In addition, in this lamination process S1, it is preferable to laminate | stack the layer thickness of Cu plating layer 4 formed directly under outermost Sn plating layer 3OL at 0.05 micrometer or more and 1 micrometer or less. When the Cu plating layer 4 immediately below the outermost Sn plating layer 3OL is laminated in such a range, Cu atoms can be appropriately diffused in the grain boundaries 3g and the inner grains 3c of the outermost Sn plating layer 3OL. Therefore, the outermost Sn plating layer 3OL can be divided at the crystal grain level.

  When the layer thickness of the Cu plating layer 4 formed immediately below the outermost Sn plating layer 3OL is less than 0.05 μm, the layer thickness is too thin, so that the grain boundary 3g and the intragranular 3c of the outermost Sn plating layer 3OL. Cu atoms diffused into the surface are insufficient, and the outermost Sn plating layer 3OL cannot be divided at the crystal grain level. Therefore, it becomes easy to generate whiskers. The layer thickness of the Cu plating layer 4 formed immediately below the outermost Sn plating layer 3OL is more preferably 0.1 μm or more.

  On the other hand, when the layer thickness of the Cu plating layer 4 formed immediately below the outermost Sn plating layer 3OL exceeds 1 μm, the layer thickness is too thick, so that the grain boundary 3g and the intragranular 3c of the outermost Sn plating layer 3OL Cu atoms diffuse too much. Therefore, many Sn—Cu alloy phases 6 are formed on the surface layer of the outermost Sn plating layer 3OL, and solderability is deteriorated. The layer thickness of the Cu plating layer 4 formed immediately below the outermost Sn plating layer 3OL is more preferably 0.6 μm or less.

  In this laminating step S1, it is preferable to laminate the intermediate Sn plating layer 3IL constituting the plating film layer 5 so that the layer thickness is not less than 0.5 μm and not more than 3 μm. The reason why the thickness of each intermediate Sn plating layer 3IL is within this range is that the intermediate Sn plating layer 3IL is divided at the crystal grain level by forming the Sn—Cu alloy phase 6 at the interface 34i and the grain boundary 3g, This is because the movement and concentration of Sn atoms can be suppressed. Thus, even if the Sn plating layer 3 on the surface is scraped off by bending or the like and the intermediate Sn plating layer 3IL is exposed on the surface, the exposed intermediate Sn plating layer 3IL is the Cu-Sn alloy phase 6 and the intermediate Sn plating layer Since 3IL is divided, there is no possibility that whiskers are generated from the bent portion.

If the thickness of the intermediate Sn plating layer 3IL is less than 0.5 μm, depending on the thickness of the Cu plating layer 4, the entire intermediate Sn plating layer 3IL becomes the Sn—Cu alloy phase 6 due to the diffusion of Cu atoms. There is a risk that. In such a state, if the surface is scraped off from the surface to the middle position of the intermediate Sn plating layer 3IL during bending, only the Sn—Cu alloy phase 6 is exposed to the surface, resulting in poor solderability. There is. The layer thickness of the intermediate Sn plating layer 3IL is more preferably 1 μm or more.
On the other hand, if the thickness of the intermediate Sn plating layer 3IL is larger than 3 μm, there is a possibility that the intermediate Sn plating layer 3IL cannot be sufficiently divided at the crystal grain level due to diffusion of Cu atoms. That is, when the intermediate Sn plating layer 3IL is scraped off from the surface to the middle position of the intermediate Sn plating layer 3IL during bending and the intermediate Sn plating layer 3IL is exposed, whiskers are likely to occur. The thickness of the intermediate Sn plating layer 3IL is more preferably 2.5 μm or less.

  In addition, in the stacking step S1, when the thickness of each intermediate Sn plating layer 3IL is stacked at 0.5 μm or more and 3 μm or less, between the intermediate Sn plating layer 3IL and between the intermediate Sn plating layer 3IL and the outermost Sn plating layer The thickness of each Cu plating layer 4 sandwiched between 3OLs is 1/10 or more of the intermediate Sn plating layer 3IL having a thicker thickness among the intermediate Sn plating layers 3IL sandwiching each Cu plating layer 4 It is preferable to laminate with a layer thickness of 1 μm or less.

  When the layer thickness of the Cu plating layer 4 is less than 1/10 of the thicker one of the intermediate Sn plating layers 3IL sandwiching the Cu plating layer 4, the amount of Cu atoms to diffuse is small. Cu atoms cannot sufficiently diffuse into the grain boundary 3g and the intragranular 3c of the intermediate Sn plating layer 3IL, and the intermediate Sn plating layer 3IL cannot be divided at the crystal grain level. The layer thickness of the Cu plating layer 4 is more preferably 1/5 or more of the thickness of the intermediate Sn plating layer 3IL having the thicker one of the intermediate Sn plating layers 3IL sandwiching the Cu plating layer 4. preferable.

  On the other hand, in this case, if the thickness of the Cu plating layer 4 sandwiched between the intermediate Sn plating layer 3IL exceeds 1 μm, the Sn—Cu alloy phase 6 is formed too much, so the solderability of the bent portion is increased. Decreases. The layer thickness of the Cu plating layer 4 is more preferably 0.8 μm or less.

[Alloy phase formation process]
Next, the alloy phase formation step S2 includes at least the grain boundary 3g of the intermediate Sn plating layer 3IL and the outermost Sn plating layer 3OL, the interface 34o between the outermost Sn plating layer 3OL and the Cu plating layer 4, and the intermediate Sn plating layer. interface 34i between 3IL and Cu plating layer 4, either by diffusing Cu atoms derived from at least one of Cu plating layer 4 and the metal substrate 2 to form an Sn-Cu alloy phase 6 of. Thereby, at least the outermost Sn plating layer 3OL is divided at the crystal grain level by the Sn—Cu alloy phase 6, and the Sn plated copper substrate 1 according to the present invention can be manufactured. In the alloy phase forming step S2, the Sn-Cu alloy phase 6 is formed by diffusing Cu derived from at least one of the Cu plating layer 4 and the metal substrate 2 into the interface 32 between the intermediate Sn plating layer 3IL and the metal substrate 2. Is preferably formed.

  Cu atoms diffuse through the Sn plating layer 3, particularly the grain boundary 3g, at high speed at room temperature. Although depending on the thickness of the Sn plating layer 3, Cu atoms diffuse through the grain boundaries 3 g in one day if the thickness of the Sn plating layer 3 is about 0.5 μm, for example. If the temperature condition of the alloy phase forming step S2 is increased, diffusion to the grain boundaries 3g is promoted, and the Sn—Cu alloy phase 6 is formed at an early stage.

  However, if the temperature condition in the alloy phase forming step S2 is too high, the grain boundary diffusion in the Sn plating layer 3 and the intragranular diffusion rate become equal, so the grain boundary 3g of the Sn plating layer 3 precedes the alloying. Therefore, the intragranular 3c of the Sn plating layer 3 is alloyed at the same speed as the grain boundary 3g. Therefore, the grain boundary 3g of the Sn plating layer 3 and the intragranular 3c of the Sn plating layer 3 become the Sn—Cu alloy phase 6 with a uniform thickness, and the Sn plating layer 3 is divided at the crystal grain level. Can not do it.

That is, as a result of the diffusion of Cu atoms into the grains 3c being promoted more than necessary, Cu atoms can diffuse to the surface of the Sn plating layer 3 when the amount of Cu atoms contributing to the diffusion is relatively small. Therefore, the occurrence of whiskers cannot be suppressed. On the other hand, when the amount of Cu atoms contributing to diffusion is relatively large, all of the Sn plating layer 3 becomes the Sn—Cu alloy phase 6 and solderability is deteriorated.
Therefore, the temperature condition of the alloy phase forming step S2 is preferably controlled to a temperature at which a difference in the diffusion rate of Cu atoms in the grain boundary 3g and the intragranular 3c of the Sn plating layer 3 occurs. For example, the temperature condition of the alloy phase forming step S2 is preferably 160 ° C. or less, more preferably 140 ° C. or less, and further preferably 130 ° C. or less.
Since the amount of Cu atoms contributing to diffusion is determined by the thickness of the Cu plating layer 4, the layer thickness of the Cu plating layer 4 is preferably controlled within the specific range described above.

  Further, it is preferable that a Kirkendall void K formed by diffusion of Cu atoms is formed in at least one of the Cu plating layer 4 and the Sn—Cu alloy phase 6 by the alloy phase forming step S2. The Kirkendall void K is formed in the Cu plating layer 4 subjected to the alloy phase forming step S1. In addition, when the layer thickness of the Cu plating layer 4 is thin or depending on the alloy phase formation temperature condition, the entire Cu plating layer 4 may become the Sn—Cu alloy phase 6. In this case, as a result, Kirkendall void K is naturally formed in the Sn—Cu alloy phase. When two or more Cu plating layers 4 are laminated, this can be formed on all the Cu plating layers 4.

  Kirkendall void K is formed by laminating the thicknesses of the Sn plating layer 3 (intermediate Sn plating layer 3IL and outermost Sn plating layer 3OL) and the Cu plating layer 4 in the above-described range in the above-described lamination step S1. It can form suitably. That is, by appropriately controlling the thicknesses of the Sn plating layer 3 and the Cu plating layer 4, Cu atoms of the Cu plating layer 4 can be appropriately diffused into the grain boundaries 3g and the intragranular 3c of the Sn plating layer 3. Therefore, Kirkendall void K can be formed.

  Next, the lead frame and connector terminal of the present invention will be described with reference to FIGS. FIG. 4 is a configuration diagram showing an example of the lead frame of the present invention. FIG. 5 is a partial cross-sectional view showing an example of the connector terminal of the present invention. FIG. 5 (a) is a view showing a state before the male terminal and the female terminal are fitted, and FIG. It is a figure which shows the state after fitting a terminal and a female terminal.

As shown in FIG. 4, the lead frame 100 of the present invention can be formed as a general lead frame having, for example, one or more bonding pads 101 and a plurality of lead portions 102 continuous therewith. .
In the lead frame 100, for example, the above-described Sn-plated copper substrate 1 is formed in a strip shape, and a plurality of lead portions 102 and bonding pads 101 are punched using a precision mold having a predetermined shape (stamping). It can be manufactured by forming by a process) or an etching process. Further, the metal substrate 2 used for the Sn-plated copper substrate 1 of the present invention described above is formed with the plurality of lead portions 102 and the bonding pads 101 described above in advance, and the plating layer film 5 and the outermost Sn plating. The layer 3OL and the Sn—Cu alloy phase 6 may be formed. In this case, since the end surface of the metal substrate 2 formed by punching or etching is also covered with the plating layer film 5, the outermost Sn plating layer 3OL, and the Sn-Cu alloy phase 6, the corrosion resistance of the metal substrate 2 and the solder at the end surface Adhesiveness is improved. Furthermore, in the edge portion and the corner portion formed by the surface of the metal substrate 2 and the corner portion, the residual compressive stress of plating is likely to occur, and whisker is likely to occur when only Sn plating is used as in the prior art. In the lead frame 100 having the Sn plating layer 3IL, the Cu plating layer 4, and the outermost Sn plating layer 3OL and further forming the Sn—Cu alloy phase 6, there is no such concern. Therefore, the lead frame 100 of the present invention may be subjected to press bending or the like as necessary to bend the lead portion 102.
The punching process, etching process, press bending process, and the like described above can be performed by a generally used technique.

Further, as shown in FIG. 5A, the connector terminal 200 of the present invention is a thin plate having an appropriate thickness, for example, having a predetermined shape, manufactured by rolling using the Sn-plated copper substrate 1 described above. By press bending using a die, the female terminal 210 and / or the male terminal 220 can be manufactured.
For example, as shown in FIG. 5A, the female terminal 210 is provided with a holding portion 213 having a bent portion 212 whose distance from at least a part of the facing wall portion 211 is reduced by press bending or the like. It is manufactured.
Further, for example, as shown in FIG. 5A, the male terminal 220 extends from the base end 221 to which the cord is connected by press bending or the like, and is fitted to the holding portion 213 of the female terminal 210 described above. It is manufactured to have a leading end 222.
As described above, even when the surface layer of the plating film layer 5 is scraped off by press bending or the like when the female terminal 210 or the male terminal 220 is manufactured, as already described in detail, the Sn of the present invention is used. Since the plated copper substrate 1 is used, the generation of whiskers can be suppressed.

Then, the female terminal 210 and the male terminal 220 are connected, for example, by inserting and fitting the front end portion 222 of the male terminal 220 into the holding portion 213 of the female terminal 210 as shown in FIG. can do.
At this time, even if the holding portion 213 and the tip portion 222 come into contact with each other and the surface layer of the plating film layer 5 is scraped off, the generation of whiskers can be suppressed because the Sn-plated copper substrate 1 of the present invention is used. .

  In the lead frame and connector terminal thus manufactured, the outermost Sn plating layer 3OL formed on the surface of the metal substrate 2 is divided at the crystal grain level in the plane direction and the layer thickness direction by the Sn—Cu alloy phase 6. Therefore, Sn atoms are unlikely to gather at a specific location, and whisker generation is prevented. Therefore, since it is hard to short-circuit, it can be used suitably for a semiconductor etc. Further, since the Sn plating layer 3 (outermost Sn plating layer 3OL) is formed on the surface of the metal substrate 2, it has good solderability.

Next, examples in which the effects of the present invention have been confirmed will be described.
[Example A]
Electrolytic degreasing agent Pakuna F made by Yuken Industry Co., Ltd., using the copper plates according to Examples 1 to 9 and Comparative Examples 1 to 5 (hereinafter simply referred to as “Examples 1 to 9 and Comparative Examples 1 to 5”, etc.) as cathodes. -1550 was immersed in an aqueous solution dissolved at 50 g / L, and electrolytic degreasing was performed under the following conditions.
[Electrolytic degreasing conditions]
Anode: Stainless steel Degreasing temperature: 50 ° C
Current density: 2 A / dm ²
Electrolysis time: 30 seconds

Examples 1-9 and Comparative Examples 1-5 were electrolytically degreased and washed with water, then immersed in a 10% by mass sulfuric acid aqueous solution for 15 seconds, washed again with water, and an Sn plating solution having the following composition made by Ishihara Pharmaceutical Co., Ltd. Using this, an Sn plating layer (hereinafter referred to as “intermediate Sn plating layer”) serving as an intermediate layer having a thickness of 5 μm was formed on the surface of the copper plate under the following conditions.
[Composition of Sn plating solution]
PF-TIN: 200mL / L
PF-ACID: 125 mL / L
PF-05M: 30mL
[Sn plating conditions]
Current density: 10 A / dm ²
Plating solution temperature: 35 ° C

  In addition, the thickness of the Sn plating layer is obtained by performing Sn plating on the copper plate in advance for various times, and obtaining the plating adhesion amount per unit area from the adhesion amount and the plating area of the Sn plating layer formed on the copper plate. The thickness of the Sn plating layer is determined by calculating the formation rate of the Sn plating layer by dividing the theoretical density of Sn by the above, and determining the plating time required to plate a predetermined layer thickness based on this formation rate. Was controlled.

Next, after washing Examples 1 to 9 and Comparative Examples 1 to 4 in which an intermediate Sn plating layer was formed, a Cu plating solution having the following composition (Kanto Chemical Co., Ltd. deer grade 1 reagent) was used, and the following: Under the conditions, a Cu plating layer having a layer thickness shown in Table 1 was formed. Note that the layer thickness of the Cu plating layer was controlled in the same manner as the control of the thickness of the Sn plating layer. In addition, about the copper plate which concerns on the comparative example 5, formation of the Cu plating layer and the Sn plating layer used as the outermost layer mentioned later (henceforth "outermost Sn plating layer") was not performed for the comparison.
[Composition of Cu plating solution]
CuCN: 47.5 g / L
KCN: 10.5g / L
K ₂ CO ₃ : 54.2 g / L
[Cu plating conditions]
Current density: 2 A / dm ²
Plating temperature: 55 ° C

  Finally, for Examples 1 to 9 and Comparative Examples 1 to 4 in which a Cu plating layer was formed, Sn plating solution having the same composition as above was used on the Cu plating layer, and Sn plating was performed under the same conditions as described above. An outermost Sn plating layer having a layer thickness shown in Table 1 was formed. Then, the Sn—Cu alloy phase was formed by leaving it to stand at room temperature (25 ° C.) for 24 hours.

  And using Examples 1-9 which changed various combinations of layer thickness of Cu plating layer, and layer thickness of outermost Sn plating layer, Comparative Examples 1-4, and Comparative Example 5 which formed only an intermediate Sn plating layer These longitudinal sections were observed with a FIB (Focused Ion Beam) apparatus.

  In the observation with the FIB apparatus, in order to protect the surface of the outermost Sn plating layer, a carbon protective film is formed on the surface with a layer thickness of about 2 μm, and then a sample (Example) is placed in the chamber of the FIB apparatus. 1 to 9 and Comparative Examples 1 to 5) were evacuated and then irradiated with gallium ions at an acceleration voltage of 30 kV, a beam diameter of 320 nm, and a beam current of about 3700 pA perpendicularly to the surface of the sample (carbon protective film surface). Then, the sample was cut in the layer thickness direction to obtain a cross-section of the plating, and the cross-section was finished by irradiating gallium ions with an acceleration voltage of 30 kV, a beam diameter of 92 nm, and a beam current of about 1400 pA in parallel with the cross-section. Later, when the cross section is irradiated with gallium ions having an acceleration voltage of 30 kV, a beam diameter of 7 nm, and a beam current of about 2 pA, the secondary emitted from the cross section Secondary electron image by child (SIM image) obtained was performed by observing this.

FIG. 6 shows a SIM image of Example 3 out of Examples 1 to 9 that satisfy the requirements of the present invention, which was taken by the FIB apparatus. The scale bar in FIG. 6 indicates 1 μm.
As shown in FIG. 6, in the SIM image of Example 3, an intermediate Sn plating layer is laminated on a copper plate that is a metal substrate, a Cu plating layer is laminated thereon, and an outermost Sn plating layer is further formed thereon. It can be seen that is formed.
The intermediate Sn plating layer and the outermost Sn plating layer have grain boundaries and intra-grain boundaries (that is, the boundary between the intermediate Sn plating layer and the outermost Sn plating layer, and the interface between the outermost Sn plating layer and the Cu plating layer). The Sn—Cu alloy phase is formed at the interface between the intermediate Sn plating layer and the Cu plating layer, and the interface between the intermediate Sn plating layer and the copper plate), and the Kirkendall void is also formed in the Cu plating layer. I understand.

Furthermore, from the SIM image of FIG. 6, the size of the crystal grains of the outermost Sn plating layer and the average thereof are also known. For example, the crystal grain size of the outermost Sn plating layer indicated by (a) (b) (c) (d) (e) (f) (g) in FIG. ) Is 1.3 μm, (c) is 0.4 μm, (d) is 3 μm, (e) is 0.5 μm, (f) is 0.9 μm, (g) is 3 μm, and the average is 1.4 μm. Met.
Further, the total thickness of the Cu plating layer and the intermediate Sn plating layer below the line formed by connecting the Kirkendall void formed on the Cu plating layer immediately below the outermost Sn plating layer is 5 to 7 μm, and The layer thickness of the intermediate Sn plating layer was 0.5 to 3 μm.

  As for Example 1, 2, and 4-9, as a result of observing a SIM image similarly to Example 3, as a result of dividing the crystal grain size of the outermost Sn plating layer and the Cu plating layer immediately below the outermost Sn plating layer, The cross-sectional area ratios of the Sn—Cu alloy phase and the Cu plating layer in the vertical cross-sectional area above the line formed by connecting the formed Kirkendall void were determined. The thickness of the intermediate Sn plating layer, the thickness of the Cu plating layer, and the thickness of the outermost Sn plating layer, as well as the crystal grain size of the outermost Sn plating layer and the longitudinal cross-sectional area ratio of the Sn-Cu alloy phase are shown. It is shown in 1. In Table 1, “-” indicates that the corresponding plating layer is not formed.

  Here, the layer thickness of the Sn plating layer above the line formed by connecting the Kirkendall void formed on the Cu plating layer immediately below the outermost Sn plating layer shown in Table 1 is the Sn plating predicted in advance from the plating adhesion amount. It almost coincided with the layer thickness.

  Subsequently, about Examples 1-9 and Comparative Examples 1-5, while evaluating solderability, the constant temperature and humidity test and the external stress test were done, and the presence or absence of whisker generation | occurrence | production was investigated.

  Solderability was evaluated by solder wettability evaluation by meniscograph method. In the meniscograph method, Examples 1 to 9 and Comparative Examples 1 to 5 were carried out at a speed of 10 mm / second perpendicular to the solder surface of Sn-3 mass% Ag-0.5 mass% Cu melted at 245 ° C. When inserted, the insertion speed was set to 0 when the tips of Examples 1 to 9 and Comparative Examples 1 to 5 were inserted from the liquid surface to a depth of 8 mm. After 5 seconds, Examples 1 to 9 and Comparative Examples 1 to 5 were soldered. Examples 1-9 and Comparative Examples 1-5 are inserted into the solder solution by measuring the change over time of the force from the solder solution applied to Examples 1-9 and Comparative Examples 1-5 in the meantime. The time until the force becomes zero for the first time (zero cross time (see FIG. 7)) is used to evaluate the solderability. In the present invention, if the zero cross time is within 2 seconds, it is determined that there is no problem in solderability (pass), and if the zero cross time exceeds 2 seconds, it is determined that there is a problem in solderability (fail). did. FIG. 7 is an explanatory view for schematically explaining the relationship between the immersion time in the solder solution by the meniscograph method and the wetting force.

Constant temperature and humidity test, the temperature 80 ° C., after exposure for 200 hours at a relative humidity of 85 RH% condition, the 0.04 mm ² to expand the surface of the outermost Sn plating layer 500-fold with a scanning electron microscope (SEM) The region was observed arbitrarily at five locations. Then, the number of whiskers generated was counted and totaled, and this value was multiplied by 5 to obtain the number of whiskers generated per mm ² .

  In the external stress test, an alumina ball having a diameter of 2 mm was pressed against the plating surface with a load of 60 N (600 g) for 240 hours, and then the area around the indentation was observed to examine the number of whiskers generated.

Solderability (zero cross time (seconds)) of Examples 1 to 9 and Comparative Examples 1 to 5, the number of whiskers generated after a constant temperature and humidity test (lines / mm ² ), and the number of whiskers generated after an external stress test ( This is shown in Table 2.

  As shown in Table 2, in Examples 1 to 9, the solderability (zero cross time) is all within 2 seconds, and the number of whiskers generated after the constant temperature and humidity test and the number of whiskers generated after the external stress test are also shown. It can be seen that it is significantly reduced as compared with Comparative Example 5.

  On the other hand, in Comparative Example 1, the outermost Sn plating layer could not be sufficiently divided because the Cu plating layer was too thin, so that the number of whiskers generated after the constant temperature and humidity test and the number of whiskers generated after the external stress test were large. became.

  In Comparative Example 2, since the Cu plating layer was too thick and most of the outermost Sn plating layer (92% of the Sn plating layer) became the Sn—Cu alloy phase, the zero cross time exceeded 2 seconds, The result was poor solderability.

  In Comparative Example 3, since the outermost Sn plating layer was too thick, Cu could not diffuse to the surface of the Sn plating layer. Therefore, the outermost Sn plating layer cannot be divided at the grain level, and the diffusion of Sn atoms is activated by the compressive stress induced by the formation of the Sn—Cu alloy phase, and whisker is generated after the constant temperature and humidity test. The number and number of whiskers generated after the external stress test were large.

  In Comparative Example 4, since the outermost Sn plating layer was too thin, all of the outermost Sn plating layer was (100%) Sn—Cu alloy phased, resulting in a zero cross time exceeding 2 seconds and poor solderability. It became.

  Since Comparative Example 5 was only the Sn plating layer, the number of whiskers generated after the constant temperature and humidity test and the number of whiskers generated after the external stress test were large.

  Next, the Example 3 and Comparative Example 5 were subjected to the constant temperature and humidity test described above, and then the surface was photographed with a scanning microscope (SEM) at a magnification of 500 times to obtain an SEM image. FIG. 8A shows an SEM image of the surface of Example 3 after the constant temperature and humidity test. Moreover, in FIG.8 (b), the SEM image of the surface of the comparative example 5 after a constant temperature and humidity test is shown. The dot 1 section shown in the lower right in FIGS. 8A and 8B indicates 10 μm (100 μm for 10 dots).

  Moreover, about Example 3 and the comparative example 5, after performing the above-mentioned external stress test, the surface was image | photographed by SEM at 500-times multiplication factor, and the SEM image was obtained. FIG. 9A shows a SEM image of the surface of Example 3 after the external stress test. FIG. 9B shows an SEM image of the surface of Comparative Example 5 after the external stress test. The dot 1 section shown in the lower right in FIGS. 9A and 9B shows 5 μm (50 μm in the 10 dot section).

  As shown in FIG. 8 (a) and FIG. 9 (a), whisker generation was not observed on the surface of Example 3 after the constant temperature and humidity test and after the external stress test. As shown in FIG. 9B, it can be seen that a plurality of whiskers are generated on the surface of Comparative Example 5 after the constant temperature and humidity test and after the external stress test.

[Example B]
Next, the copper plates according to Examples 10 to 17 and Comparative Examples 5 to 9 (hereinafter simply referred to as “Examples 10 to 17 and Comparative Examples 5 to 9”, etc.) were electrolyzed under the same conditions as [Example A]. After degreasing, the first layer (intermediate Sn plating layer) from the copper plate side, as shown in Table 3 below, depending on the Sn plating solution and Sn plating conditions described in [Example A] and the Cu plating solution and Cu plating conditions , Second layer (Cu plating layer), third layer (intermediate Sn plating layer or outermost Sn plating layer), fourth layer (Cu plating layer), fifth layer (outermost Sn plating layer), Examples 10 to 17 and Comparative Examples 6 to 9 having up to the third layer or up to the fifth layer were produced. In addition, Comparative Example 5 of [Example B] is the same as Comparative Example 5 of [Example A].
Here, the thickness of each plating layer is the same as in [Example A], and the formation rate of the Sn plating layer and the Cu plating layer is obtained, and it is necessary to form a predetermined layer thickness based on the formation rate. The plating time was determined and the thickness of each plating layer was controlled.

And the SIM image of the longitudinal section of Examples 10-17 and Comparative Examples 5-9 was image | photographed and observed with the FIB apparatus. The shooting conditions by the FIB apparatus are the same as those in [Example A].
The SIM image was observed, the layer thickness (μm) of each plating layer was measured, and the total layer thickness (μm) of each of Examples 10 to 17 and Comparative Examples 5 to 9 was measured. In Table 3, the layer thickness of each plating layer of Examples 10-17 and Comparative Examples 5-9, and a total layer thickness (micrometer) are shown. In Table 3, “-” indicates that the corresponding plating layer is not formed.

Next, for Examples 10 to 17 and Comparative Examples 5 to 9, solderability was evaluated, and a constant temperature and humidity test and an external stress test were performed to examine whether or not whisker was generated. The solderability evaluation, the constant temperature and humidity test, and the external stress test were performed under the same conditions as in [Example A]. Moreover, the cross section was observed using the SIM image of Examples 10-17 and Comparative Examples 5-9 together with this, and the condition of Sn plating layer was confirmed.
Evaluation of solderability (zero cross time (seconds)), number of whiskers generated after constant temperature and humidity test (lines / mm ² ), and number of whiskers generated after external stress test (lines) using SIM images It shows in Table 4 with the condition of the observed Sn plating layer.

  As shown in Table 4, in Examples 10 to 17, the solderability (zero cross time) is all within 2 seconds, and the number of whisker generation after the constant temperature and humidity test and the number of whisker generation after the external stress test are also comparative examples. It was found that the Sn plating layer was sufficiently divided at the crystal grain level.

  On the other hand, as described in [Example A], Comparative Example 5 had a single layer structure in which the Cu plating layer was not formed. Therefore, the Sn plating layer was not sufficiently divided at the crystal grain level, and the constant temperature was maintained. The number of whiskers generated after the constant humidity test and the number of whiskers generated after the external stress test were large.

  In Comparative Example 6, since the third layer (outermost Sn plating layer) was too thick, the third layer (outermost Sn plating layer) was insufficiently divided at the crystal grain level. Therefore, the number of whiskers generated after the constant temperature and humidity test and the number of whiskers generated after the external stress test were large.

  In Comparative Example 7, since the third layer (outermost Sn plating layer) was too thin, all of the third layer (outermost Sn plating layer) became Sn—Cu alloy phase. For this reason, the zero cross time exceeded 2 seconds, resulting in poor solderability.

  In Comparative Example 8, since the second layer (Cu plating layer) was too thick, most of the third layer (outermost Sn plating layer) was converted into a Sn—Cu alloy phase. For this reason, the zero cross time exceeded 2 seconds, resulting in poor solderability. In addition, since all the 1st layers (Sn plating layer) are alloyed, it is estimated that the solderability after bending etc. is also inferior.

  In Comparative Example 9, since the second layer (Cu plating layer) was too thin, the Sn—Cu alloy phase could not be sufficiently formed. For this reason, the third layer (outermost Sn plating layer) is not sufficiently divided at the crystal grain level. Therefore, the number of whiskers generated after the constant temperature and humidity test and the number of whiskers generated after the external stress test were large.

  Subsequently, after performing the above-described constant temperature and humidity test for Example 10, the surface was photographed with SEM at a magnification of 500 times to obtain an SEM image. FIG. 10A shows an SEM image of the surface of Example 9 after the constant temperature and humidity test. For comparison, FIG. 10B shows an SEM image of the surface of Comparative Example 5 after the constant temperature and humidity test described in [Example A]. The dot 1 section shown in the lower right in FIGS. 10A and 10B indicates 10 μm (the dot 10 section is 100 μm).

  Moreover, about Example 10, after performing the above-mentioned external stress test, the surface was image | photographed by SEM with 500-times multiplication factor, and the SEM image was obtained. FIG. 11A shows an SEM image of the surface of Example 9 after the external stress test. For comparison, FIG. 11B shows an SEM image of the surface of Comparative Example 5 after the external stress test described in [Example A]. The dot 1 section shown in the lower right in FIGS. 11A and 11B shows 5 μm (50 μm in the 10 dot section).

  As shown in FIGS. 10 (a) and 11 (a), no whisker was observed on the surface of Example 9 after the constant temperature and humidity test and after the external stress test.

  The Sn-plated copper substrate of the present invention, the method for producing the Sn-plated copper substrate, and the lead frame and connector terminal using the Sn-plated copper substrate have been specifically described according to the best mode for carrying out the invention. The gist is not limited to these descriptions, and should be broadly interpreted based on the claims. Needless to say, various changes and modifications based on these descriptions are also included in the spirit of the present invention.

It is sectional drawing which shows the structure of the Sn plating copper substrate of this invention. It is sectional drawing which illustrates the other structure of the Sn plating copper substrate of this invention. It is a figure which shows the flow of the manufacturing method of the Sn plating copper substrate of this invention. It is a block diagram which shows an example of the lead frame of this invention. BRIEF DESCRIPTION OF THE DRAWINGS It is a fragmentary sectional view which shows an example of the connector terminal of this invention, Comprising: (a) is a figure which shows the state before fitting a male terminal and a female terminal, (b) is a male terminal and a female terminal. It is a figure which shows the state after having fitted. 6 is a SIM image of Example 3. FIG. The scale bar in FIG. 6 indicates 1 μm. It is explanatory drawing which illustrates typically the relationship between the immersion time and the wetting force in the soldering liquid by the meniscograph method. (A) is the SEM image of the surface of Example 3 after a constant temperature and humidity test, (b) is the SEM image of the surface of the comparative example 5 after a constant temperature and humidity test. The dot 1 section shown in the lower right in FIGS. 8A and 8B indicates 10 μm (100 μm for 10 dots). (A) is the SEM image of the surface of Example 3 after an external stress test, (b) is the SEM image of the surface of the comparative example 5 after an external stress test. The dot 1 section shown in the lower right in FIGS. 9A and 9B shows 5 μm (50 μm in the 10 dot section). (A) is a SEM image of the surface of Example 10 after the constant temperature and humidity test, and (b) is a SEM image of the surface of Comparative Example 5 after the constant temperature and humidity test described in [Example A]. is there. The dot 1 section shown in the lower right in FIGS. 10A and 10B indicates 10 μm (the dot 10 section is 100 μm). (A) is the SEM image of the surface of Example 10 after an external stress test, (b) is the SEM image of the surface of the comparative example 5 after the external stress test demonstrated in [Example A]. The dot 1 section shown in the lower right in FIGS. 11A and 11B shows 5 μm (50 μm in the 10 dot section).

Explanation of symbols

1 Sn plated copper substrate 2 Metal substrate 3 Sn plated layer 3IL Intermediate Sn plated layer (Sn plated layer to be an intermediate layer)
3OL Outermost Sn plating layer (Sn plating layer to be outermost layer)
3g Grain boundary 3c Intragranular 32, 34i, 34o Interface 4 Cu plating layer 5 Plating film layer 6 Sn-Cu alloy phase S1 laminating step S2 alloy phase forming step

Claims (14)

On a metal substrate, either a pure copper plate, a copper alloy plate, or a copper-plated metal plate,
At least one film layer having a layer thickness of 1.5 μm or more is provided with an Sn plating layer as an intermediate layer and a Cu plating layer in this order. An Sn plating layer that is an outermost layer having a layer thickness of 2 μm or more and 1.5 μm or less is provided with a total thickness of 3 μm or more with the plating film layer,
At least a grain boundary of each of the Sn plating layers to be the intermediate layer and the outermost layer,
An interface between the Sn plating layer as the outermost layer and the Cu plating layer; and
An interface between the Sn plating layer serving as the intermediate layer and the Cu plating layer ;
A Sn-plated copper substrate having a Sn—Cu alloy phase formed by diffusing Cu derived from at least one of the Cu plating layer and the metal substrate.   The Sn-Cu alloy phase formed by diffusing Cu derived from at least one of the Cu plating layer and the metal substrate at an interface between the Sn plating layer serving as the intermediate layer and the metal substrate. Item 10. An Sn-plated copper substrate according to Item 1. At least one of the Cu plating layer and the Sn—Cu alloy phase is formed with a Kirkendall void formed by diffusion of Cu, and becomes the outermost layer formed above the Kirkendall void. The Sn-plated copper substrate according to claim 1 or 2 , wherein an average size of crystal grains of the Sn plating layer is 5 µm or less. Cross-sectional area ratio of the Sn-Cu alloy phase and the Cu plating layer in the vertical cross-sectional area above the line formed by connecting the Kirkendall void formed on the Cu plating layer immediately below the Sn plating layer as the outermost layer The Sn-plated copper substrate according to claim 3 , wherein is 30% or more and 90% or less. On a metal substrate, either a pure copper plate, a copper alloy plate, or a copper-plated metal plate,
At least one film layer is formed by laminating an Sn plating layer as an intermediate layer and a Cu plating layer in this order so that the layer thickness is 1.5 μm or more. And a lamination step of laminating an Sn plating layer, which is an outermost layer having a thickness of 0.2 μm or more and 1.5 μm or less, so that the total thickness with the plating film layer is 3 μm or more,
At least a grain boundary of each of the Sn plating layers to be the intermediate layer and the outermost layer,
An interface between the Sn plating layer as the outermost layer and the Cu plating layer; and
An interface between the Sn plating layer serving as the intermediate layer and the Cu plating layer ;
An alloy phase forming step by diffusing Cu to form a Sn-Cu alloy phase derived from at least one of the Cu plating layer and the metal substrate in any one of
The manufacturing method of Sn plating copper substrate characterized by including. In the lamination step,
The method for producing a Sn-plated copper substrate according to claim 5 , wherein a thickness of a Cu plating layer formed immediately below the Sn plating layer as the outermost layer is laminated to 0.05 µm or more and 1 µm or less. In the laminating step, when two or more film layers are laminated,
The Sn plated copper substrate according to claim 5 or 6 , wherein each of the Sn plated layers serving as the intermediate layer constituting the plated film layer is laminated with a layer thickness of 0.5 µm or more and 3 µm or less. Method. In the laminating step, when two or more film layers are laminated,
The thickness of each Cu plating layer sandwiched between the Sn plating layer as the intermediate layer and between the Sn plating layer as the intermediate layer and the Sn plating layer as the outermost layer is set to each Cu plating 8. The method for producing a Sn-plated copper substrate according to claim 7 , wherein the Sn-plated copper substrate is laminated with a thickness of 1/10 to 1 [mu] m of the Sn-plated layer having a thicker thickness among the Sn-plated layers sandwiching the layers.   By the alloy phase forming step, an Sn—Cu alloy phase formed by diffusing Cu derived from at least one of the Cu plating layer and the metal substrate at the interface between the Sn plating layer serving as the intermediate layer and the metal substrate. It forms, The manufacturing method of the Sn plating copper substrate of any one of Claims 5-8 characterized by the above-mentioned. By the alloy phase forming step, the at least one the of the Cu plating layer and the Sn-Cu alloy phase, claim from claim 5, characterized in that Kirkendall voids the Cu is diffused is formed 9 The manufacturing method of Sn plating copper substrate of any one of these. A lead frame using the Sn-plated copper substrate according to any one of claims 1 to 4 ,
A lead frame, wherein the Sn-plated copper substrate is formed in a strip shape, and a plurality of lead portions and a bonding pad continuous therewith are formed by punching or etching. A lead frame using the Sn-plated copper substrate according to any one of claims 1 to 4 , wherein a plurality of lead portions and a bonding pad continuous therewith are formed,
The lead frame in which the plurality of lead portions and the bonding pads are formed in advance on the metal substrate used for the Sn plated copper substrate. The lead frame of claim 11 or claim 1 2 wherein the lead portion is characterized in that it is bent press. A connector terminal using the Sn-plated copper substrate according to any one of claims 1 to 4 ,
A connector terminal, wherein the Sn-plated copper substrate is formed into a thin plate and pressed into a predetermined shape.