JP5074697B2 - Bridge, information processing apparatus and access control method - Google Patents

Description

  The present invention relates to a technology for accessing a processor unit from a peripheral device connected to the processor unit.

  Various peripheral devices are connected to the personal computer and the server via an IOIF (IO interface) or a bus such as a PCI (Peripheral Component Interconnect) bus to constitute an information processing system.

  In order to reduce the burden on the processor when accessing the memory of the processor from the peripheral device, it is conceivable to use a DMA (Direct Memory Access) architecture. This allows peripheral devices to directly access the processor's memory.

  However, the required access speed differs depending on the type of peripheral device. For example, a graphics card is required to be accessed faster than other peripheral devices. In order to realize efficient access, a device is required to control access from the peripheral device to the memory of the processor.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a technique capable of achieving good efficiency in accessing a memory of a processor from a peripheral device.

  One embodiment of the present invention is a bridge. This bridge connects a processor unit and peripheral devices, and has a downstream port and a relay unit.

  The downstream port is a virtual channel that is connected to the peripheral device and provided to the peripheral device, and the peripheral device uses any of the downstream channels to access the memory of the processor unit. Support.

  The relay unit is a plurality of virtual channels that are supported by the processor unit by the peripheral device to access the memory of the processor unit via the downstream port, and the memory bandwidth that can be used when accessing the memory for each channel is Relay to each assigned upstream channel.

  The relay unit has a table that stores the identifier of the downstream channel and the identifier of the upstream channel in association with each other, and refers to the table to determine the downstream channel used by the peripheral device according to the access from the peripheral device. Assign a corresponding upstream channel to the peripheral device.

  When the relay unit has a plurality of internal buses, the table includes a first table in which identifiers of downstream channels and internal buses are stored in association with each other, and identifiers of internal buses and upstream channels. You may make it comprise using the 2nd table memorize | stored by matching. In this case, the relay unit refers to the first table according to the access from the peripheral device, allocates an internal bus corresponding to the downstream channel used by the peripheral device to the peripheral device, and refers to the second table. Thus, an upstream channel corresponding to the internal bus assigned to the peripheral device is assigned to the peripheral device.

  Further, the second table stores the resource bandwidth inside the bridge, which is assigned to each internal bus, in association with the identifier of the internal bus, and the relay unit refers to the second table. The resource band used by the peripheral device that performs access may be further allocated.

  Another aspect of the present invention is an information processing apparatus. The information processing apparatus includes a processor unit, a peripheral device, and a bridge that connects the processor unit and the peripheral device.

  As the bridge, the bridge of the above-described aspect can be applied. The processor unit has an access control unit that relays an access to which any of the upstream channels is allocated by the bridge to the memory of the processor unit in a memory band allocated to the upstream channel.

  Note that any combination of the above-described constituent elements and the expression of the present invention replaced with each other between a method, an apparatus, a system, a computer program, a storage medium storing the computer program, etc. are also effective as an aspect of the present invention It is.

  The present invention can improve efficiency in accessing the memory of the processor unit from a peripheral device connected to the processor unit.

  Before describing the details of the embodiment of the present invention, first, the outline of the technique proposed by the present inventor will be described.

  Consider the information processing system shown in FIG. This information processing system has a processor unit 10 and a plurality of peripheral devices 30 as an example here, and the processor unit 10 and the peripheral devices 30 are connected by a bridge 20. The processor unit 10 may be a single processor system having a single processor or a multiprocessor system including a plurality of processors. The processor unit 10 includes a memory (not shown). In the case of a multiprocessor system, this memory is a shared memory accessible from each processor.

  FIG. 2 shows the bridge 20. The bridge 20 includes a downstream port 22 connected to the peripheral device 30, an upstream port 28 connected to the processor unit 10, and a relay unit 24. The downstream port 22 supports a plurality of virtual channels (hereinafter referred to as downstream VCs) 21 for the peripheral device 30 to access the memory of the processor unit 10, and the peripheral device 30 supports any one or a plurality of downstream VCs 21. Use to access.

  The peripheral device 30 issues an access request packet when accessing the memory of the processor unit 10. This access request packet can specify the address of the memory area to be accessed by the peripheral device 30 and includes the identifier of the downstream VC 21 used by the peripheral device 30. The upper part of FIG. 3 shows an example of an access request packet (hereinafter referred to as an input packet) issued by the peripheral device 30. The downstream VCID in the figure is an identifier of the downstream VC used by the peripheral device 30 that performs the access, and the address can indicate a predetermined position in the memory area of the access destination.

  The relay unit 24 converts the input packet received by the downstream port 22 into an output packet shown in the lower part of FIG. 3, and this output packet is output to the processor unit 10 by the upstream port 28.

  As shown in the lower part of FIG. 3, the output packet has an upstream VCID and an address. Here, the upstream VCID will be described.

  The upstream port 28 supports a plurality of virtual channels (hereinafter referred to as upstream VCs) 29 that can access the memory of the processor unit 10, and these upstream VCs 29 are also supported by the processor unit 10. The upstream VCID is an identifier of the upstream VC 29.

  Each upstream VC 29 is assigned a memory band to be used when accessing the memory of the processor unit 10. That is, the output packet output from the upstream port 28 can specify any upstream VC 29 by the upstream VCID included in the output packet, thereby specifying the memory bandwidth.

  Note that “the upstream VC 29 is assigned a memory bandwidth” means that the upstream VC 29 and the memory bandwidth need only have a predetermined correspondence relationship, and are assigned directly or indirectly. It is good to be. For example, when the IOIF connected to the upstream port 28 of the processor unit 10 supports a plurality of virtual channels to which memory bandwidths are respectively allocated, and the upstream VC 29 is allocated to a virtual channel supported by the IOIF, It can be said that the VC 29 is indirectly assigned a memory band.

  The relay unit 24 of the bridge 20 uses, for example, a table shown in FIG. 4 when converting an input packet specifying the downstream VC 21 into an output packet specifying the upstream VC 29. This table stores the identifier of the downstream VC 21 (downstream VCID) and the identifier of the upstream VC 29 (upstream VCID) in association with each other. The relay unit 24 refers to this table, converts the downstream VCID included in the input packet into an upstream VCID corresponding to the downstream VCID, and obtains an output packet.

  The processor unit 10 has an access control unit (not shown). The access control unit reads the upstream VCID included in the output packet, allocates a memory band corresponding to the designated upstream VC, and relays the access, thereby realizing reservation of the memory band for this access.

  Thus, according to this technique proposed by the present inventor, it is possible to control the memory bandwidth that can be used when accessing the memory of the processor unit 10 for each peripheral device 30. As a result, a memory band can be reserved according to the type of the peripheral device, and for example, a memory band for real-time data can be guaranteed.

  Further, the reservation of the memory bandwidth is directly performed by the cooperation of the bridge 20 and the access control unit of the processor unit 10 without using the CPU of the processor unit 10, so that overhead can be prevented.

  Next, consider the case where there are a plurality of internal buses (not shown) that carry data transfer from the downstream port 22 to the upstream port 28 in the bridge 20. In this case, the relay unit 24 of the bridge 20 can use the table shown in FIG.

  The table shown in FIG. 5 has a first table and a second table. The first table stores the downstream VCID and the internal bus identifier in association with each other. The second table stores an internal bus identifier and an upstream VCID in association with each other. The second table also stores resource ratios corresponding to internal bus identifiers and upstream VCIDs, details of which will be described later.

  The relay unit 24 of the bridge 20 first refers to the first table, obtains the identifier of the internal bus corresponding to the downstream VCID included in the input packet received from the peripheral device 30, and determines the internal bus indicated by this identifier. Assign to this access. At this time, the downstream VCID included in the input packet is converted into the identifier of the allocated internal bus. Hereinafter, this converted packet is referred to as an internal packet, and FIG. 6 shows it. In FIG. 6, the internal bus ID is an identifier of the internal bus.

  The internal packet shown in FIG. 6 is transferred to the upstream port 28 by the internal bus assigned thereto, that is, the internal bus indicated by the internal bus ID included in the internal packet. The relay unit 24 further converts the internal packet into an output packet before the internal packet is output from the upstream port 28. Specifically, referring to the second table shown in FIG. 5, the internal bus ID included in the internal packet is converted into an upstream VCID corresponding to the internal bus ID.

  In this way, an internal bus is assigned according to the downstream VC 21 and an upstream VC 29 is assigned according to the internal bus. Packet conversion or assignment is performed using two tables, and flexible setting is possible by combining the tables.

  Furthermore, the present inventor proposes that resources (not shown) such as buffers for temporarily storing commands, data, and the like can be set for each internal bus inside the bridge 20. Specifically, for example, as shown in the second table of FIG. 5, the ratio of resources allocated to the internal bus is set for each internal bus. Although the resource ratio is set for each internal bus here, the number of entries may be set.

  When the relay unit 24 converts the internal packet into the output packet with reference to the second table, the relay unit 24 also acquires the resource ratio corresponding to the internal bus ID included in the internal packet. As a result, the resources that can be used for each internal bus can be controlled, and as a result, the number of output packets that can be output for each internal bus can also be controlled.

  In the following, a system will be described by embodying the above outline of an embodiment of the present invention.

  FIG. 7 shows a configuration of an information processing system according to the embodiment of the present invention. The information processing system includes a plurality of peripheral devices, a multi-core processor 120, a main memory 180, and a bridge 110 that connects the PCI device 100 and the multi-core processor 120. The multi-core processor 120 and the main memory 180 constitute one processor unit. The plurality of peripheral devices include devices connected via the IOIF 104, the PCI device 100, and the like.

  A PCI bus is used as a connection interface of the PCI device 100. Here, the PCI bus may be based on any specification of PCI, PCIX, and PCI Express (registered trademark).

  The bridge 110 provides a plurality of virtual channels or downstream VCs with peripheral devices. The peripheral device issues an access request packet, that is, an input packet to the bridge 110 using any one or more downstream VCs.

  In addition, the IOIF 160 of the multi-core processor 120 provides a plurality of virtual channels, that is, upstream VCs, with the bridge 110. The bridge 110 converts the input packet from the peripheral device and then relays it to any upstream VC. The conversion of the input packet will be described later.

  Furthermore, the memory controller 170 of the multi-core processor 120 provides a plurality of virtual channels (hereinafter referred to as internal VCs) with the IOIF 160. A memory bandwidth for accessing the main memory 180 is assigned to each internal VC.

  The multi-core processor 120 is formed as a single chip, and includes a main processing unit PPE (Power Processing Element) 140, a plurality of, in the illustrated example, eight sub processing units SPE (Synergic Processing Element) 130, an IOIF 160, a memory controller, and the like. 170, which are connected by a ring bus 150.

  The main memory 180 is a shared memory for each processing unit of the multi-core processor 120 and is connected to the memory controller 170.

  The memory controller 170 controls access to the main memory 180. In the example shown in FIG. 7, the main memory 180 is provided outside the multi-core processor 120, but may be provided so as to be included in the multi-core processor 120.

  The IOIF 160 is connected to the bridge 110 via an IOEF bus (not shown), and allows the peripheral device to access the main memory 180 in cooperation with the bridge 110. The IOIF 160 includes an IO controller 164.

  The SPE 130 includes a core 132, a local memory 134, and a memory flow controller (hereinafter referred to as MFC) 136, and the MFC 136 includes a DMAC (Direct Memory Access Controller) 138. Note that the local memory 134 is preferably not a conventional hardware cache memory, and includes a hardware cache circuit, a cash register, a built-in chip or a chip outside the chip for realizing a hardware cache memory function. There is no cache memory controller.

  The PPE 140 includes a core 142, an L1 cache 144, an L2 cache 145, and an MFC 146. The MFC 146 includes a DMAC 148.

  Normally, the operating system (hereinafter also referred to as OS) of the multi-core processor 120 operates in the PPE 140, and a program that operates in each SPE 130 is determined based on the basic processing of the OS. The program operating on the SPE 130 may be a program (for example, a device driver or a part of a system program) that forms a part of the OS function. Note that the instruction set architectures of the PPE 140 and the SPE 130 have different instruction sets.

  When the information processing system shown in FIG. 7 is initialized, the PPE 140 of the multi-core processor 120 sets a conversion table (not shown) in the IOIF 160. FIG. 8 shows an example of this conversion table. In the figure, the upstream VCID is an identifier of a virtual channel (upstream VC) provided between the IOIF 160 and the bridge 110, and the internal VCID is an identifier of a virtual channel (internal VC) provided by the memory controller 170. The memory controller 170 relays access to the main memory 180 using the internal VC. At initialization, a memory band is also assigned to each internal VC.

  The peripheral device issues an access request packet when accessing the main memory 180. Here, the input packet shown in FIG. 3 is used as the access request packet. In this embodiment, the address included in the input packet is an effective address.

  The effective address is an address indicating a predetermined position in the effective address space of the main memory 180. The effective address space is a combination of a part of memory spaces partially cut out from the main memory 180. The multi-core processor 120 uses the effective memory space as work memory. By optimizing the internal structure of the effective memory space, the multi-core processor 120 can operate at maximum performance.

  FIG. 9 shows the configuration of the bridge 110. The bridge 110 includes a first input / output unit 112, a bridge controller 114, a plurality of (four in the illustrated example) internal bus 115, a buffer 116, and a second input / output unit 118.

  The first input / output unit 112 receives an input packet issued by a peripheral device via a downstream VC included in the input packet. The bridge controller 114 converts the input packet into an internal packet transferred on the internal bus 115, and converts the internal packet transferred through the internal bus 115 into an output packet passed to the second input / output unit 118. . Here, the formats shown in FIGS. 6 and 3 are used as the formats of the internal packet and the output packet, respectively.

  Note that the internal packet can be temporarily stored in the buffer 116 before being output by the second input / output unit 118. The second input / output unit 118 outputs the packet transferred by the internal bus 115 and converted by the bridge controller 114 to the IOIF 160 of the multi-core processor 120 via the upstream VC corresponding to the upstream VCID included in the packet. .

  The bridge controller 114 has two conversion tables (not shown), and uses these two conversion tables to convert input packets into internal packets and internal packets into output packets. Here, the table shown in FIG. 5 is used as the input packet and output packet conversion table. The “resource ratio” in the second table shown in FIG. 5 corresponds to the ratio of the buffer 116 here.

  The IO controller 164 of the IOIF 160 further outputs the output packet passed from the bridge 110 to the memory controller 170. Two conversions are performed on output. One is conversion of the upstream VCID included in the output packet into the corresponding internal VCID with reference to the table shown in FIG. The other is conversion of an effective address included in the output packet into a physical address in the main memory 180. A packet obtained by this conversion is hereinafter referred to as an IOIF command. FIG. 10 shows an IOIF command.

  The memory controller 170 relays access to the main memory 180 according to the passed IOIF command. Here, the memory controller 170 uses the table shown in FIG. 11 set at the time of system initialization. The table shown in FIG. 11 stores the identifier of the internal VC (internal VCID) and the memory bandwidth allocated to the internal VC indicated by the internal VCID in association with each other. The memory controller 170 refers to this table, relays access in the memory bandwidth corresponding to the internal VCID included in the IOIF command, and is indicated by the physical address included in this IOIF command in the main memory 180 as the access destination. Position.

  The present invention has been described based on the embodiments. The embodiments are exemplifications, and it will be understood by those skilled in the art that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are within the scope of the present invention. .

  For example, in the information processing system shown in FIG. 7, a peripheral device other than the PCI standard may be used for the PCI device 100 that is a peripheral device.

It is a figure which shows the information processing system used for description of the outline | summary of this invention. It is a figure which shows the bridge | bridging in the information processing system shown in FIG. It is a figure which shows an input packet and an output packet. It is a figure which shows the example (the 1) of the table for converting an input packet into an output packet. It is a figure which shows the example (the 2) of the table for converting an input packet into an output packet. FIG. 3 is a diagram showing an internal packet transferred on an internal bus of a bridge 20 It is a figure which shows the structure of the information processing system by embodiment concerning this invention. It is a figure which shows the example of the table for converting upstream VCID into internal VCID. It is a figure which shows the structural example of the bridge | bridging in the information processing system shown in FIG. It is a figure which shows the example of an IOIF command. It is the table which matched internal VCID and memory bandwidth.

Explanation of symbols

  10 processor units, 20 bridges, 21 downstream VCs, 22 downstream ports, 24 relay units, 28 upstream ports, 29 upstream VCs, 30 peripheral devices, 100 PCI devices, 102 IOIFs, 110 bridges, 112 first input / output units, 114 Bridge controller, 115 internal bus, 116 buffer, 118 second input / output unit, 120 multi-core processor, 130 SPE, 132 core, 134 local memory, 136 MFC, 138 DMAC, 140 PPE, 142 core, 144 L1 cache, 145 L2 Cache, 146 MFC, 148 DMAC, 150 ring bus, 160 IOIF, 164 IO controller, 170 memory controller, 18 Main memory.

Claims (3)

A bridge that connects a processor unit and peripheral devices,
A downstream port connected to the peripheral device;
The peripheral device can access the memory of the processor unit via the downstream port as a plurality of virtual channels supported by the processor unit, each channel being usable when accessing the memory of the processor unit A relay unit that relays to the upstream channel to which each memory bandwidth is allocated,
The downstream port is a virtual channel provided between the peripheral device and the peripheral device supports a plurality of downstream channels for performing the access using any of the peripheral ports,
The relay unit has a table storing the identifier of the downstream channel and the identifier of the upstream channel in association with each other,
Referring to the table, in response to the access from the peripheral device, an upstream channel corresponding to a downstream channel used by the peripheral device is assigned to the peripheral device;
The relay unit has a plurality of internal buses,
The table includes a first table storing downstream channel identifiers and internal bus identifiers in association with each other;
A second table storing the identifier of the internal bus and the identifier of the upstream channel in association with each other;
The relay unit refers to the first table according to the access from the peripheral device , acquires an identifier of the internal bus corresponding to the identifier of the downstream channel used by the peripheral device, and the acquired An internal bus is allocated to the peripheral device, and an internal packet is generated by converting the identifier of the downstream channel included in the input packet received from the peripheral device into the identifier of the allocated internal bus,
Referring to the second table, an identifier of the upstream channel corresponding to the identifier of the internal bus assigned to the peripheral device is obtained, the obtained upstream channel is assigned to the peripheral device, and the internal packet is assigned to the internal packet. Generate an output packet by converting the included internal bus identifier to the assigned upstream channel identifier,
The second table is further assigned to each internal bus, the available percentage of buffers for temporarily storing Oite the internal packet to the internal bridge, in association with the identifier of the internal bus Remember,
The relay unit refers to the second table , acquires a usable rate of a buffer corresponding to an identifier of an internal bus allocated to the peripheral device, and accesses the access according to the acquired usable rate And a buffer for temporarily storing the internal packet used by the peripheral device performing the processing . A processor unit;
Peripheral devices,
An information processing apparatus comprising the processor unit and a bridge connecting the peripheral devices,
The bridge includes a downstream port connected to the peripheral device;
The peripheral device can access the memory of the processor unit via the downstream port as a plurality of virtual channels supported by the processor unit, each channel being usable when accessing the memory of the processor unit A relay unit that relays to the upstream channel to which each memory bandwidth is allocated,
The downstream port is a virtual channel provided between the peripheral device and the peripheral device supports a plurality of downstream channels for performing the access using any of the peripheral ports,
The relay unit has a table storing the identifier of the downstream channel and the identifier of the upstream channel in association with each other,
Referring to the table, in response to the access from the peripheral device, an upstream channel corresponding to a downstream channel used by the peripheral device is assigned to the peripheral device;
The processor unit has an access control unit that relays the access to which any one of the upstream channels is allocated to the memory in a memory band allocated to the upstream channel,
The relay unit has a plurality of internal buses,
The table includes a first table storing downstream channel identifiers and internal bus identifiers in association with each other;
A second table storing the identifier of the internal bus and the identifier of the upstream channel in association with each other;
The relay unit refers to the first table according to the access from the peripheral device , acquires an identifier of the internal bus corresponding to the identifier of the downstream channel used by the peripheral device, and the acquired An internal bus is allocated to the peripheral device, and an internal packet is generated by converting the identifier of the downstream channel included in the input packet received from the peripheral device into the identifier of the allocated internal bus,
Referring to the second table, an identifier of the upstream channel corresponding to the identifier of the internal bus assigned to the peripheral device is obtained, the obtained upstream channel is assigned to the peripheral device, and the internal packet is assigned to the internal packet. Generate an output packet by converting the included internal bus identifier to the assigned upstream channel identifier,
The second table is further assigned to each internal bus, the available percentage of buffers for temporarily storing Oite the internal packet to the internal bridge, in association with the identifier of the internal bus Remember,
The relay unit refers to the second table , acquires a usable rate of a buffer corresponding to an identifier of an internal bus allocated to the peripheral device, and accesses the access according to the acquired usable rate An information processing apparatus further comprising a buffer for temporarily storing the internal packet used by a peripheral device that performs the processing. An access control method using a bridge for connecting a processor unit and a peripheral device,
A virtual channel provided between the bridge and the peripheral device, via any of a plurality of downstream channels for utilizing the peripheral device to access the memory of the processor unit. Receiving the access from a peripheral device;
Relaying the access to an upstream channel, which is a plurality of virtual channels supported by the processor unit, each of which is assigned a memory bandwidth usable when accessing the memory of the processor unit. Have
The relaying step refers to a table in which the identifier of the downstream channel and the identifier of the upstream channel are associated with each other and stores the downstream channel used by the peripheral device according to the access from the peripheral device. Assigning a corresponding upstream channel to the peripheral device,
The bridge has a plurality of internal buses,
The table includes a first table storing downstream channel identifiers and internal bus identifiers in association with each other;
A second table storing the identifier of the internal bus and the identifier of the upstream channel in association with each other;
The relaying step refers to the first table according to the access from the peripheral device , acquires an internal bus identifier corresponding to an identifier of a downstream channel used by the peripheral device, and acquires the internal bus identifier. Assigning the assigned internal bus to the peripheral device, and generating an internal packet in which the identifier of the downstream channel included in the input packet received from the peripheral device is converted into the identifier of the assigned internal bus,
Referring to the second table, an identifier of the upstream channel corresponding to the identifier of the internal bus assigned to the peripheral device is obtained, the obtained upstream channel is assigned to the peripheral device, and the internal packet is assigned to the internal packet. Generate an output packet by converting the included internal bus identifier to the assigned upstream channel identifier,
The second table is further assigned to each internal bus, the available percentage of buffers for temporarily storing Oite the internal packet to the internal bridge, in association with the identifier of the internal bus Remember,
The relaying step refers to the second table , obtains an available rate of the buffer corresponding to the identifier of the internal bus assigned to the peripheral device, and according to the obtained available rate An access control method, further comprising allocating a buffer for temporarily storing the internal packet used by the peripheral device performing the access.

Images