CN101178697B - PCIE apparatus satellite communication method and system - Google Patents
PCIE apparatus satellite communication method and system Download PDFInfo
- Publication number
- CN101178697B CN101178697B CN200710195702XA CN200710195702A CN101178697B CN 101178697 B CN101178697 B CN 101178697B CN 200710195702X A CN200710195702X A CN 200710195702XA CN 200710195702 A CN200710195702 A CN 200710195702A CN 101178697 B CN101178697 B CN 101178697B
- Authority
- CN
- China
- Prior art keywords
- pcie
- equipment
- address
- bridge
- cpu
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Abstract
The invention discloses a communication method. The method is used in a system comprising a low order CPU and two PCIE devices which claim for a high order address space. The method comprises the steps that: the operation system of the low order CPU is started; the high order address spaces of the two PCIE devices are modified; and the address of a PCIE bridge corresponding to the two PCIE devices is modified, so that the PCIE devices which claim for a high order address space can transmit data through the PCIE bridge. The invention discloses a communication system for the PCIE device. In the embodiment of the invention, the devices which claim for a super large address space (exceeding 4G) can be visited from one to another during a computer system with a 32-bit architecture; and the CPU can visit a device with a super large address space (exceeding 4G) through a read-write agent during a computer system with a 32-bit architecture.
Description
Technical field
The present invention relates to communication technical field, relate in particular to a kind of PCIE devices communicating method and system.
Background technology
PCI Express is high-performance I/O of new generation (Input/Output, an I/O) interconnection technique, is called for short PCIE, is widely used in computer platform as the local I/O bus of standard.PCIE has high-performance, simplifies I/O, advantages such as hierarchy type framework.
Fig. 1 is the exemplary topology diagram of PCIE bus.PCIE is the shared architecture for exchanging of a kind of Point-to-Point (point-to-point), and each equipment (Endpoint) has the PCIE bus of oneself, directly links switch (switching equipment), sets up the Point-to-Point communication modes.
The device addressing pattern has kept the compatibility with the PCI addressing mode, i.e. loading-storage architecture and have the individual layer address space, each equipment keeps one section PCIE space, be used for CPU (Central Process Unit, CPU (central processing unit)) and between the equipment visit mutually, the internal memory of PCIE space and computer system adopts the addressing of unified address, supports 64 bit address space, improves the convenience of access means greatly.
In the prior art, CPU is the computer system of 32 bit architectures, in the computer system starting process, BIOS is responsible for the address space according to the corresponding size of demand assignment of equipment, the computer system of 32 bit architectures can only be the address space of 32 of devices allocation, and PCIE equipment can only be applied for 32 address space, and promptly Zui Da address space is 4G, take space, a part of address if consider computer system memory, the maximum space that PCIE equipment can access will be littler than 4G.Because PCIE supports 64 bit address space, if some PCIE equipment need apply for surpassing the address space of 4G, this PCIE equipment in the computer system of 32 bit architectures with cisco unity malfunction.
Summary of the invention
The invention provides a kind of PCIE devices communicating method and system, making needs the PCIE equipment in application space, high address can operate in the computer system of low bit architecture.
The invention provides a kind of PCIE devices communicating method, be applied to comprise in the system of the PCIE equipment that hangs down bit CPU and two application spaces, high address, said method comprising the steps of:
Start the operating system of low bit CPU;
After described os starting is finished, described two PCIE device addresses are modified as high-order address space;
Revise the PCIE bridge address of two PCIE equipment correspondences, so that the PCIE equipment in space, described application high address can carry out data forwarding by the PCIE bridge.
Wherein, described two PCIE equipment carry out data forwarding by the PCIE bridge and are specially:
The one PCIE equipment is initiated write operation, and the destination address of packet is high-order address space, and packet is from a PCIE device forwards to a PCIE bridge; The destination address that a described PCIE bridge detects described packet belongs to the 2nd PCIE bridge, and a described PCIE bridge is transmitted to described the 2nd PCIE bridge with described packet; Described the 2nd PCIE bridge sends to the 2nd PCIE equipment with described packet;
And/or the one PCIE equipment initiate read request, the request of packet is read the address and is high-order address space, packet is from a PCIE device forwards to a PCIE bridge; The request that a described PCIE bridge detects described packet is read the address and is belonged to the 2nd PCIE bridge, and a described PCIE bridge is transmitted to described the 2nd PCIE bridge with described packet.
Wherein, describedly after being modified as high-order address space, described two PCIE device addresses comprise that also a PCIE proxy for equipment CPU operates the 2nd PCIE equipment.
Wherein, comprise that specifically a described PCIE proxy for equipment CPU reads described the 2nd PCIE equipment:
CPU constructs protocol package, comprising: will read the start address of the 2nd PCIE device content, and preserve the CPU internal memory start address of reading of data;
CPU writes interactive space with protocol package;
A described PCIE equipment finds to have new read request in the mode of timing scan interactive space, interruption or mailbox;
A described PCIE equipment is read content from described the 2nd PCIE equipment, and content is write in the corresponding internal memory of CPU; And/or
The one PCIE proxy for equipment CPU writes described the 2nd PCIE equipment:
CPU constructs protocol package, comprises CPU internal memory start address, and content will be for will write the data of the 2nd PCIE equipment and the address of the 2nd PCIE equipment;
CPU is written in the interactive space;
The one PCIE equipment timing scan interactive space, finding has new write request agency;
The one PCIE equipment is responsible for reading content from the internal memory of CPU, and content is write the address of described the 2nd PCIE equipment.
Wherein, described low bit CPU is 32 bit CPUs; Space, described high address is 64 bit address space.
The present invention also provides a kind of computer system, comprises the PCIE equipment in low bit CPU and two application spaces, high address, also comprises: two PCIE bridges with high address space corresponding with above-mentioned PCIE equipment;
Described low bit CPU is used to start the operating system of hanging down bit CPU,
Described PCIE equipment has high-order address space, comprises PCIE equipment and the 2nd PCIE equipment;
Described PCIE equipment carries out data forwarding by the PCIE bridge:
The one PCIE equipment has the data forwarding function, be used to initiate write operation, wherein the destination address of packet is high-order address space, packet is from a PCIE device forwards to a PCIE bridge, the destination address that a wherein said PCIE bridge detects described packet belongs to the 2nd PCIE bridge, and a described PCIE bridge is transmitted to described the 2nd PCIE bridge with described packet; Described the 2nd PCIE bridge sends to described the 2nd PCIE equipment with described packet; And/or be used to initiate read request, the request of packet is read the address and is high-order address space, packet is from a PCIE device forwards to a PCIE bridge, the request that a wherein said PCIE bridge detects described packet is read the address and is belonged to the 2nd PCIE bridge, and a described PCIE bridge is transmitted to described the 2nd PCIE bridge with described packet.
Wherein, a described PCIE equipment has the read operation of agency function, is used for the mode with timing scan interactive space, interruption or mailbox, when finding new read request is arranged, reads content from described the 2nd PCIE equipment, and content is write in the corresponding internal memory of CPU; And/or be used for the timing scan interactive space, when finding to have new write request to act on behalf of, read content from the internal memory of CPU, and content is write the address of described the 2nd PCIE equipment.
Wherein, described low bit CPU is 32 bit CPUs; Space, described high address is 64 bit address space.
The present invention also provides a kind of computer system, and comprise low bit CPU and have space, high address first and second bus apparatus,
Described low bit CPU is used to start the operating system; Described first and second bus apparatus are used for carrying out data forwarding between the two by bus bridge, and wherein first bus apparatus is acted on behalf of communicating by letter between described low bit CPU and described second bus apparatus.
Wherein, described bus is PCIE, and the PCIE bridge comprises the first and second PCIE bridges, and the described first and second PCIE equipment communicate by the first and second PCIE bridges:
The one PCIE equipment has the data forwarding function, be used to initiate write operation, wherein the destination address of packet is high-order address space, packet is from a PCIE device forwards to a PCIE bridge, the destination address that a wherein said PCIE bridge detects described packet belongs to the 2nd PCIE bridge, and a described PCIE bridge is transmitted to described the 2nd PCIE bridge with described packet; Described the 2nd PCIE bridge sends to described the 2nd PCIE equipment with described packet; And/or be used to initiate read request, the request of packet is read the address and is high-order address space, packet is from a PCIE device forwards to a PCIE bridge, the request that a wherein said PCIE bridge detects described packet is read the address and is belonged to the 2nd PCIE bridge, and a described PCIE bridge is transmitted to described the 2nd PCIE bridge with described packet.
Wherein, a described PCIE equipment is used for the mode with timing scan interactive space, interruption or mailbox, when finding new read request is arranged, reads content from described the 2nd PCIE equipment, and content is write in the corresponding internal memory of CPU; And/or be used for the timing scan interactive space, when finding to have new write request to act on behalf of, read content from the internal memory of CPU, and content is write the address of described the 2nd PCIE equipment.
In the embodiments of the invention, in the computer system of low level (for example 32) architecture, can allow the high-order address space of application (for example surpassing 4G) equipment visit mutually; And in the computer system of low bit architecture, by the read-write agency, CPU can visit high-order address space (surpassing 4G) equipment.
Description of drawings
Fig. 1 is the topological diagram of PCIE bus in the prior art;
Fig. 2 is a kind of PCIE devices communicating method flow diagram among the present invention;
Fig. 3 is the computer system topological diagram of 32 bit architectures among the present invention;
Fig. 4 redistributes synoptic diagram behind 64 the address space for PCIE equipment among the present invention;
Fig. 5 is the forwarding process figure of packet between the PCIE equipment among the present invention;
Fig. 6 is the address contents synoptic diagram of revising in the PCIE proxy for equipment scheme among the present invention.
Embodiment
The invention provides a kind of PCIE devices communicating method, be applied to comprise low bit CPU and support that this method specifically may further comprise the steps as shown in Figure 2 in the system of space, high address PCIE equipment:
Step s201 starts the operating system of hanging down bit CPU.This operating system is example with the computer system of 32 bit architectures, topology as shown in Figure 3, computer system has the 2G internal memory, the address is 0x00000000～0x8,000 0000, Root Complex (root) hangs PCIE bridge A and other PCIE bridges down, and PCIE bridge A hangs PCIE device A and PCIE equipment B down.
In the system starting process, BIOS is according to the address space of the corresponding size of demand assignment of equipment, and the address space of PCI allocation E device A is 0xF,100 0000～0xF,200 0000; The address space of PCIE equipment B is 0xF,200 0000～0xF,300 0000.Address Routing Protocol according to PCIE, the address realm of PCIE bridge A must cover the address space range of PCIE device A and PCIE equipment B, be 0xF0000000～0xF,300 0000, like this, PCIE bridge A is transmitted to PCIE device A or PCIE equipment B downwards with PCIE packet (destination address of this packet belongs to the scope of 0xF,000 0000～0xF,300 0000).
Step s202 after os starting is finished, by the method for software modification, becomes high-order address space with described two PCIE device addresses, redistributes the address space (for example 64) of a high position for PCIE equipment; And the PCIE bridge address of revising two PCIE equipment correspondences, so that the PCIE equipment in space, described application high address can carry out data forwarding by the PCIE bridge.Address contents such as Fig. 4 of revising: the address space of revising the PCIE device A is 0x4 0,000 0000～0x5 0,000 0000, the address space of PCIE equipment B is that the address space of 0x5 0,000 0000～0x6,0,000 0000, PCIE device A and PCIE equipment B respectively has 4G.According to the address Routing Protocol, the address space of revising PCIE bridge B is that the address space of 0x4 0,000 0000～0x5 0,000 0000, PCIE bridge C is 0x5 00000000～0x6 0,000 0000.
In the one embodiment of the invention, above-mentioned redistributing for PCIE equipment after one 64 the address space, PCIE equipment has big address space, can visit mutually between the PCIE equipment.The forwarding process of describing packet between the PCIE equipment in detail with example may further comprise the steps as shown in Figure 5:
Step s501, the PCIE device A is initiated write operation, and the destination address of packet is 0x5 1,000 0000, and packet is forwarded to PCIE bridge B from the PCIE device A.
Step s502, PCIE bridge B find that the destination address of packet belongs to PCIE bridge C, and PCIE bridge B is transmitted to PCIE bridge C with packet.
Step s503, PCIE bridge C issues downstream PCIE equipment B.
The foregoing description has been realized the data forwarding between the PCIE equipment, in order to realize the read-write operation of CPU to the PCIE equipment that has big address space, can pass through PCIE proxy for equipment scheme, and the address contents of modification as shown in Figure 6.The address space of revising the PCIE equipment B is 0x5 0,000 0000～0x6 0,000 0000; The address space of revising PCIE bridge C is that the address space of 0x5 0,000 0000～0x6 0,000 0000, PCIE equipment B has 4G.Implementing this programme needs the PCIE device A to have the access ability of 64 bit address, and the function of enhancing PCIE device A allows the PCIE device A serve as the agency of CPU read-write PCIE equipment B.CPU does not directly visit the PCIE equipment B, and CPU read-write PCIE equipment B needs the assistance of PCIE device A.
Specific protocol is followed in communication between CPU and read-write PCIE agency, reaches the purpose of CPU read-write PCIE equipment B, carries out communication by protocol package between CPU and the read-write PCIE agency, and the particular content of protocol package as shown in Figure 6.Src Addr and Src Upper Addr are the source start address, and Dst Addr and Dst Upper Addr are the purpose start address, and for the action that CPU reads the PCIE equipment B, source address is the address of PCIE equipment B, and destination address is the address of CPU internal memory; Write the action of PCIE equipment B for CPU, source address is the address of CPU internal memory, and destination address is the address of PCIE equipment B; Count and Upper Count are this byte number that need read or write; R/W is the read or write sign; F is a complement mark; PCIEB is that CPU stops the read-write sign; R and Reserve are for keeping the position, and expansion is in the future used.
Wherein, for the action that CPU reads the PCIE equipment B, read-write PCIE agency provides a part of space in the PCIE address space of self, and the content of protocol package is preserved in this space, is called interactive space at this.The specific implementation process comprises:
1, CPU constructs protocol package, and Src Addr and Src Upper Addr will be for reading the start address of PCIE equipment B content, and Dst Addr and Dst Upper Addr are for preserving the CPU internal memory start address of reading of data, and R/W is 0; F is 0; B is 0.
2, CPU writes interactive space with protocol package.
3, read-write PCIE acts on behalf of the timing scan interactive space, finds that R/W is 0, and F is 0, and B is 0 o'clock, and expression has new read request.
4, the read-write agency reads content from the PCIE equipment B, and start address is Src Addr and the Src Upper Addr in the protocol massages, and content is write in the internal memory of CPU, and start address is Dst Addr and the Dst Upper Addr in the protocol massages.
5, behind the complete operation, it is 1 that read-write PCIE agency is provided with F.
6, in the process of operation, read-write PCIE acts on behalf of the timing scan interactive space, finds that B is 1, and with terminating operation, it is 1 that F is set.
7, CPU timing scan interactive space finds that F is 1, and expression runs through.
Write the action of PCIE equipment B for CPU, read-write PCIE agency provides a part of space in the PCIE address space of self, and the content of protocol package is preserved in this space, is called interactive space at this.The specific implementation process comprises:
1, CPU constructs protocol package, and Src Addr and Src Upper Addr are CPU internal memory start address, and content will be for writing the data of PCIE equipment B, and Dst Addr and Dst Upper Addr are the address of PCIE equipment B, and R/W is 1; F is 0; B is 0.
2, CPU is written in the interactive space.
3, read-write PCIE acts on behalf of the timing scan interactive space, finds that R/W is 1, and F is 0, and B is 0 o'clock, and expression has new write request agency.
4, read-write PCIE agency is responsible for reading content from the internal memory of CPU, start address is Src Addr and the Src Upper Addr in the protocol massages, and content is write the address of PCIE equipment B, and start address is Dst Addr and the Dst Upper Addr in the protocol massages.
5, behind the complete operation, it is 1 that the read-write agency is provided with F.
6, in the process of operation, read-write PCIE acts on behalf of the timing scan interactive space, finds that B is 1, and with terminating operation, it is 1 that F is set.
7, CPU timing scan interactive space finds that F is 1, and expression is write and finished.
The present invention also provides a kind of communication system, the PCIE equipment that comprises low bit CPU and two application spaces, high address, described low bit CPU, be used to start the operating system of low bit CPU, modifier, described with the high-order address space of described two PCIE device addresses one-tenth in order to revise, so that the PCIE equipment in space, described application high address can be visited mutually, described two PCIE equipment carry out data forwarding by the PCIE bridge.
Wherein, a PCIE equipment has the data forwarding function, is used to initiate write operation, and the destination address of packet is high-order address space, and packet is from a PCIE device forwards to a PCIE bridge; The destination address that a described PCIE bridge detects described packet belongs to the 2nd PCIE bridge, and a described PCIE bridge is transmitted to described the 2nd PCIE bridge with described packet; Described the 2nd PCIE bridge sends to described the 2nd PCIE equipment with described packet; The one PCIE equipment is initiated read request, and the request of packet is read the address and is high-order address space, and packet is from a PCIE device forwards to a PCIE bridge; The request that a described PCIE bridge detects described packet is read the address and is belonged to the 2nd PCIE bridge, and a described PCIE bridge is transmitted to described the 2nd PCIE bridge with described packet.
A described PCIE equipment has the read operation of agency function, is used for the mode with timing scan interactive space, interruption or mailbox, when finding new read request is arranged, reads content from described the 2nd PCIE equipment, and content is write in the corresponding internal memory of CPU.A described PCIE equipment has the write operation function of agency, is used for the mode with timing scan interactive space, interruption or mailbox, when finding to have new write request to act on behalf of, reads content from the internal memory of CPU, and content is write the address of described the 2nd PCIE equipment.Described low bit CPU is 32 bit CPUs; Space, described high address is 64 bit address space.
Through the above description of the embodiments, those skilled in the art can be well understood to the present invention and can realize by the mode that software adds essential general hardware platform, can certainly pass through hardware, but the former is better embodiment under a lot of situation.Based on such understanding, the part that technical scheme of the present invention contributes to prior art in essence in other words can embody with the form of software product, this computer software product is stored in the storage medium, comprise that some instructions are with so that a computer equipment (can be a personal computer, server, the perhaps network equipment etc.) carry out the described method of each embodiment of the present invention.
More than disclosed only be several specific embodiment of the present invention, still, the present invention is not limited thereto, any those skilled in the art can think variation all should fall into protection scope of the present invention.
Claims (9)
1. a PCIE devices communicating method is applied to comprise in the system of the PCIE equipment that hangs down bit CPU and two application spaces, high address, it is characterized in that, said method comprising the steps of:
Start the operating system of low bit CPU;
After described os starting is finished, described two PCIE device addresses are modified as high-order address space;
Revise the PCIE bridge address of two PCIE equipment correspondences, so that the PCIE equipment in space, described application high address can carry out data forwarding by the PCIE bridge;
Described two PCIE equipment carry out data forwarding by the PCIE bridge and are specially:
The one PCIE equipment is initiated write operation, and the destination address of packet is high-order address space, and packet is from a PCIE device forwards to a PCIE bridge; The destination address that a described PCIE bridge detects described packet belongs to the 2nd PCIE bridge, and a described PCIE bridge is transmitted to described the 2nd PCIE bridge with described packet; Described the 2nd PCIE bridge sends to the 2nd PCIE equipment with described packet;
And/or the one PCIE equipment initiate read request, the request of packet is read the address and is high-order address space, packet is from a PCIE device forwards to a PCIE bridge; The request that a described PCIE bridge detects described packet is read the address and is belonged to the 2nd PCIE bridge, and a described PCIE bridge is transmitted to described the 2nd PCIE bridge with described packet.
2. PCIE devices communicating method according to claim 1 is characterized in that, describedly comprises that also a PCIE proxy for equipment CPU operates the 2nd PCIE equipment after described two PCIE device addresses are modified as high-order address space.
3. as PCIE devices communicating method as described in the claim 2, it is characterized in that, comprise that specifically a described PCIE proxy for equipment CPU reads described the 2nd PCIE equipment:
CPU constructs protocol package, comprising: will read the start address of the 2nd PCIE device content, and preserve the CPU internal memory start address of reading of data;
CPU writes interactive space with protocol package;
A described PCIE equipment finds to have new read request in the mode of timing scan interactive space, interruption or mailbox;
A described PCIE equipment is read content from described the 2nd PCIE equipment, and content is write in the corresponding internal memory of CPU; And/or
The one PCIE proxy for equipment CPU writes described the 2nd PCIE equipment:
CPU constructs protocol package, comprises CPU internal memory start address, and content will be for will write the data of the 2nd PCIE equipment and the address of the 2nd PCIE equipment;
CPU is written in the interactive space;
The one PCIE equipment timing scan interactive space, finding has new write request agency;
The one PCIE equipment is responsible for reading content from the internal memory of CPU, and content is write the address of described the 2nd PCIE equipment.
4. as PCIE devices communicating method as described in each in the claim 1 to 3, it is characterized in that described low bit CPU is 32 bit CPUs; Space, described high address is 64 bit address space.
5. a computer system comprises low bit CPU and two PCIE equipment of applying for the spaces, high address, it is characterized in that, also comprises: two PCIE bridges with high address space corresponding with above-mentioned PCIE equipment;
Described low bit CPU is used to start the operating system of hanging down bit CPU,
Described PCIE equipment has high-order address space, comprises PCIE equipment and the 2nd PCIE equipment;
Described PCIE equipment carries out data forwarding by the PCIE bridge:
The one PCIE equipment has the data forwarding function, be used to initiate write operation, wherein the destination address of packet is high-order address space, packet is from a PCIE device forwards to a PCIE bridge, the destination address that a wherein said PCIE bridge detects described packet belongs to the 2nd PCIE bridge, and a described PCIE bridge is transmitted to described the 2nd PCIE bridge with described packet; Described the 2nd PCIE bridge sends to described the 2nd PCIE equipment with described packet; And/or be used to initiate read request, the request of packet is read the address and is high-order address space, packet is from a PCIE device forwards to a PCIE bridge, the request that a wherein said PCIE bridge detects described packet is read the address and is belonged to the 2nd PCIE bridge, and a described PCIE bridge is transmitted to described the 2nd PCIE bridge with described packet.
6. as computer system as described in the claim 5, it is characterized in that, a described PCIE equipment has the read operation of agency function, be used for mode with timing scan interactive space, interruption or mailbox, when discovery has new read request, read content from described the 2nd PCIE equipment, and content is write in the corresponding internal memory of CPU;
And/or be used for mode with timing scan interactive space, interruption or mailbox, when finding to have new write request to act on behalf of, read content from the internal memory of CPU, and content is write the address of described the 2nd PCIE equipment.
7. as computer system as described in claim 5 or 6, it is characterized in that described low bit CPU is 32 bit CPUs; Space, described high address is 64 bit address space.
8. a computer system comprises low bit CPU and has space, high address first and second bus apparatus, it is characterized in that,
Described low bit CPU is used to start the operating system; Described first and second bus apparatus are used for carrying out data forwarding between the two by bus bridge, and wherein first bus apparatus is acted on behalf of communicating by letter between described low bit CPU and described second bus apparatus;
Described bus is PCIE, and the PCIE bridge comprises the first and second PCIE bridges, and the described first and second PCIE equipment communicate by the first and second PCIE bridges:
The one PCIE equipment has the data forwarding function, be used to initiate write operation, wherein the destination address of packet is high-order address space, packet is from a PCIE device forwards to a PCIE bridge, the destination address that a wherein said PCIE bridge detects described packet belongs to the 2nd PCIE bridge, and a described PCIE bridge is transmitted to described the 2nd PCIE bridge with described packet; Described the 2nd PCIE bridge sends to described the 2nd PCIE equipment with described packet; And/or be used to initiate read request, the request of packet is read the address and is high-order address space, packet is from a PCIE device forwards to a PCIE bridge, the request that a wherein said PCIE bridge detects described packet is read the address and is belonged to the 2nd PCIE bridge, and a described PCIE bridge is transmitted to described the 2nd PCIE bridge with described packet.
9. as computer system as described in the claim 8, it is characterized in that a described PCIE equipment, be used for mode with timing scan interactive space, interruption or mailbox, when discovery has new read request, read content, and content is write in the corresponding internal memory of CPU from described the 2nd PCIE equipment; And/or be used for mode with timing scan interactive space, interruption or mailbox, when finding to have new write request to act on behalf of, read content from the internal memory of CPU, and content is write the address of described the 2nd PCIE equipment.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200710195702XA CN101178697B (en) | 2007-12-12 | 2007-12-12 | PCIE apparatus satellite communication method and system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200710195702XA CN101178697B (en) | 2007-12-12 | 2007-12-12 | PCIE apparatus satellite communication method and system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101178697A CN101178697A (en) | 2008-05-14 |
| CN101178697B true CN101178697B (en) | 2011-08-03 |
Family
ID=39404955
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200710195702XA Expired - Fee Related CN101178697B (en) | 2007-12-12 | 2007-12-12 | PCIE apparatus satellite communication method and system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101178697B (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102393838B (en) * | 2011-07-04 | 2015-03-11 | 华为技术有限公司 | Data processing method and device, PCI-E (peripheral component interface-express) bus system, and server |
| US9684575B2 (en) | 2014-06-23 | 2017-06-20 | Liqid Inc. | Failover handling in modular switched fabric for data storage systems |
| CN106462498B (en) * | 2014-06-23 | 2019-08-02 | 利奇德股份有限公司 | Modularization architecture for exchanging for data-storage system |
| CN104820646B (en) * | 2015-05-25 | 2018-02-16 | 烽火通信科技股份有限公司 | More RC PCIE device dynamic scan method is supported under linux system |
| US20160371222A1 (en) * | 2015-06-22 | 2016-12-22 | Qualcomm Incorporated | COHERENCY DRIVEN ENHANCEMENTS TO A PERIPHERAL COMPONENT INTERCONNECT (PCI) EXPRESS (PCIe) TRANSACTION LAYER |
| CN107193760A (en) * | 2017-05-23 | 2017-09-22 | 郑州云海信息技术有限公司 | It is a kind of to avoid PCIE device from causing the method for dysfunction because of address space distribution |
-
2007
- 2007-12-12 CN CN200710195702XA patent/CN101178697B/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN101178697A (en) | 2008-05-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11929927B2 (en) | Network interface for data transport in heterogeneous computing environments | |
| US9678918B2 (en) | Data processing system and data processing method | |
| CN108268412B (en) | System and method for extending peripheral component interconnect express fabric | |
| CN101178697B (en) | PCIE apparatus satellite communication method and system | |
| JP4805314B2 (en) | Offload input / output (I / O) virtualization operations to the processor | |
| US11392528B2 (en) | Methods and apparatus for DMA engine descriptors for high speed data systems | |
| JP5681782B2 (en) | On-die system fabric block control | |
| JP5541021B2 (en) | Switch device | |
| CN103092798B (en) | The method of the access means under SOC(system on a chip) and bus | |
| US20110206051A1 (en) | I/o bus system | |
| US10698849B2 (en) | Methods and apparatus for augmented bus numbering | |
| US20170185525A1 (en) | Speculative enumeration of bus-device-function address space | |
| US8250260B2 (en) | Method, arrangement, data processing program and computer program product for exchanging message data in a distributed computer system | |
| US9830283B2 (en) | Multi-mode agent | |
| CN105359122B (en) | enhanced data transmission in multi-CPU system | |
| KR20110120094A (en) | System on chip including unified input/output memory management unit | |
| CN107250995B (en) | Memory management device | |
| WO2023086574A1 (en) | Memory pooling bandwidth multiplier using final level cache system | |
| CN105786733A (en) | TCAM (Ternary Content Addressable Memory) entry writing method and apparatus | |
| TWI467385B (en) | Mapping between two buses using serial addressing bits | |
| JP2011113163A (en) | Inter-end point communication control device and method in io access communication system | |
| JP2007241904A (en) | Bridge, information processor and access control method | |
| US9424227B2 (en) | Providing byte enables for peer-to-peer data transfer within a computing environment | |
| WO2024082944A1 (en) | Method and apparatus for data exchange between multiple processors, device, and storage medium | |
| KR20210138380A (en) | Shared memory apparatus, shared memory system and operating method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address |
Address after: 310052 Binjiang District Changhe Road, Zhejiang, China, No. 466, No. Patentee after: Xinhua three Technology Co., Ltd. Address before: 310053 Hangzhou hi tech Industrial Development Zone, Zhejiang province science and Technology Industrial Park, No. 310 and No. six road, HUAWEI, Hangzhou production base Patentee before: Huasan Communication Technology Co., Ltd. |
|
| CP03 | Change of name, title or address | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20110803 Termination date: 20191212 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |