JP5073954B2 - Semiconductor device and automatic placement and routing method thereof - Google Patents
Semiconductor device and automatic placement and routing method thereof Download PDFInfo
- Publication number
- JP5073954B2 JP5073954B2 JP2006071062A JP2006071062A JP5073954B2 JP 5073954 B2 JP5073954 B2 JP 5073954B2 JP 2006071062 A JP2006071062 A JP 2006071062A JP 2006071062 A JP2006071062 A JP 2006071062A JP 5073954 B2 JP5073954 B2 JP 5073954B2
- Authority
- JP
- Japan
- Prior art keywords
- dummy metal
- resistance layer
- semiconductor device
- resistance
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Design And Manufacture Of Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
本発明は、半導体装置に関し、特にポリシリコンからなる抵抗層を備えたアナログ用半導体装置に関する。 The present invention relates to a semiconductor device, and more particularly to an analog semiconductor device having a resistance layer made of polysilicon.
多くのアナログ用半導体装置では、不純物が添加されたポリシリコン層からなる高抵抗の抵抗層が搭載されている。 Many analog semiconductor devices are equipped with a high-resistance resistance layer made of a polysilicon layer doped with impurities.
図８は、上記の抵抗層を備えた半導体装置の一例を示す断面図である。半導体装置は、半導体基板１と、前記半導体基板１上に形成されたＳｉＯ２からなる酸化膜２と、前記酸化膜２上の一部上に形成されたポリシリコンからなる抵抗層３と、前記抵抗層３を覆うように形成されたＳＯＧ（ｓｐｉｎ ｏｎ ｇｌａｓｓ）からなる層間絶縁膜４と、前記層間絶縁膜４において前記抵抗層３の一部上に形成されたコンタクトホール６と、前記コンタクトホール６を介して前記抵抗層３と接続されたＡｌからなる抵抗配線７と、前記抵抗層３及び前記抵抗配線７を覆うように形成されたプラズマ窒化膜５と、を備えている。 FIG. 8 is a cross-sectional view showing an example of a semiconductor device provided with the above-described resistance layer. The semiconductor device includes a semiconductor substrate 1, an oxide film 2 made of SiO 2 formed on the semiconductor substrate 1, a resistance layer 3 made of polysilicon formed on a part of the oxide film 2, An interlayer insulating film 4 made of SOG (spin on glass) formed so as to cover the resistance layer 3, a contact hole 6 formed on a part of the resistance layer 3 in the interlayer insulating film 4, and the contact hole And a resistance wiring 7 made of Al connected to the resistance layer 3 through 6 and a plasma nitride film 5 formed so as to cover the resistance layer 3 and the resistance wiring 7.
前記抵抗層３は、水素イオンの添加量により抵抗値が変化することが知られている。すなわち、前記プラズマ窒化膜５は、外部からイオンが侵入することを防ぐパッシベーション膜として、アナログ回路等の半導体集積回路では必須のものである。ところが、プラズマＣＶＤ法により形成される前記プラズマ窒化膜５中には多量の水素イオンが含まれている。このため、前記プラズマ窒素膜５が形成された後に熱処理工程が行われると、前記プラズマ窒化膜５中の水素イオンが、前記層間絶縁膜４を介して前記抵抗層３中に導入され、前記抵抗層３の抵抗値が変化するという不都合が生じていた。 It is known that the resistance value of the resistance layer 3 varies depending on the amount of hydrogen ions added. That is, the plasma nitride film 5 is indispensable for a semiconductor integrated circuit such as an analog circuit as a passivation film for preventing ions from entering from the outside. However, the plasma nitride film 5 formed by the plasma CVD method contains a large amount of hydrogen ions. For this reason, when a heat treatment process is performed after the plasma nitrogen film 5 is formed, hydrogen ions in the plasma nitride film 5 are introduced into the resistance layer 3 through the interlayer insulating film 4 and the resistance is increased. There was a disadvantage that the resistance value of the layer 3 changed.
上記問題を解決すべく、例えば、前記抵抗層３をシリコン酸化膜で覆い、前記プラズマ窒化膜５中の水素イオンが前記抵抗層３中に導入されないようにする等の対策がとられてきた。
関連した技術は、例えば、以下の特許文献に記載されている。
Related techniques are described in, for example, the following patent documents.
アナログ回路で用いる抵抗は、複数本をペアで用いて、それらの抵抗比によって出力電圧や電流を決定する。したがって、アナログ回路では、ロジック回路に用いられる場合以上に、抵抗層の抵抗精度を得る必要がある。
ところで、半導体集積回路の配線は、アルゴリズムに従って自動的に設計される。すなわち、図９に示す如く、先ず抵抗層等の素子を配置し、次にアルゴリズムに従って配線を自動設計し、次に配線が形成されない疎な領域にダミーメタルを自動配置していた。
この場合、以下のような問題が生じていた。
図１０は従来技術に係る半導体装置の一例を示す平面図を示す。また、図１１（ａ）はＹ２−Ｙ２における断面図、図１１（ｂ）はＹ３−Ｙ３における断面図を示す。配線層１０が自動的に設計された場合、前記配線層１０は、各抵抗層３上にランダムに重なっていた。このとき、前記配線層１０と前記抵抗層３との重なる面積により、前記プラズマ窒化膜５から前記抵抗層３に導入される水素イオンの量が異なることになる。すなわち、各抵抗層３の抵抗比が、設計値と大きく異なっていた。
このような各抵抗層３の抵抗比の設計値とのズレは、従来のように、前記抵抗層３をシリコン酸化膜で覆う等の製造プロセス上の手段では不十分な場合もあった。
A plurality of resistors used in the analog circuit are used in pairs, and the output voltage and current are determined based on the resistance ratio. Therefore, in the analog circuit, it is necessary to obtain the resistance accuracy of the resistance layer more than that used in the logic circuit.
Incidentally, the wiring of the semiconductor integrated circuit is automatically designed according to an algorithm. That is, as shown in FIG. 9, elements such as a resistance layer are first arranged, then wiring is automatically designed according to an algorithm, and then dummy metal is automatically arranged in a sparse area where no wiring is formed.
In this case, the following problems have occurred.
FIG. 10 is a plan view showing an example of a conventional semiconductor device. 11A is a cross-sectional view taken along Y2-Y2, and FIG. 11B is a cross-sectional view taken along Y3-Y3. When the wiring layer 10 was automatically designed, the wiring layer 10 was randomly superimposed on each resistance layer 3. At this time, the amount of hydrogen ions introduced from the plasma nitride film 5 into the resistance layer 3 varies depending on the overlapping area of the wiring layer 10 and the resistance layer 3. That is, the resistance ratio of each resistance layer 3 was significantly different from the design value.
Such a deviation from the design value of the resistance ratio of each resistance layer 3 may be insufficient by means of a manufacturing process such as covering the resistance layer 3 with a silicon oxide film as in the prior art.
上記の問題に鑑み、本発明に係る半導体装置は、抵抗層と、前記抵抗層を覆うように形成された層間絶縁膜と、前記層間絶縁膜の一部上に形成された配線層及びダミーメタルと、を有し、前記抵抗層と重なる前記層間絶縁膜上には前記配線層は形成されていない半導体装置において、前記ダミーメタルは、前記抵抗層と重なる前記層間絶縁膜上に形成された第１のダミーメタルと、前記抵抗層と重ならない前記層間絶縁膜上に形成された第２のダミーメタルと、からなることを特徴とする。 In view of the above problems, a semiconductor device according to the present invention includes a resistance layer, an interlayer insulating film formed so as to cover the resistance layer, a wiring layer formed on part of the interlayer insulating film, and a dummy metal When the possess, in the semiconductor device without the wiring layer is formed on the interlayer insulating film overlapping with the resistive layer, wherein the dummy metal is first formed on the interlayer insulating film overlapping with the resistive layer The first dummy metal and the second dummy metal formed on the interlayer insulating film that does not overlap the resistance layer .
また、前記抵抗層はポリシリコンからなることを特徴とする。 The resistance layer is made of polysilicon.
また、前記抵抗層は、第１の抵抗層と、第２の抵抗層と、からなり、
前記第１の抵抗層と、前記第２の抵抗層と、はペア性を有していることを特徴とする。
In addition, the resistance layer includes a first resistance layer and a second resistance layer,
The first resistance layer and the second resistance layer have a pair property.
また、前記第１のダミーメタルは、中心と外周との最短距離が１μｍよりも小さいことを特徴とする。 The first dummy metal is characterized in that the shortest distance between the center and the outer periphery is less than 1 μm.
また、前記層間絶縁膜、前記配線層、及び前記ダミーメタルは、プラズマ窒化膜により覆われていることを特徴とする。 The interlayer insulating film, the wiring layer, and the dummy metal are covered with a plasma nitride film.
また、前記層間絶縁膜はＳＯＧ（ｓｐｉｎ ｏｎ ｇｌａｓｓ）からなることを特徴とする。 The interlayer insulating film is made of SOG (spin on glass).
また、本発明に係る半導体装置の自動配線方法は、少なくとも抵抗層の一部上にダミーメタルを配置した後に自動配置配線を行う半導体装置の自動配置配線方法において、
前記ダミーメタルは、前記抵抗層と重なる位置に配置される第１のダミーメタルと、前記抵抗層とは重ならない位置に配置される第２のダミーメタルと、からなることを特徴とする。
Further, an automatic wiring method of a semiconductor device according to the present invention is an automatic placement and wiring method of a semiconductor device that performs automatic placement and wiring after placing a dummy metal on at least a part of a resistance layer.
The dummy metal includes a first dummy metal disposed at a position overlapping with the resistance layer, and a second dummy metal disposed at a position not overlapping with the resistance layer .
本発明に係る半導体装置は、各抵抗層上に配線層が形成されないため、各抵抗層の抵抗比を設計通りに作製することができる。 In the semiconductor device according to the present invention, since the wiring layer is not formed on each resistance layer, the resistance ratio of each resistance layer can be manufactured as designed.
また、本発明に係る半導体装置の自動配置配線方法では、回路図上に抵抗のペア性の情報がなくても一律に設計できる。 In addition, the automatic placement and routing method for a semiconductor device according to the present invention can be designed uniformly even if there is no resistance pair information on the circuit diagram.
また、ダミーメタルのデータ数の増加を最小限に抑えることができる。 In addition, an increase in the number of dummy metal data can be minimized.
図１は、本発明に係る半導体装置の自動配置配線方法のフローチャートを示す。すなわち、先ず、抵抗層等の素子を配置する。次に、配置された素子に抵抗層が含まれていたら、当該抵抗層上に第１のダミーメタルを配置する。次に、アルゴリズムに従って、配線を自動設計する。このとき、抵抗層上には、第１のダミーメタルが形成されているため、配線は配置されない。その後、配線が疎な領域に第２のダミーメタルを自動配置する。このとき、第２のダミーメタルは、第１のダミーメタルよりも大きく設定する。 FIG. 1 is a flowchart of an automatic placement and routing method for a semiconductor device according to the present invention. That is, first, an element such as a resistance layer is disposed. Next, if the arranged element includes a resistance layer, a first dummy metal is arranged on the resistance layer. Next, the wiring is automatically designed according to the algorithm. At this time, since the first dummy metal is formed on the resistance layer, no wiring is arranged. Thereafter, the second dummy metal is automatically arranged in a region where wiring is sparse. At this time, the second dummy metal is set larger than the first dummy metal.
以下、図２乃至図４を参照して、本発明に係る半導体装置の自動配置配線方法を具体的に説明する。 Hereinafter, an automatic placement and routing method for a semiconductor device according to the present invention will be described in detail with reference to FIGS.
先ず、図２に示すように、ペア性を有した２つの抵抗層３が配置される。尚、図１は、半導体チップのレイアウト範囲において、前記抵抗層３が配置される一部のみを示している。したがって、本工程において、図１に示されていないレイアウト範囲には、トランジスタ等の機能素子が配置されている。 First, as shown in FIG. 2, two resistance layers 3 having a pair property are arranged. FIG. 1 shows only a part where the resistance layer 3 is arranged in the layout range of the semiconductor chip. Therefore, in this step, functional elements such as transistors are arranged in a layout range not shown in FIG.
次に、図３に示すように、前記抵抗層３に重なるように、第１のダミーメタル８が配置される。前記第１のダミーメタル８の大きさ及び形状は、例えば、一辺が０．９μｍ程度の矩形状とする。 Next, as shown in FIG. 3, the first dummy metal 8 is disposed so as to overlap the resistance layer 3. The size and shape of the first dummy metal 8 is, for example, a rectangular shape having a side of about 0.9 μm.
尚、前記第１のダミーメタル８の１辺を０．９μｍ程度としたのは、以下の理由による。すなわち、前記抵抗層３は、水素イオンの添加量により抵抗値が変化する。水素イオンは、前記抵抗層３上に形成される不図示のプラズマ窒化膜５から侵入する。したがって、前記抵抗層３とプラズマ窒化膜５との間に水素の浸入を遮断する障害物があると、前記抵抗層３に添加される水素イオンの添加量は、障害物の面積により変化する。特に、上記のように前記抵抗層３がペア性を有している場合、各前記抵抗層３上に形成される障害物の面積が異なれば、設計した抵抗比を得られないため問題となる。この点、本発明では、前記抵抗層３上に障害物たる前記第１のダミーメタル８が形成される。しかしながら、水素イオンは、障害物を横方向から０．５μｍ程度まで回り込むことができる。このため、例えば、前記抵抗層３上に形成される前記第１のダミーメタル８の一辺が１μｍよりも大きい場合、図７（ａ）に示すように、水素イオン１２は前記抵抗層３を完全には回り込まず、水素イオンが疎な領域１１が形成される。一方、本発明の如く、前記抵抗層３上に形成される前記第１のダミーメタル８の一辺が１μｍよりも小さい場合、図７（ｂ）に示すように、水素イオン１２は前記第１のダミーメタル８を完全に回り込む。したがって、前記第１のダミーメタル８の一辺が０．９μｍ程度であれば、前記抵抗層３の抵抗値は、前記第１のダミーメタル８の有無に影響を受けない。つまり、設計通りの抵抗比が容易に得られる。 The reason why one side of the first dummy metal 8 is set to about 0.9 μm is as follows. That is, the resistance value of the resistance layer 3 varies depending on the amount of hydrogen ions added. Hydrogen ions enter from a plasma nitride film 5 (not shown) formed on the resistance layer 3. Therefore, if there is an obstacle that blocks the entry of hydrogen between the resistance layer 3 and the plasma nitride film 5, the amount of hydrogen ions added to the resistance layer 3 varies depending on the area of the obstacle. In particular, when the resistance layer 3 has a pair property as described above, it becomes a problem because the designed resistance ratio cannot be obtained if the areas of the obstacles formed on the resistance layers 3 are different. . In this regard, in the present invention, the first dummy metal 8 serving as an obstacle is formed on the resistance layer 3. However, hydrogen ions can go around the obstacle from the lateral direction to about 0.5 μm. Therefore, for example, when one side of the first dummy metal 8 formed on the resistance layer 3 is larger than 1 μm, as shown in FIG. Thus, a region 11 in which hydrogen ions are sparse is formed. On the other hand, as in the present invention, when one side of the first dummy metal 8 formed on the resistance layer 3 is smaller than 1 μm, as shown in FIG. It goes around the dummy metal 8 completely. Therefore, if one side of the first dummy metal 8 is about 0.9 μm, the resistance value of the resistance layer 3 is not affected by the presence or absence of the first dummy metal 8. That is, the designed resistance ratio can be easily obtained.
次に、図４に示すように、配線層１０及び抵抗配線７の配置パターンがアルゴリズムに従って自動的に設計される。このとき、前記配線層１０は、前記第１のダミーメタル８が配置されているため、前記抵抗層３のペア情報が設定されていなくても、前記抵抗層３に重なる位置には形成されない。 Next, as shown in FIG. 4, the arrangement pattern of the wiring layer 10 and the resistance wiring 7 is automatically designed according to an algorithm. At this time, since the first dummy metal 8 is disposed, the wiring layer 10 is not formed at a position overlapping the resistance layer 3 even if the pair information of the resistance layer 3 is not set.
次に、図５に示すように、平坦性を向上するため、前記第１のダミーメタル８及び前記配線層１０が形成されておらず、レイアウトパターンが疎な場所に第２のダミーメタル９が配置される。前記第２のダミーメタル９の大きさ及び形状は、例えば、一辺が５．２μｍ程度の矩形状とする。尚、前記第２のダミーメタル９の大きさが、前記第１のダミーメタル８と等しくても、平坦性は向上する。しかしながら、この場合にはデータ数が膨大となるため、一般的な汎用計算機では対応できなくなり、計算機のグレードアップをする必要が生じる。この点、本発明では、一辺０．９μｍのダミーバンプを必要最小限に限り配置させるため、データ数の増加を最小限に抑えることができ、一般的な汎用計算機で対応ができる。 Next, as shown in FIG. 5, in order to improve flatness, the first dummy metal 8 and the wiring layer 10 are not formed, and the second dummy metal 9 is formed in a place where the layout pattern is sparse. Be placed. The size and shape of the second dummy metal 9 is, for example, a rectangular shape having a side of about 5.2 μm. Even if the size of the second dummy metal 9 is equal to that of the first dummy metal 8, the flatness is improved. However, in this case, since the number of data becomes enormous, it cannot be handled by a general general purpose computer, and it is necessary to upgrade the computer. In this respect, in the present invention, since the dummy bumps having a side of 0.9 μm are arranged as much as possible, an increase in the number of data can be suppressed to a minimum and can be handled by a general general-purpose computer.
続いて、本発明に係る半導体装置について説明する。 Next, the semiconductor device according to the present invention will be described.
図６は、図５に示す半導体装置の断面図を示す。すなわち、図６（ａ）はＸ１−Ｘ１、図６（ｂ）はＹ１−Ｙ１における断面図を示す。本発明に係る半導体装置は、半導体基板１と、前記半導体基板１上に形成されたＳｉＯ２からなる酸化膜２と、前記酸化膜２上の一部上に形成されたポリシリコンからなる抵抗層３と、前記抵抗層３を覆うように形成されたＳＯＧ（ｓｐｉｎ ｏｎ ｇｌａｓｓ）からなる層間絶縁膜４と、前記層間絶縁膜４において前記抵抗層３の一部上に形成されたコンタクトホール６と、前記コンタクトホール６を介して前記抵抗層３と接続されたＡｌからなる抵抗配線７と、前記抵抗層３の一部上に対応する前記層間絶縁膜４上に形成された第１のダミーメタル８と、前記層間絶縁膜４、前記抵抗配線７、及び前記第１のダミーメタル８を覆うように形成されたプラズマ窒化膜５と、を備えている。また、前記抵抗層３から離れた位置に配線層１０が配置されている。更に、前記配線層１０、前記第１のダミーメタルが形成されておらず、レイアウトパターンが疎な領域に、前記第１のダミーメタル８よりも大きい第２のダミーメタル９が形成されている。ここで、前記抵抗配線７、前記配線層１０、前記第１のダミーメタル８、及び前記第２のダミーメタル９は、例えばＡｌから形成される。また、前記第１のダミーメタルは、例えば、一辺０．９μｍの矩形状で形成される。また、前記第２のダミーメタル９は、例えば、一辺５．２μｍの矩形状で形成される。また、前記抵抗層３はペア性を有しており、例えば、抵抗比によって回路の出力値が決定される。斯かる機能は、例えばＢｉＣＭＯＳ等の半導体装置に備えられている。 6 shows a cross-sectional view of the semiconductor device shown in FIG. That is, FIG. 6A shows a cross-sectional view at X1-X1, and FIG. 6B shows a cross-sectional view at Y1-Y1. A semiconductor device according to the present invention includes a semiconductor substrate 1, an oxide film 2 made of SiO 2 formed on the semiconductor substrate 1, and a resistance layer made of polysilicon formed on a part of the oxide film 2. 3, an interlayer insulating film 4 made of SOG (spin on glass) formed so as to cover the resistance layer 3, and a contact hole 6 formed on a part of the resistance layer 3 in the interlayer insulating film 4 A resistance wiring 7 made of Al connected to the resistance layer 3 through the contact hole 6 and a first dummy metal formed on the interlayer insulating film 4 corresponding to a part of the resistance layer 3 8 and a plasma nitride film 5 formed so as to cover the interlayer insulating film 4, the resistance wiring 7, and the first dummy metal 8. A wiring layer 10 is disposed at a position away from the resistance layer 3. Further, the wiring layer 10 and the first dummy metal are not formed, and a second dummy metal 9 larger than the first dummy metal 8 is formed in a region where the layout pattern is sparse. Here, the resistance wiring 7, the wiring layer 10, the first dummy metal 8, and the second dummy metal 9 are made of, for example, Al. The first dummy metal is formed in a rectangular shape having a side of 0.9 μm, for example. The second dummy metal 9 is formed in a rectangular shape having a side of 5.2 μm, for example. The resistance layer 3 has a pair property, and the output value of the circuit is determined by the resistance ratio, for example. Such a function is provided in a semiconductor device such as BiCMOS.
上記の半導体装置では、前記抵抗層３の一部上に対応する前記層間絶縁膜４上には、前記配線層１０が形成されない。したがって、前記プラズマ窒化膜５に含まれる水素イオンは、前記配線層４に遮断されずに前記層間絶縁膜４を介して前記抵抗層３中に浸入する。つまり、ペア性を有する各抵抗層３に浸入する水素イオンの添加量は等しい。したがって、設計通りの抵抗比を容易に作製することが可能である。尚、前記抵抗層３と前記プラズマ窒化膜５との間の一部上には前記第１のダミーメタル８が形成されている。しかしながら、前述したように、前記第１のダミーメタル８は、一辺０．９μｍ程度の大きさで形成されているため、各抵抗層３に浸入する水素イオンの添加量には影響しない。 In the semiconductor device, the wiring layer 10 is not formed on the interlayer insulating film 4 corresponding to a part of the resistance layer 3. Accordingly, hydrogen ions contained in the plasma nitride film 5 enter the resistance layer 3 through the interlayer insulating film 4 without being blocked by the wiring layer 4. That is, the added amount of hydrogen ions entering each resistance layer 3 having a pair property is equal. Therefore, it is possible to easily produce a resistance ratio as designed. The first dummy metal 8 is formed on a part between the resistance layer 3 and the plasma nitride film 5. However, as described above, since the first dummy metal 8 is formed with a size of about 0.9 μm on a side, it does not affect the amount of hydrogen ions added to each resistance layer 3.
以上、本発明では、前記抵抗層３の一部上に前記第１のダミーメタル８を配置した後に、前記配線層１０の自動配置を行うため、回路図上に抵抗のペア性の情報がなくても、前記抵抗層３と前記配線層１０とが重ならない。したがって、ペアを組む各抵抗層３の水素添加量に差が生じないため、設計通りの抵抗比を得ることができる。 As described above, in the present invention, since the wiring layer 10 is automatically arranged after the first dummy metal 8 is arranged on a part of the resistance layer 3, there is no information on resistance pairing on the circuit diagram. However, the resistance layer 3 and the wiring layer 10 do not overlap. Therefore, there is no difference in the hydrogenation amount of each resistance layer 3 that forms a pair, and a resistance ratio as designed can be obtained.
また、前記第１のダミーメタル８よりも、前記第２のダミーメタル９の大きさを大きくすることによりデータ数の増加を最小限に抑えることができる。 Further, by increasing the size of the second dummy metal 9 as compared with the first dummy metal 8, an increase in the number of data can be minimized.
尚、本実施形態では、前記第２のダミーメタル９の大きさを前記第１のダミーメタル８よりも大きくした。しかしながら、使用している計算機の能力が優れていれば、前記第２のダミーメタル９の大きさを前記第１のダミーメタル８と等しくしても、設計通りの抵抗比が得られる。 In the present embodiment, the size of the second dummy metal 9 is made larger than that of the first dummy metal 8. However, if the capacity of the computer used is excellent, even if the size of the second dummy metal 9 is made equal to that of the first dummy metal 8, a designed resistance ratio can be obtained.
また、本実施形態では、前記第１のダミーメタル８は、平面的に見て矩形状であり、且つ全ての辺が１μｍ以下であるとした。しかしながら、本発明はこれに限定されず、例えば、前記第１のダミーメタル８が平面的に見て楕円状であっても、その中心から外周への最短距離が０．５μｍ以下である場合、水素イオンは、本実施形態と同様に前記第１のダミーメタル８を完全に回り込むことができる。 In the present embodiment, the first dummy metal 8 has a rectangular shape in plan view, and all sides are 1 μm or less. However, the present invention is not limited to this. For example, even when the first dummy metal 8 is elliptical when viewed in plan, the shortest distance from the center to the outer periphery is 0.5 μm or less. Hydrogen ions can completely wrap around the first dummy metal 8 as in the present embodiment.
１ 半導体基板
２ 酸化膜
３ 抵抗層
４ 層間絶縁膜
５ プラズマ窒化膜
６ コンタクトホール
７ 抵抗配線
８ 第１のダミーメタル
９ 第２のダミーメタル
１０ 配線層
１１ 水素イオンが疎な領域
１２ 水素イオン
DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Oxide film 3 Resistance layer 4 Interlayer insulation film 5 Plasma nitride film 6 Contact hole 7 Resistance wiring 8 First dummy metal 9 Second dummy metal 10 Wiring layer 11 Region where hydrogen ions are sparse 12 Hydrogen ions
Claims (10)
前記抵抗層を覆うように形成された層間絶縁膜と、
前記層間絶縁膜の一部上に形成された配線層及びダミーメタルと、を有し、前記抵抗層と重なる前記層間絶縁膜上には前記配線層は形成されていない半導体装置において、
前記ダミーメタルは、前記抵抗層と重なる前記層間絶縁膜上に形成された第１のダミーメタルと、前記抵抗層と重ならない前記層間絶縁膜上に形成された第２のダミーメタルと、からなることを特徴とする半導体装置。 A resistance layer;
An interlayer insulating film formed to cover the resistance layer;
In the semiconductor device without the wiring layer is formed in a part on the formed wiring layers and dummy metal, the possess, on the interlayer insulating film overlapping with the resistive layer of the interlayer insulating film,
The dummy metal includes a first dummy metal formed on the interlayer insulating film overlapping with the resistance layer, and a second dummy metal formed on the interlayer insulating film not overlapping with the resistance layer. A semiconductor device.
前記第１の抵抗層と、前記第２の抵抗層と、はペア性を有していることを特徴とする請求項１乃至３のいずれかに記載の半導体装置。 The resistance layer includes a first resistance layer and a second resistance layer,
4. The semiconductor device according to claim 1, wherein the first resistance layer and the second resistance layer have a pair property.
前記ダミーメタルは、前記抵抗層と重なる位置に配置される第１のダミーメタルと、前記抵抗層とは重ならない位置に配置される第２のダミーメタルと、からなることを特徴とする半導体装置の自動配置配線方法。 In an automatic placement and routing method of a semiconductor device for performing automatic placement and routing after placing a dummy metal on at least a part of a resistance layer,
The dummy metal includes a first dummy metal disposed at a position overlapping with the resistance layer and a second dummy metal disposed at a position not overlapping with the resistance layer. Automatic placement and routing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2006071062A JP5073954B2 (en) | 2006-03-15 | 2006-03-15 | Semiconductor device and automatic placement and routing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2006071062A JP5073954B2 (en) | 2006-03-15 | 2006-03-15 | Semiconductor device and automatic placement and routing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2007250757A JP2007250757A (en) | 2007-09-27 |
| JP5073954B2 true JP5073954B2 (en) | 2012-11-14 |
Family
ID=38594739
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2006071062A Active JP5073954B2 (en) | 2006-03-15 | 2006-03-15 | Semiconductor device and automatic placement and routing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP5073954B2 (en) |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6185851A (en) * | 1984-10-04 | 1986-05-01 | Nec Corp | Semiconductor device |
| JPH03104155A (en) * | 1989-09-18 | 1991-05-01 | Sanyo Electric Co Ltd | Semiconductor device |
| JP2936615B2 (en) * | 1990-01-31 | 1999-08-23 | ソニー株式会社 | Method for manufacturing semiconductor device |
| JP2750992B2 (en) * | 1992-08-12 | 1998-05-18 | 三菱電機株式会社 | Semiconductor device and manufacturing method thereof |
-
2006
- 2006-03-15 JP JP2006071062A patent/JP5073954B2/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| JP2007250757A (en) | 2007-09-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP5103232B2 (en) | Semiconductor device | |
| JP5061520B2 (en) | Semiconductor device and semiconductor wafer | |
| JP4777668B2 (en) | MIM type capacitor | |
| JP2000286263A (en) | Semiconductor device and its manufacture | |
| KR20120023917A (en) | Resistor array and semiconductor memory device including the same | |
| JP4785623B2 (en) | Semiconductor device and manufacturing method thereof | |
| CN102324427A (en) | Metal film resistor structure and manufacturing method thereof | |
| US9530731B2 (en) | Method of optical proximity correction for modifying line patterns and integrated circuits with line patterns modified by the same | |
| JP4803898B2 (en) | Semiconductor device | |
| US20180040558A1 (en) | Semiconductor device and method of fabricating the same | |
| JP5073954B2 (en) | Semiconductor device and automatic placement and routing method thereof | |
| US8013385B2 (en) | Semiconductor device | |
| JP2006222410A (en) | Semiconductor device and manufacturing method thereof | |
| JP4744103B2 (en) | Semiconductor device including resistance element and manufacturing method thereof | |
| JP4646891B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP2008060364A (en) | Semiconductor device, design method and design program thereof semiconductor device | |
| JP2003045973A (en) | Semiconductor device, its design method and design program | |
| JP2005303051A (en) | Semiconductor device and manufacturing method thereof | |
| US20230260930A1 (en) | Die seal ring structure | |
| JP2007273689A (en) | Semiconductor device | |
| JP2006191129A (en) | Semiconductor device and manufacturing method therefor | |
| KR100734144B1 (en) | Method of fabricating MIM capacitor | |
| JP2001053143A (en) | Semiconductor device manufacturing method and the semiconductor device | |
| US8289126B2 (en) | Resistive element and manufacturing method therefor | |
| JP2008124449A (en) | Semiconductor device and method of fabricating same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20090216 |
|
| A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A711 Effective date: 20110526 |
|
| RD02 | Notification of acceptance of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7422 Effective date: 20110526 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20120418 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20120419 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20120713 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20120731 |
|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20120823 |
|
| R150 | Certificate of patent or registration of utility model |
Ref document number: 5073954 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20150831 Year of fee payment: 3 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20150831 Year of fee payment: 3 |
|
| S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313113 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20150831 Year of fee payment: 3 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |