JP5066978B2 - Information processing apparatus fault processing method and information processing apparatus - Google Patents

Description

  The present invention relates to an information processing apparatus in which a plurality of arithmetic processing units each including a combination of a microprocessor and a memory are provided, and the microprocessors of the respective arithmetic processing units are connected so as to be able to transmit information and perform parallel arithmetic processing. The present invention relates to a failure processing method for an information processing apparatus and an improvement in the information processing apparatus itself for using a memory under the microprocessor when a failure occurs in a microprocessor of some arithmetic processing units.

  There is already known an information processing apparatus in which a plurality of arithmetic processing units each including a combination of a microprocessor and a memory are provided, and the microprocessors of the respective arithmetic processing units are connected so as to be able to transmit information to perform parallel arithmetic processing. .

Conventionally, when the microprocessor of the processing unit of some of this kind of information processing apparatus failure occurs, not only the microprocessor, the memory also a problem of unusable simultaneously working under of the microprocessor It was.

  As with microprocessors, memory accounts for a large percentage of the price of information processing equipment. In fact, memory that is not abnormal cannot be used together with a failed microprocessor because of the effective use of hardware resources and cost performance. There is a problem from the point of view.

As a technique for dealing with this type of problem, as in the multiprocessor system disclosed in Patent Document 1, one spare processor card is provided for a plurality of processor cards having a microprocessor and a memory. It has been proposed that when a failure occurs in a processor card, the function of the processor card is completely transferred to a spare processor card so that the processing request command can be prevented from being lost and the processing can be continued.
However, in this multiprocessor system, since only one spare processor card can replace the function of the processor card, even if a failure occurs in a plurality of processor cards, the function of one of the processor cards can be changed. It can only be taken over, and it cannot deal with failures of multiple processor cards at the same time. Alternatively, a plurality of spare processor cards may be provided to cope with failures of a plurality of processor cards. In such a case, however, a number of spare processor cards that are not normally used must be arranged on the same system. This causes cost problems.

International Publication No. W02004 / 0779573

  Therefore, the problem of the present invention is to improve the inconveniences of the prior art, without greatly modifying the structure of the information processing apparatus itself, and without using a special protocol. An object of the present invention is to provide a failure processing method for an information processing apparatus and an information processing apparatus capable of coping with the occurrence of a failure of a plurality of microprocessors and effectively using a memory under the microprocessor.

In the failure processing method for an information processing apparatus according to the present invention, a plurality of arithmetic processing units each including a combination of a microprocessor and a memory are provided, and the microprocessors of the respective arithmetic processing units are connected so as to be able to transmit information to perform parallel arithmetic processing. A failure processing method for an information processing device for using a memory under the microprocessor when a failure occurs in the microprocessor of the information processing device to be performed.
A data switching control unit for switching the information transmission path is provided between the microprocessor and the memory for each arithmetic processing unit, and at least two or more data switching control units are connected so as to transmit information,
When a failure occurs in any of the microprocessors, the microprocessor of the arithmetic processing unit having the data switching control unit connected to the data switching control unit of the arithmetic processing unit having the failed microprocessor is selected to Delegate data transfer of the resulting microprocessor memory,
Depending on the input source of the transfer data to each data switching control unit, the transfer data input source to the data switching control unit is a memory and the microprocessor of the data switching control unit has a failure and the data When the transfer data input source to the switching control unit is a microprocessor and the destination address specification exceeds the normal physical address of the memory in the relevant processing unit, the destination processing unit and the destination type Is attached to the transfer data, while the input source of the transfer data to the data switching control unit is another data switching control unit and the transfer destination is in the arithmetic processing unit of the data switching control unit Has a configuration characterized in that the header is deleted from the transfer data.

Acts as a proxy for data transfer to the memory under the failed microprocessor by selecting the microprocessor of the arithmetic processing unit having the data switching control unit connected to the data switching control unit of the arithmetic processing unit having the failed microprocessor In other words, among the microprocessors provided in each of the plurality of arithmetic processing units, a microprocessor that does not cause a failure is a configuration that performs data transfer of a memory under the failure of the microprocessor that has failed. Even if a special spare processor card or spare arithmetic processing unit is not redundantly provided, data transfer to the memory under the faulty microprocessor can be realized. Furthermore, by using the virtual mapping technology, a microprocessor without a failure can perform data transfer of the memory of two or more arithmetic processing units separately from the regular memory under the microprocessor, It is also possible to select two or more microprocessors that have not failed, and to transfer the data in the memory under the other microprocessor that has failed, so that there is a failure in two or more microprocessors. Even if it occurs, it is possible to realize data transfer of the memory under each microprocessor in which the failure has occurred.
In addition, when a failure occurs in the microprocessor, data is written to and read from the memory under the microprocessor in which the failure has occurred, and the data of the arithmetic processing unit having the microprocessor in which the failure has occurred is switched. Data switching control is performed according to the input source of the transfer data to each data switching control unit because it is performed via the control unit and the data switching control unit of another arithmetic processing unit connected to the data switching control unit. Information required for data transfer between copies, that is, headers that specify the processing unit of the transfer destination and the type of transfer destination are attached to or deleted from the transfer data by internal processing of each data switching control unit The protocol used to transfer data between the microprocessor and memory is itself Ku without changing, can be addressed to the data transfer memory under microprocessor occurring failures.

The information processing apparatus according to the present invention includes a plurality of arithmetic processing units each including a combination of a microprocessor and a memory, and performs parallel arithmetic processing by connecting the microprocessors of the respective arithmetic processing units so that information can be transmitted. In order to achieve the same problem as described above,
A data switching control unit for switching the information transmission path is provided between the microprocessor and the memory for each arithmetic processing unit, and at least two or more data switching control units are connected to transmit information,
Usable to store the correspondence relationship between the microprocessor of each arithmetic processing unit and the arithmetic processing unit that can substitute the data transfer of the memory in the other arithmetic processing unit via the data switching control unit of the arithmetic processing unit Stores the correspondence relationship between the gateway storage table, the microprocessor of each arithmetic processing unit, and the arithmetic processing unit in which the microprocessor performs the data transfer of the memory via the data switching control unit of the arithmetic processing unit. When a failure occurs in one of the microprocessors, the correspondence relationship between the microprocessor and the arithmetic processing unit is assumed that the microprocessor in which the failure has occurred is acting as the data transfer for the memory in all other arithmetic processing units. Used gateway to remember Deploying a table storage memory and a 憶 table,
Each of the data switching control units includes a state storage register for storing the presence or absence of a failure of the microprocessor of the arithmetic processing unit provided with the data switching control unit, and a memory of the arithmetic processing unit provided with the data switching control unit A transfer alternative microprocessor storage register for storing an arithmetic processing unit having a microprocessor that should perform the data transfer of the data, and a microprocessor of the arithmetic processing unit provided with the data switching control unit should perform the data transfer of the memory The transfer alternative domain storage register that stores the arithmetic processing unit, the input source of the transfer data to the data switching control unit and the state of the state storage register are determined, and the input source of the transfer data to the data switching control unit is Memory and the state storage register indicates a fault. And when the transfer data input source to the data switching control unit is a microprocessor and the transfer destination address specification exceeds the normal physical address of the memory in the operation processing unit, While the header specifying the type of processing unit and transfer destination is attached to the transfer data, the input source of the transfer data to the data switching control unit is another data switching control unit, and the transfer destination is the data switching control unit. A data conversion unit that deletes the header from the transfer data when it is in the arithmetic processing unit,
When a failure occurs in the microprocessor of any of the arithmetic processing units, the arithmetic processing unit can refer to the available gateway storage table and the used gateway storage table to perform data transfer in the memory of the failed microprocessor. An arithmetic processing unit having a microprocessor not stored in the used gateway storage table is selected and stored in the transfer alternative microprocessor storage register of the data switching control unit of the failed microprocessor, while the selected The arithmetic processing unit having the failed microprocessor is stored in the transfer substitution domain storage register of the arithmetic processing unit, and the microprocessor of the selected arithmetic processing unit stores the data of the arithmetic processing unit. The data transfer of the memory of the arithmetic processing unit having the faulty microprocessor via the control unit, and the faulty microprocessor transfers the data of the memory in all other arithmetic processing units The used gateway storage table is updated and set as an agent, and operation status update setting means for storing the occurrence of the failure in the state storage register of the data switching control unit of the failed microprocessor is provided. It has the structure characterized by these.

In the above configuration, the available gateway storage table in the table storage memory stores the microprocessor data of each arithmetic processing unit and the data in the memory in the other arithmetic processing unit via the data switching control unit of the arithmetic processing unit. transfer stores the correspondence between the operation processing unit capable behalf, also, a table stored in the the used gateway storage table in the memory, the data switching control of the microprocessor and the microprocessor the processing unit of each processing unit The correspondence relationship with the arithmetic processing unit acting as a proxy for the data transfer of the memory via the unit is stored. Specifically, the data transfer of the memory can be performed between the microprocessors of the arithmetic processing units in which the data switching control units are mutually connected. Since the presence / absence of connection between the data switching control units has been clarified before the operation of the information processing apparatus, the contents of the usable gateway storage table can be set in advance. In addition, since there is no faulty microprocessor at the start of the operation of the information processing apparatus, the used gateway storage table in the table storage memory is an arithmetic process that performs the data transfer of the arithmetic processing unit memory. The unit is initially set as not present.
When a failure occurs in the microprocessor of any arithmetic processing unit, the operation status update setting unit of the information processing apparatus refers to the available gateway storage table and the used gateway storage table in the table storage memory, and The data switching control unit of the microprocessor in which a failure has occurred by selecting an arithmetic processing unit having a microprocessor that is not stored in the used gateway storage table from among the arithmetic processing units that can perform data transfer of the generated microprocessor memory The processing is stored in the transfer alternative microprocessor storage register, and the processing unit having the failed microprocessor is stored in the transfer replacement domain storage register of the selected processing unit. Therefore, the data switching control unit of the arithmetic processing unit having the failing microprocessor can recognize which arithmetic processing unit's microprocessor substitutes for the data transfer of the memory of this arithmetic processing unit, In addition, the data switching control unit of the selected arithmetic processing unit can recognize which arithmetic processing unit's memory data transfer is replaced by the microprocessor of the arithmetic processing unit.
The operation status update setting means of the information processing apparatus further includes a memory of the arithmetic processing unit in which the microprocessor of the selected arithmetic processing unit has the failed microprocessor via the data switching control unit of the arithmetic processing unit. In addition, the used gateway storage table is updated and set so that the failed microprocessor is acting as the data transfer for the memory in all other arithmetic processing units. The occurrence of the failure is stored in the state storage register of the data switching control unit of the microprocessor.
As a result of the updated setting of the used gateway storage table in this way, even if a failure occurs in the microprocessor of another processing unit after that, the data transfer of the memory of another processing unit is already performed. A microprocessor that has failed or a microprocessor that has failed itself is no longer selected as a proxy for data transfer in the memory of the arithmetic processing unit that has the failed microprocessor.
On the other hand, each time the transfer data input to the data switching control unit is confirmed, the data switching control unit of each arithmetic processing unit determines the input source of the transfer data and the state of the state storage register.
When the input source of the transfer data to the data switching control unit is a memory and the state storage register stores a failure, the data conversion unit of the data switching control unit Attach a header that specifies the type of transfer destination to the transfer data. That is, since the data switching control unit is provided between the microprocessor and the memory of each arithmetic processing unit, the fact that the input source of the transfer data is the memory means that the transfer data is input from the subordinate memory. At this time, if the state storage register of the data switching control unit stores the occurrence of a failure, transfer data cannot be input to the microprocessor of the arithmetic processing unit. The data conversion unit of the control unit attaches a header specifying the transfer destination arithmetic processing unit and the transfer destination type to the transfer data, and then the data switching control unit of another arithmetic processing unit connected to the data switching control unit Forward to. Specifically, as the processing unit of the transfer destination, the processing unit stored at that time is designated in the transfer alternative microprocessor storage register of the data switching control unit, and the type of transfer destination is the micro processor. A processor will be specified.
In addition, even when the input source of the transfer data to the data switching control unit is a microprocessor and the address designation of the transfer destination exceeds the normal physical address of the memory in the arithmetic processing unit, the data switching control unit The data conversion unit attaches a header that specifies the processing unit of the transfer destination and the type of transfer destination to the transfer data, and then transfers it to the data switching control unit of another processing unit connected to the data switching control unit To do. As described above, since the data switching control unit is provided between the microprocessor and the memory of each arithmetic processing unit, the fact that the input source of the transfer data is the microprocessor has the data switching control unit. This means that there is no failure in the microprocessor of the arithmetic processing unit, and that the address designation of the transfer destination exceeds the normal physical address of the memory in the arithmetic processing unit. This is because it means that the processor substitutes the data transfer to be performed by the microprocessor of another arithmetic processing unit by the virtual mapping technique. Specifically, as the processing unit of the transfer destination, the processing unit stored at that time in the transfer substitution domain storage register of the data switching control unit, that is, the microprocessor of the processing unit at this time transfers the data. An arithmetic processing unit having an alternative microprocessor is designated, and a memory is designated as the transfer destination type.
On the other hand, if the input source of the transfer data to the data switching control unit is another data switching control unit and the transfer destination is in the arithmetic processing unit of the data switching control unit, this transfer data is finally Is input to the microprocessor or memory of the processing unit, and whether the destination is a microprocessor or a memory depending on the type of transfer destination recorded in the header attached to the transfer data. Since it is clear, the data conversion unit of the data switching control unit deletes the header from the transfer data, performs packet conversion in the same manner as before, and transfers the transfer data to the microprocessor or memory of the arithmetic processing unit. Whether or not the transfer destination of the transfer data is in the arithmetic processing unit of the data switching control unit includes the arithmetic processing unit of the transfer destination recorded in the initial header and the data switching control unit. It can be determined based on the relationship with the arithmetic processing unit. If the processing unit of the transfer destination recorded in the original header does not match the processing unit in which the data switching control unit is arranged, another data switching control unit is provided via this data switching control unit. The data conversion unit of the data switching control unit does not perform the process of deleting the header from the transfer data, and the other arithmetic processing unit connected to the data switching control unit. The transfer data is transferred as it is to the data switching control unit.
As described above, when a failure occurs in the microprocessor, the writing of data to the memory under the microprocessor in which the failure has occurred and the reading of data from the memory have the microprocessor in which the failure has occurred. Transfer data transfer between each data switching control unit is performed via the data switching control unit of the arithmetic processing unit and the data switching control unit of another arithmetic processing unit connected to the data switching control unit. Only the header used to specify the processing unit of the transfer destination and the type of the transfer destination is used at the time, so the protocol itself used for data transfer between the microprocessor and the memory is not changed at all. Deal with data transfer in the memory under the failing microprocessor Can.
In addition, among the microprocessors provided in each of the plurality of arithmetic processing units, a microprocessor in which no failure has occurred is configured to perform the data transfer of the memory under the failure of the microprocessor in which the failure has occurred. Even without redundantly arranging a processor card and a spare arithmetic processing unit, it is possible to realize data transfer to a memory under the microprocessor in which a failure has occurred. By using the virtual mapping technology, a microprocessor without a failure can perform data transfer of the memory of two or more arithmetic processing units separately from the regular memory under the microprocessor, It is also possible to select two or more microprocessors that have not failed and substitute the data transfer of the memory under the other microprocessor that has failed, so that two or more microprocessors have failed. Even in this case, it is possible to realize data transfer of the memory under each microprocessor in which the failure occurs.

  The operation status update setting means of the information processing apparatus may be configured by a microprocessor independent of each arithmetic processing unit, or may be configured by firmware of the information processing apparatus.

  The failure processing method and information processing apparatus of an information processing apparatus according to the present invention selects a microprocessor of an arithmetic processing unit having a data switching control unit connected to a data switching control unit of the arithmetic processing unit having the failed microprocessor. In other words, the configuration is such that the data transfer of the memory under the faulty microprocessor is substituted, that is, among the microprocessors provided in each of the plurality of processing units, the faultless microprocessor is the faulty microprocessor. Data transfer to the memory under the processor, so that data transfer to the memory under the faulty microprocessor can be performed without redundant provision of a special spare processor card or spare arithmetic processing unit. Can be realized.

  Furthermore, if virtual mapping technology is used, a microprocessor in which no failure has occurred can transfer the data in the memory of two or more arithmetic processing units separately from the regular memory under the microprocessor, It is also possible to select two or more microprocessors that have not failed and substitute the data transfer of the memory under the other microprocessor that has failed, so that two or more microprocessors have failed. Even in such a case, it is possible to realize data transfer to the memory under each microprocessor in which a failure has occurred.

  In addition, when a failure occurs in the microprocessor, data is written to and read from the memory under the microprocessor in which the failure has occurred, and the data of the arithmetic processing unit having the microprocessor in which the failure has occurred is switched. Data switching control is performed according to the input source of the transfer data to each data switching control unit because it is performed via the control unit and the data switching control unit of another arithmetic processing unit connected to the data switching control unit. Information required for data transfer between copies, that is, headers that specify the processing unit of the transfer destination and the type of transfer destination are attached to or deleted from the transfer data by internal processing of each data switching control unit The protocol used to transfer data between the microprocessor and memory is itself Ku without changing, can be addressed to the data transfer memory under microprocessor occurring failures.

  Next, the best mode for carrying out the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram showing an outline of a configuration of an information processing apparatus according to an embodiment to which a failure processing method of the present invention is applied.

  The information processing apparatus 1 is an information processing apparatus that includes four arithmetic processing units each including a combination of a microprocessor and a memory, and performs parallel arithmetic processing by connecting the microprocessors of the respective arithmetic processing units so that information can be transmitted. is there.

  Since the four sets of arithmetic processing units have the same configuration, the structure will be described here by taking up one arithmetic processing unit 2a. The arithmetic processing unit 2a includes one microprocessor 3a and four memories (Dual Inline Memory Modules) 4a, 5a, 6a, 7a, and data for switching an information transmission path between the microprocessor 3a and the memory 4a. A switching control unit 8a is provided.

  The configuration of the other three arithmetic processing units 2b, 2c, and 2d is the same as that of the arithmetic processing unit 2a. Among them, the data switching control unit 8a of the arithmetic processing unit 2a and the data switching control unit of the arithmetic processing unit 2b 8b, and the data switching control unit 8c of the arithmetic processing unit 2c and the data switching control unit 8d of the arithmetic processing unit 2d are connected so as to be able to transmit information.

  Further, the microprocessors 3a, 3b, 3c, 3d of the respective arithmetic processing units 2a, 2b, 2c, 2d are all connected so as to be able to transmit information because of the parallel arithmetic processing.

  Next, the configuration of the data switching control units 8a, 8b, 8c, and 8d, which are components unique to this embodiment, will be described with reference to the functional block diagram of FIG. 2 taking the data switching control unit 8a as an example.

  The data switching control unit 8a is provided with a state storage register 9 for storing the presence or absence of a failure of the microprocessor 3a of the arithmetic processing unit 2a provided with the data switching control unit 8a, and the data switching control unit 8a. When a failure occurs in the microprocessor 3a of the arithmetic processing unit 2a, the arithmetic processing unit for storing the data transfer of the memories 4a, 5a, 6a, 7a provided in the arithmetic processing unit 2a is stored. Transfer alternative domain storage for storing the transfer alternative microprocessor storage register 10 and other arithmetic processing units in which the microprocessor 3a of the arithmetic processing unit 2a provided with the data switching control unit 8a should perform the data transfer of the memory The register 11 and the data switching control unit 8a are provided. In order to store the self-domain storage register 12 for storing the number of the arithmetic processing unit 2a as a domain name and the maximum number of memory connections that can be mounted in the arithmetic processing unit 2a provided with the data switching control unit 8a. Connection memory number storage register 13, output destination changeover switch 14, data converter 15, and routing table 22.

  The arithmetic processing unit 2a is provided with four memories 4a, 5a, 6a, and 7a. Since the value corresponding to the first memory 4a is defined as 0, the number of connected memories is stored. The value of the maximum number of connected memories actually stored in the register 13 is “3”.

  The output destination changeover switch 14 includes an information transmission path for connecting the microprocessor 3a and the memory 4a in the arithmetic processing unit 2a provided with the data changeover control unit 8a, one of the memory 4a and the microprocessor 3a, and the other. An information transmission path for connecting the data switching control unit 8b of the arithmetic processing unit 2b and an information transmission path for connecting either the memory 4a or the microprocessor 3a and a data switching control unit of another arithmetic processing unit. This is a switch for selectively closing one of the information transmission paths from the inside.

Further, the data conversion unit 15 performs packet conversion of transfer data, and also performs an arithmetic processing unit or transfer destination as a transfer destination for transfer data input / output to / from the data switching control unit 8a via the output destination changeover switch 14. A function for attaching or deleting a header designating the type of memory (either memory or microprocessor) is provided.
Specifically, the input source of the transfer data to the data switching control unit 8a and the state of the state storage register 9 of the data switching control unit 8a are determined, and the input source of the transfer data to the data switching control unit 8a is When the memory 4a, 5a, 6a, 7a and the state storage register 9 stores a failure, the input source of the transfer data to the data switching control unit 8a is the microprocessor 3a, and the transfer destination address is specified. When the normal physical address of the memory in the arithmetic processing unit 2a (the value of the number of connected memories is 3) is exceeded, a header specifying the processing unit of the transfer destination and the type of the transfer destination is attached to the transfer data While transferring to another data switching control unit (data switching control unit 8b in the examples of FIGS. 1 and 2), the data switching control unit 8a When the transfer data input source is another data switching control unit (data switching control unit 8b in the examples of FIGS. 1 and 2) and the transfer destination is in the arithmetic processing unit 2a of the data switching control unit 8a. When the designation of the transfer destination by the header is the arithmetic processing unit 2a, the header is deleted from the transfer data, and the transfer data is transferred to the microprocessor 3a or the memories 4a, 5a, 6a, 7a according to the type designation by the header.

  The main part of the data conversion unit 15 is configured by a switching control microprocessor 23 mounted in the data switching control unit 8a, and the output destination switching switch 14 is driven and controlled by the switching control microprocessor 23. Further, the switching control microprocessor 23 accesses the status storage register 9, the transfer alternative microprocessor storage register 10, the transfer alternative domain storage register 11, the self domain storage register 12, the connected memory number storage register 13, and the routing table 22. Is possible.

  An outline of the structure of the header attached to the transfer data is shown in the conceptual diagram of FIG. The main part of the header designates a domain designation unit 19 for designating one of the arithmetic processing units 2a, 2b, 2c, and 2d as a data transfer destination and whether the transfer destination is a microprocessor or a memory. It is comprised with the type designation | designated part 20. FIG.

  Since the data switching control unit 8a is provided with a routing table 22 that stores the correspondence between the data transfer destinations and the data transfer paths, the switching control microprocessor 23 is clear even the data transfer destinations. For example, the data transfer path corresponding to the data transfer destination is searched from the routing table 22, and the data is transferred to the target transfer destination via the other data switching control unit or the microprocessor of another arithmetic processing unit. It is possible to transfer.

  The configuration of the data switching control units 8b, 8c, and 8d is basically the same as that of the above-described data switching control unit 8a, and only the connection relationship of the output destination switching switch 14 in each data switching control unit 8b, 8c, 8d. This is different from the data switching control unit 8a. The connection relationship of the output destination changeover switch 14 is as shown in FIG. 1, and the data switching control unit 8a of the arithmetic processing unit 2a, the data switching control unit 8b of the arithmetic processing unit 2b, and the data switching control of the arithmetic processing unit 2c. The unit 8c and the data switching control unit 8d of the arithmetic processing unit 2d are connected so as to be able to transmit information.

  Usable to store the correspondence relationship between the microprocessor of each arithmetic processing unit and the arithmetic processing unit that can substitute the data transfer of the memory in the other arithmetic processing unit via the data switching control unit of the arithmetic processing unit Use for storing the correspondence relationship between the gateway storage table 16, the microprocessor of each arithmetic processing unit, and the arithmetic processing unit in which the microprocessor performs the data transfer of the memory via the data switching control unit of the arithmetic processing unit As shown in FIG. 1, the completed gateway storage table 17 is provided in a table storage memory 18 composed of a nonvolatile RAM or the like installed in the information processing apparatus 1.

  The logical configuration of the available gateway storage table 16 is shown in the conceptual diagram of FIG. 4, and the logical configuration of the used gateway storage table 17 is shown in the conceptual diagram of FIG.

  Each of the numbers 0, 1, 2, 3 in the row direction of the available gateway storage table 16 shown in FIG. 4 corresponds to the arithmetic processing units 2a, 2b, 2c, 2d, and the numbers 0, 1, 1, in the column direction. 2 and 3 correspond to the microprocessors 3a, 3b, 3c and 3d, respectively. In the example shown in FIG. 1, the data switching control unit 8a of the arithmetic processing unit 2a and the data switching control unit 8b of the arithmetic processing unit 2b, and the data switching control of the data switching control unit 8c of the arithmetic processing unit 2c and the arithmetic processing unit 2d. Since the unit 8d is connected to be able to transmit information, only the microprocessor 3b of the arithmetic processing unit 2b can replace the data transfer of the memories 4a, 5a, 6a, and 7a of the arithmetic processing unit 2a. The first row of the possible gateway storage table 16 is set to 0, 1, 0, 0 by the process at the time of initial setting. Here, the value “1” set in the [1,2] spot corresponding to the [arithmetic processing unit 2a, microprocessor 3b] indicates that the microprocessor 3b of the arithmetic processing unit 2b gives the microprocessor 3a of the arithmetic processing unit 2a. Instead, the value indicates that the data transfer in the memories 4a, 5a, 6a, and 7a of the arithmetic processing unit 2a can be replaced. Since only the microprocessor 3a of the arithmetic processing unit 2a can replace the data transfer of the memories 4b, 5b, 6b, and 7b of the arithmetic processing unit 2b, the second row of the available gateway storage table 16 includes 1, 0, 0, 0 is set in the process at the time of initial setting. As described above, the value “1” set in the [2,1] spot corresponding to [the arithmetic processing unit 2b, the microprocessor 3a] indicates that the microprocessor 3a of the arithmetic processing unit 2a is the microprocessor 3b of the arithmetic processing unit 2b. Instead of the data transfer in the memories 4b, 5b, 6b, 7b of the arithmetic processing unit 2b. Similarly, only the microprocessor 3d of the arithmetic processing unit 2d can replace the data transfer in the memories 4c, 5c, 6c, and 7c of the arithmetic processing unit 2c. Is set to 0, 0, 0, 1 in the initial setting process. The value “1” set in the [3,4] spot corresponding to the [arithmetic processing unit 2c, microprocessor 3d] is calculated by replacing the microprocessor 3d of the arithmetic processing unit 2d with the microprocessor 3c of the arithmetic processing unit 2c. The value indicates that the data transfer in the memories 4c, 5c, 6c, and 7c of the processing unit 2c can be replaced. Since only the microprocessor 3c of the arithmetic processing unit 2c can replace the data transfer of the memories 4d, 5d, 6d, and 7d of the arithmetic processing unit 2d, the fourth row of the available gateway storage table 16 includes In the initial setting process, 0, 0, 1, 0 are set. The value “1” set in the [4, 3] spot corresponding to [the arithmetic processing unit 2d, the microprocessor 3c] is calculated by the microprocessor 3c of the arithmetic processing unit 2c instead of the microprocessor 3d of the arithmetic processing unit 2d. The value indicates that the data transfer in the memories 4d, 5d, 6d, and 7d of the processing unit 2d can be replaced.

  The logical configuration of the used gateway storage table 17 is substantially the same as the logical configuration of the available gateway storage table 16, and the numbers 0, 1, 2, and 2 in the row direction of the used gateway storage table 17 shown in FIG. 3 corresponds to the arithmetic processing units 2a, 2b, 2c, and 2d, and the numbers 0, 1, 2, and 3 in the column direction correspond to the microprocessors 3a, 3b, 3c, and 3d, respectively. Since there is no faulty microprocessor at the start of operation of the information processing apparatus 1, the used gateway storage table 17 is used to transfer the data of the memories of the other arithmetic processing units 2a, 2b, 2c, and 2d. Assuming that no microprocessor is present, all the columns from [1, 1] spot to [4, 4] spot indicate that the memory data transfer is not performed in the initial setting process. “0” is set as shown in FIG. Specifically, for example, the [1,2] spot value “0” in the used gateway storage table 17 of FIG. 7 indicates that the microprocessor 3b of the arithmetic processing unit 2b replaces the microprocessor 3a of the arithmetic processing unit 2a. The value indicates that the data transfer of the memories 4a, 5a, 6a, and 7a of the arithmetic processing unit 2a is not substituted. If the value “1” is set in the [1,2] spot in the used gateway storage table 17, the meaning of the value “1” is calculated by the microprocessor 3b of the arithmetic processing unit 2b. Instead of the microprocessor 3a of the unit 2a, the data transfer of the memories 4a, 5a, 6a and 7a of the arithmetic processing unit 2a is replaced.

  As shown in FIG. 1, the operation status update setting means in this embodiment is implemented by a failure processing microprocessor 21 provided in the information processing apparatus 1 independently of each arithmetic processing unit 2a, 2b, 2c, 2d. It is configured.

  The failure processing microprocessor 21 functioning as the operation status update setting means has the data switching control units 8a, 8b, 8c, 8d via the switching control microprocessors 23 of the data switching control units 8a, 8b, 8c, 8d. Operations such as initial setting processing and data rewriting for each state storage register 9, each transfer alternative microprocessor storage register 10, each transfer alternative domain storage register 11, each self domain storage register 12, and each connected memory number storage register 13. So that information can be transmitted to all of the data switching control units 8a, 8b, 8c, and 8d. At the same time, the microprocessors 3a, 3b, 3c, and 3d are also connected to the respective microprocessors 3a, 3b. , 3c, 3d so that failure notification signals can be read Connected, further connected available gateway storage table 16 and the used gateway storage initialization data for the table 17 and the reference and the rewrite process can be manner also for the table storing memory 18.

  Next, an outline of initialization processing executed by each switching control microprocessor 23 functioning as a data conversion unit in the data switching control units 8a, 8b, 8c, 8d of the arithmetic processing units 2a, 2b, 2c, 2d will be described. To do.

  Here, the initialization process executed by the switching control microprocessor 23 of the data switching control unit 8a will be described as an example. However, the initialization process by each switching control microprocessor 23 of the data switching control units 8b, 8c, and 8d is also substantial. The content is equivalent.

  Upon initialization of the system, the switching control microprocessor 23 of the data switching control unit 8a first sets a value “0” indicating that the data switching control unit 8a is under the control of the arithmetic processing unit 2a to the data switching control unit 8a. Set in the self-domain storage register 12 (see FIG. 8).

  Similarly, the microprocessor 23 for switching control of the data switching control unit 8b sets the value “1” indicating that the data switching control unit 8b is under the arithmetic processing unit 2b to the self-domain storage register 12 of the data switching control unit 8b. The switching control microprocessor 23 of the data switching control unit 8c sets the value “2” indicating that the data switching control unit 8c is under the arithmetic processing unit 2c to the self-domain storage register 12 of the data switching control unit 8c. The switching control microprocessor 23 of the data switching control unit 8d sets the value “3” indicating that the data switching control unit 8d is under the control of the arithmetic processing unit 2d to the self-domain storage register 12 of the data switching control unit 8d. Set to.

  Next, an outline of the initial setting process of the usable gateway storage table 16 executed by the failure processing microprocessor 21 of the information processing apparatus 1 will be described with reference to the flowchart of FIG.

  The failure processing microprocessor 21 that has started the initial setting process first polls the switching control microprocessor 23 mounted on the data switching control unit 8a under the arithmetic processing unit 2a to output the data switching control unit 8a. It is confirmed whether or not the destination changeover switch 14 is connected to the output destination changeover switch of another data changeover control unit (step a1), and the data changeover control connected to the output destination changeover switch 14 of the data changeover control unit 8a. It can be used for the arithmetic processing unit having a section, assuming that the microprocessor under the arithmetic processing unit can replace the data transfer of the memories 4a, 5a, 6a and 7a of the arithmetic processing unit 2a. [Operation processing unit 2a, connection of gateway storage table 16] Microprocessor of previous arithmetic processing unit] A value “1” indicating substitution is set in the spot column (step a2), while the data switching control unit not connected to the output destination switching switch 14 of the data switching control unit 8a It is assumed that the microprocessor under the arithmetic processing unit cannot be used as a substitute for the data transfer of the memories 4a, 5a, 6a and 7a of the arithmetic processing unit 2a. A value “0” indicating that substitution is not possible is set in the column of [arithmetic processing unit 2a, microprocessor of arithmetic processing unit not connected to] in the storage table 16 (step a3).

As already described, in the example shown in FIG. 1, the data switching control unit 8a of the arithmetic processing unit 2a and the data switching control unit 8b of the arithmetic processing unit 2b are connected so as to be able to transmit information. Only the microprocessor 3b of the arithmetic processing unit 2b can replace the data transfer of 4a, 5a, 6a, and 7a, and the first row of the available gateway storage table 16 has 0, 1 as shown in FIG. , 0, 0 are set.
Note that the [1, 1] spot [operation processing unit 2a, microprocessor 3a of operation processing unit 2a] field is set to “1” because the microprocessor 3a has a failure when the microprocessor 3a fails. This is because the processing cannot be replaced by the microprocessor 3a.

  Thereafter, the failure processing microprocessor 21 sequentially polls the replacement control microprocessor 23 of the data switching control units 8b, 8c, and 8d under the arithmetic processing units 2b, 2c, and 2d, similarly to the above, as shown in FIG. By repeatedly executing the initial setting process, 1, 0, 0, 0 is stored in the second row of the available gateway storage table 16, and 0, 0, 0, 1 is stored in the third row of the available gateway storage table 16. 0, 0, 1, 0 are set in the fourth row of the available gateway storage table 16 (see FIG. 6).

  Further, since there is no faulty microprocessor at the start of operation of the information processing apparatus 1, the used gateway storage table 17 has a microprocessor acting as a proxy for data transfer in the memory of another arithmetic processing unit. Is present in all the columns [1, 1] to [4, 4], the value “0” indicating that the data transfer of the memory is not performed by the failure processing microprocessor 21. Similarly, the arithmetic processing to which the data switching control units 8a, 8b, 8c, and 8d belong to all the state storage registers 9 of the data switching control units 8a, 8b, 8c, and 8d. The value “Enable” indicating that there is no failure in the microprocessors 3a, 3b, 3c, 3d of the units 2a, 2b, 2c, 2d is, for example, It is set as shown in 8.

  Furthermore, since all four memories are provided in the arithmetic processing units 2a, 2b, 2c, and 2d, the connection memory number storage register 13 of the data switching control units 8a, 8b, 8c, and 8d includes, for example, Taking the data switching control unit 8a as an example, as shown in FIG. 8, all “3” are set. As described above, the maximum number of connections is set to “3” because the value corresponding to the first memory is defined as 0.

  Next, when a failure occurs in the microprocessor of any of the arithmetic processing units, the status storage register 9, the transfer replacement microprocessor storage register 10, the transfer replacement executed by the failure processing microprocessor 21 as operation status update setting means The setting update processing of the domain storage register 11 and the used gateway storage table 17 will be described with reference to the flowchart of FIG.

  Here, the case where a failure occurs in the microprocessor 3a of the arithmetic processing unit 2a will be described as an example, but the processing in the case where a failure occurs in the microprocessors 3b, 3c, 3d of the other arithmetic processing units 2b, 2c, 2d is also described. It is the same as this.

When a failure notification signal from the microprocessor 3a of the arithmetic processing unit 2a is detected, the failure processing microprocessor 21 functioning as an operation status update setting unit first stores information corresponding to the arithmetic processing unit 2a. The first row of the gateway storage table 16 and the first row of the used gateway storage table 17 storing information corresponding to the arithmetic processing unit 2a are searched (step b1), and the operation to which the failed microprocessor 3a belongs is searched. It is determined whether there is a microprocessor capable of acting as a proxy for data transfer of the memories 4a, 5a, 6a, 7a provided in the processing unit 2a. Can replace the data transfer of other microprocessors It determines Luke (step b2).
In the example of the usable gateway storage table 16 in FIG. 6, the microprocessor 3b of the arithmetic processing unit 2b can replace the processing of the microprocessor 3a of the arithmetic processing unit 2a (see [1,2] spot in FIG. 6). As shown in the used gateway storage table 17 of FIG. 7, the microprocessor 3b of the arithmetic processing unit 2b does not transfer the data in the memory of other arithmetic processing units at this time (see the second column in FIG. 7). The microprocessor 3b of the arithmetic processing unit 2b is selected as a microprocessor that replaces the data transfer in the memories 4a, 5a, 6a, and 7a under the microprocessor 3a of the arithmetic processing unit 2a that has newly failed. Become.

  Therefore, the failure processing microprocessor 21 functioning as the operation status update setting means sets the value “1” representing the operation processing unit 2b having the microprocessor 3b to the data switching of the operation processing unit 2a having the failed microprocessor 3a. By setting the transfer substitution microprocessor storage register 10 in the control unit 8a, the data switching is performed when the microprocessor 3b is selected as the microprocessor that substitutes the data transfer of the memories 4a, 5a, 6a, and 7a of the arithmetic processing unit 2a. The memory in the control unit 8a (see step b3 and FIG. 11) and the transfer substitution domain storage register 11 in the data switching control unit 8b of the arithmetic processing unit 2b having the microprocessor 3b have a failed microprocessor. By setting the value “0” representing the arithmetic processing unit 2a having “a”, the microprocessor 3b is selected as the microprocessor that performs the data transfer of the memories 4a, 5a, 6a, and 7a of the arithmetic processing unit 2a. This is stored in the data switching control unit 8b (see step b4 and FIG. 12).

Next, the failure processing microprocessor 21 functioning as the operation status update setting means sets all the spots in the first row of the used gateway storage table 17 storing the information corresponding to the failed microprocessor 3a to be non-replaceable. By setting the value “1” to be indicated, it is stored that the failed microprocessor 3a cannot replace the data transfer of any other microprocessor, and the data transfer of the failed microprocessor 3a is replaced. By setting a value “1” indicating non-replacement to all the spots in the second row of the used gateway storage table 17 that stores information corresponding to the microprocessor 3b that is supposed to be transferred, the data transfer of the microprocessor 3a The load on the microprocessor 3b increases due to the replacement of Stores further no longer reserve capacity to replace the data transfer other microprocessor on the microprocessor 3b (see step b5, Figure 13).
Here, the process of setting the value “1” indicating non-replacement to all the spots in the first column of the used gateway storage table 17 is performed by the microprocessor 3a in which the failure has occurred in all the other arithmetic processing units 2b and 2c. , 2d is substantially equivalent to the processing for setting the used gateway storage table 17 on the assumption that the data transfer of the memory in 2d is performed.

  In this embodiment, it is assumed that one microprocessor replaces only the data transfer of the other microprocessor. However, depending on the processing capacity of the microprocessor and the setting of the virtual mapping, one microprocessor is the other. It is also possible to replace the data transfer of two or more microprocessors, and in such a case, information corresponding to the microprocessor 3b that has replaced the data transfer of the failed microprocessor 3a is obtained. It is not always necessary to set the value “1” indicating non-replacement to all the spots in the second row of the stored used gateway storage table 17, and it is not appropriate to replace only the [1,2] spots of the used gateway storage table 17. A value “1” indicating “1” is set and the microprocessor 3b further sets another value. It may be leave room for alternative data transfer microprocessor.

  Next, the failure processing microprocessor 21 functioning as the operation status update setting means sets a value “indicating the occurrence of the failure in the state storage register 9 in the data switching control unit 8a of the arithmetic processing unit 2a having the failed microprocessor 3a. “Disable” is set, and the fact that a failure has occurred in the microprocessor 3a of the arithmetic processing unit 2a to which the data switching control unit 8a belongs is stored in the data switching control unit 8a (see step b6 and FIG. 14), and the state storage register 9. The setting update processing of the transfer alternative microprocessor storage register 10, the transfer alternative domain storage register 11, and the used gateway storage table 17 is finished.

  Next, processing executed by the data switching control units 8a, 8b, 8c, and 8d in a situation where a failure occurs in the microprocessor of any arithmetic processing unit, in particular, the data switching control units 8a, 8b, 8c, and 8d. The processing operation of the switching control microprocessor 23 functioning as the data converter 15 will be described with reference to the flowchart of FIG.

  Here, as an example, a failure occurs in the microprocessor 3a of the arithmetic processing unit 2a, and the microprocessor 3b of the arithmetic processing unit 2b replaces the microprocessor 3a to transfer data to the memories 4a, 5a, 6a, and 7a of the arithmetic processing unit 2a. Although the case where it substitutes is demonstrated, the process when a failure occurs in the microprocessors 3b, 3c, 3d of the other arithmetic processing units 2b, 2c, 2d is the same as this.

  The switching control microprocessor 23 functioning as the data conversion unit 15 constantly monitors the input of the transfer data to the data switching control unit in which the switching control microprocessor 23 is installed, and confirms the input of the transfer data. Each time, the input source of the transfer data is determined (step c1).

  Here, when the input source of the transfer data to the data switching control unit is a memory, the data switching control unit is provided between the microprocessor and the memory of each arithmetic processing unit. It is clear that the data transfer is from a memory in the same arithmetic processing unit directly connected to the switching control unit.

  Therefore, the switching control microprocessor 23 functioning as the data conversion unit 15 further determines whether the setting state of the state storage register 9 of the data switching control unit is “Enable” or “Disable”. Determine (step c6).

When the setting state of the state storage register 9 is “Enable”, it means that no failure has occurred in the microprocessor of the arithmetic processing unit having the data switching control unit, and thus functions as the data conversion unit 15. The switching control microprocessor 23 controls the output destination changeover switch 14 to connect the memory in the arithmetic processing unit and the microprocessor in the arithmetic processing unit, and transfer data from the memory as it is to the arithmetic processing unit. (Step c7).
For example, when transfer data from the memories 4b, 5b, 6b, and 7b in the arithmetic processing unit 2b is input to the data switching control unit 8b in the arithmetic processing unit 2b, the data switching control is performed as shown in FIG. Since the setting state of the state storage register 9 of the unit 8b is “Enable”, the transfer data from the memories 4b, 5b, 6b, and 7b remains in the arithmetic processing unit 2b as it is via the data switching control unit 8b. To the microprocessor 3b (see X1 in FIG. 16).

On the other hand, if the determination result in step c6 is false, that is, if the setting state of the state storage register 9 is “Disable”, the microprocessor of the arithmetic processing unit having the data switching control unit is faulty. Therefore, data cannot be transferred from the subordinate memory to the microprocessor of the arithmetic processing unit. Accordingly, in this case, the switching control microprocessor 23 functioning as the data conversion unit 15 attaches a header specifying the transfer destination arithmetic processing unit and the transfer destination type to the transfer data (step c8), and outputs it. The destination switching switch 14 is controlled to connect the memory in the arithmetic processing unit to another data switching control unit connected to the data switching control unit, and the data switching control unit closest to the transfer destination is connected to the data switching control unit from the memory. The transfer data is sent out (step c9).
For example, when transfer data from the memories 4a, 5a, 6a, and 7a in the arithmetic processing unit 2a is input to the data switching control unit 8a in the arithmetic processing unit 2a, as shown in FIG. 14, the state storage register 9 is “Disable”, the switching control microprocessor 23 of the data switching control unit 8a refers to the transfer alternative microprocessor storage register 10 of the data switching control unit 8a as shown in FIG. Then, a value “1” representing the microprocessor 3b of the arithmetic processing unit 2b serving as the transfer destination is set in the domain specifying unit 19, and a header in which the type of the transfer destination microprocessor is set in the type specifying unit 20 is transferred data. And the output destination changeover switch 14 is connected to the data changeover control unit 8a. Connected to a certain data switching control unit 8b, the transfer data from the memories 4a, 5a, 6a, 7a in the arithmetic processing unit 2a is sent to the data switching control unit 8b (see X3 in FIG. 16). .

  Further, when the transfer data input source to the data switching control unit is a microprocessor in the determination process of step c1, the data switching control unit is provided between the microprocessor and the memory of each arithmetic processing unit. Therefore, it is clear that the data transfer is from the microprocessor in the same arithmetic processing unit directly connected to the data switching control unit.

  Therefore, the switching control microprocessor 23 functioning as the data conversion unit 15 further determines whether or not the addressing of the transfer destination memory of the transfer data exceeds the normal physical address of the memory in the arithmetic processing unit. Whether the addressing is within the range of the maximum number of connections “3” or the range of virtual mapping exceeding the maximum number of connections “3” (in this embodiment, one microprocessor transfers data to another microprocessor) Therefore, it is determined whether the address designation value in the virtual mapping is 4-7 (step c2).

If the address designation is within the range of the maximum number of connections “3” and the determination result of step c2 is true, it means that the transfer data is destined for the memory in the arithmetic processing unit. The switching control microprocessor 23 that functions as the data conversion unit 15 controls the output destination changeover switch 14 to connect the memory in the arithmetic processing unit and the microprocessor in the arithmetic processing unit to transfer data from the microprocessor. As it is to the memory in the arithmetic processing unit (step c3).
For example, when data is transferred from the microprocessor 3b of the arithmetic processing unit 2b to the memories 4b, 5b, 6b, and 7b of the arithmetic processing unit 2b, the address designation is within the range of the maximum connection number “3”. Transfer data from the processor 3b is transferred to the memories 4b, 5b, 6b, and 7b in the arithmetic processing unit 2b via the data switching control unit 8b (see X1 in FIG. 16).

On the other hand, if the determination result in step c2 is false, that is, if the address designation exceeds the range of the maximum number of connections “3”, the transfer data is originally stored in the microprocessor of the arithmetic processing unit. Although the data should not be transferred via the microprocessor, it is data that needs to be transferred because the microprocessor of the relevant processing unit replaces the data transfer of the microprocessor of another processing unit. Therefore, the switching control microprocessor 23 functioning as the data conversion unit 15 attaches a header specifying the processing unit of the transfer destination and the type of the transfer destination to the transfer data (step c4), and outputs it. Control the destination switch 14 to another data switching control unit connected to the data switching control unit. Connect the microprocessor in the processing unit, sends data transferred from the microprocessor of the arithmetic processing unit to the nearest data switching control unit to the destination (step c5).
For example, if transfer data from the microprocessor 3b of the arithmetic processing unit 2b is input to the data switching control unit 8b in the arithmetic processing unit 2b, and the address designation exceeds the range of the maximum connection number “3” at that time. The transfer data is not supposed to be transferred by the microprocessor 3b of the arithmetic processing unit 2b, but because the microprocessor 3a has a fault, the microprocessor 3b of the arithmetic processing unit 2b uses the virtual mapping address. Therefore, the switching control microprocessor 23 of the data switching control unit 8b uses the transfer substitution domain storage of the data switching control unit 8b as shown in FIG. Referring to the register 11, the processing unit serving as the transfer destination A value “0” representing 2a is set in the domain specifying unit 19 and a header in which the type of the transfer destination is set in the type specifying unit 20 is attached to the transfer data, and then the output destination changeover switch 14 is switched to the data Connected to the data switching control unit 8a connected to the control unit 8b, the transfer data from the microprocessor 3b in the arithmetic processing unit 2b is sent to the data switching control unit 8a (see X2 in FIG. 16). reference).

  Further, when the transfer data input source to the data switching control unit is another data switching control unit in the determination process of step c1, the data is transferred from the microprocessor or the memory in another arithmetic processing unit. It is clear.

  Therefore, the switching control microprocessor 23 functioning as the data conversion unit 15 further confirms that the transfer destination arithmetic processing unit specified in the transfer data header matches the arithmetic processing unit of the data conversion unit 15. It is determined whether or not (step c10).

When the processing unit of the transfer destination specified in the header of the transfer data matches a certain processing unit of the data conversion unit 15, the switching control microprocessor 23 functioning as the data conversion unit 15 Further, it is determined whether the type specified in the header of the transfer data is a microprocessor or a memory (step c11). If it is a memory, a header specifying the transfer destination and type is determined from the transfer data. Delete the packet and perform packet conversion of the transfer data as in the conventional case (step c12), control the output destination changeover switch 14 to connect the memory in the arithmetic processing unit and the input source data switching control unit, and Transfer data from the data switching control unit is delivered to the memory in the arithmetic processing unit (step c13). .
For example, the transfer data sent from the data switching control unit 8b of the arithmetic processing unit 2b using the virtual mapping address by the microprocessor 3b of the arithmetic processing unit 2b in the processing of steps c4 and c5 described above is the data of the arithmetic processing unit 2a. When input to the switching control unit 8a, the value “0” representing the arithmetic processing unit 2a that is the transfer destination is set in the domain specifying unit 19, and the memory that is the type of the transfer destination is set in the type specifying unit 20. Since the transfer data having the header is input from the data switching control unit 8b of the arithmetic processing unit 2b to the data switching control unit 8a of the arithmetic processing unit 2a, the arithmetic processing of the transfer destination specified by the header of the transfer data The value “0” representing the unit and the self of the data switching control unit 8a as shown in FIG. Since the value “0” in the main storage register 12 matches and the type specified in the header of the transfer data is a memory, the switching control microprocessor functions as the data conversion unit 15 of the data switching control unit 8a. 23 deletes a header consisting of a value “0” (domain specifying unit 19) indicating the arithmetic processing unit 2a that is a transfer destination and a type specification (type specifying unit 20) indicating a memory from the transfer data. The packet conversion of the transfer data is performed in the same manner as described above, and the output destination changeover switch 14 is controlled to connect the memories 4a, 5a, 6a and 7a in the arithmetic processing unit 2a to the input source data switching control unit 8b. The transfer data from the data switching control unit 8b is transferred to the memories 4a, 5a, 6a, and 7a in the arithmetic processing unit 2a. Becomes Doo (see X2 in FIG. 16).
Note that the packet conversion here is an operation for returning the addressing by virtual mapping to the original addressing used in the arithmetic processing unit, and only one data transfer of one microprocessor to another microprocessor is performed. In the present embodiment in which the maximum number of connections of the memory is “3”, the value “4” is subtracted from the address designation by the virtual mapping. Return to addressing. For example, the address designation by virtual mapping is “7” (the seventh memory virtualized on the arithmetic processing unit 2b (actually the eighth memory because the value corresponding to the first memory is defined as 0)). For example, the destination is converted to “3” (substantially the fourth memory because the value corresponding to the first memory is defined as 0 on the arithmetic processing unit 2a).

On the other hand, if the determination result in step c11 is false, that is, if the type specified in the header of the transfer data is a microprocessor, the switching control microprocessor 23 functioning as the data converter 15 is: The header designating the transfer destination and type is deleted from the transfer data, the transfer data packet conversion is performed in the same manner as in the prior art (step c14), the output destination changeover switch 14 is controlled, and the microprocessor in the arithmetic processing unit The input source data switching control unit is connected, and the transfer data from the input source data switching control unit is delivered to the microprocessor in the arithmetic processing unit (step c15).
For example, the transfer data of the memories 4a, 5a, 6a, and 7a in the arithmetic processing unit 2a is sent from the data switching control unit 8a in the arithmetic processing unit 2a in the above-described steps c8 and c9, and the data of the arithmetic processing unit 2b is transmitted. When input to the switching control unit 8b, the value “1” representing the arithmetic processing unit 2b that is the transfer destination is set in the domain specifying unit 19 and the microprocessor that is the type of the transfer destination is set in the type specifying unit 20. Since the transfer data having the specified header is input from the data switching control unit 8a of the arithmetic processing unit 2a to the data switching control unit 8b of the arithmetic processing unit 2b, the transfer destination specified by the header of the transfer data The value “1” representing the arithmetic processing unit and the self-domain of the data switching control unit 8b as shown in FIG. The value “1” in the data storage register 12 matches, and the type specified in the header of the transfer data is a microprocessor, so that the switching control microprocessor functioning as the data conversion unit 15 of the data switching control unit 8b. The processor 23 deletes the header composed of the value “1” (domain specifying unit 19) indicating the arithmetic processing unit 2b as the transfer destination and the type specification (type specifying unit 20) indicating the microprocessor from the transfer data. The packet conversion of the transfer data is performed as in the conventional case, the output destination changeover switch 14 is controlled, the microprocessor 3b in the arithmetic processing unit 2b is connected to the input source data switching control unit 8a, and the input source data switching is performed. Transfer data from the control unit 8a is sent to the microprocessor 3b in the arithmetic processing unit 2b. It will be passed can (see X3 in Fig. 16).
The packet conversion here is an operation for changing the address specification used in the arithmetic processing unit to the address specification by virtual mapping, and one microprocessor substitutes only for data transfer of one other microprocessor. In this embodiment where the maximum number of memory connections is “3”, a virtual mapping address is generated by adding a value “4” to the address designation used in the arithmetic processing unit. Is done. For example, the address designation used in the arithmetic processing unit is “3” [actually third on the arithmetic processing unit 2a (actually fourth because the value corresponding to the first memory is defined as 0) [7] [7th memory (actually the eighth memory because the value corresponding to the first memory is defined as 0]] on the arithmetic processing unit 2b. Is converted.

  If the determination result in step c10 is false, that is, it is determined that the processing unit of the transfer destination specified by the header of the transfer data does not match the processing unit of the data conversion unit 15. In this case, the data switching control unit is merely a relay point, and it is necessary to transfer the data to another data switching control unit via the data switching control unit. The switching control microprocessor 23 functioning as 15 does not perform the process of deleting the header from the transfer data, but directly transfers the transfer data to the data switching control unit of another arithmetic processing unit connected to the data switching control unit. It will be transferred (step c16).

  As described above, in this embodiment, when a failure occurs in any of the microprocessors 3a, 3b, 3c, and 3d of the arithmetic processing units 2a, 2b, 2c, and 2d, the subordinates of the failed microprocessors are subordinate. Data switching between the data switching control unit of the arithmetic processing unit having the failed microprocessor and other arithmetic processing units connected to the data switching control unit for writing data into and reading data from the memory. In this case, only when transferring transfer data between each data switching control unit, a transfer destination arithmetic processing unit and a header for designating the transfer destination type are used. The protocol used to transfer data between the microprocessor and memory is itself The data transfer of the memory under the faulty microprocessor can be dealt with without any change.

  In addition, among the microprocessors 3a, 3b, 3c, and 3d provided in each of the plurality of arithmetic processing units 2a, 2b, 2c, and 2d, the memory under the failure of the failed microprocessor is the microprocessor that has not failed. Therefore, even if a special spare processor card or spare arithmetic processing unit is not redundantly installed, it is possible to realize data transfer to the memory under the faulty microprocessor. it can.

  Here, all the memories under the failed microprocessor, for example, the memories 4a, 4b, 4c, and 4d under the microprocessor 3a are grouped together, and the data transfer is replaced with another microprocessor, for example, the microprocessor 3b. However, it is technically possible to assign a different microprocessor as a data transfer substitute microprocessor for each memory, for example, for each of the memories 4a, 4b, 4c, and 4d.

  In this embodiment, the description has been made on the assumption that one microprocessor replaces only the data transfer of the other microprocessor. However, depending on the processing capacity of the microprocessor and the setting of the virtual mapping, one microprocessor may It is possible to replace the data transfer of two or more microprocessors, and also select two or more non-failed microprocessors to transfer data in the memory under the other microprocessors that have failed. For example, if a failure occurs in the microprocessor 3a and the microprocessor 3c at the same time, the microprocessor 3b and the microprocessor 3d can replace the data transfer processing of the microprocessor 3a and the microprocessor 3c. 2 or more micropros Even when a failure occurs in the processor, it is possible to easily realize the data transfer of the memory under each microprocessor in which the failure has occurred.

  As the operation status update setting means, in addition to the failure processing microprocessor 21, when the information processing device 1 functions as a lower device of another device, a control program on the higher device side can be used. The substantial operation status update setting means can be configured by the firmware incorporated in the information processing apparatus 1.

It is the block diagram shown about the outline of the structure of the information processing apparatus of one Embodiment to which the failure processing method of this invention was applied. It is the functional block diagram shown about the structure of the data switching control part of the information processing apparatus of the embodiment. It is the conceptual diagram which showed the outline of the structure of the header attached to transfer data. 3 is a conceptual diagram illustrating a logical configuration of an available gateway storage table in the information processing apparatus of the embodiment. FIG. It is the conceptual diagram which showed the logical structure of the used gateway memory table in the information processing apparatus of the embodiment. It is the conceptual diagram which showed the state by which the usable gateway storage table in the information processing apparatus of the embodiment was initialized. It is the conceptual diagram which showed the state by which the used gateway storage table in the information processing apparatus of the embodiment was initialized. It is the conceptual diagram which showed an example of the initial setting state of the various registers of the data switching control part in the information processing apparatus of the embodiment. 5 is a flowchart illustrating an outline of an initialization process of an available gateway storage table executed by a data switching control unit of each arithmetic processing unit in the information processing apparatus of the embodiment. A status storage register executed by a failure processing microprocessor as an operation status update setting means when a failure occurs in a microprocessor of any of the arithmetic processing units in the information processing apparatus of the embodiment, a transfer alternative microprocessor storage register, It is the flowchart shown about the outline of the setting update process of a transfer alternative domain storage register and a used gateway storage table. It is the conceptual diagram which showed an example of the update setting of the transfer alternative microprocessor memory register of the data switching control part in the information processing apparatus of the embodiment. It is the conceptual diagram which showed an example of the update setting of the transfer alternative domain storage register of the data switching control part in the information processing apparatus of the embodiment. It is the conceptual diagram which showed an example of the update setting of the used gateway storage table in the information processing apparatus of the embodiment. It is the conceptual diagram which showed an example of the update setting of the state memory register of the data switching control part in the information processing apparatus of the embodiment. 5 is a flowchart showing processing executed by a data switching control unit in the information processing apparatus of the embodiment, particularly processing operation of a switching control microprocessor functioning as a data conversion unit in each data switching control unit. It is the conceptual diagram shown about the example of the flow of data transfer when a failure arises in one of the arithmetic processing units in the information processing apparatus of the embodiment.

Explanation of symbols

1 Information processing devices 2a, 2b, 2c, 2d Arithmetic processing units 3a, 3b, 3c, 3d Microprocessors 4a, 4b, 4c, 4d Memory (Dual Inline Memory Module)
5a, 5b, 5c, 5d Memory (Dual Inline Memory Module)
6a, 6b, 6c, 6d Memory (Dual Inline Memory Module)
7a, 7b, 7c, 7d Memory (Dual Inline Memory Module)
8a, 8b, 8c, 8d Data switching control unit 9 State storage register 10 Transfer alternative microprocessor storage register
11 Transfer Alternate Domain Storage Register 12 Self Domain Storage Register 13 Connected Memory Number Storage Register 14 Output Destination Switch 15 Data Conversion Unit 16 Available Gateway Storage Table 17 Used Gateway Storage Table 18 Table Storage Memory 19 Domain Specification Unit 20 Type Specification Unit 21 Fault processing microprocessor (operation status update setting means)
22 Routing table 23 Microprocessor for switching control

Claims (4)

A failure occurred in the microprocessor of an information processing apparatus that performs parallel arithmetic processing by connecting a plurality of arithmetic processing units composed of a combination of a microprocessor and a memory and connecting the microprocessors of each arithmetic processing unit so that information can be transmitted. A failure processing method of an information processing device for using a memory under control of the microprocessor,
A data switching control unit for switching the information transmission path is provided between the microprocessor and the memory for each arithmetic processing unit, and at least two or more data switching control units are connected so as to transmit information,
When a failure occurs in any of the microprocessors, the microprocessor of the arithmetic processing unit having the data switching control unit connected to the data switching control unit of the arithmetic processing unit having the failed microprocessor is selected to Delegate data transfer of the resulting microprocessor memory,
Depending on the input source of the transfer data to each data switching control unit, the transfer data input source to the data switching control unit is a memory and the microprocessor of the data switching control unit has a failure and the data When the transfer data input source to the switching control unit is a microprocessor and the destination address specification exceeds the normal physical address of the memory in the relevant processing unit, the destination processing unit and the destination type Is attached to the transfer data, while the input source of the transfer data to the data switching control unit is another data switching control unit and the transfer destination is in the arithmetic processing unit of the data switching control unit And a failure processing method for an information processing apparatus, wherein the header is deleted from the transfer data. In an information processing apparatus in which a plurality of arithmetic processing units each including a combination of a microprocessor and a memory are provided, and the microprocessors of the respective arithmetic processing units are connected so as to be able to transmit information to perform parallel arithmetic processing.
A data switching control unit for switching the information transmission path is provided between the microprocessor and the memory for each arithmetic processing unit, and at least two or more data switching control units are connected to transmit information,
Usable to store the correspondence relationship between the microprocessor of each arithmetic processing unit and the arithmetic processing unit that can substitute the data transfer of the memory in the other arithmetic processing unit via the data switching control unit of the arithmetic processing unit Stores the correspondence relationship between the gateway storage table, the microprocessor of each arithmetic processing unit, and the arithmetic processing unit in which the microprocessor performs the data transfer of the memory via the data switching control unit of the arithmetic processing unit. When a failure occurs in one of the microprocessors, the correspondence relationship between the microprocessor and the arithmetic processing unit is assumed that the microprocessor in which the failure has occurred is acting as the data transfer for the memory in all other arithmetic processing units. Used gateway to remember Deploying a table storage memory and a 憶 table,
Each of the data switching control units includes a state storage register for storing the presence or absence of a failure of the microprocessor of the arithmetic processing unit provided with the data switching control unit, and a memory of the arithmetic processing unit provided with the data switching control unit A transfer alternative microprocessor storage register for storing an arithmetic processing unit having a microprocessor that should perform the data transfer of the data, and a microprocessor of the arithmetic processing unit provided with the data switching control unit should perform the data transfer of the memory The transfer alternative domain storage register that stores the arithmetic processing unit, the input source of the transfer data to the data switching control unit and the state of the state storage register are determined, and the input source of the transfer data to the data switching control unit is Memory and the state storage register indicates a fault. And when the transfer data input source to the data switching control unit is a microprocessor and the transfer destination address specification exceeds the normal physical address of the memory in the operation processing unit, While the header specifying the type of processing unit and transfer destination is attached to the transfer data, the input source of the transfer data to the data switching control unit is another data switching control unit, and the transfer destination is the data switching control unit. A data conversion unit that deletes the header from the transfer data when it is in the arithmetic processing unit,
When a failure occurs in the microprocessor of any of the arithmetic processing units, the arithmetic processing unit can refer to the available gateway storage table and the used gateway storage table to perform data transfer in the memory of the failed microprocessor. An arithmetic processing unit having a microprocessor not stored in the used gateway storage table is selected and stored in the transfer alternative microprocessor storage register of the data switching control unit of the failed microprocessor, while the selected The arithmetic processing unit having the failed microprocessor is stored in the transfer substitution domain storage register of the arithmetic processing unit, and the microprocessor of the selected arithmetic processing unit stores the data of the arithmetic processing unit. The data transfer of the memory of the arithmetic processing unit having the faulty microprocessor via the control unit, and the faulty microprocessor transfers the data of the memory in all other arithmetic processing units The used gateway storage table is updated and set as an agent, and operation status update setting means for storing the occurrence of the failure in the state storage register of the data switching control unit of the failed microprocessor is provided. An information processing apparatus characterized by the above.   The information processing apparatus according to claim 2, wherein the operation status update setting unit is configured by a microprocessor independent of each arithmetic processing unit.   The information processing apparatus according to claim 2, wherein the operation status update setting unit is configured by firmware of the information processing apparatus.

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