JP5060453B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

Info

Publication number
JP5060453B2
JP5060453B2 JP2008279838A JP2008279838A JP5060453B2 JP 5060453 B2 JP5060453 B2 JP 5060453B2 JP 2008279838 A JP2008279838 A JP 2008279838A JP 2008279838 A JP2008279838 A JP 2008279838A JP 5060453 B2 JP5060453 B2 JP 5060453B2
Authority
JP
Japan
Prior art keywords
conductor film
bonding wire
semiconductor chip
heat
main electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2008279838A
Other languages
Japanese (ja)
Other versions
JP2010109158A (en
Inventor
宇幸 串間
克明 斉藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP2008279838A priority Critical patent/JP5060453B2/en
Publication of JP2010109158A publication Critical patent/JP2010109158A/en
Application granted granted Critical
Publication of JP5060453B2 publication Critical patent/JP5060453B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H01L2224/48139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

本発明は、主電極に主電流を流す半導体チップを有する半導体装置に関する。   The present invention relates to a semiconductor device having a semiconductor chip for supplying a main current to a main electrode.

半導体装置、特に、電力用半導体モジュールは、ＩＧＢＴ（Insulated Gate Bipolar Transistor）に代表される電力制御用半導体チップまたは整流用ダイオードチップを、絶縁基板を介して放熱用支持基板に取付けている。前記絶縁基板の両面に導体膜を備え、電力制御用半導体チップ等と絶縁基板上面の導体膜、絶縁基板下面の導体膜と放熱用支持基板はそれぞれ、はんだや高熱伝導の接着剤等で接合されている。電力制御用半導体チップ等の表面と半導体装置の端子は、アルミニウム（Ａｌ）材等によるワイヤボンディングにより直接的または絶縁基板上面の導体膜を経由して接続されている。   In a semiconductor device, in particular, a power semiconductor module, a power control semiconductor chip represented by an IGBT (Insulated Gate Bipolar Transistor) or a rectifying diode chip is attached to a heat dissipation support substrate via an insulating substrate. Conductor films are provided on both sides of the insulating substrate, and the power control semiconductor chip and the like are connected to the conductor film on the upper surface of the insulating substrate, and the conductor film on the lower surface of the insulating substrate and the support substrate for heat dissipation are bonded to each other with solder or a high thermal conductive adhesive. ing. The surface of the power control semiconductor chip or the like and the terminal of the semiconductor device are connected directly or via a conductor film on the upper surface of the insulating substrate by wire bonding using an aluminum (Al) material or the like.

半導体装置の動作時に、電力制御用半導体チップ等に発生する熱は、主に電力制御用半導体チップの下面から絶縁基板及び放熱用金属板を経て、半導体装置の外へ放熱される。半導体装置の放熱（冷却）構造に関しては、特開２００１−３３２６６４号公報等で提案されている。
特開２００１−３３２６６４号公報 During operation of the semiconductor device, heat generated in the power control semiconductor chip or the like is radiated from the lower surface of the power control semiconductor chip to the outside of the semiconductor device through the insulating substrate and the heat dissipation metal plate. Japanese Unexamined Patent Application Publication No. 2001-332664 proposes a heat dissipation (cooling) structure of a semiconductor device.
JP 2001-332664 A

半導体装置の放熱の経路としては、電力制御用半導体チップの下面から絶縁基板及び放熱用金属板を経る経路だけでなく、電力制御用半導体チップ等の上面からそこに接続するボンディングワイヤを経る経路も考えられる。しかし、電力制御用半導体チップ等の上面からボンディングワイヤを経る経路は、半導体装置の動作時には、ボンディングワイヤに大電流が流れ、ボンディングワイヤ自身も発熱するため、ボンディングワイヤを経由した放熱は期待できないと従来から考えられていた。   The heat dissipation path of the semiconductor device includes not only the path from the lower surface of the power control semiconductor chip through the insulating substrate and the metal plate for heat dissipation, but also the path from the upper surface of the power control semiconductor chip or the like to the bonding wire connected thereto. Conceivable. However, the path through the bonding wire from the upper surface of the power control semiconductor chip or the like is that a large current flows through the bonding wire and the bonding wire itself generates heat during operation of the semiconductor device, so heat dissipation through the bonding wire cannot be expected. It has been thought of in the past.

一般に、ボンディングワイヤは、良導体であり、熱伝導率も高いことから、大量の熱を伝導できるのであるが、それでも、ボンディングワイヤが、電力制御用半導体チップ等で発生した熱を、伝導できないのは、前記のようにボンディングワイヤ自身も発熱しているからである。しかし、ボンディングワイヤは、電力制御用半導体チップ等に容易に接続できるので、ボンディングワイヤを発熱しないように電力制御用半導体チップ等に接続できれば、放熱用に好適であると考えられる。
そこで、本発明の目的は、ボンディングワイヤを用いて効率的に放熱することができる半導体装置を提供することにある。 In general, bonding wires are good conductors and have high thermal conductivity, so they can conduct a large amount of heat. Nevertheless, bonding wires cannot conduct heat generated by power control semiconductor chips, etc. This is because the bonding wire itself generates heat as described above. However, since the bonding wire can be easily connected to a power control semiconductor chip or the like, if the bonding wire can be connected to the power control semiconductor chip or the like so as not to generate heat, it is considered suitable for heat dissipation.
Accordingly, an object of the present invention is to provide a semiconductor device capable of efficiently radiating heat using a bonding wire.

前記目的を達成するために、本発明は、半導体チップと放熱用支持基板との間に設けられた絶縁基板上に設置され電流又は電圧を外部と入出力する外部導出端子に接続せず主電流が流れないダミー導体膜と、半導体チップの主電極とダミー導体膜を接続するボンディングワイヤとを有することを特徴としている。 In order to achieve the above object , the present invention provides a main current that is installed on an insulating substrate provided between a semiconductor chip and a support substrate for heat dissipation without being connected to an external lead-out terminal that inputs / outputs current or voltage to / from the outside. A dummy conductor film that does not flow, and a bonding wire that connects the main electrode of the semiconductor chip and the dummy conductor film.

本発明によれば、ボンディングワイヤを用いて効率的に放熱することができる半導体装置を提供することができる。   ADVANTAGE OF THE INVENTION According to this invention, the semiconductor device which can thermally radiate efficiently using a bonding wire can be provided.

次に、本発明の実施形態について、適宜図面を参照しながら詳細に説明する。なお、各図において、共通する部分には同一の符号を付し重複した説明を省略する。   Next, embodiments of the present invention will be described in detail with reference to the drawings as appropriate. In each figure, common portions are denoted by the same reference numerals, and redundant description is omitted.

図１に、本発明の実施形態に係る半導体装置１０の平面図を示し、図２に、図１のＡ−Ａ方向の矢視断面図を示す。   FIG. 1 is a plan view of a semiconductor device 10 according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along the line AA in FIG.

半導体装置（電力用半導体モジュール）１０は、ＩＧＢＴやＦＥＴ（電界効果トランジスタ）に代表される（電力制御用）半導体チップ１ａと整流用ダイオードチップ（半導体チップ）１ｂを、絶縁基板２を介して放熱用支持基板（ヒートシンク）４に取付けている。絶縁基板２の上面に導体膜３ａを備え、半導体チップ１ａ、１ｂの下面と導体膜３ａとは、半田５ａ、５ｂや高熱伝導の接着剤等で接合されている。また、絶縁基板２の下面に導体膜３ｅを備え、導体膜３ｅと放熱用支持基板４の上面とは、半田６や高熱伝導の接着剤等で接合されている。   The semiconductor device (power semiconductor module) 10 radiates heat from the semiconductor chip 1a (for power control) represented by IGBT and FET (field effect transistor) and the diode chip (semiconductor chip) 1b for rectification via the insulating substrate 2. It is attached to a support substrate (heat sink) 4 for use. A conductor film 3a is provided on the upper surface of the insulating substrate 2, and the lower surfaces of the semiconductor chips 1a and 1b and the conductor film 3a are joined together by solders 5a and 5b, an adhesive having high thermal conductivity, or the like. In addition, a conductor film 3e is provided on the lower surface of the insulating substrate 2, and the conductor film 3e and the upper surface of the heat dissipation support substrate 4 are joined by solder 6 or a highly heat conductive adhesive.

半導体チップ１ａには、主電流を流す主電極１１ｂ（半導体チップ１ａがＩＧＢＴであればエミッタ電極に対応する）と、制御電極１１ａが設けられている。制御電極１１ａに制御電流を流すことで、主電極１１ｂを流れる主電流を制御することができる。半導体チップ１ａの主電極１１ｂと、半導体チップ１ｂの上面（一方の電極）とは、ボンディングワイヤ９ｂ、９ｈによって接続され、半導体チップ１ｂの上面（一方の電極）は、ボンディングワイヤ９ａによって外部導出端子７ａに接続されている。また、半導体チップ１ａの下面の主電極と、半導体チップ１ｂの下面（他方の電極）とは、絶縁基板２の上面に設けられている導体膜３ａによって接続され、導体膜３ａは、ボンディングワイヤ９ｃによって外部導出端子７ｂに接続されている。このように、半導体チップ１ａと半導体チップ１ｂとは、外部導出端子７ａと外部導出端子７ｂの端子間に、並列接続されている。   The semiconductor chip 1a is provided with a main electrode 11b for supplying a main current (corresponding to an emitter electrode if the semiconductor chip 1a is an IGBT) and a control electrode 11a. By flowing a control current through the control electrode 11a, the main current flowing through the main electrode 11b can be controlled. The main electrode 11b of the semiconductor chip 1a and the upper surface (one electrode) of the semiconductor chip 1b are connected by bonding wires 9b and 9h, and the upper surface (one electrode) of the semiconductor chip 1b is connected to an external lead terminal by the bonding wire 9a. 7a. The main electrode on the lower surface of the semiconductor chip 1a and the lower surface (the other electrode) of the semiconductor chip 1b are connected by a conductor film 3a provided on the upper surface of the insulating substrate 2, and the conductor film 3a is bonded to the bonding wire 9c. To the external lead-out terminal 7b. Thus, the semiconductor chip 1a and the semiconductor chip 1b are connected in parallel between the external lead-out terminal 7a and the external lead-out terminal 7b.

絶縁基板２は、半導体チップ１ａ、１ｂと放熱用支持基板４との間に設けられている。絶縁基板２は、主電流が流れることで半導体チップ１ａ、１ｂに生じる熱を、放熱用支持基板４へ伝導させる。   The insulating substrate 2 is provided between the semiconductor chips 1 a and 1 b and the heat dissipation support substrate 4. The insulating substrate 2 conducts heat generated in the semiconductor chips 1a and 1b to the heat dissipation support substrate 4 when the main current flows.

放熱用支持基板４は、主電流が流れることで半導体チップ１ａ、１ｂに生じる熱を、絶縁基板２から受け、外部に放熱する。放熱用支持基板４の部材には、例えば銅（Ｃｕ）を用いることができる。   The heat dissipation support substrate 4 receives heat generated in the semiconductor chips 1a and 1b from the insulating substrate 2 when the main current flows, and dissipates the heat to the outside. For example, copper (Cu) can be used as a member of the support substrate 4 for heat dissipation.

そして、半導体装置１０は、絶縁基板２の上面に設けられるダミー導体膜３ｄを有している。ダミー導体膜３ｄは、ボンディングワイヤ９ｉによって主電極１１ｂに接続しているが、電流又は電圧を外部と入出力する外部導出端子７ａ〜７ｄは接続しておらず、ダミー導体膜３ｄに、主電流が流れることはない。ダミー導体膜３ｄは、導体膜３ａから離れ絶縁されている。なお、ダミー導体膜３ｄは、ボンディングワイヤ９ｉによって主電極１１ｂに接続しているので、主電極１１ｂと同電位になっている。ダミー導体膜３ｄは、主電極１１ｂの電位の変動に伴って電位が変動し、その際に電流が流れ充放電されるが、主電流ほどの大電流が長時間にわたり流れることはない。このため、ボンディングワイヤ９ｉが過度に発熱することはなく、ボンディングワイヤ９ｉは、半導体チップ１ａのボンディングワイヤ９ｉの接続する主電極１１ｂの周辺で発生した熱を、吸収しダミー導体膜３ｄへ伝導させることができる。ダミー導体膜３ｄへ伝導した熱は、絶縁基板２、半田６、放熱用支持基板４を順に経由して外部に放出される。このように、ダミー導体膜３ｄとダミー導体膜３ｄに接続するボンディングワイヤ９ｉを用いて効率的に放熱することができる。   The semiconductor device 10 has a dummy conductor film 3 d provided on the upper surface of the insulating substrate 2. Although the dummy conductor film 3d is connected to the main electrode 11b by the bonding wire 9i, the external lead-out terminals 7a to 7d for inputting / outputting current or voltage to / from the outside are not connected, and the main current is supplied to the dummy conductor film 3d. Will not flow. The dummy conductor film 3d is separated from the conductor film 3a and insulated. Since the dummy conductor film 3d is connected to the main electrode 11b by the bonding wire 9i, it has the same potential as the main electrode 11b. In the dummy conductor film 3d, the potential fluctuates as the potential of the main electrode 11b fluctuates. At that time, a current flows and is charged and discharged, but a large current as the main current does not flow for a long time. For this reason, the bonding wire 9i does not generate excessive heat, and the bonding wire 9i absorbs the heat generated around the main electrode 11b to which the bonding wire 9i of the semiconductor chip 1a is connected and conducts it to the dummy conductor film 3d. be able to. The heat conducted to the dummy conductor film 3d is released to the outside through the insulating substrate 2, the solder 6, and the heat dissipation support substrate 4 in order. In this way, heat can be efficiently radiated using the dummy conductor film 3d and the bonding wire 9i connected to the dummy conductor film 3d.

ところで、主電極１１ｂには、主電流を流すために、ボンディングワイヤ９ｂ、９ｈが接続されているが、そのボンディングワイヤ９ｂ、９ｈの本数は、ボンディングワイヤの９ｂ、９ｈの径（断面積）と主電極１１ｂの面積とで決まる接続可能な最大の本数に達している場合がある。このような場合には、ボンディングワイヤ９ｂと、ボンディングワイヤ９ｉとを、主電極１１ｂ上で１本のボンディングワイヤを切断することなく主電極１１ｂ上の１点に接続することで、形成する。すなわち、ボンディングワイヤ９ｂと、ボンディングワイヤ９ｉとは、連続した１本のボンディングワイヤで形成されている。１本のボンディングワイヤの主電極１１ｂとの接続点から一方の側は、ボンディングワイヤ９ｂとして機能し、他方の側は、ボンディングワイヤ９ｉとして機能している。このようにすれば、ダミー導体膜３ｄに接続するボンディングワイヤ９ｉを、ボンディングワイヤ９ｂ、９ｈの本数によらず、確実に主電極１１ｂに接続することができる。なお、このような接続は、ボンディングワイヤ９ｂ、９ｈの本数が多く、接続可能な最大の本数に達している場合に限って使用するものではなく、本数が少なくても多くても使用してよい。そして、このような接続によれば、熱は、ボンディングワイヤ９ｂと主電極１１ｂとの接合面で主に集中するところ、その集中箇所にボンディングワイヤ９ｉを接続できるので効率よく熱を吸収でき優先的に冷却することができるからである。   Incidentally, bonding wires 9b and 9h are connected to the main electrode 11b in order to flow a main current. The number of the bonding wires 9b and 9h is the diameter (cross-sectional area) of the bonding wires 9b and 9h. In some cases, the maximum number that can be connected is determined by the area of the main electrode 11b. In such a case, the bonding wire 9b and the bonding wire 9i are formed by connecting to one point on the main electrode 11b without cutting one bonding wire on the main electrode 11b. That is, the bonding wire 9b and the bonding wire 9i are formed by one continuous bonding wire. One side from the connection point of one bonding wire to the main electrode 11b functions as a bonding wire 9b, and the other side functions as a bonding wire 9i. In this way, the bonding wire 9i connected to the dummy conductor film 3d can be reliably connected to the main electrode 11b regardless of the number of bonding wires 9b and 9h. Such a connection is not used only when the number of bonding wires 9b and 9h is large and the maximum number of wires that can be connected is reached, and may be used when the number is small or large. . According to such a connection, heat is concentrated mainly on the bonding surface between the bonding wire 9b and the main electrode 11b. Since the bonding wire 9i can be connected to the concentrated portion, heat can be absorbed efficiently and preferentially. This is because it can be cooled.

また、半導体装置１０は、絶縁基板２の上面に設けられるモニタ導体膜３ｃを有している。モニタ導体膜３ｃは、少なくとも２本以上のボンディングワイヤ９ｅによって主電極１１ｂに接続しており、電流又は電圧を外部に出力する外部導出端子７ｃにボンディングワイヤ９ｇによって接続している。モニタ導体膜３ｃは、導体膜３ａとダミー導体膜３ｄとから離れ絶縁されている。外部導出端子７ｃは、外部から半導体チップ１ａをモニタするための端子であるので、外部導出端子７ｃ、さらには、モニタ導体膜３ｃに、主電流のような大電流が流れることはない。モニタ導体膜３ｃと、少なくとも２本以上のボンディングワイヤ９ｅに、主電流のような大電流が流れないので、ボンディングワイヤ９ｅが過度に発熱することはなく、ボンディングワイヤ９ｅは、半導体チップ１ａのボンディングワイヤ９ｅの接続する主電極１１ｂの周辺で発生した熱を、吸収しモニタ導体膜３ｃへ伝導させる。   Further, the semiconductor device 10 has a monitor conductor film 3 c provided on the upper surface of the insulating substrate 2. The monitor conductor film 3c is connected to the main electrode 11b by at least two or more bonding wires 9e, and is connected to the external lead-out terminal 7c that outputs current or voltage to the outside by the bonding wires 9g. The monitor conductor film 3c is insulated from the conductor film 3a and the dummy conductor film 3d. Since the external lead-out terminal 7c is a terminal for monitoring the semiconductor chip 1a from the outside, a large current such as a main current does not flow through the external lead-out terminal 7c and the monitor conductor film 3c. Since a large current such as a main current does not flow through the monitor conductor film 3c and at least two or more bonding wires 9e, the bonding wires 9e do not generate excessive heat, and the bonding wires 9e are bonded to the semiconductor chip 1a. The heat generated around the main electrode 11b to which the wire 9e is connected is absorbed and conducted to the monitor conductor film 3c.

半導体チップ１ａをモニタするために電流又は電圧を外部に出力するのであれば、流れる電流も小さいので、モニタ導体膜３ｃと主電極１１ｂとの間を接続するボンディングワイヤ９ｅの本数は、１本でよいが、少なくとも２本以上接続することにより、ボンディングワイヤ９ｅによって半導体チップ１ａから吸収・放出される熱量を増やすことができる。モニタ導体膜３ｃへ伝導した熱は、絶縁基板２、半田６、放熱用支持基板４を順に経由して外部に放出される。このように、モニタ導体膜３ｃとモニタ導体膜３ｃに接続する少なくとも２本以上のボンディングワイヤ９ｅを用いて効率的に放熱することができる。   If a current or voltage is output to monitor the semiconductor chip 1a, the flowing current is small, so the number of bonding wires 9e connecting the monitor conductor film 3c and the main electrode 11b is one. However, the amount of heat absorbed and released from the semiconductor chip 1a by the bonding wires 9e can be increased by connecting at least two wires. The heat conducted to the monitor conductor film 3c is released to the outside through the insulating substrate 2, the solder 6, and the heat dissipation support substrate 4 in order. Thus, heat can be efficiently radiated using the monitor conductor film 3c and at least two bonding wires 9e connected to the monitor conductor film 3c.

また、半導体装置１０は、絶縁基板２の上面に設けられる制御導体膜３ｂを有している。制御導体膜３ｂは、少なくとも２本以上のボンディングワイヤ９ｄによって制御電極１１ａに接続しており、電流又は電圧を外部から入力する外部導出端子７ｄにボンディングワイヤ９ｆによって接続している。制御導体膜３ｂは、導体膜３ａとダミー導体膜３ｄとモニタ導体膜３ｃとから離れ絶縁されている。外部導出端子７ｄは、外部から半導体チップ１ａを制御するための端子であるので、外部導出端子７ｄ、さらには、制御導体膜３ｂに、主電流のような大電流が流れることはない。制御導体膜３ｂと、少なくとも２本以上のボンディングワイヤ９ｄに、主電流のような大電流が流れないので、ボンディングワイヤ９ｄが過度に発熱することはなく、ボンディングワイヤ９ｄは、半導体チップ１ａのボンディングワイヤ９ｄの接続する制御電極１１ａの周辺の主電極１１ｂで発生した熱を、吸収し制御導体膜３ｂへ伝導させる。   Further, the semiconductor device 10 has a control conductor film 3 b provided on the upper surface of the insulating substrate 2. The control conductor film 3b is connected to the control electrode 11a by at least two or more bonding wires 9d, and is connected to an external lead-out terminal 7d that inputs current or voltage from the outside by bonding wires 9f. The control conductor film 3b is insulated from the conductor film 3a, the dummy conductor film 3d, and the monitor conductor film 3c. Since the external lead-out terminal 7d is a terminal for controlling the semiconductor chip 1a from the outside, a large current such as a main current does not flow through the external lead-out terminal 7d and further to the control conductor film 3b. Since a large current such as a main current does not flow through the control conductor film 3b and at least two bonding wires 9d, the bonding wire 9d does not generate excessive heat, and the bonding wire 9d is bonded to the semiconductor chip 1a. Heat generated in the main electrode 11b around the control electrode 11a to which the wire 9d is connected is absorbed and conducted to the control conductor film 3b.

半導体チップ１ａを制御するために電流又は電圧を外部から入力するのであれば、流れる電流も小さいので、制御導体膜３ｂと制御電極１１ａとの間を接続するボンディングワイヤ９ｄの本数は、前記したボンディングワイヤ９ｅと同様、１本でよいが、少なくとも２本以上接続することにより、ボンディングワイヤ９ｄによって半導体チップ１ａから吸収・放出される熱量を増やすことができる。制御導体膜３ｂへ伝導した熱は、絶縁基板２、半田６、放熱用支持基板４を順に経由して外部に放出される。このように、制御導体膜３ｂと制御導体膜３ｂに接続する少なくとも２本以上のボンディングワイヤ９ｄを用いて効率的に放熱することができる。ボンディングワイヤ９ａ〜９ｉには、例えばアルミニウム（Ａｌ）材を用いることができる。   If current or voltage is input from the outside in order to control the semiconductor chip 1a, the flowing current is small. Therefore, the number of bonding wires 9d connecting between the control conductor film 3b and the control electrode 11a is the same as that described above. As with the wire 9e, only one wire may be used. However, by connecting at least two wires, the amount of heat absorbed and released from the semiconductor chip 1a by the bonding wire 9d can be increased. The heat conducted to the control conductor film 3b is released to the outside through the insulating substrate 2, the solder 6, and the heat dissipation support substrate 4 in order. Thus, heat can be efficiently radiated using the control conductor film 3b and at least two bonding wires 9d connected to the control conductor film 3b. For example, an aluminum (Al) material can be used for the bonding wires 9a to 9i.

絶縁基板２の周囲には、樹脂形成ケース８が設けられ、樹脂形成ケース８は、下部を放熱用支持基板４の外周部に固定されている。樹脂形成ケース８は、外部導出端子７ａ〜７ｄを内側から外側へ貫通させながら支持している。その樹脂形成ケース８の内側には、シリコーンゲルのような充填剤１２が充填されている。なお、図１は、充填剤１２を透視して描かれている。   A resin forming case 8 is provided around the insulating substrate 2, and the lower portion of the resin forming case 8 is fixed to the outer peripheral portion of the heat dissipation support substrate 4. The resin forming case 8 supports the external lead-out terminals 7a to 7d while penetrating from the inside to the outside. Inside the resin forming case 8, a filler 12 such as silicone gel is filled. Note that FIG. 1 is drawn through the filler 12.

本実施形態によれば、主電流の通電に寄与しないダミー導体膜３ｄと半導体チップ１ａの表面の主電極１１ｂを接続することにより、半導体チップ１ｂの表面からボンディングワイヤ９ｉを介する絶縁基板２への伝熱路を副放熱路とすることができる。ボンディングワイヤ９ｉに主電流が流れず、ボンディングワイヤ９ｉに流れる電流をごく小さくできるので、半導体装置１０の動作に伴う発熱はボンディングワイヤ９ｉでは抑えられ、ボンディングワイヤ９ｉを放熱器としてのみ利用することができるので、効率良く放熱することが可能となる。また、主電極１１ｂに接続するボンディングワイヤの表面積が、ボンディングワイヤ９ｂ、９ｈにボンディングワイヤ９ｉを加えたことにより、増えるので、ボンディングワイヤ表面からの放熱性を向上させることができる。また、本実施形態の従来技術との変更点は、絶縁基板２上にダミー導体膜３ｄを形成するために絶縁基板２の上面の導体膜形成時のレイアウトを変更する点と、及び、ボンディングワイヤ９ｉを形成するためにワイヤボンディング時のレイアウトを変更する点である。従って、製造プロセスは従来技術を変更することなく用い、簡単な変更点のみで、本実施形態を実施でき、半導体装置１０の放熱性を向上させることができる。   According to the present embodiment, by connecting the dummy conductor film 3d that does not contribute to energization of the main current and the main electrode 11b on the surface of the semiconductor chip 1a, the surface of the semiconductor chip 1b is connected to the insulating substrate 2 via the bonding wires 9i. The heat transfer path can be a sub-heat radiation path. Since the main current does not flow through the bonding wire 9i and the current flowing through the bonding wire 9i can be very small, heat generated by the operation of the semiconductor device 10 can be suppressed by the bonding wire 9i, and the bonding wire 9i can be used only as a radiator. Therefore, it is possible to dissipate heat efficiently. Further, since the surface area of the bonding wire connected to the main electrode 11b is increased by adding the bonding wire 9i to the bonding wires 9b and 9h, the heat dissipation from the bonding wire surface can be improved. In addition, the present embodiment is different from the prior art in that the layout at the time of forming the conductor film on the upper surface of the insulating substrate 2 is changed in order to form the dummy conductor film 3d on the insulating substrate 2, and the bonding wire This is to change the layout at the time of wire bonding in order to form 9i. Therefore, the manufacturing process can be used without changing the prior art, and this embodiment can be implemented with only simple changes, and the heat dissipation of the semiconductor device 10 can be improved.

本発明の実施形態に係る半導体装置の平面図（ただし、充填剤を透視している）である。It is a top view (however, seeing through a filler) of a semiconductor device concerning an embodiment of the present invention. 図１のＡ−Ａ方向の矢視断面図である。It is arrow sectional drawing of the AA direction of FIG.

符号の説明Explanation of symbols

１ａ 半導体チップ（ＩＧＢＴ）
１ｂ 半導体チップ（ダイオード）
２ 絶縁基板
３ａ 導体膜
３ｂ 制御導体膜
３ｃ モニタ導体膜
３ｄ ダミー導体膜
３ｅ 導体膜
４ 放熱用支持基板（ヒートシンク）
５ａ、５ｂ、６ 半田
７ａ、７ｂ、７ｃ、７ｄ 外部導出端子
８ 樹脂形成ケース
９ａ、９ｂ、９ｃ、９ｄ、９ｅ、９ｆ、９ｇ、９ｈ ボンディングワイヤ
１０ 半導体装置
１１ａ 制御電極
１１ｂ 主電極（エミッタ電極）
１２ 充填剤（シリコーンゲル） 1a Semiconductor chip (IGBT)
1b Semiconductor chip (diode)
2 Insulating substrate 3a Conductor film 3b Control conductor film 3c Monitor conductor film 3d Dummy conductor film 3e Conductor film 4 Heat dissipation support substrate (heat sink)
5a, 5b, 6 Solder 7a, 7b, 7c, 7d External lead-out terminal 8 Resin forming case 9a, 9b, 9c, 9d, 9e, 9f, 9g, 9h Bonding wire 10 Semiconductor device 11a Control electrode 11b Main electrode (emitter electrode)
12 Filler (silicone gel)

Claims (2)

主電極に主電流を流す半導体チップと、
前記主電流が流れ前記半導体チップで生じる熱を外部に放熱する放熱用支持基板と、
前記半導体チップと前記放熱用支持基板との間に設けられ、前記熱を伝導させる絶縁基板と、
前記絶縁基板上に設けられ、電流又は電圧を外部と入出力する外部導出端子に接続せず、前記主電流が流れないダミー導体膜と、
前記主電極と前記ダミー導体膜を接続するボンディングワイヤとを有することを特徴とする半導体装置。 A semiconductor chip for supplying a main current to the main electrode;
A support substrate for heat dissipation in which the main current flows and radiates heat generated in the semiconductor chip to the outside;
An insulating substrate that is provided between the semiconductor chip and the heat dissipation support substrate and conducts the heat;
A dummy conductor film that is provided on the insulating substrate and is not connected to an external lead-out terminal that inputs and outputs current or voltage to and from the outside, and the main current does not flow;
A semiconductor device comprising: a bonding wire connecting the main electrode and the dummy conductor film. 前記主電極に接続され、前記主電流を流すボンディングワイヤを有し、
前記主電流を流すボンディングワイヤと、前記主電極と前記ダミー導体膜を接続するボンディングワイヤとは、前記主電極上で連続していることを特徴とする請求項１に記載の半導体装置。 A bonding wire connected to the main electrode and for flowing the main current;
The semiconductor device according to claim 1, wherein the bonding wire for flowing the main current and the bonding wire for connecting the main electrode and the dummy conductor film are continuous on the main electrode .
JP2008279838A 2008-10-30 2008-10-30 Semiconductor device Active JP5060453B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008279838A JP5060453B2 (en) 2008-10-30 2008-10-30 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008279838A JP5060453B2 (en) 2008-10-30 2008-10-30 Semiconductor device

Publications (2)

Publication Number Publication Date
JP2010109158A JP2010109158A (en) 2010-05-13
JP5060453B2 true JP5060453B2 (en) 2012-10-31

Family

ID=42298305

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008279838A Active JP5060453B2 (en) 2008-10-30 2008-10-30 Semiconductor device

Country Status (1)

Country Link
JP (1) JP5060453B2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5832731B2 (en) * 2010-08-10 2015-12-16 株式会社東芝 Semiconductor element
JP2013258321A (en) * 2012-06-13 2013-12-26 Fuji Electric Co Ltd Semiconductor device
JP6642719B2 (en) * 2016-08-10 2020-02-12 三菱電機株式会社 Semiconductor device
JP6804421B2 (en) * 2017-10-06 2020-12-23 三菱電機株式会社 Semiconductor device

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0917908A (en) * 1995-06-27 1997-01-17 Hitachi Ltd Semiconductor device and electronic device using it
JP4040838B2 (en) * 2000-12-18 2008-01-30 三菱電機株式会社 Power semiconductor device

Also Published As

Publication number Publication date
JP2010109158A (en) 2010-05-13

Similar Documents

Publication Publication Date Title
JP6520437B2 (en) Semiconductor device
US20160005675A1 (en) Double sided cooling chip package and method of manufacturing the same
JP6065979B2 (en) Semiconductor device
JP7199167B2 (en) Power semiconductor module, power converter, and method for manufacturing power semiconductor module
JP6218898B2 (en) Power semiconductor device
JP4985810B2 (en) Semiconductor device
WO2014097798A1 (en) Semiconductor device
JP2011228638A (en) Semiconductor device equipped with semiconductor module
JP2006303290A (en) Semiconductor device
JP2015076562A (en) Power module
WO2013088864A1 (en) Semiconductor device
WO2022215357A1 (en) Semiconductor device
JP4575034B2 (en) Inverter device
JP6381764B1 (en) Semiconductor power module
JP5060453B2 (en) Semiconductor device
JP6590952B2 (en) Semiconductor device
JP2005116702A (en) Power semiconductor module
WO2019038876A1 (en) Semiconductor device
JP2009021445A (en) Inverter apparatus
JP4375299B2 (en) Power semiconductor device
JP4120581B2 (en) Power module
JP2011100855A (en) Power semiconductor device
JP2006066464A (en) Semiconductor device
JP2004096135A5 (en)
JP2005268496A (en) Semiconductor device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20110117

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20120213

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20120221

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120420

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20120724

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20120803

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20150810

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Ref document number: 5060453

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350