JP5055644B2 - Mounting evaluation structure and mounting evaluation method - Google Patents

Description

  The present invention relates to a mounting evaluation structure and a mounting evaluation method for evaluating a state in which a chip is mounted on a substrate by a flip chip bonding method, and in particular, a flip chip bonding mounting machine (hereinafter referred to as a flip chip bonder). The present invention relates to a mounting evaluation structure and a mounting evaluation method for evaluating bonding accuracy.

  In the conventional flip chip mounting evaluation method, when evaluating the process of flip chip mounting a bumped LSI chip on a wiring board, a product bump is formed on one side of a dummy chip made of transparent glass and having the same size and shape as the LSI chip of the product. Trial of flip chip mounting is performed using a dummy chip with bumps in which the same bumps are arranged in the same arrangement as the LSI chip with bumps of the product and through the same bump base metal film, and the bonding part of the trial product and its periphery are tested. The bonding position accuracy, bump connection shape, and the like are checked by visually observing through the dummy chip (see, for example, Patent Document 1).

Further, although not belonging to the technical field related to the flip chip bonder, an element that measures an alignment error based on capacitance is also known. For example, in Patent Document 2, a lower conductive film extending in the Y direction is formed on a base insulating layer, and an insulating layer is further formed thereon. On the insulating layer, a strip-shaped upper conductive film is formed adjacent to the lower conductive film and extending in the Y direction. In addition, the conventional mask-to-wafer measurement apparatus described in Patent Document 3 creates an electrode pattern on either the surface of the mask that faces the wafer or the surface of the wafer that faces the mask. And a capacitive position sensor including the electrode pattern.
JP 2001-68514 A JP 2003-172601 A JP 63-107022 A

  However, the conventional flip mounting evaluation method evaluates the flip mounting process visually, and is not necessarily accurate, and there is a problem that a defect in the bonding portion may be overlooked.

  In particular, the conventional flip mounting evaluation method checks the bonding position accuracy by visually confirming the bonding portion through a transparent dummy chip, and the positional deviation on the xy plane (two-dimensional displacement). However, there has been a problem that the displacement in the z direction (three-dimensional displacement) cannot be checked.

  The alignment error measuring element in the conventional semiconductor device does not evaluate the bonding accuracy but measures the misalignment amount (alignment error) of the etching mask processed by using the photolithography technique. That is, since the measurement of the alignment error by the conventional measuring element is detected by the change in the capacitance value of the capacitor itself formed of the interlayer insulating film, there is a problem that the shift amount in the z direction cannot be measured.

  Here, when a plurality of ball bumps are formed on the chip, the bump height varies. For this reason, even if the chip is mounted on the substrate and the parallelism between the chip and the substrate is maintained, the portion of the ball bump where the bump height is the minimum value is connected to the chip and the substrate via the ball bump. May not be in contact (conducting).

  On the other hand, the conventional gap measuring device between the mask and the wafer can measure the gap between the mask and the wafer based on the electrostatic capacitance of the opposing electrodes. The feature of this gap measuring device is the flip chip bonder. It is considered that the idea of evaluating the conduction state between the chip and the substrate cannot be easily conceived by simply applying to the above.

  The present invention has been made to solve the above-described problems, and provides a mounting evaluation structure and a mounting evaluation method capable of three-dimensionally evaluating the mounting state of a chip on a substrate without relying on visual observation. To do.

  In the mounting evaluation structure according to the present invention, a plurality of first electrode patterns disposed on the substrate and a plurality of second electrode patterns disposed on the chip so as to face the first electrode patterns, respectively. Are formed, the capacitances in the plurality of capacitance units are compared, and the mounting state of the chip on the substrate is evaluated based on the comparison result.

  In the mounting evaluation structure according to the present invention, a plurality of first electrode patterns disposed on the substrate and a plurality of second electrode patterns disposed on the chip so as to face the first electrode patterns, respectively. And forming a plurality of capacitance portions, comparing the capacitance in the plurality of capacitance portions, and evaluating the mounting state of the chip on the substrate based on the comparison result, The mounting state of the chip on the substrate can be evaluated accurately and in a short time by electrical measurement instead of optical measurement as in the flip mounting evaluation method.

(First embodiment of the present invention)
FIG. 1 is a plan view showing a schematic configuration of a mounting evaluation substrate according to the first embodiment, FIG. 2 is a plan view showing a schematic configuration of a mounting evaluation chip according to the first embodiment, and FIG. FIG. 4 is a cross-sectional view taken along line AA in the bonding state of the mounting evaluation substrate shown in FIG. 2 and the mounting evaluation chip shown in FIG. 2, and FIG. 4 is an explanatory diagram for explaining a measurement method by configuring a bridge circuit FIG. 3 is a plan view showing an example of a stress evaluation pattern.

  As shown in FIG. 1, a mounting evaluation substrate 10 that is an RS (reference substrate) has a plurality of pads (hereinafter referred to as first pads 11) corresponding to ball bumps 1 of a mounting evaluation chip 20 described later. The mounting evaluation chip 20 is mounted on the mounting surface 10a by a flip chip bonding method.

  In the following description, when the mounting evaluation chip 20 is mounted on the mounting surface 10a of the mounting evaluation substrate 10, the region where the mounting evaluation chip 20 overlaps on the mounting surface 10a is referred to as an overlapping region S. An area other than the overlapping area S on the surface 10a will be referred to as a peripheral area P for explanation. The mounting evaluation substrate 10 and the mounting evaluation chip 20 are collectively referred to as a mounting evaluation device 100.

  Moreover, although the board | substrate 10 for mounting evaluation which concerns on this embodiment uses the glass substrate which made the planar shape square with the planar shape as 15.0 mm x 15.0 mm, and made the material into quartz glass as a base material. However, it is not limited to this specification.

  In addition, the first pad 11 according to the present embodiment has a mounting surface 10a with a planar shape of square, a planar dimension of 40 μm × 40 μm, a material of Al—Si alloy, and an interval between adjacent pads of 50 μm. 136 (total of 544) are arranged in parallel on each side of the overlapping region S, but the present invention is not limited to this specification.

  The first electrode pattern 30a is disposed in the overlapping region S of the mounting surface 10a of the mounting evaluation substrate 10, and a connection wiring portion (hereinafter referred to as a first connection wiring portion 12) disposed in the overlapping region S. And connected to the external terminal 14 disposed on the peripheral portion of the mounting surface 10a through the lead wiring portion 13 disposed in the peripheral region P.

  Further, the first electrode pattern 30a is disposed at a predetermined position on the mounting surface 10a of the mounting evaluation substrate 10 in order to form the electrostatic capacitance portion 30 so as to face a second electrode pattern 30b described later. The In particular, in order to achieve the effects of the present invention, which will be described later, a plurality of capacitance portions 30 are required. Therefore, the first electrode pattern 30a is an overlapping region of the mounting surface 10a of the mounting evaluation substrate 10. A plurality of S are arranged.

  Note that the first electrode pattern 30a according to the present embodiment has a planar shape of a square, a planar dimension of 2.0 mm × 2.0 mm, a material of Al—Si alloy, and the overlapping region S of the mounting surface 10a. One (a total of four) is arranged in the vicinity of each corner. If a desired capacitance in the capacitance unit 30 (for example, 2 pF which is the resolution of the measuring device) can be obtained, this It is not limited to specifications.

  The external terminal 14 is exposed on the mounting surface 10a of the mounting evaluation board 10 in order to abut a probe of a measuring device (not shown) provided with a signal processing circuit for detecting the capacitance in the capacitance section 30. ing.

  In addition, the external terminal 14 according to the present embodiment has a planar shape of a rectangle, a planar dimension of 1.5 mm × 0.7 mm, and a material made of an Al—Si alloy, and each of the mounting surfaces 10 a of the mounting evaluation substrate 10. Although 10 pieces (40 pieces in total) are juxtaposed on the side, it is not limited to this specification.

  Moreover, it is preferable that the plurality of external terminals 14 according to the present embodiment be arranged so that at least one of the adjacent external terminals 14 is a ground terminal. As a result, a high-frequency probe whose characteristic impedance is matched can be connected to the signal terminal and the ground terminal, which are the external terminals 14, and accurate high-frequency impedance measurement between the first electrode pattern 30a and the second electrode pattern 30b can be performed. Can be done.

  The high-frequency probe has a coaxial structure and a coplanar structure, and the characteristic impedance is generally 50Ω. The measurable frequency band differs depending on the measuring device used and the high-frequency probe. For example, as a high-frequency probe, a high-frequency probe having a coplanar structure in which the distance between the signal electrode and the ground electrode is 0.5 mm or less. If a high-frequency vector network analyzer is used as a measuring device, high-frequency impedance measurement up to about 20 GHz can be performed.

  Incidentally, if no ground terminal is provided in the vicinity of the signal terminal, which is the external terminal 14, an impedance-matched high-frequency probe cannot be connected, so that the reflection loss and insertion loss of the high-frequency signal are large and accurate. I cannot perform high frequency impedance measurement. In this case, the upper limit of the measurable frequency is several tens of MHz.

  In particular, an existing coplanar high-frequency probe having a ground-signal 1-signal 2-ground electrode arrangement that can contact four terminals at the same time by arranging ground terminals on both sides across two signal terminals is used. It becomes possible to do. As a result, since a probe having two signal lines per probe can be used, the number of probes used is halved and the cost of the probe can be reduced. Further, the probe time for the mounting evaluation apparatus 100 can be reduced by half compared to the case where an existing coplanar high-frequency probe (hereinafter referred to as a single-line probe) having an electrode arrangement of only signal-ground is used. In addition, since the two signal terminals can be contacted by the same probe, the mechanical contact position between the probe and the signal terminal is always constant, and depends on the instability at the mechanical contact position that is a problem in the single-wire probe. Measurement instability can be removed.

  In addition, as shown in FIG. 3, the mounting evaluation substrate 10 according to the present embodiment forms a thin film of Al-Si engagement gold on a glass substrate as a base material and patterns it into a desired shape. The first electrode pattern 30a, the first pad 11, the first connection wiring portion 12, the lead wiring portion 13, and the external terminal 14 are formed in a single layer.

  As shown in FIG. 2, a mounting evaluation chip 20 that is a TEG (test element group) is formed on a plurality of pads (hereinafter referred to as second pads 21) disposed along the peripheral edge of the lower surface 20 a. A plurality of ball bumps 1 are respectively disposed.

  Further, the mounting evaluation chip 20 has a configuration in which the ball bump 1 is not disposed in the central region of the lower surface 20a but only in the vicinity of the peripheral portion, and the bonding state with the mounting evaluation substrate 10 in the peripheral portion is evaluated. Use a chip to do that.

  The mounting evaluation chip 20 according to the present embodiment uses a glass chip having a square shape as a base, a plane size of 7.4 mm × 7.4 mm, and a material made of quartz glass. However, it is not limited to this specification.

  In addition, the second pad 21 according to the present embodiment has a planar shape of square, a planar dimension of 40 μm × 40 μm, a material of Al—Si alloy, and an interval between adjacent pads of 50 μm for mounting evaluation. Although 136 pieces (total of 544 pieces) are arranged in parallel on each side of the lower surface 20a of the chip 20, it is not limited to this specification.

The second electrode pattern 30b is disposed on the lower surface 20a of the mounting evaluation chip 20, and is connected to the second pad 21 via a connection wiring portion (hereinafter referred to as a second connection wiring portion 22). .
Also, the second electrode pattern 30b is formed on the mounting evaluation substrate 10 by mounting the mounting evaluation chip 20 on the mounting evaluation substrate 10 by the flip chip bonding method. The first pad 11 is electrically connected, and is connected to the external terminal 14 through the lead wiring portion 13 connected to the first pad 11.

  Further, the second electrode pattern 30b is disposed at a predetermined position on the lower surface 20a of the mounting evaluation chip 20 in order to form the electrostatic capacitance portion 30 so as to face the first electrode pattern 30a. In particular, since a plurality of capacitance portions 30 are necessary to achieve the effects of the present invention described later, a plurality of second electrode patterns 30b are arranged on the lower surface 20a of the mounting evaluation chip 20. Let

  The second electrode pattern 30b according to the present embodiment has a square shape as a planar shape, a planar dimension as 2.0 mm × 2.0 mm, and a material as an Al—Si alloy, and the lower surface 20a of the mounting evaluation chip 20. 1 (total of 4) are arranged in the vicinity of each corner, but if the desired capacitance in the capacitance unit 30 (for example, 2 pF which is the resolution of the measuring device) can be obtained, It is not limited to this specification.

  In addition, as shown in FIG. 3, the mounting evaluation chip 20 according to the present embodiment forms a thin film of Al-Si engagement gold on a glass chip as a base material and patterns it into a desired shape. The second electrode pattern 30b, the second pad 21, and the second connection wiring portion 22 are formed in a single layer.

  The electrostatic capacity unit 30 has a first electrode pattern 30a and a second electrode pattern 30b facing each other having the same planar shape and planar dimensions, and a plurality of electrostatic capacity units 30 (here, four electrostatic capacity units). The first electrode patterns 30a and the second electrode patterns 30b of 30) have the same planar shape and planar dimensions. That is, all the first electrode patterns 30a and the second electrode patterns 30b have the same planar shape and planar dimensions.

  In addition, the capacitance unit 30 is flip-chip mounted on the mounting evaluation substrate 10 so that the mounting evaluation chip 20 is normal (the mounting evaluation substrate 10 and the mounting evaluation chip 20 are substantially parallel and facing each other). When bonded, the first electrode pattern 30a and the second electrode pattern 30b facing each other completely overlap in the direction perpendicular to the mounting evaluation substrate 10.

  That is, when the mounting evaluation chip 20 is normally flip-chip bonded on the mounting evaluation substrate 10, the distance between the first electrode pattern 30a and the second electrode pattern 30b facing each other is the total capacitance. Since the areas where the first electrode pattern 30a and the second electrode pattern 30b facing each other are equal in the portion 30 and are equal in all the capacitance portions 30, the capacitances in the four capacitance portions 30 are , All become equal values.

  Therefore, in the mounting evaluation structure according to the present embodiment, each of the capacitances in the plurality of capacitance units 30 is measured. If all the measured values are equal, the mounting evaluation chip 20 is mounted on the mounting evaluation substrate 10. It can be determined that the mounting state is normally flip-chip bonded. Further, if the capacitances in the plurality of capacitance units 30 are not all equal measurement values, the mounting evaluation chip 20 is mounted abnormally (inclined) on the mounting evaluation substrate 10 by flip chip bonding. It can be determined that the state is present.

  In particular, in the mounting evaluation structure according to the present embodiment, the overlapping area S of the first electrode pattern 30a and the second electrode pattern 30b facing each other, and between the first electrode pattern 30a and the second electrode pattern 30b facing each other. The value of the gap d between the first electrode pattern 30a and the second electrode pattern 30b is calculated based on the dielectric constant ε and the measured value of the capacitance C in the capacitance section 30. When the gap d between the first electrode pattern 30a and the second electrode pattern 30b is smaller than the minimum bump height due to height variation in the formation of the ball bump 1, the mounting evaluation chip 20 and the mounting chip are mounted. It can be determined that all the ball bumps 1 are in contact with the evaluation substrate 10 (conductive state).

  In addition, since the mounting evaluation apparatus 100 according to the present embodiment includes a plurality of capacitance units 30, the difference between the capacitances in the plurality of capacitance units 30 can be calculated. The configuration is not limited to the configuration including the four capacitance units 30.

  However, when the mounting evaluation apparatus 100 according to the present embodiment includes only two capacitance units 30, the mounting evaluation chip 20 uses the straight line connecting the two capacitance units 30 as a rotation axis. When the flip chip mounting is performed at an inclination, the capacitances of the two capacitance units 30 have the same value, so that an abnormality in the mounting state cannot be detected.

Therefore, it is preferable that the mounting evaluation apparatus 100 according to the present embodiment includes three or more capacitance units 30 in which all the capacitance units 30 are not arranged in parallel on the same straight line.
In addition, the mounting evaluation apparatus 100 according to the present embodiment includes the four electrostatic capacity units 30, so that when evaluating the mounting state, the four electrostatic capacity units 30 may be connected to form a bridge circuit. It is done.

  With this configuration, the voltage is applied to the primary side (one diagonal) of the bridge circuit, the voltage on the secondary side (the other diagonal) is measured, and the secondary side voltage is zero (including the allowable range). In this case, since the capacitances of the four capacitance units 30 are in an equilibrium state, it can be determined that the mounting evaluation chip 20 is normally flip-chip bonded on the mounting evaluation substrate 10.

  In addition, the mounting evaluation apparatus 100 according to the present embodiment inputs a voltage to the primary side (one diagonal) of the wiring pattern connecting the adjacent capacitance units 30 and the bridge circuit in order to configure the bridge circuit. Even if the terminal and the wiring pattern for measuring the voltage on the secondary side (other diagonal) of the bridge circuit and the wiring pattern for measuring the voltage on the secondary side of the bridge circuit are formed on the mounting surface 10a of the mounting evaluation substrate 10 in advance. Good.

  Note that the mounting evaluation apparatus 100 according to the present embodiment does not particularly limit the arrangement of the capacitance unit 30, but each of the overlapping regions S of the mounting evaluation substrate 10 (the lower surface 20a of the mounting evaluation chip 20). By disposing the capacitance part 30 in the vicinity of the corner, when the mounting evaluation chip 20 is mounted with an inclination, compared to the case where the capacitance part 30 is disposed in the central portion of the overlapping region S. Therefore, it is preferable because a difference in capacitance between the plurality of capacitance units 30 can be detected largely, and an abnormal mounting state can be detected without omission.

Next, a method for evaluating the mounting state of the mounting evaluation chip 20 on the mounting evaluation substrate 10 using the mounting evaluation structure will be described.
First, the mounting evaluation chip 20 and the mounting evaluation substrate 10 are put into a flip chip bonder (not shown), which is a target device for verifying bonding accuracy.

  The mounting evaluation chip 20 and the mounting evaluation substrate 10 are positioned based on an alignment mark (not shown) or the like, and the second pad 21 (ball bump 1) of the mounting evaluation chip 20 and the first of the mounting evaluation substrate 10 are displayed. The pad 11 is brought into close contact with each other and bonded by applying heat and pressure.

  The bonding evaluation chip 20 and the mounting evaluation substrate 10 that are joined together are a first electrode that forms a pair of the capacitance unit 30 by contacting a probe of a measuring device (not shown) to the external terminal 14 of the mounting evaluation substrate 10. The capacitance between the pattern 30 a and the second electrode pattern 30 b is measured for each of the four capacitance units 30. As a measuring device, an existing measuring device such as a Q meter, an LCR meter, or an impedance analyzer is used.

  Based on the measurement values of the capacitances in the four capacitance units 30, if the capacitances of the four capacitance units 30 are all equal measurement values, the mounting evaluation substrate 10 is used for mounting evaluation. It is determined that the chip 20 is mounted normally (in a directly facing state).

  On the other hand, if the capacitances of the four capacitance units 30 are not all equal measurement values based on the measurement values of the capacitances in the four capacitance units 30, the mounting is performed on the mounting evaluation substrate 10. It is determined that the evaluation chip 20 is mounted abnormally (tilted state).

As described above, the four electrostatic capacitance units 30 are connected to form a bridge circuit, a voltage is applied to the primary side (one diagonal) of the bridge circuit, and the secondary side (the other diagonal) is applied. The mounting state of the mounting evaluation chip 20 with respect to the mounting evaluation substrate 10 can also be evaluated by measuring the voltage.
In this case, for example, it is conceivable to evaluate the mounting state with a circuit configuration as shown in FIG.

  The measuring apparatus 200 brings the probe 201 (201a to 201h) into contact with the external terminal 14 (14a to 14h), thereby making one external part of the first capacitance unit 31 out of the four capacitance units 30. The terminal 14a and the other external terminal 14h of the fourth capacitance unit 34, the other external terminal 14b of the first capacitance unit 31, the one external terminal 14c of the second capacitance unit 32, the second The other external terminal 14d and the third external capacitance portion 32 of the third electrostatic capacitance section 32, the other external terminal 14f of the third electrostatic capacitance section 33 and the fourth electrostatic capacity section. One external terminal 14g of 34 is connected, and the bridge circuit 2 is comprised.

  Further, the connection point ha between the external terminal 14a of the first capacitance unit 31 and the external terminal 14h of the fourth capacitance unit 34, and the external terminal 14d of the second capacitance unit 32 and the third terminal An AC voltage is applied from the AC voltage generation circuit 202 of the measuring apparatus 200 to a coupling point de with the external terminal 14e of the capacitance unit 33.

  In addition, the differential amplifier circuit 203 of the measuring apparatus 200 includes an AC signal supplied from a coupling point bc between the external terminal 14 b of the first capacitance unit 31 and the external terminal 14 c of the second capacitance unit 32. The differential component between the AC signal supplied from the coupling point fg between the external terminal 14 f of the third capacitance unit 33 and the external terminal 14 g of the fourth capacitance unit 34 is amplified.

  With such a configuration, when the differential signal between the AC signal at the coupling point bc and the AC signal at the coupling point fg is not output from the differential amplifier circuit 203, it can be seen that the bridge circuit 2 is in a balanced state.

  In addition, since there is an error in each capacitance in the four capacitance units 30, even in a normal mounting state, there may be a case where a differential signal is output from the differential amplifier circuit 203. It is preferable to set an allowable range for determining that the differential signal output from the differential amplifier circuit 203 is in a normal mounting state.

  That is, the voltage comparator circuit 204 of the measuring apparatus 200 outputs an H level detection signal when the voltage of the differential signal output from the differential amplifier circuit 203 is higher than the reference voltage set by the variable resistor 205 or the like. Output.

  The voltage comparator circuit 204 outputs an L level detection signal when the voltage of the differential signal output from the differential amplifier circuit 203 is lower than the reference voltage set by the variable resistor 205 or the like.

  Thus, when an H level detection signal is output, it can be determined that the mounting state of the mounting evaluation chip 20 on the mounting evaluation substrate 10 is abnormal (inclined state), and an L level detection signal is output. In the case where it is determined, it can be determined that the mounting state of the mounting evaluation chip 20 with respect to the mounting evaluation substrate 10 is normal (a state facing directly).

  As shown in FIG. 4, the bridge circuit 2 is connected to the measuring apparatus 200, whereby an AC voltage is applied to the coupling point ha and the coupling point de, and an AC signal at the coupling point bc and an AC signal at the coupling point fg. Is configured to detect the presence / absence of a difference signal between the coupling point bc and the coupling point fg, and the presence / absence of a difference signal between the alternating signal at the coupling point ha and the alternating current signal at the coupling point de is detected. A circuit configuration may be adopted. Thereby, as a measuring method using the bridge circuit 2, there are two possible methods.

  In the mounting evaluation apparatus 100 according to the present embodiment, all the first electrode patterns 30a and the second electrode patterns 30b are configured to have the same planar shape and planar dimensions (first capacitance in each capacitance unit 30). The electrode patterns 30a and the second electrode patterns 30b overlap with each other in the overlapping area). However, the first electrode patterns 30a and the second electrode patterns 30b of the plurality of capacitance units 30 are mutually connected. A configuration having different planar shapes and planar dimensions (a configuration in which the overlapping areas of the first electrode pattern 30a and the second electrode pattern 30b in each capacitance unit 30 are different) may be used.

  In this case, each capacitance (the first electrode pattern 30a and the second electrode pattern) in the plurality of capacitance units 30 when the mounting evaluation chip 20 is mounted on the mounting evaluation substrate 10 in a normal state. 30b overlapping area) is calculated or measured in advance. Then, based on the value calculated or measured in advance, the measurement device is provided with a calculation function for correcting the difference between the capacitances of the plurality of capacitance units 30 to zero. The state can be evaluated.

  However, the mounting evaluation apparatus 100 can make the counter electrode of the electrostatic capacitance unit 30 into a simple and uniform shape, and corrects the difference between the electrostatic capacitances in the plurality of electrostatic capacitance units 30 to zero. Since it is not necessary to provide the calculation function to the measurement apparatus, it is preferable that all the first electrode patterns 30a and the second electrode patterns 30b described above have the same planar shape and planar dimensions.

  In the mounting evaluation apparatus 100 according to the present embodiment, the first electrode pattern 30a (first connection wiring portion 12) is formed on the glass substrate that is RS, and the second electrode pattern is formed on the glass chip that is TEG. By forming 30b (second connection wiring portion 22), the capacitance of the plurality of capacitance portions 30 can be measured, but it is opposed to the actual wiring board and semiconductor chip. Each of the electrode patterns to be formed may be formed so that the capacitances of the plurality of capacitance units 30 can be measured.

  In this case, for example, the first electrode pattern 30a and the second electrode pattern 30b are respectively connected to a calculation unit built in the semiconductor chip, and the calculation unit sets each electrostatic capacitance in the plurality of capacitance units 30. A configuration in which the mounting state of the mounting evaluation chip 20 on the mounting evaluation substrate 10 is evaluated by calculating the difference in capacitance is also conceivable.

  As described above, it is possible to determine whether or not the mounting evaluation chip 20 is inclined with respect to the mounting evaluation substrate 10 by detecting the difference between the electrostatic capacities in the plurality of capacitance units 30, and the flip chip bonder. The bonding accuracy can be evaluated.

  In the mounting evaluation apparatus 100 according to the present embodiment, any configuration may be used as long as it can measure at least the capacitance between the first electrode pattern 30a and the second electrode pattern 30b that form a pair of the capacitance unit 30. However, it is good also as a structure which can use another evaluation test together.

  For example, the stress evaluation pattern 3, which is a vernier, may be disposed in the vicinity of the corner in the overlapping region S of the mounting surface 10 a of the mounting evaluation substrate 10 or in the vicinity of the corner of the lower surface 20 a of the mounting evaluation chip 20. For example, as shown in FIG. 5, the stress evaluation pattern 3 is a rectangular pattern having a material length of Cr, a pattern length of 60 μm, and a pattern width of 4.8 μm. A scale shape is formed by arranging them in parallel at a pitch of 75 μm and projecting the pattern length of 70 μm at intervals of four lines.

  Since the mounting evaluation chip 20 according to the present embodiment uses a transparent glass chip, even when the stress evaluation pattern 3 is disposed on the lower surface 20a of the mounting evaluation chip 20, The mounting evaluation chip 20 can be imaged before and after the mounting evaluation chip 20 is mounted on the mounting evaluation substrate 10, and the mounting evaluation chip 20 is compared by performing image processing and comparing the differences. The degree (strain) of the stress applied to can be detected.

  On the other hand, even when the opaque mounting evaluation chip 20 is used, if the thickness of the mounting evaluation chip 20 is 50 μm or less, infrared light can be transmitted through the mounting evaluation chip 20. The degree (strain) of the stress applied to the mounting evaluation chip 20 can be detected.

  In particular, when an underfill (not shown) is formed in the gap between the mounting evaluation substrate 10 and the mounting evaluation chip 20, the mounting evaluation chip 20 may be expanded and contracted, and this is added to the mounting evaluation chip 20 due to underfill. The degree of stress can be detected.

Underfill is a first-in type where a chip is mounted after a liquid resin is applied or a film-like resin is laid on the substrate, and a liquid resin is injected by capillary action after the chip is mounted on the substrate. There is a last-in type. Therefore, the fact that the mounting evaluation substrate 10 and / or the mounting evaluation chip 20 is transparent also has the effect that the state of the underfill inserted into the gap between the mounting evaluation substrate 10 and the mounting evaluation chip 20 can be visually recognized. is there.
Moreover, the following structures are also considered as a structure which can use together the other evaluation test of the mounting evaluation apparatus 100 which concerns on this embodiment.

  For example, the adjacent first pads 11 in the mounting evaluation substrate 10 are not connected or connected so as to be alternately open or short, and the adjacent second pads 21 in the mounting evaluation chip 20 are for mounting evaluation. It is good also as a structure provided with the single line which makes the chain which has a start end and a termination | terminus by inverting with respect to the non-connection or connection between the adjacent 1st pads 11 in the board | substrate 10, and making it a connection or non-connection.

  With this configuration, when the mounting evaluation chip 20 is mounted on the mounting evaluation substrate 10, a signal is input from the starting end of the single line, and the presence / absence of a signal at the terminal end is checked, so that all the first between the both ends are checked. The conduction state by the ball bump 1 between the first pad 11 and the second pad 21 can be evaluated at a time. However, even if it can be determined that the single line is disconnected, the location where the single line is disconnected cannot be specified. In particular, since there are hundreds of places where the ball bumps 1 are connected to the first pad 11 and the second pad 21 in the vicinity of the peripheral edge of the mounting evaluation chip 20, the non-conductive first pad 11. And it is difficult to specify the second pad 21.

  For this reason, in order to identify a contact failure or a non-conducting place due to a crack occurring in the solder that fixes between the first pad 11 and the second pad 21, time domain reflection (hereinafter referred to as TDR) is referred to. ) Method can be considered. This TDR method is a measurement method that can know the line impedance, line length, and transmission speed, and sends a step signal with a high-speed switching operation with a rise time of about 20 to 50 ps to the transmission line, and reflects the reflected waveform in a high band. Observe with an oscilloscope with special characteristics.

  That is, when a contact failure or non-conduction occurs due to the ball bumps 1 of the first pad 11 and the second pad 21 on the single line passing through the first pad 11 and the second pad 21 in the mounting evaluation apparatus 100. In this case, the impedance of the single line fluctuates, and the location of contact failure or non-conduction can be specified by the TDR method. In particular, when the first pad 11 and the second pad 21 are disconnected and the single line is disconnected, the non-conductive portion where the transmission path from the start end is the shortest is the end, and the incident light incident from the start end The wave is reflected at the non-conducting portion, and the reflected wave is detected at the start end.

  When the pitch between adjacent ball bumps 1 (first pad 11 and second pad 21) is too narrow (for example, 120 μm), the line length may not be detected using the TDR method. For this reason, it is preferable to connect between the 1st pads 11 (2nd pad 21) with the space | interval which can detect line length using a TDR method. For example, when the interval between adjacent first pads 11 (second pads 21) is d and the interval at which the line length can be detected using the TDR method is 2d, the first pads 11 ( The adjacent first pads 11 (second pads 21) are not connected to each other and the first pads 11 (second pads 21) are spaced so that the distance between the second pads 21) is 2d. ), The line length between the first pads 11 (second pads 21) to be connected can be earned. Then, using the TDR method, an analysis is performed, such as observing a cross-sectional shape in the vicinity of the location where the reference is provided, by providing a reference to a location where contact failure or non-conduction between the first pad 11 and the second pad 21 is established. Thus, it is possible to specify a contact failure or non-conduction place between the first pad 11 and the second pad 21.

It is a top view which shows schematic structure of the board | substrate for mounting evaluation which concerns on 1st Embodiment. It is a top view which shows schematic structure of the chip | tip for mounting evaluation which concerns on 1st Embodiment. It is sectional drawing of the arrow AA of the bonding state of the mounting evaluation board | substrate shown in FIG. 1, and the mounting evaluation chip | tip shown in FIG. It is explanatory drawing for demonstrating the measuring method by comprising a bridge circuit. It is a top view which shows an example of the pattern for stress evaluation.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Ball bump 2 Bridge circuit 3 Stress evaluation pattern 10 Mounting evaluation board | substrate 10a Mounting surface 11 1st pad 12 1st connection wiring part 13 Lead wiring part 14, 14a, 14b, 14c, 14d, 14e, 14f, 14g , 14h External terminal 20 Mounting evaluation chip 20a Lower surface 21 Second pad 22 Second connection wiring portion 30 Capacitance portion 30a First electrode pattern 30b Second electrode pattern 31 First capacitance portion 32 First 2 electrostatic capacity part 33 3rd electrostatic capacity part 34 4th electrostatic capacity part 100 Mounting evaluation apparatus 200 Measuring apparatus 201 Probe 202 AC voltage generation circuit 203 Differential amplifier circuit 204 Voltage comparator circuit 205 Variable resistor P Peripheral area S Overlapping area bc, de, fg, ha Join point

Claims (4)

A chip in which a plurality of ball bumps are disposed along the edge of the lower surface is mounted on a substrate on which a plurality of pads corresponding to the plurality of ball bumps are disposed by a flip chip bonding method. In the implementation evaluation structure that evaluates
A plurality of electrostatic patterns comprising a plurality of first electrode patterns disposed on the substrate and a plurality of second electrode patterns disposed on the chip so as to face the first electrode patterns, respectively. A mounting evaluation structure characterized in that a capacitance portion is formed, the capacitances in the plurality of capacitance portions are compared, and the mounting state of the chip on the substrate is evaluated based on the comparison result. In the mounting evaluation structure according to claim 1,
Based on the capacitance in the capacitance section, the value of the gap between the first electrode pattern and the second electrode pattern is calculated, and the gap height is a bump height due to height variation in the formation of the ball bump. A mounting evaluation structure characterized by determining that the mounting state is normal when the value is smaller than the minimum value. In the mounting evaluation method using the mounting evaluation structure according to claim 1 or 2,
A first step of mounting the chip on the substrate by flip chip bonding;
A second step of measuring each capacitance in the plurality of capacitance units,
Based on the measured value of each capacitance obtained in the second step, when all the capacitances in the plurality of capacitance parts are equal, the mounting state of the chip on the substrate is normal. A third step of determining that there is,
A mounting evaluation method characterized by comprising: In the mounting evaluation structure according to claim 2,
A first step of mounting the chip on the substrate by flip chip bonding;
A second step of connecting the four capacitance units so as to form a bridge circuit, applying a voltage to the primary side of the bridge circuit, and measuring a secondary side voltage;
A third step of determining that the mounting state of the chip on the substrate is normal when the secondary voltage obtained in the second step is zero;
A mounting evaluation method characterized by comprising:

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