JP5050905B2 - Semiconductor circuit design program and semiconductor circuit design apparatus - Google Patents

Description

The present invention relates to a semiconductor circuit design program and a semiconductor circuit design equipment designing a semiconductor circuit.

  In recent years, various ASICs such as a gate array (hereinafter referred to as “G / A”) and an embedded array (hereinafter referred to as “E / A”) are used in order to cope with various and complicated semiconductor circuit designs. Is provided. G / A is an ASIC that is configured from a wafer on which a large number of transistors are formed, and a user designs only the wiring layer above the wafer. E / A is an ASIC of a system in which wafer manufacture of a cell base IC and circuit design are performed in parallel (see, for example, Patent Document 1 below).

  Both G / A and E / A have the feature that the design period and manufacturing process can be expected to be shortened, but on the other hand, the arrangement of elements of FFs and other transistors constituting the semiconductor circuit is patterned. Therefore, depending on the design contents, there is a possibility that the configuration includes redundant elements. Therefore, in recent years, standard cells (hereinafter referred to as “S / C”) have been provided and widely used as ASICs that can be flexibly handled depending on the design contents (for example, see Patent Document 2 below).

  In the case of S / C, macrocells prepared in advance can be placed and wired on a blank wafer. Further, since S / C has higher integration and circuit speed than G / A and E / A, the area can be reduced. On the other hand, since the S / C is manufactured from the diffusion layer of the wafer in order to realize the above-described degree of freedom, the manufacturing process and development costs tend to be higher than those of G / A and E / A. . Therefore, the semiconductor circuit designer has used the optimum method in consideration of the design environment of the semiconductor circuit, the design environment such as the application and the development cost.

JP 2004-13205 A US Pat. No. 6,242,767

  However, when a semiconductor circuit designed by G / A or E / A is manufactured as in Patent Document 1, power consumption is higher than that of a semiconductor circuit designed by S / C having an equivalent function. There was a problem of getting bigger.

  Further, when using S / C as in Patent Document 2, the designed semiconductor circuit has a configuration in which a certain amount of flip-flops are embedded in each block unit. Therefore, depending on the configuration content of the logic circuit included in the semiconductor circuit, the FF may be excessive or insufficient. In order to eliminate such a situation, there is a problem that the semiconductor circuit has a redundant layout, resulting in an inefficient circuit configuration.

  Further, in recent years, since the miniaturization of semiconductor circuits has progressed, there has been a problem that manufacturing variations during the manufacture of semiconductor circuits become large regardless of which method is used.

An object of the present invention is to provide a semiconductor circuit design program and a semiconductor circuit design apparatus for designing a semiconductor circuit that has low power consumption, a circuit-saving size, and an easy layout in order to solve the above-described problems caused by the prior art. And

In order to solve the above-described problems and achieve the object, the semiconductor circuit design program and the semiconductor circuit design apparatus obtain a net list relating to a semiconductor circuit to be designed, and a flip-flop included in the obtained net list And the transistors outside the flip-flops, and the extracted flip-flops are integrated for each predetermined number so that the flip-flops have a larger number of input / output bits than the flip-flops, the number of flip-flops after the integration, calculates the ratio between the number of the extracted transistors, basic blocks and the number of the number and the transistors of the flip-flop after the integration according to the ratio the calculated And a process for generating design data of the semiconductor circuit.

  According to the semiconductor circuit design program and the semiconductor circuit design apparatus, since the flip-flop described in the netlist is integrated into the flip-flop having a larger number of bits, the number of flip-flops included in the semiconductor circuit to be designed Can be reduced. Further, since the basic block is set based on the ratio between the number of flip-flops after integration and the number of transistors, a semiconductor circuit configured with the minimum number of flip-flops can be designed.

In addition, the semiconductor circuit design program and the semiconductor circuit design apparatus may use the number of transistors per one flip-flop after integration as a basic block based on the ratio .

  According to the semiconductor circuit design program and the semiconductor circuit design apparatus, a semiconductor circuit is formed by a basic block including one flip-flop (flip-flop after integration) and a number of transistors based on the ratio calculated as described above. Design data can be generated.

  The semiconductor circuit design program and the semiconductor circuit design apparatus may generate the design data using a basic block group in which the flip-flop after integration and the transistor are arranged in the same manner.

  According to the semiconductor circuit design program and the semiconductor circuit design apparatus, it is possible to generate design data in which the semiconductor circuit is configured only by the same basic block.

According to the semiconductor circuit design program and the semiconductor circuit design apparatus, it is possible to design and provide a semiconductor circuit that has low power consumption, a small circuit size, and an easy layout.

Exemplary embodiments of a semiconductor circuit design program and a semiconductor circuit design apparatus will be described below in detail with reference to the accompanying drawings.

(Outline of semiconductor circuit design process)
First, an outline of the semiconductor circuit design process according to the present embodiment will be described. FIG. 1 is an explanatory diagram showing an outline of a semiconductor circuit design process according to the present embodiment. As shown in FIG. 1, in the present embodiment, the design data 120 of the design target circuit 111 is generated by the semiconductor circuit design apparatus 100. In FIG. 1, the semiconductor circuit design apparatus 100 is realized by causing a general-purpose information processing apparatus to execute a semiconductor circuit design program 101. Note that the present invention is not limited to the configuration shown in FIG. 1, and a device provided with a functional unit to be described later may be provided as a semiconductor circuit design device 100.

  As a procedure of the semiconductor circuit design process, first, as in the conventional semiconductor circuit design, the net list 110 of the design target circuit 111 is acquired. Then, the semiconductor circuit design device 100 extracts flip-flops (hereinafter referred to as “FF”) and transistors outside the FF constituting the design target circuit 111 from the acquired description of the netlist 110.

  Here, the net list 110 is data representing connection information between terminals in the design target circuit 111. Further, the transistor outside the FF represents a transistor other than the transistors constituting the FF included in the design target circuit 111.

  The extracted FF is integrated into an FF having a larger number of bits. In order to perform integration, first, if the FF described in the netlist 110 is a 1-bit FF whose input / output is 1 bit, this 1-bit FF is converted into a 2-bit FF, 4-bit FF, etc. Convert to The converted FFs are further integrated for each FF number corresponding to the number of input / output bits, thereby integrating the FFs.

  Specifically, for example, if the extracted FF is a 1-bit FF, when these 1-bit FFs are integrated into a 2-bit FF, the input and output of the two FFs are combined into one 2-bit FF. Integration is performed by converting to FF. Similarly, four 1-bit FFs may be integrated into a 4-bit FF, and two 2-bit FFs may be integrated into a 4-bit FF.

  When integrating the FFs as described above, the number of FF bits for converting the extracted FFs may be integrated into a FF having a preset number of bits, or during the semiconductor circuit design process. The number of bits to be integrated into the FF by the designer may be appropriately selected according to the design conditions. In any case, in the design target circuit 111 represented by one net list 110, the FFs used for FF integration need to have the same number of bits.

  In the semiconductor circuit design device 100, after the FFs are integrated, the FFs (after integration) in the design target circuit 111 are compared with the number of transistors, and the ratio is calculated. Further, the basic block 122 is set based on the calculated ratio. Then, the design data 120 of the design target circuit 111 is generated using the basic block 122.

  The semiconductor circuit 121 manufactured by the design data 120 is constituted by a set of basic blocks 122. That is, in order to manufacture the semiconductor circuit 121, the same basic block 122 including FFs (black blocks) and transistors (white blocks) arranged at a fixed ratio may be manufactured. Therefore, since the same pattern manufacturing is repeated, manufacturing variations can be suppressed.

  As described above, in this embodiment, the basic block 122 in which FFs are integrated from the net list 110 is set, and the design data 120 of the design target circuit 111 is generated using the basic block 122. The semiconductor circuit 121 configured by the above can be manufactured. Therefore, it is possible to prevent an increase in area and an increase in power consumption caused by excessive arrangement of FFs in the semiconductor circuit 121 as in the conventional ASIC.

  Hereinafter, a specific apparatus configuration and processing contents for realizing the above-described semiconductor circuit design processing will be specifically described.

(Hardware configuration of semiconductor circuit design equipment)
First, the hardware configuration of the semiconductor circuit design apparatus 100 according to the present embodiment will be described. FIG. 2 is an explanatory diagram showing a hardware configuration of the semiconductor circuit design apparatus according to the present embodiment.

  In FIG. 2, the semiconductor circuit design device 100 is composed of a computer main body 210, an input device 220, and an output device 230, and a network 240 such as a LAN, WAN, or Internet via a router or modem (not shown). Can be connected to.

  The computer main body 210 has a CPU, a memory, and an interface. The CPU controls the entire semiconductor circuit design apparatus 100. The memory is composed of ROM, RAM, HD, optical disk 211, and flash memory. The memory is used as a work area for the CPU.

  Various programs are stored in the memory, and loaded according to instructions from the CPU. Data read / write of the HD and the optical disk 211 is controlled by a disk drive. The optical disk 211 and the flash memory are detachable from the computer main body 210. The interface controls input from the input device 220, output to the output device 230, and transmission / reception with respect to the network 240.

  The input device 220 includes a keyboard 221, a mouse 222, a scanner 223, and the like. The keyboard 221 includes keys for inputting characters, numbers, various instructions, and the like, and inputs data. Further, it may be a touch panel type. The mouse 222 performs cursor movement, range selection, window movement, size change, and the like. The scanner 223 optically reads an image. The read image is captured as image data and stored in a memory in the computer main body 210. Note that the scanner 223 may have an OCR function.

  Examples of the output device 230 include a display 231, a speaker 232, and a printer 233. The display 231 displays data such as a document, an image, and function information as well as a cursor, an icon, or a tool box. The speaker 232 outputs sounds such as sound effects and reading sounds. The printer 233 prints image data and document data.

(Functional configuration of semiconductor circuit design equipment)
Next, a functional configuration of the semiconductor circuit design apparatus 100 will be described. FIG. 3 is a block diagram showing a functional configuration of the semiconductor circuit design apparatus. 3, the semiconductor circuit design device 100 includes an acquisition unit 301, an extraction unit 302, an integration unit 303, a calculation unit 304, and a generation unit 305. Each of these functions 301 to 305 realizes the function by causing the CPU to execute a program related to the function 301 to 305 stored in the storage unit of the semiconductor circuit design apparatus 100 or by using an input / output I / F. Can do.

  First, the acquisition unit 301 acquires the netlist 110 in which the configuration of the design target circuit 111 is described. The acquisition unit 301 may acquire the netlist 110 stored in advance by the designer from the memory of the computer main body 210 (see FIG. 2), or may newly acquire it from the input device 220 or the network 240.

  The extraction unit 302 extracts FFs included in the netlist 110 acquired by the acquisition unit 301 and transistors outside the FFs. By this extraction processing, it is possible to total the number of FFs and transistors arranged in the design target circuit 111.

  The integration unit 303 integrates the FFs extracted by the extraction unit 302 so that the number of input / output bits is larger than that of the FFs every predetermined number. As described above, the number of FFs of what number of bits is arranged in the design target circuit 111 by the extraction unit 302 is totalized. Therefore, it is determined how many FFs can be integrated based on the total number of FFs and the number of bits, and the extracted FFs are integrated as FFs having a large number of bits every predetermined number.

  The calculation unit 304 calculates a ratio between the number of FFs after integration by the integration unit 303 and the number of transistors extracted by the extraction unit 302. At this time, the calculation unit 304 further calculates the ratio of transistors per FF after integration as a ratio from the number of FFs after integration by the integration unit 303 and the number of transistors extracted by the extraction unit 302. Also good.

  The generation unit 305 generates design data 120 of the semiconductor circuit 121 having the integrated FFs and transistors according to the ratio calculated by the calculation unit 304 as basic blocks 122. As shown in FIG. 1, the design data 120 is configured such that the semiconductor circuit 121 is realized by a group of basic blocks 122 having the same arrangement of FFs and transistors.

  As described above, when the calculation unit 304 calculates the ratio of transistors per FF after integration as a ratio, the generation unit 305 includes one FF (integrated FF) and the number corresponding to the ratio. Design data 120 is generated using the basic block 122 in which the transistors are arranged.

(Semiconductor circuit design process)
Next, a procedure of semiconductor circuit design processing by the semiconductor circuit design apparatus 100 will be described. FIG. 4 is a flowchart showing a procedure of a semiconductor circuit design process in the semiconductor circuit design apparatus. In the flowchart of FIG. 4, first, the netlist 110 is acquired (step S401).

  Next, FFs and transistors are extracted from the description content of the netlist 110 (step S402). The transistor extracted in step S402 means a transistor other than FF among the semiconductor elements constituting the design target circuit 111 as described above.

  FIG. 5 is a circuit diagram showing an equivalent circuit of the acquired netlist. The equivalent circuit 111a in FIG. 5 represents the description contents of the netlist 110. In the description of the netlist 110, the design target circuit 111 has a configuration in which four 1-bit FFs FF501 to FF504 are arranged. Therefore, the integration unit 303 integrates these extracted FFs into FFs having a large number of bits (step S403).

  FIG. 6 is a circuit diagram showing an equivalent circuit of the netlist after FF integration. The equivalent circuit 111b in FIG. 6 represents the description content of the converted netlist 110 after the FF integration processing in step S403. Here, four 1-bit FFs are integrated into one 4-bit FF 601.

  When the integration in step S403 is completed, the calculation unit 304 calculates the ratio between the integrated FF and the transistor (step S404). Then, the basic block 122 is set from the calculated ratio (step S405). When the basic block 122 is set, finally, the generation unit 305 generates the design data 120 of the semiconductor circuit 121 configured by the basic block 122 (step S406), and the process of the example is finished.

  As described above, in the semiconductor circuit design process according to the present embodiment, the basic block 122 corresponding to the description of the net list 110 is set, and an efficient semiconductor circuit configured by the basic block 122 can be designed. In particular, since the FFs are integrated when setting the basic block 122, the cell area of the semiconductor circuit 121 can be remarkably reduced.

  FIG. 7 is an explanatory diagram showing a size comparison of the cell areas of the circuit to be designed. As shown in FIG. 7, when the cell areas of the 1-bit FF and the transistors outside the FF are compared from the description of the netlist 110, the ratio (F (FF): T (transistor)) as in the block 710 is obtained. Therefore, in order to realize the function of the equivalent circuit 111a shown in FIG. 5, the cell area is at least block 710 × 4, and the ratio is as in block 720.

  On the other hand, the present embodiment includes processing for integrating a plurality of FFs into FFs having a large number of bits. For example, as shown in FIG. 5, when four 1-bit FFs are integrated into one 4-bit FF, the cell area of the FF portion is integrated into ¼, resulting in a ratio like block 730. As is clear from an area comparison between the block 720 before FF integration and the block 730 after FF integration, the cell area of the semiconductor circuit 121 is greatly reduced by integration of the FFs.

  As described above, since the semiconductor circuit 121 designed by the semiconductor circuit design process according to the present embodiment can be configured by the minimum necessary FFs and transistors, the power consumption generated by arranging the surplus FFs can be reduced. Can be reduced.

  Further, in the case of the semiconductor circuit 121 designed by the semiconductor circuit design process according to the present embodiment, the FF extracted from the netlist 110 is integrated into the FF having a larger number of bits, so that the number of FFs is significantly reduced. You can also.

  Furthermore, in the semiconductor circuit design process according to the present embodiment, since the basic block 122 is set based on the FF extracted from the net list 110, an efficient circuit configuration is realized without requiring a redundant layout. be able to. In addition, since the manufacture of the basic block 122 having the same configuration is repeated at the time of circuit manufacture, manufacturing variations at the time of circuit manufacture can be minimized.

  As described above, according to the present embodiment, it is possible to design and provide a semiconductor circuit that has power consumption, a circuit saving size, and an easy layout.

  The semiconductor circuit design process described in this embodiment can be realized by executing a program prepared in advance on a computer such as a personal computer or a workstation. This program is recorded on a computer-readable recording medium such as a hard disk, a flexible disk, a CD-ROM, an MO, and a DVD, and is executed by being read from the recording medium by the computer. The program may be a medium that can be distributed via a network such as the Internet.

  In addition, the semiconductor circuit design apparatus 100 described in the present embodiment includes a specific cell IC (hereinafter simply referred to as “ASIC”) such as a standard cell or a structured ASIC (Application Specific Integrated Circuit), or a PLD (Programmable) such as an FPGA. It can also be realized by Logic Device). Specifically, for example, the functions 301 to 305 of the semiconductor circuit design apparatus 100 described above are defined by HDL description, and the HDL description is logically synthesized and given to the ASIC or PLD to manufacture the semiconductor circuit design apparatus 100. can do.

  The following additional notes are disclosed with respect to the embodiment described above.

(Supplementary Note 1) Acquisition means for acquiring a net list relating to a semiconductor circuit to be designed;
Extraction means for extracting flip-flops included in the netlist acquired by the acquisition means, and transistors outside the flip-flops;
Integration means for integrating the flip-flops extracted by the extraction means for each predetermined number so as to be a flip-flop having a larger number of input / output bits than the flip-flop;
Calculation means for calculating a ratio between the number of flip-flops after integration by the integration means and the number of transistors extracted by the extraction means;
Generating means for generating design data of the semiconductor circuit having the integrated flip-flop and the transistor as basic blocks according to the ratio calculated by the calculating means;
A semiconductor circuit design program characterized by causing a computer to execute

(Supplementary note 2) The semiconductor circuit design program according to supplementary note 1, wherein the generation means uses one integrated flip-flop and the ratio of transistors as basic blocks.

(Additional remark 3) The said production | generation means produces | generates the said design data using the basic block group with the same arrangement | positioning of the flip-flop and the said transistor after the integration, The additional data 1 or 2 characterized by the above-mentioned Semiconductor circuit design program.

(Supplementary Note 4) Acquisition means for acquiring a net list related to a semiconductor circuit to be designed;
Extraction means for extracting flip-flops included in the netlist acquired by the acquisition means, and transistors outside the flip-flops;
Integration means for integrating the flip-flops extracted by the extraction means for each predetermined number so as to be a flip-flop having a larger number of input / output bits than the flip-flop;
Calculation means for calculating a ratio between the number of flip-flops after integration by the integration means and the number of transistors extracted by the extraction means;
Generating means for generating design data of the semiconductor circuit having the integrated flip-flop and the transistor as basic blocks according to the ratio calculated by the calculating means;
A semiconductor circuit design apparatus comprising:

(Supplementary note 5) The semiconductor circuit design apparatus according to supplementary note 4, wherein the generation means uses one integrated flip-flop and the transistor having the ratio as a basic block.

(Additional remark 6) The said production | generation means produces | generates the said design data using the basic block group with the same arrangement | positioning of the flip-flop and the said transistor after the integration, The additional data 4 or 5 characterized by the above-mentioned Semiconductor circuit design equipment.

(Supplementary Note 7) An acquisition step of acquiring a netlist related to a semiconductor circuit to be designed;
An extraction step of extracting flip-flops included in the netlist acquired by the acquisition step, and transistors outside the flip-flops;
An integration step of integrating the flip-flops extracted by the extraction step every predetermined number so that the flip-flops have a larger number of input / output bits than the flip-flops;
A calculation step of calculating a ratio between the number of flip-flops after integration by the integration step and the number of transistors extracted by the extraction step;
Generating step of generating design data of the semiconductor circuit having the integrated flip-flop and the transistor as a basic block according to the ratio calculated by the calculating step;
A method of designing a semiconductor circuit, comprising:

(Additional remark 8) The semiconductor circuit manufactured by the design data produced | generated by the semiconductor circuit design program as described in any one of additional remark 1-3.

It is explanatory drawing which shows the outline | summary of the semiconductor circuit design process concerning this Embodiment. It is explanatory drawing which shows the hardware constitutions of the semiconductor circuit design apparatus concerning this Embodiment. It is a block diagram which shows the functional structure of a semiconductor circuit design apparatus. It is a flowchart which shows the procedure of the semiconductor circuit design process in a semiconductor circuit design apparatus. It is a circuit diagram which shows the equivalent circuit of the acquired net list. It is a circuit diagram which shows the equivalent circuit of the netlist after FF integration. It is explanatory drawing which shows the size comparison of the cell area of a design object circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Semiconductor circuit design apparatus 110 Net list 111 Design object circuit 120 Design data 121 Semiconductor circuit 210 Computer main body 220 Input device 230 Output device 301 Acquisition part 302 Extraction part 303 Integration part 304 Calculation part 305 Generation part

Claims (6)

Computer
An acquisition means for acquiring a netlist relating to a semiconductor circuit to be designed;
Extraction means for extracting flip-flops included in the netlist acquired by the acquisition means, and transistors outside the flip-flops ;
Integration means for integrating the flip-flops extracted by the extraction means for each predetermined number so as to be a flip-flop having a larger number of input / output bits than the flip-flop;
Calculation means for calculating a ratio between the number of flip-flops after integration by the integration means and the number of transistors extracted by the extraction means;
It is made to function as a generation means for generating design data of the semiconductor circuit having the number of flip-flops after integration and the number of transistors according to the ratio calculated by the calculation means as basic blocks. Semiconductor circuit design program. 2. The semiconductor circuit design program according to claim 1, wherein the generation unit uses, as a basic block, the number of transistors per one flip-flop after integration , based on the ratio .   3. The semiconductor circuit design according to claim 1, wherein the generation unit generates the design data by using a basic block group having the same arrangement of the flip-flop after integration and the transistor. program. An acquisition means for acquiring a netlist relating to a semiconductor circuit to be designed;
Extraction means for extracting flip-flops included in the netlist acquired by the acquisition means, and transistors outside the flip-flops;
Integration means for integrating the flip-flops extracted by the extraction means for each predetermined number so as to be a flip-flop having a larger number of input / output bits than the flip-flop;
Calculation means for calculating a ratio between the number of flip-flops after integration by the integration means and the number of transistors extracted by the extraction means;
Generating means for generating design data of the semiconductor circuit having as a basic block the number of flip-flops after integration and the number of transistors according to the ratio calculated by the calculating means;
A semiconductor circuit design apparatus comprising: 5. The semiconductor circuit design device according to claim 4, wherein the generation unit uses, as a basic block, the number of the transistors per one flip-flop after the integration based on the ratio .   6. The semiconductor circuit design according to claim 4, wherein the generation unit generates the design data using a basic block group in which the flip-flops after integration and the transistors are arranged in the same manner. apparatus.

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