JP2007026178A - Data generation apparatus and method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data generation apparatus and method capable of keeping secrecy of data while a physical designer maintains timing convergence in a layout stage by applying naming conversion to a netlist, floor plan information and layout wiring information. <P>SOLUTION: A library provision method is provided with a naming conversion means for applying naming conversion to the netlist, a floor plan, and the layout wiring information, and a inverse naming conversion means for inversely converting verification data generated in the netlist after the naming conversion. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a data generation apparatus and method for a net list, floor plan, and placement and routing information, which are design data for LSI development.

  Conventionally, when designing an LSI, a logic circuit designer obtains library data from a semiconductor manufacturer, describes an RTL (Register Transfer Level) such as HDL (Hardware Description Language), and then creates a netlist using a logic synthesis means. I was making it. The created netlist was submitted to the semiconductor manufacturer as LSI design data for physical design as a subsequent process.

  In the design flow in which the netlist is used as interface data with the semiconductor manufacturer in this way, the logic circuit designer performs timing verification using the wire load model at the logic synthesis stage. The wire load model is configured as a table for calculating virtual delay information, and the die size, the number of fan-outs, the gate scale, etc. are defined as parameters.

  However, when the semiconductor process is in the deep submicron era as in recent years, the circuit scale mounted on the LSI to be developed increases with the evolution of the semiconductor process, and the delay time used for timing verification is a logic cell. The influence of the wiring length at the time of actual placement and routing is more dominant than the single unit. For this reason, the error between the delay time due to the wire load model of the temporary wiring length and the delay time during actual placement and wiring tends to increase.

  In the conventional design flow, a logic circuit designer estimates a temporary timing using a wire load model with a temporary wiring length, and a physical designer performs final timing convergence at the layout stage. In the layout stage, by adjusting the arrangement of each functional block and the wiring length between the functional blocks, more optimal arrangement wiring information is determined and the timing is improved. Therefore, in order for the physical designer to efficiently converge the timing at the layout stage, the logical circuit designer keeps the original block name, net name, and instance name at the RTL design stage for the physical designer. I had to submit a netlist and floor plan.

As a conventional example, for example, Patent Document 1 can be cited.
Japanese Patent Laid-Open No. 7-12801

  However, in the conventional method, the logic circuit designer submits the netlist and floor plan to the physical designer while retaining the original block name, net name, and instance name in the RTL design stage. When viewed by a third party, the hierarchical structure is easily analyzed, and there is a risk that the logical structure is understood.

  Therefore, in order to avoid the above danger, conventionally, the hierarchy of specific functional blocks in the netlist is expanded and flattened to make it difficult to understand the logical structure, and the block name, net name, and instance name are converted to a logical structure. The method of making it difficult to analyze was taken. However, in the former case, even if the netlist hierarchy is expanded and flattened, the original block name, net name, and instance name remain in the RTL design stage, so it is relatively easy to analyze the logical structure. Met. In the latter case, the block name, net name, and instance name are renamed, so that the confidentiality of the netlist is maintained, but there remains a problem that the development TAT (Turn Around Time) increases.

  In other words, in the conventional design flow, physical designers efficiently place and route at the layout stage to converge timing, so if there is a problem with timing convergence, the netlist after the naming conversion first shows the location of the problem occurrence. Next, the netlist before naming conversion corresponding to the problem occurrence part is specified. For this reason, both the logic circuit designer and the physical designer increase the man-hours for timing convergence at the layout stage and increase TAT (Turn Around Time).

  In this way, it is difficult for the logic circuit designer to simultaneously maintain the confidentiality of the netlist, floor plan information, and placement and routing information, and to allow the physical designer to converge the timing efficiently at the layout stage. It was.

  In the present invention, in order to solve the above-described conventional problems, the physical designer maintains the timing convergence in the layout stage by performing the naming conversion of the net list, the floor plan information, and the placement and routing information, while Provided are a data generation device and a method capable of maintaining confidentiality of data.

  For this purpose, the library providing method and method according to claim 1 are generated in a netlist, a floor plan, naming conversion means for converting the layout and wiring information, and a netlist after the naming conversion. Inverse naming conversion means for inversely converting the verification data is provided.

  To this end, the library providing method and method according to claim 2 are configured to transfer the net list after the naming conversion, the floor plan after the naming conversion, and the placement and routing information after the naming conversion to the physical design side. And providing data.

  For this purpose, the library providing method and method according to claim 3 include a step of simultaneously displaying the two netlists and the floor plan before the naming conversion and after the naming conversion.

  As described above, by providing the LSI design data by converting the LSI design data that has been verified in advance for placement and routing and timing convergence on the logic circuit design side, it is possible to maintain confidentiality without sacrificing placement and routing and timing convergence. Provided are a data generation apparatus and method that can be retained.

  As described above, the original block name, net name, and instance name given by the logic circuit designer are converted to the physical designer by naming conversion of the netlist, floor plan information, and placement and routing information. As a result, data with confidentiality can be provided. In addition, since the logic circuit designer confirms the timing convergence beforehand and generates the netlist, floor plan, and placement and routing information before the naming conversion, the physical designer can create the netlist, floor plan, In addition, by using the placement and routing information, it is possible to reduce the man-hour for timing convergence.

  In addition, delay information generated from post-layout placement and routing information generated by a physical designer for timing verification purposes can be easily generated by simultaneously generating and processing an inverse naming conversion means for performing inverse conversion of naming conversion at the time of naming conversion. Can be read, and verification work can proceed.

  In addition, by displaying the netlist, floor plan, delay information, etc. before the naming conversion and the data after the naming conversion at the same time, the logic circuit designer can obtain the netlist, floorplan, and temporary placement and routing information by the naming conversion. It becomes possible to grasp easily.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a design flow in the embodiment of the present invention.

  The logic circuit designer inputs the original net list (105) generated from the RTL (Register Transfer Level) description and the floor plan image information (106) to the floor plan generation means (101) using the logic synthesis means.

  As shown in FIG. 9, the floor plan image information (106) includes data necessary for generating a chip level floor plan of the LSI. For example, “data flow information” indicating how the input data is processed in each function block in the chip, “function block connection information” indicating connection information between function blocks and function blocks. , “Built-in RAM connection information”, which is connection information between the function block and the built-in RAM, “I / O connection information”, which is connection information between the function block and the I / O Pad, and a gate scale that represents the scale of each functional block Information “,” “clock domain information” that is information on the clock used in each functional block, and the like.

  The floor plan generation means (101) arranges each functional block from various information of the original net list (105) and the floor plan image information (106) so that the processing data satisfies the data flow from the input terminal to the output terminal. A first floor plan (107) is created.

  In the first floor plan (107), the floor plan is created from the connection information between the functional blocks and the built-in RAM. However, no problem has been confirmed in the actual placement and wiring.

  Therefore, when the original netlist (105) and the first floor plan (107) are input to the temporary placement and routing means (102) and placed and routed on the first floor plan, there is a problem in wiring congestion and timing convergence. Check if there is any. Here, unlike the detailed placement and routing means (104) that finally performs placement and routing, the temporary placement and routing means (102) extracts a fatal problem in a short time. Become.

  If a problem is found in wiring congestion and timing convergence at the stage of temporary placement and routing using the temporary placement and routing means (102), the process returns to the floor plan generation means (101) as shown in FIG. In order to make it converge, a constraint plan is included and a floor plan is created again.

  From the temporary placement and routing means (102), second floor plan information (108) and temporary placement and routing information (109) are generated. The generated second floor plan information (108) includes, in addition to the first floor plan information (107), connection information between functional blocks added at the stage of provisional placement and routing, and RAM placement information. Constraint information and the like are also included. Further, in the temporary placement and routing information (109), physical temporary placement and routing information of each functional block based on the hierarchical information of the first floor plan (107) is generated.

  The naming conversion means (103) receives the original net list (105), the second floor plan information (108), and the temporary placement and routing information (109), and converts the block name, net name, instance name, etc. Is done.

  From the naming conversion means (103), the post-naming converted netlist (110) obtained by converting the original netlist (105) and the post-naming-converted temporary placement and routing information (109) as a result of the naming conversion of the temporary placement and routing information (109). 111), post-naming-converted floor plan information (112) that is a result of naming conversion of the second floor plan information (108), naming conversion information (113) that outputs the processing contents of the naming conversion, and detailed placement and routing are performed. An inverse naming conversion means (114) for inversely converting delay information generated on the physical design side into the original naming is generated.

  As shown in FIG. 10, the naming conversion information (113) is output in the format of the name before conversion and the name after conversion. For example, in the netlist before naming conversion, the function block names defined in “Screen Sub-1” and “Screen Sub-2” are “S1”, “S2”, “Filter Sub-1”, “Filter Sub The function block names defined by “-2” have a one-to-one correspondence such as “F1” and “F2”.

  Further, since the inverse naming conversion means (114) generated by the naming conversion means (103) is an inverse conversion process of the naming conversion means (103), it can be easily converted using the naming conversion information (113). I can do it.

  Here, in the logic circuit design, the following three points are provided to the physical designer among the information generated by the naming conversion means. The first is a netlist after naming conversion (110), the second is provisional placement and wiring information after naming conversion (111), and the third is floorplan information after naming conversion (112).

  In the logic circuit design, the detailed placement and routing means (104) is inputted with the netlist after naming conversion (110), the provisional placement and routing information after naming conversion (111), and the floorplan information after naming conversion (112) and detailed placement and routing. To generate detailed placement and routing information (115) and delay information (116).

  On the other hand, FIG. 2 shows a conventional design flow (1).

  Conventionally, a logic circuit designer creates an original netlist (205) generated from an RTL (Register Transfer Level) description and floor plan image information (206) by using a logic synthesis means and provides the information to the physical designer. It was. The floor plan image information (206) used here is the one described with reference to FIG.

  The physical designer inputs the original net list (205) and the floor plan image information (206) to the floor plan generation means (201), arranges each functional block from various information of the floor plan image information (206), The first floor plan (207) that satisfies the data flow was created.

  In the first floor plan (207), the floor plan is created from the connection information between the functional blocks and the built-in RAM, but the problem in the actual placement and wiring is not determined.

  Therefore, the first floor plan (207) was input to the temporary placement and routing means (202), and it was confirmed that there was no problem in wiring congestion and timing convergence when placing and wiring in the first floor plan. .

  If a problem is found in wiring congestion and timing convergence at the stage of temporary placement and routing using the temporary placement and routing means (202), the process returns to the floor plan generation means (201) as shown in FIG. Incorporate constraints for convergence and create a floor plan again.

  From the temporary placement and routing means (202), second floor plan information (208) and placement and routing information (209) are generated. The generated second floor plan information (208) includes, in addition to the first floor plan information (207), connection information between functional blocks added at the stage of provisional placement and routing, and RAM placement information. Constraint information and the like are also included. In addition, in the temporary placement and routing information (209), physical placement and routing information of each functional block based on the hierarchical information of the first floor plan (207) is generated.

  The detailed placement and routing information (215) is entered by inputting the original netlist (205), the second floor plan information (208), and the temporary placement and routing information (209) to the detailed placement and routing means (204). And delay information (216).

  However, in the conventional design flow (1) in FIG. 2, the work is divided into RTL design and logic circuit design for generating a netlist by performing logic verification, and physical design from acquiring the netlist to actual placement and routing. Yes.

  Therefore, the floor plan image information (206) is exchanged between the logical circuit design and the physical design. Therefore, if a problem such as misrecognition of both sides or excess or deficiency of information occurs, TAT (Turn Around Time until the information is converged) ) Will increase.

  On the other hand, from the standpoint of maintaining the confidentiality of design data, the design flow causes timing to converge in the layout, so there is a risk that the circuit structure can be read because the name at the RTL design stage is used.

  Furthermore, in order to minimize the risk, only the minimum necessary information is submitted from the logic circuit design to the physical design side. As a result, there is a problem that the generated floor plan is not sufficiently optimized.

  In order to avoid these problems, the logic circuit design side as shown in the conventional design flow (2) in Fig. 3 is executed up to the temporary placement and routing process, and the congestion of the placement and routing and the timing convergence are confirmed. This technique is adopted.

  In FIG. 3, the logic circuit designer creates an original net list (305) and floor plan image information (306) generated from the RTL (Register Transfer Level) description using logic synthesis means or the like, and generates floor plan generation means ( 301).

  The floor plan image information (306) used here is the one described with reference to FIG.

  The floor plan generation means (301) arranges each functional block from various information of the original net list (305) and the floor plan image information (306) so that the processing data satisfies the data flow from the input terminal to the output terminal. A first floor plan (307) is created.

  In the first floor plan (307), a floor plan is created from connection information between functional blocks, built-in RAM, etc., but it is not determined whether or not there is a problem in actual placement and wiring.

  Therefore, the first floor plan (307) is input to the temporary placement and routing means (302), and it is confirmed whether there is any problem in wiring congestion and timing convergence when the first floor plan is placed and routed on the first floor plan.

  For example, if a problem is found in the wiring congestion or timing convergence at the stage of temporary placement and routing using the temporary placement and routing means (302), the problem is returned to the floor plan generation means (301) as shown in FIG. Create a floor plan again, including constraints to avoid and converge.

  From the temporary placement and routing means (302), second floor plan information (308) and placement and routing information (309) are generated. The generated second floor plan information (308) includes, in addition to the first floor plan information (307), connection information between functional blocks added at the stage of provisional placement and routing, and RAM placement information. Constraint information and the like are also included. In addition, in the temporary placement and routing information (309), physical information on the temporary placement and routing of each functional block based on the hierarchical information of the first floor plan (307) is generated.

  On the logic circuit design side, the original netlist (305), temporary placement and routing information (309), and second floor plan information (308) are input to the detailed placement and routing means (304) to perform detailed placement and routing. Place and route information (315) and delay information (316) are generated.

  In the conventional design flow (2) of FIG. 3, the problem of the conventional design flow (1) development TAT of FIG. 2 becomes a problem at the time of detailed placement and routing by creating a floor plan and temporary placement and routing on the logic circuit design side. Wiring congestion and timing convergence can be confirmed in advance.

  However, from the viewpoint of maintaining the confidentiality of the design data, the circuit structure is not confidential because the design data is provided to the physical design with the original name at the time of design remaining in the netlist or floor plan data.

  Therefore, when a third party obtains this design data netlist and floorplan data, the configuration and connection information of each block constituting the LSI design data is read from the floorplan information, and from the netlist, Each instance name and net name will be read.

  Therefore, by adopting the design flow of the present invention of FIG. 1, the confidentiality of design data is maintained while considering the problems of wiring congestion and timing convergence.

Specifically, as shown in the design flow of FIG. 1, the temporary placement and routing means (102) performs temporary placement and routing using the first floor plan information (107) created by the floor plan creation means (101). Then, the layout and wiring performance and timing of the entire LSI chip are checked. When it is confirmed that there is no problem, temporary placement and routing information (109) in which the input / output position information of the outer end of each functional block is fixed is generated.
Here, an example of the floor plan of FIG. 4 will be described.

  FIG. 4 shows the hierarchical structure of the LSI design data chip (401).

  The Screen processing block (402) has “Screen-sub1” and “Screen-sub2” as sub-layers, and includes built-in RAMs (RAM1, RAM2) used for Screen processing.

  Similarly, the Filter processing block (403) includes “Filter-sub1”, “Filter-sub2”, and “Filter-sub3” as sub-layers, and built-in RAM (RAM3, RAM4, RAM5) used for Filter processing. Is included.

  Further, func1 (404) is a function processing block, func4 (405) is a function processing block, PLL (406), Hard Macro (407), RAM6 (408), RAM7 (409), RAM8 (410), RAM9 (411). It consists of

  FIG. 5 shows an example of block names before naming conversion.

  FIG. 5 is a block display of the Screen processing block (402) of FIG. 4. Screen (501), Screen-sub1 (502) which is a sub-hierarchy of Screen processing, and Screen-sub2 which is a sub-hierarchy of Screen processing (502), RAM1 (504) used in Screen-sub1, and RAM2 (505) used in Screen-sub2.

  On the other hand, FIG. 6 shows an example of the block name after the naming conversion.

  FIG. 6 is a block display of the Screen processing block (402) of FIG. 4. “S” (601) is “S1” (602), “S2” (603), “S1-R” (604). ), “S2-R” (605).

  FIG. 10 is an example of naming conversion information (113) representing the correspondence between the functional blocks of FIGS.

  Here, “Screen-sub1” is “S1”, “Screen-sub2” is “S2”, “Filter-sub1” is “F1”, “Filter” by the naming conversion process of the naming conversion means (103). "-sub2" indicates that it has been converted to "F2".

  Further, the layout / wiring information in the layout is held at the outer end of Screen-sub1 (802) in FIG. 8, and the positional information of the cells and the wiring connecting the cells is fixed and the temporary layout / wiring information (109) is output. .

  On the physical design side, the generated second floor plan information (108) and provisional placement and routing information (109) are used by the detailed placement and routing means (104), so that each functional block is placed with the name after the naming conversion. Wiring property, timing convergence, etc. can be confirmed. At the same time, it becomes difficult to read the names of the functional blocks, so that it is difficult to analyze the design data, and the confidentiality of the design data can be maintained.

  However, this means that detailed placement and routing information generated by physical design and delay information are similarly difficult to read by naming conversion. Therefore, in the logic circuit design, the naming conversion means (103) generates reverse naming conversion means (107) that performs reverse naming conversion on the names of detailed placement and routing information and delay information generated on the physical design side.

  On the logic circuit design side, reverse naming conversion means (107) is applied to the information generated in the physical design, and the information is converted to the original name before the naming conversion and analyzed.

  As described above, on the physical design side, the problems of placement and routing and timing convergence are the net conversion after naming conversion (110), the provisional placement and routing information after naming conversion (111), and the post-naming conversion that are confirmed in advance by the logic circuit designer. By using the floor plan information (112), it is possible to suppress the TAT increase in the input / output positions of the outer ends of the functional blocks and the physical design of the placement and routing. Further, from the viewpoint of maintaining the confidentiality of the design data, since the design data used on the physical design side is data after the naming conversion means (103), the circuit structure is analyzed from the name of each functional block. Making it difficult.

  In the above description, the case where the naming conversion is executed only for the block name is described, but it goes without saying that the same effect can be obtained even if the naming conversion is performed at each net and each instance level.

  In addition, in order to control the data creation time for naming conversion, it is possible to adaptively switch the level for naming conversion by block name, instance name, and net name.

  Further, the present invention has a function of simultaneously displaying block names before and after the naming conversion as shown in FIG.

  FIG. 7 is an example of a block name overlapping display in the graphical user interface.

  701 is “Screen” and “S”, 702 is “Screen-sub1” and “S1”, 703 is “Screen-sub2” and “S2”, 704 is “RAM1” and “S-R1”, Reference numeral 705 denotes “RAM2” and “S-R2”.

  As described above, a plurality of block names in FIGS. 5 and 6 are simultaneously displayed by the simultaneous display function of this functional block as names before and after naming conversion, and the block names after naming conversion are expressed in parentheses. ing.

  In this way, by displaying the netlist, floorplan, delay information, etc. before the naming conversion and the data after the naming conversion at the same time, the netlist, floorplan, and temporary placement and routing information after the naming conversion is provided to the physical design. Even in this case, analysis is easy and confidentiality of design data can be maintained.

The design flow of the present invention. Conventional design flow (1). Conventional design flow (2). An example of a floor plan. An example of a block name before naming conversion. An example of the block name after naming conversion. Example of simultaneous display of block names before and after naming conversion. An example of fixing the outer edge of a block. Floor plan image information. An example of naming conversion information.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 Floor plan production | generation means 102 Temporary placement and routing means 103 Naming conversion means 104 Detailed placement and routing means 105 Original net list 106 Floor plan image information 107 First floor plan information 108 Second floor plan information 109 Temporary placement and wiring information 110 Naming conversion Subsequent netlist 111 Temporary placement and routing information after naming conversion 112 Floor plan information after naming transformation 113 Naming conversion information 114 Reverse naming conversion means 115 Detailed placement and routing information 116 Delay information 201 Floor plan generation means 202 Temporary placement and routing means 204 Detailed placement and routing means 205 Original Net List 206 Floor Plan Information 207 First Floor Plan Information 208 Second Floor Plan Information 209 Temporary Place and Route Information 215 Detailed Place and Route Information 216 Delay information 301 Floor plan generation means 302 Temporary placement and routing means 304 Detailed placement and routing means 305 Original net list 306 Floor plan image information 307 First floor plan information 308 Second floor plan information 309 Temporary placement and routing information 315 Detailed placement Wiring information 316 Delay information 401 Chip level floor plan 402 Screen processing block 403 Filter processing block 404 func1 processing block 405 func4 processing block 406 PLL
407 Hard Macro
408 RAM6
409 RAM7
410 RAM8
411 RAM9
501 Screen processing block (data before naming conversion)
502 Sub-block of screen processing (data before naming conversion)
503 Sub-block of screen processing (data before naming conversion)
504 Screen processing RAM1 block (data before conversion)
505 Screen processing RAM2 block (data before naming conversion)
601 Screen processing block (data after naming conversion)
602 Sub-block of screen processing (data after naming conversion)
603 Sub-block of screen processing (data after naming conversion)
604 Screen processing RAM 1 block (data after naming conversion)
605 Screen processing RAM 2 blocks (data after naming conversion)
701 Screen processing block (data before and after naming conversion)
702 Sub-block of screen processing (data before naming conversion, data after naming conversion)
703 Sub-block of screen processing (data before naming conversion and after naming conversion)
704 Screen processing RAM 1 block (data before naming conversion, data after naming conversion)
705 Screen processing RAM 2 blocks (pre-naming conversion and post-naming conversion data)
801 Screen processing block 802 Screen processing sub 1 block 803 Screen processing sub 2 block

Claims (3)

Naming conversion means for converting the net list, floor plan, and placement and routing information;
A data generation apparatus comprising: an inverse naming conversion means for inversely converting verification data generated in the netlist after the naming conversion.   2. The data generation apparatus according to claim 1, wherein the netlist after the naming conversion, the floor plan after the naming conversion, and the placement and routing information after the naming conversion are provided to the physical design side.   3. The data generation apparatus according to claim 1, wherein two netlists and a floor plan before the naming conversion and after the naming conversion are displayed at the same time.

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