JP5030068B2 - Communication path equalization apparatus and method - Google Patents

Description

  The present invention relates to a communication path equalization apparatus and method for equalizing communication lines such as a wireless communication path and a wired communication path.

  In a wireless communication system, a transmitted signal is reflected by an obstacle, and a receiver receives a plurality of signals having different arrival times. Usually, a signal that arrives after a delay becomes an interference signal, which is a major factor in performance degradation. As a main method for improving this, there is a method of removing an interference signal by signal processing using an equalizer. This method has been studied by many researchers so far and many results have been reported.

  Equalizers that have been studied so far can be classified into two main categories. One is equalization processing by linear convolution operation, and the other is frequency domain equalization (FDE) processing (see, for example, Non-Patent Document 2). FIG. 4 is a block diagram showing a configuration of an equalization circuit based on a linear convolution operation according to the prior art. In FIG. 4, the equalization circuit based on the linear convolution operation includes a shift register 41, a plurality of N multipliers 42-0 to 42-(N−1), and a weighting coefficient register that stores a plurality of N weighting coefficients. 43-0 to 43- (N-1) and an equalization controller 40 using an algorithm for adjusting the weighting factor.

In FIG. 4, the received sample sequence r = (r ₀ , r ₁ , r ₂ ,...) Is sequentially input to the shift register 41. For each sample sequence, multipliers 42-0 to 42- (N-1) use weighting factors w _i (i = 0, 1, 2, and 2) from the respective weighting factor registers 43-0 to 43- (N-1). .., N-1) are multiplied and then synthesized and output. By sequentially performing this, an output sample sequence (vector) y after equalization filtering is obtained. A weighting coefficient (vector) w is calculated from the sample series y according to a predetermined rule. The main difference between equalization by linear convolution and frequency domain equalization processing is that the former performs the equalization processing sequentially for each input sample, while the latter uses a sample sequence as a block. Dividing and performing equalization processing in units of blocks.

  FIG. 5 is a block diagram showing the configuration of a frequency domain equalization circuit according to the prior art. In FIG. 5, the frequency domain equalization circuit includes a serial-parallel converter (hereinafter referred to as an S / P converter) 51, a fast Fourier transformer (FFT) 52, and an inverse Fourier transformer (IFFT). Inverse Fast Fourier Transformer) 53, parallel-serial converter (hereinafter referred to as P / S converter) 54, weight coefficient registers 42-0 to 42- (N-1) for storing a plurality of N weight coefficients. And an equalization controller 50 using an algorithm for adjusting the weighting coefficient in the frequency domain.

In FIG. 5, the received sample sequence (vector) r is converted into a parallel signal sequence by the S / P converter 51. Thereafter, the parallel signal sequence is converted into a frequency domain signal (hereinafter referred to as a frequency component signal) by the fast Fourier transformer 52. For each frequency component signal, the multipliers 42-0 to 42- (N-1) use the weighting factors w _i (i = 0, 1, 2, 2) from the weighting factor registers 43-0 to 43- (N-1). .., N-1), and then converted into a time domain signal by an inverse Fourier transformer 53. Thereafter, the time domain signal is converted into a serial signal sequence by the P / S converter 54 to obtain an output sample sequence (vector) y. The update of the weighting factor w _i is performed by transmitting a training signal, which is a predetermined signal between the transmitter and the receiver, from the transmitter and receiving it by the receiver, and an error between the received signal and the predetermined training signal. The weighting factor w _i is updated according to a predetermined rule so that is minimized.

JP 2003-046473 A. Japanese Patent Laid-Open No. 2005-236771. US Patent Application Publication US 2006 / 0034398-A1. Tomohiro Yamazaki et al. “A Study on Multicode Transmission with Cyclic Prefix”, Proceedings of the IEICE General Conference, B-5-113, pp. 466, The Institute of Electronics, Information and Communication Engineers, March 2006. T. Walzman et al. "Automatic equalization using the discrete frequency domain", IEEE Transactions on Information Theory, Vol. IT-19, No. 1, pp.59-68, January 1973. S. Haykin, "Adaptive Filter theory", Prentice Hall, 2002. C. Cheng et al., “Hardware efficient fast DCT based on novel cyclic convolution structures”, IEEE Transactions on Signal Processing, Vol.54, No.11, pp.4419-4434, November 2006. Yoji Iiguni, “Adaptive Signal Processing Algorithm”, Baifukan, pp. Issued 23-35, July 2007. A. H. Sayed, "Fundamentals of adaptive filtering", Wiley-IEEE Press, pp.276-277, June 2003. Edited by Naohisa Goto et al., “Antenna / Wireless Handbook”, Ohmsha, pp. 402-412, October 2006. Kyohei Fujimoto et al., “Antenna System for Mobile Communications”, General Electronic Publishing Company, pp. 164-185. Tomoyuki Aono et al., “Blind Adaptive Control Algorithm Comparison Experiment on ESPAR Antenna”, IEICE Technical Report, IEICE Technical Report, Vol. 103, no. 125, June 2003, pp. 1-6.

  Since the above-described frequency domain equalization process divides the sample sequence into blocks, if a signal of a block before the block is included in a certain block section, an error occurs and accurate equalization process cannot be performed. For this reason, in the frequency domain equalization process, a periodically expanded signal called a cyclic prefix (CP) is often used.

  FIG. 6 is a diagram showing a signal waveform of a signal to which a cyclic prefix (hereinafter referred to as CP) according to the prior art is added. In FIG. 6, Ts and Te represent the symbol time and the CP duration, respectively. In the receiver, the periodically expanded signal is not used for demodulation. If the arrival time difference of the reflected wave is within the CP interval, equalization can be performed without receiving inter-block interference (IBI) from the previous signal block. In the CP section, redundant signals are transmitted, which causes a power loss and a decrease in transmission speed. However, in a parallel transmission system such as multi-code transmission or OFDM, the influence is small. Is often used in combination with such a transmission method.

  In addition to these methods, Non-Patent Document 1 and Patent Document 3 show a method based on matrix calculation. In this method, the channel characteristic H is expressed using a matrix, and the inverse process is performed to perform equalization processing. In particular, in a system to which CP is added, a matrix representing the channel characteristic H can be represented by a cyclic matrix, and the least mean square error (MMSE) or zero forcing (Zero Forcing; Hereinafter, equalization processing can be performed by inverse matrix calculation based on the ZF method.

  FIG. 7 is a block diagram showing a configuration of an equalization circuit based on matrix calculation according to the prior art. In FIG. 7, the matrix calculation equalizer circuit includes an S / P converter 51, a matrix calculator 55, a P / S converter 54, and an equalization controller 50. Here, assuming that the length of the CP is Ne and the arrival delay time of the delayed wave is within this interval, the channel characteristic (matrix) H of the quasi-static fading channel can be expressed by the following equation. In this specification, the formula number (number number) in black brackets in which the formula is imaged and the formula number (number number) in square brackets in which the formula is entered are used in combination. As a series of mathematical formula numbers in the specification, a formula number is assigned to the last part of the formula using the format of “formula (1)” (there are also formulas that are not given).

  The matrixes to be multiplied in the equalization processing are as follows for the matrix based on the MMSE criterion and the matrix based on the ZF criterion. Note that the superscript H of the matrix is a complex conjugate transpose.

MMSE: (HH ^H + σ ² I) H ^H (2)
ZF: (HH ^H ) ⁻¹ H ^H (3)

  Since this matrix changes depending on the condition of the communication channel, it uses training signals and weights using algorithms such as least mean square (LMS) and recursive least squares (RLS). The coefficient is updated (see, for example, Non-Patent Document 3).

  As described above, the frequency domain equalization process and the equalization process using matrix operation have a problem that it is necessary to generate an equalization circuit having a very large circuit scale.

  The object of the present invention is to solve the above problems and provide a communication path equalization apparatus and method that can be configured with a very small circuit scale as compared with conventional equalization processing such as frequency domain equalization processing and matrix calculation. There is to do.

A communication path equalizing apparatus according to a first invention is
Conversion means for receiving a signal transmitted from the transmission device by the reception device, and performing serial-parallel conversion on the received signal to a parallel signal of a plurality of columns and outputting the same;
Arithmetic means for performing a circular convolution operation on the parallel signal output from the conversion means and a predetermined weighting coefficient and outputting a signal after the circular convolution operation;
Control means for computing the weighting factor for equalizing the channel characteristics between the transmitting device and the receiving device based on the signal outputted from the computing means, and outputting and setting to the computing means And
The channel characteristic between the transmitting device and the receiving device is equalized by the circular convolution operation.

In the communication path equalization device, the signal transmitted from the transmission device includes a reference signal,
The control means compares the reference signal included in the signal output from the arithmetic means with the same reference signal as the reference signal, and updates the weighting coefficient so that the error is substantially minimized. The weighting factor is calculated and output to the calculation means and set.

Further, in the communication path equalization apparatus, the computing means is
It has a plurality of registers connected so that the signal stored in each register circulates, inputs the parallel signal output from the conversion means, stores it in each register, outputs it, and stores it in one register A cyclic shift register that sequentially circulates and stores and outputs the output signal to the next connected register for storage.
Multiplying means for multiplying a parallel signal output from the cyclic shift register by a predetermined weighting factor and outputting a signal after multiplication;
And adding means for adding the signals after multiplication output from the multiplication means and outputting the signals after addition.

  Here, the cyclic shift register, the multiplication means, and the addition means are constituted by a single high-speed computing unit.

The channel equalization method according to the second invention is:
Receiving a signal transmitted from the transmitting device by the receiving device, serially parallel-converting the received signal into a plurality of parallel signals, and outputting,
Performing a circular convolution operation on the parallel signal and the predetermined weighting factor to output a signal after the circular convolution operation;
Based on the signal after the circular convolution operation, the weighting factor for equalizing the channel characteristics between the transmitting device and the receiving device is calculated and used as a weighting factor for the circular convolution operation. Including the step of setting,
The channel characteristic between the transmitting device and the receiving device is equalized by the circular convolution operation.

In the channel equalization method, the signal transmitted from the transmitter includes a reference signal,
The step of calculating and setting the weighting factor compares the reference signal included in the signal after the circular convolution operation with the same reference signal as the reference signal so that the error is substantially minimized. The method includes calculating the weighting factor by updating the weighting factor, outputting the setting to the calculating unit, and setting the weighting factor.

Further, in the communication channel equalization method, a conversion step of receiving a training signal transmitted from a transmission device by a reception device, serially parallel-converting the training signal into a plurality of parallel signals, and outputting the training signal;
A calculation step of performing a predetermined weighting factor and a circular convolution operation on each of the parallel signals and outputting a signal after the circular convolution operation,
The signal after the circular convolution operation is compared with the same training signal as the training signal, the weighting factor is updated so that the error is substantially minimized, and the weighting factor is updated using the updated weighting factor. And an equalizing step for equalizing the channel characteristics between the transmitting device and the receiving device.

Furthermore, in the channel equalization method, the calculation step includes:
Using a cyclic shift register having a plurality of registers connected so that the signal stored in each register circulates, the parallel signal is input, stored and output in each register, and stored in one register And sequentially circulating and storing and outputting the received signal to a connected register and storing it,
Multiplying the parallel signal output from the cyclic shift register by a predetermined weighting factor and outputting the multiplied signal;
Adding the signals after the multiplication and outputting the signal after the addition.

  According to the communication path equalization apparatus and method according to the present invention, a signal transmitted from a transmission apparatus is received by a reception apparatus, the received signal is serial-parallel converted into a plurality of columns of parallel signals, and output. A cyclic convolution operation is performed on the parallel signal and a predetermined weight coefficient to output a signal after the cyclic convolution operation, and between the transmission device and the reception device based on the signal after the cyclic convolution operation The weighting factor for equalizing the channel characteristics of the channel is calculated and set as a weighting factor for the circular convolution operation, and the communication path between the transmitting device and the receiving device is calculated by the circular convolution operation. Equalize the characteristics. Therefore, the circuit scale can be greatly reduced as compared with the prior art, and thus the manufacturing cost can be greatly reduced.

(A) is a block diagram which shows the structure of the wireless transmitter which concerns on embodiment of this invention, (b) shows the structure of the wireless receiver for receiving the radio signal from the wireless transmitter of (a). It is a block diagram. FIG. 2 is a block diagram showing a configuration of an equalization circuit 24 in FIG. 1. FIG. 3 is a block diagram showing a configuration of an equalization circuit 24A, which is a modification of the equalization circuit of FIG. It is a block diagram which shows the structure of the equalization circuit by the linear convolution operation based on a prior art. It is a block diagram which shows the structure of the frequency domain equalization circuit based on a prior art. It is a figure which shows the signal waveform of the signal which added the cyclic prefix which concerns on a prior art. It is a block diagram which shows the structure of the equalization circuit by the matrix calculation based on a prior art.

Explanation of symbols

11: Encoder,
12: Series-parallel converter (S / P converter),
13: Sign multiplier,
14 ... Parallel-serial converter (P / S converter),
15 ... cyclic prefix adder (CP adder),
16 ... wireless transmission circuit,
17 ... antenna,
18, 18A ... Training signal generator,
21 ... antenna,
22 ... a wireless receiving circuit,
23. Cyclic prefix remover (CP remover),
24 ... Equalization circuit,
25 ... Series-parallel converter (S / P converter),
26: Sign multiplier,
27 ... Parallel-serial converter (P / S converter),
28: Decoder,
30 ... Equalization controller,
31 ... Series-parallel converter (S / P converter),
32 ... cyclic shift register,
32A ... High-speed circular convolution operator,
33-0 to 33- (N−1)... Multiplier
34-0 to 34- (N−1)... Weight coefficient register,
35 ... adder,
36: Clock generator.

  Hereinafter, embodiments according to the present invention will be described with reference to the drawings. In addition, in each following embodiment, the same code | symbol is attached | subjected about the same component. In the embodiment according to the present invention, an equalization circuit based on a circular convolution operation is proposed in order to reduce the circuit scale of the frequency domain equalization circuit and the equalization circuit based on a matrix operation.

  FIG. 1A is a block diagram showing a configuration of a wireless transmission device according to an embodiment of the present invention, and FIG. 1B is provided for receiving a wireless signal from the wireless transmission device of FIG. FIG. 2 is a block diagram illustrating a configuration of a wireless reception device including an equalization circuit 24. FIG. 2 is a block diagram showing the configuration of the equalization circuit 24 of FIG. The equalization circuit 24 according to the embodiment achieves the same performance as the frequency domain equalization circuit and the matrix calculation equalization circuit by reducing the circuit scale.

  First, with reference to FIG. 1, a radio communication system using CP and having an equalization circuit 24 will be described in detail below.

  In the wireless communication system, the transmitted signal is reflected and scattered, and the receiver receives a plurality of signals having a delay time. A signal that arrives with a delay becomes an interference signal, which is a major factor in performance degradation. In this embodiment, a multi-code transmission system to which a CP is added in order to reduce performance degradation due to a delayed wave will be described.

In the radio transmission apparatus of FIG. 1A, an input information bit (vector) b is converted into an encoded bit (vector) b _c to which redundant bits are added by an encoder 11. Subsequently, after being converted into a plurality of low-speed M parallel signals by the S / P converter 12, they are assigned to different branches. After multiplying the different codes in each branch, they are combined. In FIG. 1A, this operation is performed by the sign multiplier 13 and the P / S converter 14. A multi-code signal (vector) s, which is a signal after synthesis, is represented by s = C ^T b _c, where C is a code set (matrix) to be multiplied. Thereafter, the signal is periodically extended by adding the same signal (CP) as the end of the symbol to the front of the transmission signal by the CP adder 15. The transmission signal is modulated and power amplified by the wireless transmission circuit 16 and then radiated from the antenna 17.

  In a system to which a CP is added, the transfer function of the wireless communication path can be expressed using a cyclic matrix. If the transfer function (matrix) of the wireless channel is H, the received signal (vector) is given by r = Hs. In the wireless reception device of FIG. 1B, the reception signal is received by the wireless reception circuit 22 and amplified with low noise, and then predetermined wireless reception processing such as low-frequency conversion and demodulation is executed. Then, after the CP added by the CP adder 15 of the wireless transmission apparatus is removed by the CP remover 23, the equalization circuit 24 performs a line equalization process, which will be described in detail later, and then the same by the S / P converter 25. Are copied to a plurality of M branches. In each branch, the code multiplier 26 multiplies the same code as the code multiplied by the wireless transmission device to obtain an output signal. Further, it is converted into a serial signal by the P / S converter 27 and decoded by the decoder 28 to obtain received data.

Note that, for the equalization processing of the equalization circuit 24, in the wireless transmission device, a predetermined training signal is generated by the training signal generator 18 and input to the CP adder 15 before the data transmission to be originally transmitted. On the other hand, the radio receiving device demodulates the radio signal including the training signal and extracts the training signal, and then the equalization controller 30 of the equalization circuit 24 transmits the demodulated training signal to the radio A predetermined algorithm such as a known least mean square method or a sequential least square method is used by comparing the same training signal as the training signal generated on the transmitter side with the training signal generated by the training signal generator 18A. weight so that the error of the comparison result is substantially minimized Te coefficients _w i (i = 0,1,2, , It carried out N-1) update.

  Next, the equalization circuit 24 according to the present embodiment will be described below with reference to FIG. The equalization circuit 24 includes an S / P converter 31, a cyclic shift register 32, a plurality of N multipliers 33-0 to 33- (N-1), and weight coefficient registers 34-0 to 34- ( N-1), an adder 35, a clock generator 36, and an equalization controller 30.

In FIG. 2, the serial sample sequence (vector) r = (r ₀ , r ₁ , r ₂ ,..., R _N−1 ) input from the CP remover 23 is _N by the S / P converter 31. After being converted into parallel data, it is input to the cyclic shift register 32. The cyclic shift register 32 includes a plurality of N registers 37-0 to 37- (N-1), and output data from the first register 37-0 is input to the last register 37- (N-1). The data is circulated (circulated). That is, the held data value is shifted to the next register in accordance with the clock from the clock generator 36. As described above, both ends of the cyclic shift register 32 are connected, and the sample sequence circulates in the cyclic shift register 32. The sample values held in the respective registers 37-0 to 37- (N-1) are weight coefficients w _i (i = 0, 1) output from the weight coefficient registers 34-0 to 34- (N-1). , 2,..., N-1) are multiplied and synthesized by the adder 35, and then output to the S / P converter 25 and the equalization controller 30. The equalization controller 30 calculates the weighting factor w _i from the output value from the adder 35 according to a predetermined algorithm, updates these values, and stores the weighting factor registers 34-0 to 34- (N−1). To do. That is, the data value in the cyclic shift register 32 is deleted when the data value for one cycle of one block circulates, and the next block is operated. Here, the cyclic shift register 32, the N multipliers 33-0 to 33-(N−1), and the adder 35 constitute a circular convolution operation circuit. In addition, the updating of the weighting factor w _i by the equalization controller 30 is performed by the training signal generator 18A generating the same training signal as the training signal generated on the wireless transmission device side, as in the other prior art methods. The training signal output from the adder 35 is compared with the training signal generated by the training signal generator 18A so that the error of the comparison result is substantially minimized by using an algorithm such as LMS or RLS. The weighting coefficient w _i is updated. With the above configuration, line equalization processing is performed by executing a circular convolution operation.

  Next, the theoretical relationship between the cyclic convolution operation equalization apparatus according to the present embodiment and the equalization apparatus using frequency domain equalization and matrix operation will be described below.

  Here, taking the MMSE-based equalization process as an example, the frequency domain equalization process according to Non-Patent Document 2 and the like, the equalization process by matrix operation according to Patent Document 3, and the circular convolution operation equalization according to the present embodiment The relationship with processing will be described. As the MMSE weight matrix, the matrix weight is selected so as to minimize the error between the transmission signal (vector) s and the reception signal (vector) y. This is a known least square problem, and its solution is expressed by the following equation.

  Since the channel characteristic H is expressed by a cyclic matrix as shown in Expression (1), it can be rewritten as shown in the following expression.

H = FΛF ^H (6)

  Here, the matrix F represents a DFT matrix, and the matrix Λ is represented by the following equation.

Λ = diag (H ₀ , H ₁ ,..., H _N-1 ) (7)

  Here, diag (•) represents a diagonal matrix having an argument (•). By substituting equation (6) into equation (5), the weight coefficient (matrix) w based on MMSE is rewritten as the following equation.

w = F (Λ ² + σ ² I) ⁻¹ Λ ^H F ^H (8)

Here, σ ² represents the variance of noise power. Since (Λ ² + σ ² I) ⁻¹ Λ ^H is a diagonal matrix, w is a cyclic matrix. Here, it is assumed that a cyclic matrix w of weighting factors is expressed by the following equation.

w = (w ₀ , w ₁ , w ₂ ,..., w _N−1 ) (9)

At this time, the vector w ₀ of the first column satisfies the relationship of the following equation from the characteristics of the cyclic matrix w.

  Only in formula (10), * represents a complex conjugate. At this time, the output signal (vector) wr of the MMSE-based equalization circuit is expressed by the following equation.

は、それぞれアダマール積、循環畳込みを表す。以上より、周波数領域におけるＭＭＳＥ等化処理及び時間領域における行列演算によるＭＭＳＥ等化処理と、本実施形態に係る循環畳込み演算等化処理は、同一の結果を得ることが確認できる。なお、循環畳込み演算方法については、例えば、非特許文献４において開示されており、当該非特許文献４では、同じ乗算を省いたり、加算に置き換えることにより、演算効率を上げる方法が開示されている。here,

Represents Hadamard product and cyclic convolution, respectively. From the above, it can be confirmed that the MMSE equalization process in the frequency domain and the MMSE equalization process by the matrix operation in the time domain and the circular convolution operation equalization process according to the present embodiment obtain the same result. The cyclic convolution calculation method is disclosed in, for example, Non-Patent Document 4, and the Non-Patent Document 4 discloses a method for improving the calculation efficiency by omitting the same multiplication or replacing it with addition. Yes.

  FIG. 3 is a block diagram showing a configuration of an equalization circuit 24A according to a modification of the equalization circuit of FIG. 3, compared with FIG. 2, the cyclic shift register 32, N multipliers 33-0 to 32-(N−1), and an adder 35 are combined into one high-speed circular convolution calculator 32 </ b> A. It is characterized by comprising. The high-speed circular convolution calculator 32A is, for example, a DSP (digital signal processor), and includes a cyclic shift register 32, N multipliers 33-0 to 32- (N-1), an adder 35, These operations are realized by a calculation process based on a program. With this configuration, the equalization circuit 24A in FIG. 3 has the advantage that the number of computations can be reduced and the computation result can be obtained earlier in time compared to the equalization circuit 24 in FIG.

  In the above embodiment, the equalization circuits 24 and 24A for equalizing the communication path characteristics of the wireless channel between the wireless transmission device and the wireless reception device have been described. However, the present invention is not limited to this, and the wired circuit is not limited thereto. The present invention can also be applied to an equalization circuit that equalizes the channel characteristics of a line.

  In the above-described embodiment, the reference signal included in the received signal from the transmission device using the reference signal that is the training signal, using the LMS algorithm, the RLS algorithm, or the like (see, for example, Non-Patent Document 5) Compare the reference signal with the same reference signal, and update the weighting factor for the circular convolution operation that equalizes the communication path between the transmitting device and the receiving device so that the error is substantially minimized. After calculating and setting the weighting factor, the cyclic convolution operation is performed on the body signal such as the data signal that is not the reference signal using the calculated weighting factor, thereby The main body signal can be received with the communication path equalized. However, the present invention is not limited to this, and based on a body signal such as a data signal that is not a reference signal included in a received signal from a transmission device, CMA (Constant Modulus Algorithm), MMA (Multi-Modulus Algorithm), RCA (Reduced) Using a known blind adaptive control algorithm such as Constellation Algorithm) or ZF (Zero Forcing) method (for example, refer to Non-Patent Document 6-9), equalizing the communication path between the transmission device and the reception device; A cyclic convolution calculation weight coefficient may be calculated. That is, the present invention is particularly characterized in that the communication path between the transmission device and the reception device is equalized by a circular convolution operation.

  As described above in detail, according to the communication path equalization apparatus and method according to the present invention, a signal transmitted from a transmission apparatus is received by a reception apparatus, and the received signal is serially parallel to a plurality of parallel signals. Converting and outputting, performing a circular convolution operation on the parallel signal and a predetermined weight coefficient, outputting a signal after the circular convolution operation, and transmitting the signal based on the signal after the circular convolution operation The weighting factor for equalizing the channel characteristics between the transmission device and the receiving device is calculated and set as a weighting factor for the circular convolution operation. Equalizes the channel characteristics with the device. Therefore, the circuit scale can be greatly reduced as compared with the prior art, and thus the manufacturing cost can be greatly reduced.

Claims (8)

Conversion means for receiving a signal transmitted from the transmission device by the reception device, and performing serial-parallel conversion on the received signal to a parallel signal of a plurality of columns and outputting the same;
Arithmetic means for performing a circular convolution operation on the parallel signal output from the conversion means and a predetermined weighting coefficient and outputting a signal after the circular convolution operation;
Control means for computing the weighting factor for equalizing the channel characteristics between the transmitting device and the receiving device based on the signal outputted from the computing means, and outputting and setting to the computing means And
A communication path equalization circuit characterized by equalizing communication path characteristics between the transmission apparatus and the reception apparatus by the circular convolution operation. The signal transmitted from the transmission device includes a reference signal,
The control means compares the reference signal included in the signal output from the arithmetic means with the same reference signal as the reference signal, and updates the weighting coefficient so that the error is substantially minimized. 2. The communication path equalizing circuit according to claim 1, wherein the weighting factor is calculated and output to the calculating means and set. The computing means is
It has a plurality of registers connected so that the signal stored in each register circulates, inputs the parallel signal output from the conversion means, stores it in each register, outputs it, and stores it in one register A cyclic shift register that sequentially circulates and stores and outputs the output signal to the next connected register for storage.
Multiplying means for multiplying a parallel signal output from the cyclic shift register by a predetermined weighting factor and outputting a signal after multiplication;
3. The communication path equalizing circuit according to claim 1, further comprising an adding unit that adds the signals after multiplication output from the multiplication unit and outputs the signal after addition.   The circuit for performing circular convolution constituted by the cyclic shift register, the multiplying means, and the adding means is constituted by a single high-speed arithmetic unit using a high-speed circular convolution algorithm. Item 4. The communication path equalization circuit according to Item 3. Receiving a signal transmitted from the transmitting device by the receiving device, serially parallel-converting the received signal into a plurality of parallel signals, and outputting,
Performing a circular convolution operation on the parallel signal and the predetermined weighting factor to output a signal after the circular convolution operation;
Based on the signal after the circular convolution operation, the weighting factor for equalizing the channel characteristics between the transmitting device and the receiving device is calculated and used as a weighting factor for the circular convolution operation. Including the step of setting,
A channel equalization method characterized by equalizing channel characteristics between the transmission device and the reception device by the circular convolution operation. The signal transmitted from the transmission device includes a reference signal,
The step of calculating and setting the weighting factor compares the reference signal included in the signal after the circular convolution operation with the same reference signal as the reference signal so that the error is substantially minimized. 6. The communication path equalization method according to claim 5, further comprising: calculating the weighting coefficient by updating the weighting coefficient, and outputting and setting the weighting coefficient to the calculating means. A conversion step of receiving the training signal transmitted from the transmission device by the reception device, serially parallel-converting the training signal into a plurality of parallel signals, and outputting,
A calculation step of performing a predetermined weighting factor and a circular convolution operation on each of the parallel signals and outputting a signal after the circular convolution operation,
The signal after the circular convolution operation is compared with the same training signal as the training signal, the weighting factor is updated so that the error is substantially minimized, and the weighting factor is updated using the updated weighting factor. The communication path equalization method according to claim 5 or 6, further comprising an equalization step of equalizing communication path characteristics between the transmission apparatus and the reception apparatus. The above calculation steps are:
Using a cyclic shift register having a plurality of registers connected so that the signal stored in each register circulates, the parallel signal is input, stored and output in each register, and stored in one register And sequentially circulating and storing and outputting the received signal to a connected register and storing it,
Multiplying the parallel signal output from the cyclic shift register by a predetermined weighting factor and outputting the multiplied signal;
8. The channel equalization method according to claim 7, further comprising the step of adding the signals after multiplication and outputting the signal after addition.

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