JP5020443B2 - Method and apparatus for accessing shared resource - Google Patents

Description

【００４３】
ある要求部からのメモリアクセス要求は先入れ／先出しされ、対応プログラム可能レジスタにより決定されるＮサイクル毎に、その先入れ／先出しされた要求のうちの１つが調停される。これにより、帯域幅制御回路が要求フィルタとして機能し、例えばこれら要求部が一度に大量の要求を生成し、他の要求部も同様に要求を生成している場合、特定の要求部によるメインメモリ１１２へのアクセス要求をスローダウンさせることができる。従って、特定の要求部がメインメモリ１１２へのデータ書き込み要求を大量に生成しているような場合、その帯域幅制御回路が、これら要求が調停される割合を制御するようプログラミングされる。どの要求部もアクセスを主張していない場合、ある要求部からの要求が直ちに処理される。
【００４４】
帯域幅制御回路は、対応マスタのためにメモリ帯域幅を制御する。例えば、コマンドプロセッサのプログラム可能レジスタの内容がメモリサイクル毎に加算される、アキュムレータのビット８（すなわち最上位ビット）が１でない場合、待ち状態のコマンドプロセッサ要求があったとしても、アキュムレータのビット８が１に等しくなるように十分なサイクルが経過するまで、又は他のマスタからの待ち状態の要求がなくなるまで、その要求は調停されない。メモリコントローラ１５２は、帯域幅制御回路の設定により、メインメモリ１１２がアイドル状態にならないようにするのが好ましい。帯域幅制御回路６２０−１〜６２０−５は、マスタに対応するアキュムレータのビット８（すなわち最上位）が１に等しくなるまで、そのマスタからの要求をマスキングすることにより、この調停方式に作用する。
【００４５】
このように、帯域幅制御回路６２０−１〜６２０−５は、マスタからの要求を調停する頻度をプログラム可能に制御することにより、主要メモリの「ホグ」によるメモリの使用に影響を及ぼす。ある書き込みマスタ用の帯域幅制御回路は、例えば、そのマスタからの書き込み要求をグローバル書き込み用バッファＷＱ０にスロットリングすることにより、その書き込みマスタからメインメモリ１１２への書き込みをスローダウンさせることができる。ここで、帯域幅制御回路のプログラム可能レジスタ設定により、許可されない未処理読み出し要求がある場合、調停によりメインメモリ１１２をアイドル状態にしないことが好ましい。この場合、スロットリングされる要求部の間で、ラウンドロビン方式が用いられる。例えば、２つの要求部がラウンドロビン方式に関与すると仮定すると、調停コントロール６２２は、最初の要求部に１番目のメモリサイクルを与え、２つ目の要求部に２番目のメモリサイクルを与え、最初の要求部に３番目のメモリサイクルを与える。
【００４６】
このシステム例においては、読み出しはすべて単一キャッシュライン（３２バイト）である。そのため、キャッシュラインの読み出しには２００ＭＨｚで２サイクル要し、新規読み出しは１０ナノ秒毎に行われる。その他要求部の間でのラウンドロビン調停において、メインプロセッサ１１０からの読み出し要求が最優先される。メモリ所有権は、読み出し要求部の間で１０ナノ秒毎に変わってリフレッシュされるが、書き込みキューは、常に全体にわたって書き込みされる。書き込みキューは、あるレベルまで、又はあるレベルを超えて満たされたとき、あるいはメインプロセッサ読み出し要求が書き込み用バッファのエントリにマッチしたときに、要求を開始する。これらには、要求の頻度に関して以下の制限が課せられる。
・メインプロセッサの読み出しは、２つ連続して行えない。
・システムの読み出しは、２つ連続して行えない。
・１０ナノ秒のリフレッシュサイクル中、２行リフレッシュされる。５ナノ秒毎に１行。
ここに記載する帯域幅制御回路は、ある特定の調停プロセスとの使用に限定されない。読み出しキュー調停方式例と書き込みキュー調停方式例とを以下に説明するが、これらは例示であって制限ではない。これら例示調停方式のさらなる詳細は、共に名称が「機能向上型メモリコントローラを用いたグラフィックス処理システム」である、上記仮出願番号６０／２２６，８９４、及び対応出願番号０９／７２６，２２０に記載されている。
【００４７】
（読み出しキューの調停例）
メインプロセッサ１１０は、以下の場合を除いて最優先される。
・メインプロセッサ１１０が先のアクセスに対するマスタである場合
・メインプロセッサ読み出しマスタ用のアキュムレータのビット８（ＭＳＢ）が１に等しくなく、アキュムレータのビット８（ＭＳＢ）が１に等しい他のマスタによる他の要求がある場合
・書き込み用バッファが完全なフル状態で、書き込みサイクルの最中である場合
・先のメインプロセッサアドレスが、書き込み用バッファをフラッシュさせるプロセッサインタフェースローカル書き込み用バッファ、又はグローバル書き込み用バッファにおける有効なメインプロセッサ書き込みアドレスに合致する場合
【００４８】
コマンドプロセッサ２００又はテクスチャユニット５００が、その他のシステムマスタ（すなわち、オーディオＤＳＰ１５６、周辺（Ｉ／Ｏ）コントローラ１６２、ビデオコントローラ１６４）と同じ優先度を有し、従って、以下の条件以外でシステムマスタをラウンドロビン方式でメモリ調停する。
・オーディオＤＳＰ１５６、周辺（Ｉ／Ｏ）コントローラ１６２又はビデオコントローラ１６４が、先のアクセスに対するマスタである場合
・コマンドプロセッサ読み出し又はテクスチャユニット読み出しのアキュムレータのビット８（ＭＳＢ）が１に等しくなく、その対応アキュムレータのビット８が１に等しい他のマスタによる他の要求がある場合。
【００４９】
オーディオＤＳＰ１５６（又は周辺（Ｉ／Ｏ）コントローラ１６２、又はビデオコントローラ１６４）の読み出しは、その他グラフィックスマスタ（コマンドプロセッサ２００及びテクスチャユニット５００）と同じ優先度を有し、従って、以下の条件以外でグラフィックスマスタをラウンドロビン方式でメモリ調停する。
・オーディオＤＳＰ１５６（又は周辺（Ｉ／Ｏ）コントローラ１６２、又はビデオコントローラ１６４）が、先のアクセスに対するマスタである場合
【００５０】
グローバル書き込み用バッファＷＱ０は、以下の状態以外でメインプロセッサ１１０、グラフィックス又はシステムマスタより低い優先度を有する。
・グローバル書き込み用バッファＷＱ０が完全なフル状態で、ラウンドロビン方式で調停を行う場合
・メインプロセッサ読み出しアドレスは、グローバル書き込み用バッファＷＱ０内の書き込みアドレスと合致する場合、最優先される。
・優先度が高いその他のマスタのアキュムレータのビット８が１に等しくない場合
【００５１】
以下の条件以外で、リフレッシュは最低の優先度を有する。
・リフレッシュ要求の合計がしきい値に達すると、その優先度はメインプロセッサ読み出しのすぐ下のレベルまであがる。
・優先度が高いその他のマスタのアキュムレータのビット８が１に等しくない場合
【００５２】
（書き込みキューの調停例）
メインプロセッサ１１０、ピクセルエンジン７００、オーディオＤＳＰ１５６及び周辺（Ｉ／Ｏ）コントローラ１６２は、書き込みキューの４つのマスタである。メインプロセッサによる書き込みは最優先され、その他３つのマスタは以下の状態以外の場合にラウンドロビン方式で調停される。
・メインプロセッサ書き込みのアキュムレータのビット８（ＭＳＢ）が１に等しくなく、そのアキュムレータのビット８（ＭＳＢ）が１に等しい書き込みマスタが他にある場合
【００５３】
上記説明は、メモリ装置へのアクセスについてであるが、本発明はこれに限定されるものではなく、ここに説明するコンセプトは、バス（例えば、ＰＣＩバス）、プロセッサ（例えば、非埋め込み型プロセッサ）等の共有リソースへのアクセスを複数の要求部が要求するような状況下でも、十分に適用可能である。
【００５４】
（その他互換性のあるインプリメンテーション例）
上記システム装置５０は、上述したホームビデオゲームコンソール構成以外でも実現され得る。例えば、システム５０をエミュレート、そうでなければ互換性がある違った構成を有するプラットフォーム上で、システム５０向けに記述されたグラフィックスアプリケーションや他のソフトウェアを実行することができる。システム５０のハードウェア及びソフトウェアリソースの一部又はすべてを、エミュレート、シミュレート及び／又は提供できるプラットフォームであれば、ソフトウェアを首尾良く実行することができる。
【００５５】
例えば、エミュレータは、システム５０のハードウェア及び／又はソフトウェア構成（プラットフォーム）とは異なるハードウェア及び／又はソフトウェア構成（プラットフォーム）を提供し得る。このエミュレータシステムは、アプリケーションソフトウェアが記述されたシステムのハードウェア及び／又はソフトウェア構成要素の一部又はすべてを、エミュレート又はシミュレートするソフトウェア及び／又はハードウェア構成要素を含むこともある。例えば、このエミュレータシステムは、システム５０のハードウェア及び／又はファームウェアをシミュレートするソフトウェアエミュレータプログラムを実行するパーソナルコンピュータのような汎用デジタルコンピュータを備えることもある。上記オーディオシステムのＤＳＰ処理は、パーソナルコンピュータ上でエミュレート可能である。
【００５６】
汎用デジタルコンピュータ（例えば、ＩＢＭやマッキントッシュのパーソナルコンピュータ、及びその互換機）によっては、ＤｉｒｅｃｔＸやその他の標準３ＤグラフィックスコマンドＡＰＩに準拠する３Ｄグラフィックスパイプラインを提供する、３Ｄグラフィックスカードを装備している。あるいは、サウンドコマンドの標準セットに基づく高品質な立体的サウンドを可能にする、立体的サウンドカードも装備していることがある。このような、エミュレータソフトウェアを実行するマルチメディアハードウェア対応パーソナルコンピュータは、システム５０のグラフィックス及びサウンド性能を近似させるのに十分な性能を有し得る。エミュレータソフトウェアは、パーソナルコンピュータのプラットフォーム上のハードウェアリソースを制御して、ゲームプログラマがゲームソフトウェアを記述したホームビデオゲームコンソールプラットフォームの処理、３Ｄグラフィックス、サウンド、周辺、及びその他機能をシミュレートする。
【００５７】
図１３に、ホストプラットフォーム１２０１、エミュレータ構成１３０３及び記憶媒体６２に用意されたゲームソフトウェアの実行可能な２値画像を用いた、包括的なエミュレーション処理の例を示す。ホスト１２０１は、例えば、パーソナルコンピュータ、ビデオゲームコンソール又はその他十分な演算能力を有するプラットフォームのような、汎用又は特殊目的用デジタル演算装置である。エミュレータ１３０３は、ホストプラットフォーム１２０１上で実行され、記憶媒体６２からのコマンド、データ及び情報をホスト１２０１により処理可能な形式にリアルタイムに変換するソフトウェア及び／又はハードウェアである。例えば、エミュレータ１３０３は、システム５０による実行を意図する「ソース」２値画像プログラム命令を記憶媒体６２から取り出し、これらプログラム命令をホスト１２０１が実行又は処理可能な対象形式に変換する。
【００５８】
例えば、ソフトウェアが、ＩＢＭ Ｐｏｗｅｒ ＰＣ等の特定のプロセッサを用いて、プラットフォーム上で実行されるよう記述されたものであり、ホスト１２０１がそれとは異なる（例えば、インテルの）プロセッサを使用したパーソナルコンピュータである場合、エミュレータ１３０３は、記憶媒体６２から２値画像のプログラム命令を１つ又はそのシーケンスを取り出して、これらプログラム命令を１つ又はそれ以上の同等なインテルの２値画像プログラム命令に変換する。エミュレータ１３０３は、グラフィックス＆オーディオプロセッサ１１４による処理向けのグラフィックスコマンドとオーディオコマンドも取り出し及び／又は生成し、これらコマンドを、ホスト１２０１上で使用可能なハードウェア及び／又はソフトウェアグラフィックス及びオーディオ処理リソースにより処理され得るフォーマットに変換する。一例として、エミュレータ１３０３は、これらのコマンドを、ホスト１２０１の特定グラフィックス及び／又はオーディオハードウェアで処理され得るコマンドに変換してもよい（例えば、標準ＤｉｒｅｃｔＸ、ＯｐｅｎＧＬ及び／又はサウンドＡＰＩを用いて）。
【００５９】
上記ビデオゲームシステムの特長の一部又はすべてを提供するために使用されるエミュレータ１３０３は、グラフィックスユーザインタフェース（ＧＵＩ）を備えていてもよく、これによりエミュレータを用いて実行されるゲームの様々なオプションやスクリーンモードの選択が簡易化又は自動化される。例えば、このようなエミュレータ１３０３は、本来のソフトウェア用ホストプラットフォームと比べてさらに機能が拡張されていてもよい。
【００６０】
図１４に、エミュレータ１３０３と共に使用するのに適したエミュレーションホストシステム１２０１を示す。システム１２０１は、処理ユニット１２０３及びシステムメモリ１２０５を含む。システムバス１２０７は、システムメモリ１２０５を始めとする様々なシステム構成要素を処理ユニット１２０３に接続する。システムバス１２０７は、メモリバス又はメモリコントローラを含むバス構造のいくつかのタイプのうちの１つであり、様々なバスアーキテクチャのうちの１つを利用した周辺バス及びローカルバスである。システムメモリ１２０７は、読み出し専用メモリ（ＲＯＭ）１２５２、及びランダムアクセスメモリ（ＲＡＭ）１２５４を含む。起動中等、パーソナルコンピュータシステム１２０１の内部要素の間での情報転送に役立つ基本ルーチンを含む基本入出力システム（ＢＩＯＳ）１２５６は、ＲＯＭ１２５２に格納される。システム１２０１は、さらに様々なドライブと、それに関連するコンピュータ読み出し可能媒体を含む。ハードディスクドライブ１２０９は、（典型的に固定の）磁気ハードディスク１２１１からの読み出し／への書き込みを行う。追加（できればオプションで）磁気ディスクドライブ１２１３は、着脱可能な「フロッピー」又はその他の磁気ディスク１２１５からの読み出し／への書き込みを行う。光ディスクドライブ１２１７は、ＣＤ−ＲＯＭやその他の光学媒体等の着脱可能な光ディスク１２１９から読み出しを行い、構成によっては書き込みも行う。ハードディスクドライブ１２０９及び光ディスクドライブ１２１７は、それぞれハードディスクドライブインタフェース１２２１と光ドライブインタフェース１２２５とによって、システムバス１２０７に接続される。そのドライブとそれに関連するコンピュータ読み出し可能媒体とは、コンピュータ読み出し可能命令、データ構造、プログラムモジュール、ゲームプログラム及びその他パーソナルコンピュータシステム１２０１向けのデータを、不揮発的に記憶する。他の構成において、データを格納し、コンピュータによってアクセスされ得るコンピュータ読み出し可能媒体（例えば、磁気カセット、フラッシュメモリカード、デジタルビデオディスク、ベルヌーイカートリッジ、ランダムアクセスメモリ（ＲＡＭ）、読み出し専用メモリ（ＲＯＭ）等）も使用され得る。
【００６１】
エミュレータ１３０３を含む数多くのプログラムモジュールは、ハードディスク１２１１、着脱式磁気ディスク１２１５、光ディスク１２１９、及び／又はシステムメモリ１２０５のＲＯＭ１２５２及び／又はＲＡＭ１２５４上に記憶される。このようなプログラムモジュールは、グラフィックス＆サウンドＡＰＩ、１つ又はそれ以上のアプリケーションプログラム、その他プログラムモジュール、プログラムデータ及びゲームデータを提供するオペレーティングシステムを含んでいてもよい。ユーザは、キーボード１２２７、ポインティング装置１２２９、マイク、ジョイスティック、ゲームコントローラ、衛星放送用アンテナ、スキャナ等の入力装置を通して、パーソナルコンピュータシステム１２０１にコマンドや情報を入力する。例えば、これらの入力装置は、システムバス１２０７に接続されるシリアルポートインタフェース１２３１を介して処理ユニット１２０３に接続され得るが、もちろん他のインタフェース、例えばパラレルポート、ゲームポートファイアワイヤバス又はユニバーサルシリアルバス（ＵＳＢ）によっても接続され得る。モニタ１２３３等の表示装置も、ビデオアダプタ１２３５等のインタフェースを介してシステムバス１２０７に接続される。
【００６２】
システム１２０１は、モデム１１５４やその他のネットワークインタフェース手段も含み、インターネット等のネットワーク１１５２を介して通信を確立する。内部、外部を問わず、モデム１１５４は、シリアルポートインタフェース１２３１を介してシステムバス１２３に接続される。ネットワークインタフェース１１５６も備えられていてもよく、これによりシステム１２０１がローカルエリアネットワーク１１５８を介して、リモート演算装置１１５０（別システム１２０１等）と通信可能になる（この通信は、広域ネットワーク１１５２、又はダイアルアップやその他の通信手段等の通信パスでもかまわない）。システム１２０１は、典型的には、プリンタやその他の標準的な周辺装置等、その他周辺出力装置を含む。
【００６３】
例えば、ビデオアダプタ１２３５は、マイクロソフトのＤｉｒｅｃｔ７．０、又はその他のバージョン等の標準３Ｄグラフィックスアプリケーションプログラマインタフェースに基づいて送出される３Ｄグラフィックスコマンドに応答して、高速３Ｄグラフィックスレンダリングを行う３Ｄグラフィックスパイプラインチップを含んでいてもよい。ステレオスピーカ１２３７のセットは、バス１２０７からのサウンドコマンドに基づいて、高品質な立体的サウンドを生成するためのハードウェア及び組み込みソフトウェアサポートを提供する、従来の「サウンドカード」のようなサウンド生成インタフェースを介して、システムバス１２０７に接続される。これらハードウェア機能により、システム１２０１が、記憶媒体６２に格納されているソフトウェアをプレイするための、十分なグラフィックス及びサウンドスピード性能を提供する。
【００６４】
以上、本発明を、最も実用的で好ましい実施形態であると現時点で判断される内容に関して説明してきたが、本発明は、開示された実施形態にのみ制限されるべきものではなく、反対に記載した請求項の範囲内において、様々に変更、及び同等な内容が適用されるものとする。
【図面の簡単な説明】
【図１】対話式コンピュータグラフィックスシステム例の全体図である。
【図２】図１に示すコンピュータグラフィックスシステム例を示すブロック図である。
【図３】図２に示すグラフィックス＆オーディオプロセッサ例を示すブロック図である。
【図４】図３に示す３Ｄグラフィックスプロセッサ例を示すブロック図である。
【図５】図４のグラフィックス＆オーディオプロセッサのロジカルフロー例を示す図である。
【図６】メモリコントローラ１５２とその他のシステム構成要素との関係を示す全体図である。
【図７】メインメモリ１１２へのアクセスの競合に関与する動作のいくつかを示す図である。
【図８】メモリコントローラ１５２のインタフェースを詳細に示す図である。
【図９】メモリコントローラ１５２の帯域幅制御回路６２０−１〜６２０−５を示す図である。
【図１０】メモリコントローラ１５２のためのアドレスパス及び読み出しデータパスをそれぞれ示す図である。
【図１１】メモリコントローラ１５２のためのアドレスパス及び読み出しデータパスをそれぞれ示す図である。
【図１２】帯域幅制御回路６２０−１〜６２０−５の詳細を示すブロック図である。
【図１３】別の互換的な実施例を示す図である。
【図１４】別の互換的な実施例を示す図である。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method and apparatus for accessing a shared resource, and more particularly to a method and apparatus for accessing a shared resource of an interactive graphics system, such as an interactive graphic for a home video game platform.
[0002]
[Prior art]
Increasingly, fantasy creatures, such as dinosaurs, aliens, and animated toys, are seeing very realistic movies. Such moving images are made possible by computer graphics. By using this technique, the computer graphics artist can identify the shape of each object and the appearance changes that occur over time. Then, the computer models the object and displays it on the screen of a home television or computer. Each part of the display image is colored and formed based on the distance and orientation of objects in the scene, the illumination direction for each object, the texture of the surface of each object, and various other factors. The computer takes care of many of the processes necessary for this.
[0003]
Due to the complexity of the computer graphics generation process, until just a few years ago, the use of computer generated 3D graphics was limited to expensive and specialized flight simulators, high-end graphics workstations and supercomputers. It was. People could see the images produced by these computer systems in movies and high-cost television commercials, but could not come into contact with the computers that actually created the graphics. is there. However, the situation has changed with the advent of relatively inexpensive graphics platforms for personal computers, such as Nintendo 64 (registered trademark) and various 3D graphics cards. Now it is possible to interactively create powerful 3D animations and simulations in homes and offices using affordable computer graphics systems.
[0004]
[Problems to be solved by the invention]
In computer graphics systems, resources are often “shared” by a number of different components. For example, the operation of a graphics processor or main processor tends to end up with numerous access requests to system memory. It is known to use an arbitrator circuit to ensure proper allocation of memory access to each request. For arbitration, several different techniques can be applied, such as a technique in which one of the components is given high priority or a round robin method in which all of the components are given a memory access opportunity. is there. In this specification, a controller that can be configured to control the frequency of access requests to a shared resource related to the arbitration process, such as a memory controller, will be described.
[0005]
[Means for Solving the Problems]
One aspect of the present invention includes a controller that controls access to a shared resource. This controller is implemented as a state machine, for example, and includes an arbitrator for arbitrating a plurality of access requests to the shared resource, and a programmable bandwidth control circuit for controlling the arbitration frequency of requests by the arbitrator.
[0006]
The shared resource may be a computer readable medium and the request may include requests to read from and write to the computer readable medium. The bandwidth control circuit may be composed of programmable registers and associated accumulators. The contents of the programmable registers are repeatedly added to each corresponding accumulator and arbitrated when the corresponding accumulator value reaches a predetermined value (eg, when a particular bit is set / cleared). The registers are programmable using an application programming interface.
[0007]
Another aspect of the present invention is a method for controlling access to a shared resource, which arbitrates a plurality of access requests to the shared resource and controls the arbitration frequency of these requests in a programmable manner.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
An example of an interactive 3D computer graphics system 50 is shown in FIG. System 50 can be used to play interactive 3D video games with intriguing stereo sound. Furthermore, it can be used for various other applications.
[0009]
In this example, the system 50 has a function of interactively processing a digital representation or a three-dimensional world model in real time. The system 50 can display the world partially or entirely from any viewpoint. For example, the system 50 can interactively change viewpoints in response to real-time input from handheld controllers 52a and 52b, or other input devices. Thereby, the game player can see the world through the eyes of someone inside or outside the world. The system 50 can be used for applications that do not require real-time interactive 3D display (eg, 2D display generation and / or non-interactive display), but its high quality 3D image ultra-high speed display capability greatly It can be used to create realistic and powerful gameplay or other graphical interactions.
[0010]
To play an application such as a video game using the system 50, the user first connects the main unit 54 to his or her color television set 56 or other display device using the cable 58. The main unit 54 generates a video signal and an audio signal, and controls the color television set 56. The video signal controls an image displayed on the television screen 59, and the audio signal is reproduced as sound through the television stereo speakers 61L and 61R.
[0011]
Further, the user connects the main unit 54 to a power source. This power source is a conventional AC adapter (not shown) that is plugged into a standard household electrical outlet and converts the household current into a low DC voltage signal suitable for powering the main unit 54. . The battery can be used in other embodiments.
[0012]
The user may control the main unit 54 with the handheld controllers 52a and 52b. For example, the control unit 60 may be used to specify the direction in which the character displayed on the television 56 moves in the three-dimensional world (up and down, left and right, approach and move away). The control unit 60 further provides input to other applications (for example, menu selection, pointer / cursor control, etc.). The controller 52 can take a variety of forms. In the present example, the illustrated controller 52 includes a control unit 60 such as a joystick, a push button, and / or a direction switch. The controller 52 may be connected to the main unit 54 by cable or wireless via electromagnetic (wireless, infrared, etc.) waves.
[0013]
When playing an application such as a game, the user appropriately selects a storage medium 62 that stores an application that the user wants to play, such as a video game, and inserts the storage medium into the slot 64 of the main unit 54. The storage medium 62 may be, for example, a specially encoded and / or encrypted optical and / or magnetic disk. The user operates the power switch 66 to turn on the main unit 54 and starts execution of an application such as a video game based on software stored in the storage medium 62. The user may operate the controller 52 to give input to the main unit 54. For example, when the control unit 60 is operated, an application such as a game can be started. When the other control unit 60 is moved, the animated characters can move in different directions, or the user's viewpoint in the three-dimensional world can change. The specific software stored in the storage medium 62 allows each control unit 60 on the controller 52 to perform different functions at different times.
[0014]
(Example of electronic components of the entire system)
FIG. 2 is a block diagram illustrating exemplary components of the system 50. The main components are:
Main processor (CPU) 110
Main memory 112, and
・ Graphics & Audio Processor 114
Is included.
[0015]
In this example, main processor 110 (eg, enhanced IBM Power PC 750) receives input from handheld controller 52 (and / or other input device) via graphics and audio processor 114. The main processor 110 interactively responds to user input and executes a video game or other program provided by the external storage medium 62 via a mass storage access device 106 such as, for example, an optical disc drive. For example, in a video game play situation, the main processor 110 can perform collision detection and moving image processing in addition to various interactive control functions.
[0016]
In this example, the main processor 110 generates a 3D graphics command and an audio command, and sends them to the graphics & audio processor 114. The graphics and audio processor 114 processes these commands, generates a dynamic visual image on the display 59, and produces high quality stereo sound from the stereo speakers 61R and 61L or other suitable sound generator. Output.
[0017]
The exemplary system 50 receives image signals from the graphics and audio processor 114 and displays analog and analog signals suitable for displaying on standard display devices such as computer monitors and home color television sets 56. And / or a video encoder 120 for converting to a digital video signal. The system 150 further includes an audio codec (compressor / decompressor) 122 that compresses / decompresses the digitized audio signal and further converts between a digital audio signal format and an analog audio signal format as needed. The audio codec 122 receives audio inputs via the buffer 124 and processes them (mixes other audio signals generated by the processor and audio signals received via the audio output stream of the mass storage access device 106). It can also be provided to the graphics and audio processor 114 for this purpose. The graphics and audio processor 114 in this example can store audio related information in an audio memory 126 that can be used for audio tasks. The graphics and audio processor 114 outputs the processed audio output signal to the audio codec 122 for decompression and conversion into an analog signal (for example, via the buffer amplifiers 128L and 128R), and as a result, a speaker. It can be played by 61L and 61R.
[0018]
The graphics and audio processor 114 has a function of communicating with various additional devices existing in the system 50. For example, parallel digital bus 130 may be used for communication with mass storage access device 106 and / or other components. The serial peripheral bus 132 is, for example,
Programmable read only memory and / or real time clock 134
A modem 136 or other networking interface (which may connect the system 50 to a telecommunications network 138, such as the Internet or other digital network, from which program instructions and / or data may be downloaded or uploaded)
-Flash memory 140
May be used to communicate with various peripheral devices. Note that the additional external serial bus 142 may be used for communication with a device such as an additional expansion memory 144 (for example, a memory card). The connectors may be used to connect various devices to the buses 130, 132, 142.
[0019]
(Example of graphics and audio processor)
FIG. 3 is a block diagram illustrating an example of the graphics and audio processor 114. The graphics & audio processor 114 is, for example, a one-chip ASIC (application specific integrated circuit). In this example, the graphics and audio processor 114 is
Processor interface 150
Memory interface / controller 152
3D graphics processor 154
Audio digital signal processor (DSP) 156
Audio memory interface 158
・ Audio Interface & Mixer 160
The peripheral controller 162, and
Display controller 164
Is provided.
[0020]
The 3D graphics processor 154 performs graphics processing tasks. Audio digital signal processor 156 performs audio processing tasks. Display controller 164 accesses the image information in main memory 112 and provides it to video encoder 120 for display on display device 56. The audio interface & mixer 160 is connected to the audio codec 122 to connect audio from different sources (for example, an audio stream from the mass storage access device 106, an output from the audio DSP 156, and external audio received via the audio codec 122). Input) can be mixed. The processor interface 150 performs data supply and interface control between the main processor 110 and the graphics & audio processor 114.
[0021]
As will be described in detail later, the memory interface 152 performs data supply and interface control between the graphics & audio processor 114 and the memory 112. In this example, the main processor 110 accesses the main memory 112 via the processor interface 150 and the memory interface 152 that are part of the graphics and audio processor 114. The peripheral controller 162 performs data supply and interface control between the graphics & audio processor 114 and the various peripheral devices described above. The audio memory interface 158 serves as an interface with the audio memory 126.
[0022]
(Example of graphics pipeline)
FIG. 4 illustrates a graphics processing system that illustrates the 3D graphics processor 154 illustrated in FIG. 3 in more detail. The 3D graphics processor 154 includes a command processor 200 and a 3D graphics pipeline 180 in addition to other components. The main processor 110 communicates a data stream (eg, a graphics command stream or a display list) to the command processor 200. Main processor 110 includes a two-level cache 115 to minimize memory latency. Further, the main processor 110 includes a write gathering buffer 111 for an uncached data stream for the graphics and audio processor 114. The write gathering buffer 111 collects cache lines partially to make a full cache line, and sends data to the graphics and audio processor 114 at one cache line at a time in order to make maximum use of the bus.
[0023]
The command processor 200 receives display commands from the main processor 110 and analyzes them. If there is additional data necessary to perform this process, the additional data is acquired from the memory 112 shared via the memory controller 152. Command processor 200 provides a stream of vertex commands to graphics pipeline 180 for 2D and / or 3D processing and rendering. The graphics pipeline 180 generates an image based on these commands. The resulting image information is transferred to the main memory 112 and accessed by a display controller / video interface unit 164 that displays the frame buffer output of the pipeline 180 on the display 56.
[0024]
FIG. 5 is a logic flow diagram illustrating exemplary processing performed using graphics processor 154. The main processor 110 may store the graphics command stream 210, the display list 212, and the vertex array 214 in the main memory 112, and send a pointer to the command processor 200 via the processor / bus interface 150. Main processor 110 stores graphics commands in one or more graphics first in first out (FIFO) buffers 210 allocated in main memory 112. The command processor 200
Command stream from main memory 112 via on-chip FIFO memory buffer 216 that receives and buffers graphics commands for synchronization / flow control and load balancing
A display list 212 from the main memory 112 via the on-chip call FIFO memory buffer 218, and
A command stream in the main memory 112 via the vertex cache 220 and / or vertex attributes from the vertex array 214;
Capture.
[0025]
The command processor 200 performs a command processing operation 200a, converts the attribute type to floating point format, and sends the resulting complete vertex polygon data to the graphics pipeline 180 for rendering and rasterization. Programmable memory arbitration circuit 130 (see FIG. 4) arbitrates access to shared main memory 112 among graphics pipeline 180, command processor 200, and display controller / video interface unit 164.
FIG.
・ Conversion unit 300
Setup / rasterizer 400
-Texture unit 500
The texture environment unit 600, and
Pixel engine 700,
A graphics pipeline 180 comprising:
[0026]
The conversion unit 300 performs various 2D and 3D conversions and other operations 300a (see FIG. 5). The conversion unit 300 includes one or more matrix memories 300b and stores a matrix used in the conversion process 300a. The conversion unit 300 converts the received figure for each vertex from the object space to the screen space, or converts the received texture coordinates to obtain the coordinates of the projected texture (300c). The conversion unit 300 further performs polygon clipping / culling 300d. The illumination processing 300e is similarly performed by the conversion unit 300, and illumination calculation is performed for each vertex to obtain, for example, up to eight levels of brightness. The conversion unit 300 further creates texture coordinates (300c), and obtains an emboss type bump mapping effect as in the polygon clipping / culling process (300d).
[0027]
The setup / rasterizer 400 receives the vertex data from the transform unit 300 and sends the triangle setup information to one or more rasterization units (400b) that perform edge rasterization, texture coordinate rasterization, and color rasterization. Contains units.
[0028]
The texture unit 500 (which may include an on-chip texture memory (TMEM) 502) may perform various processes related to texture, such as
Acquisition of texture 504 from main memory 112,
-For example, multi-texture processing, post-cache texture stretching, texture filtering, embossing, shading and lighting using projected textures, texture processing including alpha transparency and depth BLIT (500a),
Bump map processing for calculating texture coordinate shifts for bump mapping, pseudo-texture, and texture tiling effect (500b), and
-Indirect texture processing (500c),
I do.
[0029]
The texture unit 500 outputs the filtered texture value to the texture environment unit 600 for texture environment processing (600a). The texture environment unit 600 can blend the polygon and texture color / alpha / depth and perform texture fog processing (600b) to obtain a reverse range based on the fog effect. Texture environment unit 600 may comprise a plurality of stages for performing various interesting environment-related functions based on, for example, color / alpha modulation, embossing, detail texturing, texture swapping, clamping, and depth blending.
[0030]
The pixel engine 700 performs depth (Z) comparison (700a) and pixel blending (700b). In this example, the pixel engine 700 stores data in an embedded (on-chip) frame buffer memory 702. The graphics pipeline 180 may include one or more embedded DRAM memories 702 and store frame buffer and / or texture information locally. The Z comparison 700a ′ may be performed at an early stage of the graphics pipeline 180, depending on the current rendering mode (if alpha blending is not required, the Z comparison may be performed at an early stage). The pixel engine 700 performs a copy operation 700 c that periodically writes the on-chip frame buffer 702 to the main memory 112 to prepare for access to the display / video interface unit 164. Further, the copy operation 700 c can be used when copying the contents of the embedded frame buffer 702 to the texture in the main memory 112 in order to obtain a dynamic texture synthesis effect. Anti-aliasing and other filtering is performed during the copy-out operation. The frame buffer output of the graphics pipeline 180 (finally stored in the main memory 112) is read out frame by frame by the display / video interface unit 164. The display controller / video interface 164 outputs digital RGB pixel values for display on the display 56.
[0031]
(Example of memory controller)
FIG. 6 is an overall view showing the relationship between the memory controller 152 and other system components. 3 and 4, the memory controller 152 and the graphics memory request arbitration 130 are depicted as being separate components, but in the following embodiment, the memory controller 152 has this configuration. Contains both elements.
[0032]
The memory controller 152 controls access requests to the main memory 112. The main memory 112 is made of, for example, Mosys, and includes an SRAM such as 1TSRAM that automatically performs an internal refresh operation. An access request to the main memory 112 includes
3D graphics processor 154 (specifically, command processor 200, texture unit 500 and pixel engine 700),
A main processor 110 via a processor interface 150;
Audio DSP 156,
A display controller 164, and
A peripheral controller 162 for various I / O units (eg, mass storage access device 106),
Etc.
[0033]
These “requesting units” compete for access to the main memory 112. FIG. 7 shows some typical operations related to this contention. Numbered arrows in FIG. 7 indicate the following operations.
1. Loading texture images from the mass storage device 62 (eg DVD) for the new game sector or level into the main memory 112
2. Load shape vertex display list from mass storage device 62 to main memory 112 for new game sector or level
3. Dynamic rendering of texture maps by main processor 110
4). Dynamic generation or modification of vertices by main processor 110
5. Light and matrix animation by main processor 110
6). Creation of display list by main processor 110
7). Generation of graphics command stream by main processor 110 Reading of graphics command stream by 8.3D graphics processor 154
9. Reading display list by 3D graphics processor 154
Vertex access for rendering by 10.3D graphics processor 154
Texture access for rendering by 11.3D graphics processor 154
[0034]
These operations are exemplary and are only some of the many operations related to reading and writing to the main memory 112. In addition, the memory controller 152 arbitrates for ports involved in main memory read and write operations. More specifically, referring to FIG. 8, the memory controller 152
Read port 602 for texture unit 500
Read port 604 for command processor 200
Write port 606 for pixel engine 700
Read / write port 608 for processor interface 150
Read / write port 610 for audio DSP 156
A read port 612 for the display controller / video interface 164, and
Read / write port 614 for peripheral controller 162
Mediate between.
[0035]
Of course, these ports are for illustrative purposes, and in some embodiments, the number of ports may be more or less. Further, the bus / signal line widths shown in FIG. 8 etc. are for illustrative purposes only and do not limit the scope of the present invention. The memory controller 152 arbitrates between these ports and assigns access to the main memory 112. In this example, the memory controller 152 and all of its inputs and outputs operate at, for example, 200 MHz. Address and control signals are directly connected to the I / O pins of the memory controller 152, while the 128-bit 200 MHz data bus is clocked, for example, at 400 MHz via the memory access controls MAC0-MAC3. Each MAC converts 32 bits on the memory controller data bus to 16 bits for communication on the main memory bus. In the following description, the operation of the device that issues a request sent to the main memory 112 is referred to as “master”.
[0036]
Some of the masters are memory “hogs” (eg, main processor read master, command processor read master, texture unit read master, main processor write master, and pixel engine write master). As schematically shown in FIG. 9, the memory controller 152 includes bandwidth control circuits 620-1 to 620-5, which will be described in detail below, and affects the use of the main memory by these memory hogs. The bandwidth control circuits 620-1 to 620-5 may be regarded as “dial”, and the request by the corresponding master may be set to be masked by the memory arbitrator 622. The memory arbitrator 622 arbitrates the request to allocate access to the main memory 112 with a bandwidth of, for example, 3.2 gigabytes. The bandwidth control circuits 620-1, 620-2, and 620-3 control the rate at which read requests from the corresponding read master participate in the arbitration process of the memory arbitrator 622 and give read requests to the main memory 112. . For example, the bandwidth control circuit associated with the command processor read master and the texture unit read master may provide a rate at which command processor read requests are supplied to the memory arbitrator 622 and texture unit read requests are supplied to the memory arbitrator 622. Used to configure in relation to the percentage. The bandwidth control circuits 620-4 and 620-5 control the rate at which write requests from the corresponding write master participate in the arbitration process of the memory arbitrator 622 and give write requests to the global write buffer queue. . For example, the bandwidth control circuit associated with the main processor write master and the pixel engine write master may indicate the rate at which the main processor write request is placed in the global write buffer queue and the pixel engine write request is placed in the global write buffer queue. It may be used to configure in relation to a certain percentage. Therefore, the bandwidth control circuit can slow down the write request of the write master, for example, by throttling the entry in the global write buffer (decreasing the entry ratio). The global write buffer is usually stored in the main memory 112 when its queue is full, when a certain level is exceeded, or when a main processor read request matches an entry to the global write buffer. Start a write request to
[0037]
The arbitration scheme is typically set and balanced to the intended overall system operation. Thereby, in an arbitration method, the main processor read request has the highest priority. However, depending on the application, it may be preferable to give a lower priority to the main processor read and give more bandwidth to the graphics processing. In this case, the main processor bandwidth control circuit may be configured such that the main processor read-out is not arbitrated every cycle. This allows the system performance to be well tuned for the application.
[0038]
10 and 11 show an address path and a read data path for the memory controller 152, respectively. Read masters seeking access to the main memory 112 are associated with corresponding ones of the read queues RQ1 to RQ6 to form a queue of read requests (addresses) for reading from the main memory 112. Write masters seeking access to the main memory 112 are associated with corresponding ones of the write queues WQ1 to WQ4 to form a write address and corresponding data queue for writing to the main memory 112. The memory arbitrator 622 assigns access to the main memory to the read queues RQ1 to RQ6 in a predetermined arbitration process, and which write request from the write queues WQ1 to WQ4 is given to the global write buffer WQ0 To control. The rate at which at least some of the requests are supplied to this arbitration process can be controlled according to the settings of the bandwidth control circuit. By appropriately setting the bandwidth control circuit for a particular operation, an insightful user can adjust the flow of requests to the arbitration process and improve system performance in that operation. Is possible.
[0039]
There is an arbitration scheme for the global write buffer WQ0. This is because there are cases where four request units make a write request to the main memory 112. In the arbitration method for the global write buffer, arbitration is performed between these four request units. Each write master has a local queue (ie one of WQ1-WQ4) and arbitrates other entries into the global write buffer whenever the local queue for a particular write master is not empty. . The main processor 110 write always has the highest priority, so the bandwidth control circuit is “dialed down” to this priority. The pixel engine 700 has the same write priority as the audio DSP 156 and the peripheral (I / O) controller 162. However, the pixel engine 700 uses a 128-bit bus, and when copying is performed to the main memory 112, the pixel engine 700 may make a write request every cycle. Therefore, the bandwidth control circuit gives “dial down” to the write request unit so that the write request is not arbitrated every cycle.
[0040]
By collecting write requests in the global write buffer WQ0, switching from read to write and write to read is reduced, and dead memory cycles that occur when the main memory bus is changed can be minimized. The write request is supplied to the global write buffer WQ0, while the read request is processed according to the arbitration method. When the global write buffer WQ0 is filled to a certain level, or when a read request from the main processor matches an entry in the global write buffer, the main memory bus is often switched from read to write state. By this switchover, the global write buffer WQ0 is flushed in order to write data to a specific address in the main memory 112.
[0041]
FIG. 12 shows an implementation example of the bandwidth control circuits 620-1 to 620-5. Of course, the bandwidth control circuit can be realized by other methods, and the present invention is not limited to this. In the example embodiment, each bandwidth control circuit includes a programmable hardware register 710 and a hardware accumulator 720. The programmable register is a 9-bit register (bit 8 to bit 0), and the data for programming is in 1.8 format (that is, x.xxxxxxxx). The accumulator 720 is initialized to a predetermined number (eg, 0.00000000), and the number programmed in the programmable register 710 is automatically added to the accumulator 720 every cycle. When bit 8 (most significant bit) of accumulator 720 is set, the corresponding request is arbitrated in that cycle and either read from main memory or placed in the global write buffer queue. This is represented in FIG. 12 by the closure of the signal path between the input request and the arbitrator 622. If the programmable register 710 is set to 0x1.00, the corresponding request is arbitrated every cycle. For example, to arbitrate requests from a master every other cycle, the corresponding programmable register is set to 0x80. The default value of the programmable register in this case is 0x1.00, and the register is programmable via an application programming interface (API).
[0042]
An example of a programmable register is shown below.
[Table 1]

[0043]
A memory access request from a request unit is first-in / first-out, and one of the first-in / first-out requests is arbitrated every N cycles determined by the corresponding programmable register. As a result, the bandwidth control circuit functions as a request filter. For example, when these request units generate a large number of requests at a time and other request units generate requests in the same manner, the main memory by a specific request unit The access request to 112 can be slowed down. Thus, if a particular requester is generating a large number of data write requests to main memory 112, its bandwidth control circuit is programmed to control the rate at which these requests are arbitrated. If no request unit claims access, a request from a request unit is processed immediately.
[0044]
The bandwidth control circuit controls the memory bandwidth for the corresponding master. For example, if the accumulator bit 8 (ie, the most significant bit) is not 1, the contents of the command processor's programmable register are incremented every memory cycle, even if there is a waiting command processor request, the accumulator bit 8 The request is not arbitrated until enough cycles have passed so that is equal to 1 or until there are no more pending requests from other masters. The memory controller 152 preferably prevents the main memory 112 from entering an idle state by setting the bandwidth control circuit. Bandwidth control circuits 620-1 through 620-5 operate on this arbitration scheme by masking requests from the master until bit 8 (ie, most significant) of the accumulator corresponding to the master is equal to 1. .
[0045]
Thus, the bandwidth control circuits 620-1 to 620-5 control the frequency of arbitrating requests from the master in a programmable manner, thereby affecting the use of the memory by the “hog” of the main memory. The bandwidth control circuit for a certain write master can slow down the write from the write master to the main memory 112 by, for example, throttling the write request from the master to the global write buffer WQ0. Here, when there is an unprocessed read request that is not permitted due to the programmable register setting of the bandwidth control circuit, it is preferable that the main memory 112 not be idled by arbitration. In this case, a round robin method is used between requesting parts to be throttled. For example, assuming that two request units are involved in the round robin scheme, arbitration control 622 provides the first request unit with the first memory cycle and the second request unit with the second memory cycle. The third memory cycle is given to the request part.
[0046]
In this example system, all reads are a single cache line (32 bytes). Therefore, two cycles are required for reading out the cache line at 200 MHz, and new reading is performed every 10 nanoseconds. In round robin arbitration between other request units, the read request from the main processor 110 is given the highest priority. Memory ownership changes and refreshes every 10 nanoseconds between read request parts, but the write queue is always written throughout. The write queue initiates a request when it is filled up to or beyond a certain level, or when a main processor read request matches an entry in the write buffer. These are subject to the following restrictions on the frequency of requests:
• Two main processor reads cannot be performed in succession.
• Two system reads cannot be performed in succession.
• Two rows are refreshed during a 10 nanosecond refresh cycle. One line every 5 nanoseconds.
The bandwidth control circuit described herein is not limited to use with any particular arbitration process. A read queue arbitration scheme example and a write queue arbitration scheme example are described below, but these are examples and not limitations. Further details of these exemplary arbitration methods are described in the provisional application number 60 / 226,894 and the corresponding application number 09 / 726,220, both of which are named “graphics processing system using a function-enhanced memory controller”. Has been.
[0047]
(Read queue arbitration example)
The main processor 110 has the highest priority except in the following cases.
When the main processor 110 is a master for previous access
The accumulator bit 8 (MSB) for the main processor read master is not equal to 1 and there is another request by another master where the accumulator bit 8 (MSB) is equal to 1.
When the write buffer is completely full and in the middle of a write cycle
-The previous main processor address matches the valid main processor write address in the processor interface local write buffer or the global write buffer that flushes the write buffer.
[0048]
The command processor 200 or texture unit 500 has the same priority as the other system masters (ie, audio DSP 156, peripheral (I / O) controller 162, video controller 164), and therefore, the system master is assigned under the following conditions. Arbitrate memory using a round-robin method.
When the audio DSP 156, peripheral (I / O) controller 162, or video controller 164 is the master for the previous access
-Command processor read or texture unit read accumulator bit 8 (MSB) is not equal to 1 and there is another request by another master whose corresponding accumulator bit 8 is equal to 1.
[0049]
The readout of the audio DSP 156 (or peripheral (I / O) controller 162 or video controller 164) has the same priority as the other graphics masters (command processor 200 and texture unit 500), and therefore graphics except under the following conditions: Memory arbitration is performed in a round robin manner.
The audio DSP 156 (or peripheral (I / O) controller 162 or video controller 164) is the master for previous access
[0050]
The global write buffer WQ0 has a lower priority than the main processor 110, graphics, or system master except in the following states.
When the global write buffer WQ0 is completely full and arbitration is performed using the round robin method
The main processor read address has the highest priority when it matches the write address in the global write buffer WQ0.
If bit 8 of the other high-priority master accumulator is not equal to 1
[0051]
Except for the following conditions, refresh has the lowest priority.
When the total refresh request reaches the threshold, its priority goes up to the level just below the main processor read.
If bit 8 of the other high-priority master accumulator is not equal to 1
[0052]
(Example of write queue arbitration)
The main processor 110, pixel engine 700, audio DSP 156, and peripheral (I / O) controller 162 are the four masters of the write queue. Writing by the main processor has the highest priority, and the other three masters are arbitrated in a round-robin manner except in the following states.
When there is another write master in which the accumulator bit 8 (MSB) of the main processor write is not equal to 1 and bit 8 (MSB) of the accumulator is equal to 1.
[0053]
Although the above description is about access to a memory device, the present invention is not limited to this, and the concepts described here include a bus (eg, a PCI bus), a processor (eg, a non-embedded processor). The present invention is sufficiently applicable even in a situation where a plurality of requesting units request access to a shared resource such as the above.
[0054]
(Other compatible implementation examples)
The system device 50 can be realized by a configuration other than the home video game console configuration described above. For example, graphics applications and other software written for the system 50 can be run on platforms having different configurations that emulate the system 50 or are otherwise compatible. Any platform that can emulate, simulate, and / or provide some or all of the hardware and software resources of the system 50 can successfully execute the software.
[0055]
For example, the emulator may provide a hardware and / or software configuration (platform) that is different from the hardware and / or software configuration (platform) of the system 50. The emulator system may include software and / or hardware components that emulate or simulate some or all of the hardware and / or software components of the system in which the application software is written. For example, the emulator system may include a general purpose digital computer such as a personal computer that executes a software emulator program that simulates the hardware and / or firmware of the system 50. The DSP processing of the audio system can be emulated on a personal computer.
[0056]
Some general-purpose digital computers (eg, IBM and Macintosh personal computers and compatibles) are equipped with a 3D graphics card that provides a 3D graphics pipeline that conforms to DirectX and other standard 3D graphics command APIs. . Alternatively, it may be equipped with a stereo sound card that allows high quality stereo sound based on a standard set of sound commands. Such a multimedia hardware capable personal computer running emulator software may have sufficient performance to approximate the graphics and sound performance of the system 50. The emulator software controls hardware resources on the personal computer platform to simulate the processing, 3D graphics, sound, peripherals, and other functions of the home video game console platform in which the game programmer has written the game software.
[0057]
FIG. 13 shows an example of comprehensive emulation processing using binary images executable by game software prepared in the host platform 1201, the emulator configuration 1303, and the storage medium 62. Host 1201 is a general purpose or special purpose digital computing device such as a personal computer, video game console or other platform with sufficient computing power. The emulator 1303 is software and / or hardware that is executed on the host platform 1201 and converts commands, data, and information from the storage medium 62 into a format that can be processed by the host 1201 in real time. For example, the emulator 1303 takes “source” binary image program instructions intended for execution by the system 50 from the storage medium 62 and converts these program instructions into a target format that the host 1201 can execute or process.
[0058]
For example, the software is written to be executed on a platform using a specific processor such as an IBM Power PC, and the host 1201 is a personal computer using a different processor (for example, Intel). In some cases, emulator 1303 retrieves one or more binary image program instructions from storage medium 62 and converts these program instructions into one or more equivalent Intel binary image program instructions. The emulator 1303 also retrieves and / or generates graphics commands and audio commands for processing by the graphics & audio processor 114 and generates these commands on hardware and / or software graphics and audio processing available on the host 1201. Convert to a format that can be processed by the resource. As an example, emulator 1303 may convert these commands into commands that can be processed by specific graphics and / or audio hardware of host 1201 (eg, using standard DirectX, OpenGL, and / or sound APIs). ).
[0059]
The emulator 1303 used to provide some or all of the features of the video game system may include a graphics user interface (GUI), which allows a variety of games to be run using the emulator. Selection of options and screen modes is simplified or automated. For example, such an emulator 1303 may be further expanded in function as compared to the original software host platform.
[0060]
FIG. 14 shows an emulation host system 1201 suitable for use with the emulator 1303. The system 1201 includes a processing unit 1203 and a system memory 1205. The system bus 1207 connects various system components including the system memory 1205 to the processing unit 1203. The system bus 1207 is one of several types of bus structures including a memory bus or memory controller, and is a peripheral bus and a local bus utilizing one of various bus architectures. The system memory 1207 includes read only memory (ROM) 1252 and random access memory (RAM) 1254. A basic input / output system (BIOS) 1256 containing basic routines useful for transferring information between internal elements of the personal computer system 1201, such as during startup, is stored in the ROM 1252. System 1201 further includes various drives and associated computer readable media. The hard disk drive 1209 reads / writes from (typically fixed) magnetic hard disk 1211. An additional (preferably optional) magnetic disk drive 1213 reads / writes to / from a removable “floppy” or other magnetic disk 1215. The optical disk drive 1217 reads from a removable optical disk 1219 such as a CD-ROM or other optical medium, and writes depending on the configuration. The hard disk drive 1209 and the optical disk drive 1217 are connected to the system bus 1207 by a hard disk drive interface 1221 and an optical drive interface 1225, respectively. The drive and associated computer readable media store computer readable instructions, data structures, program modules, game programs, and other data for the personal computer system 1201 in a nonvolatile manner. In other configurations, computer readable media that stores data and can be accessed by a computer (eg, magnetic cassette, flash memory card, digital video disk, Bernoulli cartridge, random access memory (RAM), read only memory (ROM), etc. ) Can also be used.
[0061]
Many program modules including the emulator 1303 are stored on the hard disk 1211, the removable magnetic disk 1215, the optical disk 1219, and / or the ROM 1252 and / or RAM 1254 of the system memory 1205. Such a program module may include a graphics and sound API, one or more application programs, other program modules, an operating system that provides program data and game data. A user inputs commands and information into the personal computer system 1201 through input devices such as a keyboard 1227, a pointing device 1229, a microphone, a joystick, a game controller, a satellite broadcasting antenna, and a scanner. For example, these input devices may be connected to the processing unit 1203 via a serial port interface 1231 connected to the system bus 1207, but of course other interfaces such as parallel ports, game port firewire buses or universal serial buses ( USB). A display device such as a monitor 1233 is also connected to the system bus 1207 via an interface such as a video adapter 1235.
[0062]
The system 1201 also includes a modem 1154 and other network interface means to establish communication via a network 1152 such as the Internet. Whether inside or outside, the modem 1154 is connected to the system bus 123 via the serial port interface 1231. A network interface 1156 may also be provided, which allows the system 1201 to communicate with a remote computing device 1150 (such as another system 1201) via the local area network 1158 (this communication may be a wide area network 1152 or dial-up). Or other communication means, etc.) System 1201 typically includes other peripheral output devices, such as printers and other standard peripheral devices.
[0063]
For example, the video adapter 1235 is a 3D graphics that performs high-speed 3D graphics rendering in response to 3D graphics commands sent based on a standard 3D graphics application programmer interface such as Microsoft Direct 7.0 or other versions. It may include a pipeline chip. A set of stereo speakers 1237 is a sound generation interface, such as a traditional “sound card”, that provides hardware and built-in software support for generating high quality stereoscopic sound based on sound commands from the bus 1207. To the system bus 1207. With these hardware features, the system 1201 provides sufficient graphics and sound speed performance to play software stored on the storage medium 62.
[0064]
Although the present invention has been described in terms of what is presently determined to be the most practical and preferred embodiment, the present invention should not be limited to only the disclosed embodiment, but is described in reverse. Various changes and equivalents shall be applied within the scope of the appended claims.
[Brief description of the drawings]
FIG. 1 is an overall view of an example interactive computer graphics system.
FIG. 2 is a block diagram illustrating an example of a computer graphics system shown in FIG.
3 is a block diagram illustrating an example of the graphics and audio processor shown in FIG. 2. FIG.
4 is a block diagram illustrating an example of the 3D graphics processor shown in FIG. 3. FIG.
FIG. 5 is a diagram showing an example of a logical flow of the graphics & audio processor of FIG. 4;
6 is an overall view showing the relationship between the memory controller 152 and other system components. FIG.
7 is a diagram illustrating some of the operations involved in contention for access to the main memory 112. FIG.
FIG. 8 is a diagram showing in detail the interface of the memory controller 152;
9 is a diagram showing bandwidth control circuits 620-1 to 620-5 of the memory controller 152. FIG.
10 is a diagram showing an address path and a read data path for the memory controller 152, respectively. FIG.
11 is a diagram showing an address path and a read data path for the memory controller 152, respectively. FIG.
12 is a block diagram showing details of bandwidth control circuits 620-1 to 620-5. FIG.
FIG. 13 shows another compatible embodiment.
FIG. 14 illustrates another compatible embodiment.

Claims (21)

A controller that controls access to shared resources,
Arbitrator that arbitrates multiple access requests to a shared resource, and a bandwidth control circuit that can be programmed to control the rate at which access requests are arbitrated by the arbitrator by being programmed according to the amount of the access request A controller.   The controller of claim 1, wherein the bandwidth control circuit comprises a programmable register. The bandwidth control circuit further comprises an accumulator,
The contents of the programmable register is repeatedly added to the corresponding accumulators, the access request corresponding to the programmable register, wherein the value of the accumulator is arbitrated and reaches a predetermined value, according to claim 2 Controller. 4. The controller of claim 3 , wherein the contents of the programmable register are repeatedly added to the corresponding accumulators according to the clock signal. The controller of claim 2 , wherein the programmable register is programmable using an application programming interface.   The controller of claim 1, wherein the bandwidth control circuit has a default setting to arbitrate the corresponding access request. A 3D graphics system,
A graphics processing circuit for processing graphics commands for generating a 3D visual image for display;
Memory accessible to the graphics processing circuit,
Arbitrator for arbitrating multiple memory access requests from the graphics processing circuit, and the rate at which access requests are arbitrated by the arbitrator can be programmed to be controlled by programming according to the amount of access requests 3D graphics system with a flexible bandwidth control circuit. The 3D graphics system of claim 7 , wherein the bandwidth control circuit comprises a programmable register. The bandwidth control circuit further comprises an accumulator,
The contents of the programmable register is repeatedly added to the corresponding accumulators, the access request corresponding to the programmable register, wherein the value of the accumulator is arbitrated and reaches a predetermined value, according to claim 8 3D graphics system. 10. The 3D graphics system of claim 9 , wherein the contents of the programmable register are repeatedly added to the corresponding accumulators according to the clock signal. The 3D graphics system of claim 8 , wherein the programmable register is programmable using an application programming interface. The 3D graphics system of claim 7 , wherein the bandwidth control circuit has a default setting to arbitrate the corresponding access request. A video game system,
Main processor,
A graphics processing circuit for processing graphics commands for generating a 3D visual image for display;
An audio processing circuit for processing an audio command for generating audio content with a 3D visual image;
A memory accessible to the graphics processing circuit and the audio processing circuit;
Arbitrator for arbitrating a plurality of memory access requests from at least the main processor and the graphics processing circuit, and a rate at which the access request is arbitrated by the arbitrator is controlled by being programmed according to the amount of the access request. A video game system comprising a programmable bandwidth control circuit. The video game system of claim 13 , wherein the bandwidth control circuit comprises a programmable register. The bandwidth control circuit further comprises an accumulator,
The contents of the programmable register is repeatedly added to the corresponding accumulators, the access request corresponding to the programmable register, wherein the value of the accumulator is arbitrated and reaches a predetermined value, according to claim 14 Video game system. 16. The video game system of claim 15 , wherein the contents of the programmable register are repeatedly added to the corresponding accumulators according to the clock signal. The video game system of claim 14 , wherein the programmable register is programmable using an application programming interface. 14. The video game system of claim 13 , wherein the bandwidth control circuit has a default setting that arbitrates corresponding access requests. A method of controlling access to a shared resource,
A method of arbitrating a plurality of access requests to a shared resource and controlling a rate at which the access requests are arbitrated by being programmed according to the amount of the access request. A method for controlling access to memory in a 3D graphics system comprising:
Processing graphics commands to generate 3D visual images for display;
A method of arbitrating a plurality of memory access requests during the process, and controlling a rate at which the access requests are arbitrated by being programmed according to an amount of the access requests. An information processing program to be executed by a computer of an information processing apparatus that controls access to a shared resource,
The computer,
An access request arbitration unit that arbitrates a plurality of access requests to a shared resource, and a program that controls a rate at which an access request is arbitrated by the access request arbitration unit by being programmed according to the amount of the access request An information processing program that functions as a possible bandwidth control means.

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