JP4698894B2 - Method, apparatus and program for texture tiling in a graphics system - Google Patents

Description

【００６０】

【００６１】
上記の関数は、上述の間接テクスチャタイリング方法または疑似３次元テクスチャタイリング方法を特定するために用いることができる。なお、タイルの大きさと間隔とは個別に指定することが可能である。タイルの大きさよりも大きな間隔を用いる理由の例としては、ミップマッピングのための境界を持たせることがある。ミップマップスタックの高さによっては、タイルの外側にあるテクセルが、ミップマップ用のフィルタリング計算に含まれる場合がある。この関数により、所定の入力に基づいて適切に、マトリックスおよびスケール値が設定される。どのマトリックススロットを使用するかを指定しさえすればよい。ｂｉａｓＳｅｌやａｌｐｈａＳｅｌパラメータを用いるのは、疑似３次元ルックアップの場合のみである。これらは、通常の２次元タイリングの場合には、（それぞれ）ＧＸ＿ＩＴＢ＿ＮＯＮＥおよびＧＸ＿ＩＴＢＡ＿ＯＦＦに設定される。なお、テクスチャタイリングは、間接マップおよび通常（直接）マップに同一のテクスチャ座標を利用することができる。しかしながら、通常のテクスチャ座標の所望のスケール値は、タイル定義を含む通常マップの大きさと直接は関係していない。通常、テクスチャ座標のスケールの大きさは、ルックアップされるマップの大きさに設定され、テクスチャ座標が共用される場合には、通常マップの大きさが好ましい。テクスチャタイリングによって、異なるスケールが必要なので、以下の関数を用いることができる。
【００６２】

【００６３】
ＧＸＳｅｔＣｏｏｒｄＳｃａｌｅＭａｎｕａｌｌｙが呼び出されて、イネーブルがＧＸ＿Ｔｒｕｅに設定されると、関数が再び呼び出されるまで、所定のテクスチャ座標スケール値が固定される。関数が呼び出されてイネーブルがＧＸ＿Ｆａｌｓｅに設定されると、自動テクスチャ座標スケーリングが、当該テクスチャ座標に対して再び引き継ぐ。テクスチャタイリングでは、所望のテクスチャ座標スケールは、タイルの大きさと間接マップの大きさの積である。その後、ＧＸＳｅｔＩｎｄＴｅｘＣｏｏｒｄＳｃａｌｅを用いて、タイルの大きさを分割して、間接マップへのアクセスに使用する。
【００６４】
疑似３次元テクスチャルックアップに対応するために、本例では、ＧＸＳｅｔＴｅｖＩｎｄＴｉｌｅを２つの隣接するＴＥＶステージのために呼び出さなければならない。第１のステージは、通常の２次元タイリングの仕様と似ている。第２のステージでは、バイアス選択およびアルファ選択を指定する。バイアスを用いて、タイルスタック方向を選択する。次のタイルがＳ次元のオフセットである場合は、ＧＸ＿ＩＴＢ＿Ｓが用いられ、次のタイルがＴ次元のオフセットである場合は、ＧＸ＿ＩＴＢ＿Ｔが用いられる。その後、バンプアルファを選択して、第１のルックアップからのタイルおよび第２のルックアップからのタイルをブレンドする。なお、本例においては、疑似３次元テクスチャでは８ビットフォーマットを用いることはできない。代わりに、３、４、および５ビットフォーマットを用いることができる。このようなフォーマットは、−１２８の代わりに＋１のバイアス値を用いる。＋１バイアスを用いて、第２のステージの「次の」タイルを得る。
【００６５】
＜互換可能な他の実施例＞
上述のシステム構成要素５０のうちのあるものは、上述の家庭用ビデオゲームコンソール以外であっても実施できる。たとえば、システム５０のために書き込まれているグラフィックスアプリケーションなどのソフトウェアを、システム５０をエミュレートするかまたはそれと互換性のある他の構成を用いたプラットフォーム上で実行することができる。他のプラットフォームが、システム５０のハードウェアおよびソフトウェア資源の一部または全部をうまくエミュレート、模倣、および／または提供できるのであれば、当該他のプラットフォームは、ソフトウェアをうまく実行することができるであろう。
【００６６】
一例として、エミュレータは、システム５０のハードウェアおよび／またはソフトウェア構成（プラットフォーム）とは異なるハードウェアおよび／またはソフトウェア構成（プラットフォーム）を提供してもよい。エミュレータシステムは、アプリケーションソフトウェアを書き込む対象であるシステムのハードウェアおよび／またはソフトウェア構成要素の一部またはすべてをエミュレートするハードウェアおよび／またはソフトウェア構成要素を含んでいてもよい。たとえば、エミュレータシステムは、パーソナルコンピュータなどの汎用デジタルコンピュータを備えることができ、これによって、システム５０のハードウェアおよび／またはファームウェアを模倣するソフトウェアエミュレータプログラムが実行される。
【００６７】
汎用デジタルコンピュータの中には（たとえば、ＩＢＭまたはマッキントッシュ製パーソナルコンピュータおよびその互換機）、現在、ＤｉｒｅｃｔＸ３Ｄやその他の標準グラフィックスコマンドＡＰＩに対応したグラフィックスパイプラインを提供する３Ｄグラフィックスカードが搭載されているものもある。これらには、また、標準的なサウンドコマンドに基づいて高品質の立体音響を提供する立体音響サウンドカードも搭載されている場合もある。エミュレータソフトウェアを実行させるこのようなマルチメディアハードウェアを搭載したコンピュータは、システム５０のグラフィックス性能およびサウンド性能を近似するに充分な性能を有している場合がある。エミュレータソフトウェアは、パーソナルコンピュータプラットフォーム上のハードウェア資源を制御して、ゲームプログラマがゲームソフトウェアを書き込む対象である家庭用ビデオゲームゲームコンソールプラットフォームの処理性能、３Ｄグラフィックス性能、サウンド性能、周辺性能などを模倣する。
【００６８】
図４０は、エミュレーション処理全体の例を示しており、この処理は、ホストプラットフォーム１２０１と、エミュレータ構成要素１３０３と、記憶媒体６２上に与えられているバイナリ画像を実行可能なゲームソフトウェアとを用いる。ホスト１２０１は、汎用または専用デジタルコンピューティング装置であってもよく、たとえばパーソナルコンピュータやビデオゲームコンソールなど、充分な計算能力を備えたプラットフォームが挙げられる。エミュレータ１３０３は、ホストプラットフォーム１２０１上で実行されるソフトウェアおよび／またはハードウェアであってもよく、コマンドやデータなどの記憶媒体６２からの情報をリアルタイムで変換して、ホスト１２０１が処理可能な形式にすることができる。たとえば、エミュレータ１３０３は、システム５０が実行しようとする「ソース」バイナリ画像プログラム命令を記憶媒体６２から取り出して、実行可能な形式またはホスト１２０１によって処理可能な形式に当該プログラム命令を変換する。
【００６９】
一例として、ＩＢＭのＰｏｗｅｒＰＣなどの特定のプロセッサを用いたプラットフォーム上で実行するためにソフトウェアが書き込まれており、ホスト１２０１は、異なる（たとえば、インテルの）プロセッサを用いたパーソナルコンピュータである場合、エミュレータ１３０３は、バイナリ画像プログラム命令の１つまたはシーケンスを記憶媒体１３０５から取り出して、これらのプログラム命令を、インテルのバイナリ画像プログラム命令に相当するものに変換する。また、エミュレータ１３０３は、グラフィックス音声プロセッサ１１４によって処理されるグラフィックスコマンドや音声コマンドを取り出しおよび／または生成し、ハードウェアおよび／またはソフトウェアグラフィックスおよびホスト１２０１で利用可能な音声処理資源によって処理可能な形式に、これらコマンドを変換する。一例として、エミュレータ１３０３は、これらのコマンドを、ホスト１２０１の特定のグラフィックスおよび／またはサウンドハードウェアによって処理可能なコマンドに変換する（たとえば、ＤｉｒｅｃｔＸ、ＯｐｅｎＧＬおよび／またはサウンドＡＰＩを用いる）。
【００７０】
エミュレータ内の特定のグラフィックス対応ハードウェアが間接テクスチャ参照機能や図７から３９に示す機能を含まない場合には、エミュレータ設計者は以下のうちいずれかの選択を行う。
・間接テクスチャ参照コマンドを、グラフィックス対応ハードウェアが解釈できる他のグラフィックスＡＰＩコマンドに変換する。
・間接テクスチャ参照をソフトウェア内で実施する。これに応じて、プロセッサの処理速度によっては性能の低下を余儀なくされる可能性がある。または、
・間接テクスチャ参照をコマンドを「スタブ」（すなわち、無視する）して、間接テクスチャ参照を用いた効果を含まないレンダリング済み画像を提供する。
【００７１】
図３６および３９の論理図は、すべてソフトウェア、すべてハードウェア、およびハードウェアとソフトウェアとの組み合わせによって実施可能であるが、好ましい実施例においては、ほとんどの計算を（バンプ部５００ｂを用いて）ハードウェアで行い速度性能や他の利点を得るようにする。それにもかかわらず、他の実施形態においては（たとえば、非常に高速のプロセッサが利用可能な場合）、本記載のすべてのうちのいくらかの処理をソフトウェアで行って、同様なまたは同一の画像結果を得るようにしてもよい。
【００７２】
上述のビデオゲームシステムの機能の一部または全部を提供するために用いられるエミュレータ１３０３には、エミュレータを用いて実行される様々なオプションや画面モードの選択を簡略化または自動化するグラフィックユーザインターフェース（ＧＵＩ）が与えられてもよい。一例として、そのようなエミュレータ１３０３は、ソフトウェアが本来対象としていたホストプラットフォームに比較して、拡張された機能をさらに含んでいてもよい。
【００７３】
図４１は、エミュレータ１３０３と共に用いられるのに適したエミュレーションホストシステム１２０１を示す。システム１２０１は、処理部１２０３と、システムメモリ１２０５とを含む。システムバス１２０７は、システムメモリ１２０５から処理部１２０３までを含む様々なシステム構成要素を結合する。システム１２０７は、メモリバスまたはメモリコントローラ、周辺機器バス、ローカルバスなど、様々なバスアーキテクチャのいずれかを用いたものを含む、数種のバス構成のいずれであってもよい。システムメモリ１２０７は、読み出し専用メモリ（ＲＯＭ）１２５２と、ランダムアクセスメモリ（ＲＡＭ）１２５４とを含む。ベーシック入出力システム（ＢＩＯＳ）１２５６は、パーソナルコンピュータシステム１２０１内の要素間において情報を転送するのを助ける基本ルーチンを含んでおり、ＲＯＭ１２５２に記憶される。システム１２０１は、様々なドライブや、関連したコンピュータが読み取り可能な媒体をさらに含む。ハードディスクドライブ１２０９は、（典型的には固定された）磁気ハードディスク１２１１からの読み出しやそれに対する書き込みを行う。付加的な（選択可能な）磁気ディスクドライブ１２１３は、着脱可能な「フロッピー」などの磁気ディスク１２１５からの読み出しやそれに対する書き込みを行う。随意のディスクドライブ１２１７は、ＣＤＲＯＭなどの随意の媒体のような着脱可能な光ディスク１２１９からの読み出しや、構成によってはそれに対する書き込みも行う。ハードディスクドライブ１２０９および光ディスクドライブ１２１７は、それぞれ、ハードディスクドライブインターフェース１２２１および光ドライブインターフェース１２２５によって、システムバス１２０７に接続している。ドライブやそれに関連するコンピュータが読み出し可能な媒体によって、コンピュータが読み出し可能な命令、データ構造、プログラムモジュール、ゲームプログラムなどのパーソナルコンピュータシステム１２０１のためのデータが不揮発的に記憶される。他の構成においては、コンピュータが読み出し可能な他の種類の媒体が用いられていてもよく、コンピュータによってアクセス可能なデータを記憶できる媒体（たとえば、磁気カセット、フラッシュメモリカード、デジタルビデオディスク、ベルヌーイカートリッジ、ランダムアクセスメモリ（ＲＡＭ）、読み出し専用メモリ（ＲＯＭ）など）であってもよい。
【００７４】
エミュレータ１３０３を含む多くのプログラムモジュールは、ハードディスク１２１１、着脱可能な磁気ディスク１２１５、光学ディスク１２１９、および／またはシステムメモリ１２０５のＲＯＭ１２５２および／またはＲＡＭ１２５４に記憶されてもよい。そのようなプログラムモジュールは、グラフィックスやサウンドＡＰＩを提供するオペレーティングシステム、１つ以上のアプリケーションプログラム、他のプログラムモジュール、プログラムデータ、ゲームデータを含んでもよい。ユーザは、コマンドや情報を、キーボード１２２７、ポインティングデバイス１２２９、マイク、ジョイスティック、ゲームコントローラ、衛星アンテナ、スキャナなどの入力装置を通じて、パーソナルコンピュータシステム１２０１に対して入力する。このような入力装置は、システムバス１２０７に結合されたシリアルポートインターフェース１２３１を介して処理部１２０３に接続されることが可能であるが、パラレルポートや、ゲームポートファイアワイヤーバス、またはユニバーサルシリアルバス（ＵＳＢ）などの他のインターフェースによって接続されてもよい。モニタ１２３３などの表示装置も、ビデオアダプタ１２３５などのインターフェースを介して、システムバス１２０７に接続される。
【００７５】
また、システム１２０１は、インターネットのようなネットワーク１１５２上での通信を確立するための、モデム１１５４などのネットワークインターフェース手段を含んでもよい。モデム１１５４は、内蔵であっても外付けであってもよく、シリアルポートインターフェース１２３１を介してシステムバス１２３に接続される。また、ローカルエリアネットワーク１１５８を介して（または、ワイドエリアネットワーク１１５２、ダイアルアップなどの他の通信路、または他の通信手段を介してもよい）、システム１２０１が遠隔コンピューティング装置１１５０（たとえば、他のシステム１２０１）と通信できるように、ネットワークインターフェース１１５６が与えられてもよい。システム１２０１は、典型的には、プリンタなどの標準周辺機器のような、他の周辺出力装置を含む。
【００７６】
一例において、ビデオアダプタ１２３５は、Ｍｉｃｒｏｓｏｆｔ製ＤｉｒｅｃｔＸ７．０などのバージョンのような標準３Ｄグラフィックスアプリケーションプログラマインターフェースに基づいて出される３Ｄグラフィックスコマンドに応答して、高速３Ｄグラフィックスレンダリングを提供するグラフィックスパイプラインチップセットを含んでいてもよい。立体音響スピーカセット１２３７も、システムバス１２０７に対して、従来の「サウンドカード」のような音声生成インターフェースを介して接続されている。そのようなインターフェースは、バス１２０７から与えられたサウンドコマンドに基づいて高品質な立体音響を生成するための支援をハードウェアや組み込みソフトウェアに対して行う。このようなハードウェアの機能によって、システム１２０１は、記憶媒体６２に記憶されたソフトウェアを実行するのに充分なグラフィックスおよび音響の速度性能を提供することができる。
【００７７】
本発明は、現時点において最も現実的で最適な実施例と思われるものに関連して説明してきたが、本発明は、開示された実施例に限定されるものではなく、添付の請求項の範囲に含まれる様々な変形例や相当する仕組みを含むことを意図していると解釈されるべきである。
【図面の簡単な説明】
【図１】対話式コンピュータグラフィックスシステムの一例の概略図である。
【図２】図１のコンピュータグラフィックスシステムの例のブロック図である。
【図３】図２に示すグラフィックス＆音声プロセッサの例のブロック図である。
【図４】図３に示す３Ｄグラフィックスプロセッサの例のブロック図である。
【図５】図４のグラフィックス＆音声プロセッサの論理フロー図の例である。
【図６】本発明に係る間接テクスチャ処理の論理概要を示すブロック図である。
【図７】通常（非間接）テクスチャルックアップの単純な基本例を示す機能ブロック図である。
【図８】間接テクスチャルックアップの単純な基本例を示す機能ブロック図である。
【図９】本発明に係る間接テクスチャ処理を実施するための物理的な構成例の概要を示すブロック図である。
【図１０】テクスチャアドレス（座標／データ）プロセッサ処理の論理概要を示すブロック図である。
【図１１】テクスチャリングパイプラインの実施例において、インターリーブされた直接および間接テクスチャ処理の結果である、ピクセル直接座標データおよびピクセル間接テクスチャデータの相関的な経過を示すブロック図群である。
【図１２】テクスチャリングパイプラインの実施例において、インターリーブされた直接および間接テクスチャ処理の結果である、ピクセル直接座標データおよびピクセル間接テクスチャデータの相関的な経過を示すブロック図群である。
【図１３】テクスチャリングパイプラインの実施例において、インターリーブされた直接および間接テクスチャ処理の結果である、ピクセル直接座標データおよびピクセル間接テクスチャデータの相関的な経過を示すブロック図群である。
【図１４】テクスチャリングパイプラインの実施例において、インターリーブされた直接および間接テクスチャ処理の結果である、ピクセル直接座標データおよびピクセル間接テクスチャデータの相関的な経過を示すブロック図群である。
【図１５】テクスチャリングパイプラインの実施例において、インターリーブされた直接および間接テクスチャ処理の結果である、ピクセル直接座標データおよびピクセル間接テクスチャデータの相関的な経過を示すブロック図群である。
【図１６】テクスチャリングパイプラインの実施例において、インターリーブされた直接および間接テクスチャ処理の結果である、ピクセル直接座標データおよびピクセル間接テクスチャデータの相関的な経過を示すブロック図群である。
【図１７】テクスチャリングパイプラインの実施例において、インターリーブされた直接および間接テクスチャ処理の結果である、ピクセル直接座標データおよびピクセル間接テクスチャデータの相関的な経過を示すブロック図群である。
【図１８】テクスチャリングパイプラインの実施例において、インターリーブされた直接および間接テクスチャ処理の結果である、ピクセル直接座標データおよびピクセル間接テクスチャデータの相関的な経過を示すブロック図群である。
【図１９】テクスチャリングパイプラインの実施例において、インターリーブされた直接および間接テクスチャ処理の結果である、ピクセル直接座標データおよびピクセル間接テクスチャデータの相関的な経過を示すブロック図群である。
【図２０】テクスチャリングパイプラインの実施例において、インターリーブされた直接および間接テクスチャ処理の結果である、ピクセル直接座標データおよびピクセル間接テクスチャデータの相関的な経過を示すブロック図群である。
【図２１】テクスチャリングパイプラインの実施例において、インターリーブされた直接および間接テクスチャ処理の結果である、ピクセル直接座標データおよびピクセル間接テクスチャデータの相関的な経過を示すブロック図群である。
【図２２】本発明に係る間接テクスチャ処理を実施するためのステップ例を示す、フローチャートである。
【図２３】本発明に係る、通常（非間接）テクスチャ処理の例を示す機能処理図である。
【図２４】本発明に係る、通常（非間接）および間接テクスチャ処理両方の例を示す、機能処理図である。
【図２５】図５に示すテクスチャ座標／バンプ処理部の詳細例を示す、ブロック図である。
【図２６】図２５に示す間接テクスチャルックアップデータ／座標処理ロジック（ｐｒｏｃ）の詳細例を示すブロック図である。
【図２７】図２６の処理ロジック回路（ｐｒｏｃ）によって用いられるテクスチャオフセットマトリックスの例を示す。
【図２８】図２６の処理ロジック回路（ｐｒｏｃ）によって用いられるテクスチャオフセットマトリックスの例を示す。
【図２９】図２６の処理回路内の処理を制御するための制御ロジックレジスタのデータフィールドフォーマット例を示すブロック図である。
【図３０】本発明の好ましい実施例に係る、第１のタイリング方法の一般的な機能ブロック図である。
【図３１】本発明の好ましい実施例に係る、第２のタイリング方法の一般的な機能ブロック図である。
【図３２】図３０の第１のタイリング方法のより詳細な機能ブロック図である。
【図３３】本発明の第１のタイリング方法の３つの例を示す。
【図３４】本発明の第１のタイリング方法の３つの例を示す。
【図３５】本発明の第１のタイリング方法の３つの例を示す。
【図３６】本発明の第１のタイリング方法の例図である。
【図３７】図２５の第２のタイリング方法のフローチャートである。
【図３８】本発明の第２のタイリング方法の例である。
【図３９】本発明の第２のタイリング方法の論理ブロック図の例である。
【図４０】他の代替可能な実施例を示す。
【図４１】他の代替可能な実施例を示す。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to computer graphics, and more particularly to interactive graphics systems such as home video game platforms. Even more specifically, an improved texture tiling method and apparatus that uses an indirect texture index map to reference a texture tile in a tile definition map and map the texture tile to a rendered primitive. About. The present invention further allows composite (blended) texture tiles to be created from the tile definition map, and the texture tiles can be mapped to primitives in such a way that texture patterns do not appear repeatedly.
[0002]
[Prior art]
Many of us have seen images of imaginary creatures such as dinosaurs, aliens, and animated toys that are very realistic. Such animation is made possible by computer graphics. Using such techniques, computer graphics producers can specify how each object looks and what appearance changes over time. The computer models the object and displays it on a display such as a television or a computer screen. Coloring and shape of each part of the display image is performed properly based on the position and orientation of each object in the scene, the illumination direction for each object, the texture of the surface of each object, and various other factors The computer takes care of many of the tasks that are necessary.
[0003]
Due to the complexity of computer graphics generation, until just a few years ago, the use of computer-generated 3D graphics was almost limited to expensive and specialized flight simulators, high-end graphics workstations, and supercomputers. It was. Although people see images generated by computer systems in movies and high-cost television advertising, they have not been able to touch the computer that generates the graphics. This situation has changed due to the emergence of relatively inexpensive 3D graphics platforms such as Nintendo 64 (registered trademark) and various 3D graphics cards that can be used in personal computers. Now, at home and at work, it is possible to interact with powerful 3D animations and simulations on a relatively inexpensive computer graphics system.
[0004]
The problem once faced by graphics system designers is how to create realistic surface details for rendered objects without using polygons or other geometric primitives. there were. Simulating surface details is possible, for example, by performing shading with inter-vertex interpolation on a myriad of small triangles, but as the desired details become more sophisticated and more complex, Clear modeling with primitives such as triangles increases the burden on the graphics system and is not very realistic. E. Developed by Catmul, F. Bryn and M.C. E. Another technique improved by Newwell is to “map” images to surfaces by digitization or synthesis (“Subdivision Algorithms for Curved Computer Displays”, E. Catmul, PhD thesis, Report UTEC-CSc-74-133, School of Computer Science, University of Utah, Salt Lake City, Utah, December 1994, and “Textures and Reflections of Computer Generated Images”, J. F. Blin and M. E. New Well, CACM, 19 (10), October 1976, pages 452-457). This technique is known as texture mapping (or pattern mapping) and the image is called a texture map (or simply referred to as texture). Alternatively, the texture map may be defined by processing rather than images.
[0005]
Typically, a texture map is defined in a two-dimensional rectangular coordinate space and parameterized using orthogonal texture coordinate pairs, such as (u, v) or (s, t). Individual components within a texture map are often referred to as texels. At each rendered pixel, the selected texel is used to replace or scale one or more key characteristics of the rendered object surface. This process is often referred to as texture mapping or “texturing”.
[0006]
Currently, most 3D graphics rendering systems include a texturing subsystem. The system is for obtaining a texture from memory and mapping the texture to the rendered object surface. The problem facing graphics system designers is how to perform more sophisticated texture related effects such as “texture tiling” in an efficient and convenient way. In texture tiling, texture tile style textures are typically mapped on a tile-by-tile basis to a rendered object surface, such as a two-dimensional surface. The texture tile is defined by the tile shape portion of the texture stored in the texture memory. An array or matrix of different tiles can also be defined in the texture memory. The size and shape of the tile can be chosen to facilitate mapping the tile to the particular surface rendered. Tile sizes vary and may be defined as multiple tiles are required to cover the rendered surface. Once defined, texture tiles are placed at specific locations on the rendered surface to create a textured surface.
[0007]
This tiling effect has been achieved in the past, for example by drawing polygons for each desired tile. However, this method can be expensive in terms of processing overhead and memory usage. Furthermore, a problem arising from prior art tiling techniques is that the tiled surface may have a repeating pattern as seen by the viewer. The reason for the repeated pattern is that the number of different texture tiles available to the programmer when tiling the surface is usually limited. Thus, the same texture tile is used over and over to completely cover the entire large surface such as walls, floors, and ground cover plants. The repeated use of such identical tiles can impair the realism of the rendered scene. This is because, in many cases, the human eye recognizes the repeated texture pattern generated by the tiling process. Another problem facing graphics system designers is how to use indirect texture processing to perform texture tiling. This allows and is hopeful for further improvements despite significant past research related to texture tiling.
[0008]
The present invention solves this problem and provides techniques and mechanisms that can be used to efficiently implement texture tiling in a graphics system. The present invention allows the creation of a more realistic textured surface that reduces the viewer viewing the displayed textured surface from noticing repetitive patterns in the texture. , You can make it disappear at all. Further, according to the present invention, a pseudo three-dimensional texture can be created by blending between texture tiles. Furthermore, according to the present invention, texture tiling can be achieved by performing indirect texture processing in an efficient and effective manner.
[0009]
According to one aspect provided by the present invention, a texture tiling method comprising:
-Generate texture coordinates,
・ Modify the texture coordinates using the indirect tile index map,
Use the modified texture coordinates to select a texture tile from the tile definition map,
A method comprising displaying selected texture tiles;
[0010]
According to another aspect of the present invention, there is provided a pseudo three-dimensional tiling method,
Define a set of texture coordinates directly,
Define a set of indirect texture coordinates,
・ Indirect texture coordinates are used to obtain offset values,
Combining the offset value with at least one direct texture coordinate to generate a first modified texture coordinate;
Obtaining a first texture tile from the tile definition map using a first modified set of texture coordinates;
・ Bias the offset value,
-Correct texture coordinates directly using biased offset values,
Combining the modified offset value with at least one direct texture coordinate to generate a second set of modified texture coordinates;
Using the second modified set of texture coordinates to obtain a second texture tile from the tile definition map;
A method comprising blending a first texture tile and a second texture tile to produce a composite texture tile.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 shows an example of an interactive 3D computer graphics system 50. The system 50 can be used to play interactive 3D video games with intriguing stereophony. It can also be applied to various other uses.
[0012]
In this example, the system 50 can interactively process digital representations and 3D world models in real time. The system 50 can display all or part of the world from any viewpoint. For example, the system 50 can interactively change the viewpoint in response to real-time input from input devices such as handheld controllers 52a and 52b. Thereby, the game player can see the world viewed from inside or outside the world. The system 50 can be used for applications that do not require real-time 3D interactive display (eg, 2D display generation and / or non-interactive display), but the ability to display high quality 3D images very quickly is It can be used to generate visual dialogues such as high realistic gameplay.
[0013]
In order to play an application such as a video game using the system 50, the user first connects the main unit 54 to a display device such as the user's color television 56 using the cable 58. The main unit 54 generates a video signal and an audio signal for controlling the color television 56. The video signal controls an image displayed on the television screen 59, and the audio signal is reproduced as sound through the stereo speakers 61L and 61R of the television.
[0014]
Further, the user needs to connect the main unit 54 to a power source. This power source may be a conventional AC adapter (not shown) that plugs into an electrical outlet on the wall of the home, and a lower DC voltage signal suitable for powering the home current to the main unit 54. Convert to As another embodiment, a battery can be used.
[0015]
The user may control the main unit 54 using the hand controllers 52a and 52b. For example, the operation unit 60 can be used to specify the direction (up or down, left or right, near or far) in which the character displayed on the television 56 should move within the three-dimensional world. The operation unit 60 also provides input for other uses (for example, menu selection, pointer / cursor control, etc.). The controller 52 can take a variety of forms. In the present example, each illustrated controller 52 includes an operation unit 60 such as a joystick, a push button, and / or a direction switch. The connection of the controller 52 to the main unit 54 may be a cable or may be wireless via electromagnetic waves (for example, radio waves or infrared waves).
[0016]
In order to play an application such as a game, the user selects an appropriate storage medium 62 storing the application such as the video game that he / she wants to play, and inserts the storage medium into the slot 64 in the main unit 54. To do. The storage medium 62 may be, for example, a specifically encoded and / or encrypted optical and / or magnetic disk. The user may operate the power switch 66 to turn on the main unit 54 and start execution of an application such as a video game based on software stored in the storage medium 62. The user may operate the controller 52 to give input to the main unit 54. For example, when the operation unit 60 is operated, an application such as a game may be started. When the other operation unit 60 is moved, the moving character can be moved in a different direction, or the viewpoint of the user in the 3D world can be changed. Based on the specific software stored in the storage medium 62, the various controllers 60 on the controller 52 can perform different functions at different times.
[0017]
<Example of electronic circuit of the entire system>
FIG. 2 shows a block diagram of example components of system 50. The main components include:
A main processor (CPU) 110,
Main memory 112, and
・ Graphics & Audio Processor 114
[0018]
In this example, main processor 110 (eg, enhanced IBM Power PC 750) receives input from handheld controller 108 (and / or other input devices) via graphics & audio processor 114. The main processor 110 interactively responds to user input and executes programs such as video games supplied from the external storage medium 62 via a mass storage access device 106 such as an optical disk drive. As an example, in the case of video game play, the main processor 110 can perform collision detection and moving image processing in addition to various interactive control functions.
[0019]
In this example, the main processor 110 generates 3D graphics commands and audio commands and sends them to the graphics and audio processor 114. The graphics & audio processor 114 processes these commands to generate an intriguing visual image on the display 59, or intriguing stereophonic sound to an appropriate sound generator such as stereo speakers 61R and 61L. Or generate.
[0020]
The video encoder 120 included in the system 50 of the present example receives an image signal from the graphics and audio processor 114 and displays the image signal on a standard display device such as a computer monitor or a home color television 56. To analog and / or digital video signals suitable for The audio codec (compressor / decompressor) 122 included in the system 50 compresses and expands the digitized audio signal, and converts it into a digital or analog audio signal format as necessary. Also good. The audio codec 122 can receive the audio input via the buffer 124 and provide it to the graphics and audio processor 114 for processing (eg, mixing with other audio signals generated by the processor and / or). Received via streaming audio output of mass storage access device 106). The graphics and audio processor 114 of this example can store audio related information in the audio memory 126 that is available for audio tasks. The graphics & audio processor 114 provides the processed audio output signal to the audio codec 112 for decompression or analog signal (eg, via buffer amplifiers 128L and 128R) so that it can be played back by the speakers 61L and 61R. Conversion is performed.
[0021]
Graphics and audio processor 114 can communicate with various additional devices within system 50. For example, the parallel digital bus 130 may be used for communication with the mass storage access device 106 and / or other components. The serial peripheral device bus 132 may be used for communication with devices such as various peripheral devices. Examples of such devices include the following.
A programmable read-only memory and / or real-time clock 134,
A network interface such as modem 136 (such as connecting system 50 to a telecommunications network 138 capable of downloading and uploading program instructions and / or data, such as a digital network such as the Internet; May be)
A flash memory 140;
[0022]
Another external serial bus 142 may be used for communication with devices such as additional expansion memory 144 (eg, a memory card). Connectors may be used to connect buses 130, 132, and 142 to various devices.
[0023]
<Example of graphics and audio processor>
FIG. 3 is a block diagram of an example of the graphics and audio processor 114. As an example, the graphics and audio processor 114 may be a single chip ASIC (application specific IC). In this example, the graphics and audio processor 114 includes:
Processor interface 150,
Memory interface / controller 152,
3D graphics processor 154,
An audio digital signal processor (DSP) 156,
-Voice memory interface 158
・ Audio interface & mixer 160
The peripheral device controller 162, and
A display controller 164;
[0024]
The 3D graphics processor 154 performs graphics processing tasks. The audio digital signal processor 156 performs audio processing tasks. The display controller 164 accesses the image information from the main memory 112, gives it to the video encoder 120, and displays it on the display device 56. Audio interface & mixer 160 interfaces with audio codec 122 and also receives audio from another source (eg, streaming audio from mass storage access device 106, output of audio DSP 156, and audio codec 122. It is also possible to mix (external audio input). The processor interface 150 provides a data and control interface between the main processor 110 and the graphics and audio processor 114.
[0025]
Memory interface 152 provides an interface for data and control between graphics and audio processor 114 and memory 112. In this example, the main processor 110 accesses the main memory 112 via a processor interface 150 and a memory interface 152 that are part of the graphics and audio processor 114. Peripheral controller 162 provides an interface for data and control between graphics and audio processor 114 and the various peripherals described above. The audio memory interface 158 provides an interface with the audio memory 126.
[0026]
<Example of graphics pipeline>
FIG. 4 is a more detailed diagram of an example 3D graphics processor 154. The 3D graphics processor 154 includes a command processor 200 and a 3D graphics pipeline 180, among others. The main processor 110 transmits a data stream (for example, a graphics command stream or a data list) to the command processor 200. The main processor 110 has a two-level cache 115 to minimize memory latency, and also has a write gathering buffer 111 for an uncached data stream for the graphics and audio processor 114. The write gathering buffer 111 collects partial cache lines to form a complete cache line, and sends this data to the graphics & audio processor 114 one cache line at a time so that the bus can be used to the maximum.
[0027]
The command processor 200 receives a display command from the main processor 110, analyzes it, and acquires additional data necessary for processing from the common memory 112. Command processor 200 provides a stream of vertex commands to graphics pipeline 180 for 2D and / or 3D processing and rendering. The graphics pipeline 180 generates an image based on these commands. The generated image information may be transferred to the main memory 112 and made accessible by the display controller / video interface unit 164, thereby displaying the frame buffer output of the pipeline 180 on the display 56.
[0028]
FIG. 5 is a logic flow diagram of the graphics processor 154. The main processor 110 may store the graphics command stream 210, the display list 212, and the vertex array 214 in the main memory 112, and passes a pointer to the command processor 200 via the bus interface 150. The main processor 110 stores graphics commands in one or more graphics first in first out (FIFO) buffers 210 allocated in the main memory 110. The command processor 200 retrieves:
A command stream from the main memory 112 via an on-chip FIFO memory buffer 216 that receives and buffers graphics commands for synchronization / flow control and load balancing;
The display list 212 from the main memory 112 via the on-chip call FIFO memory buffer 218, and
Vertex attributes from the command stream and / or from the vertex array 214 in the main memory 112 via the vertex cache 220.
[0029]
The command processor 200 performs a command processing operation 200a to convert the attribute type to a floating-point format, and passes the resulting complete vertex polygon data to the graphics pipeline 180 for rendering / rasterization. Programmable memory arbitration circuit 130 (see FIG. 4) arbitrates access to main memory 112 that is common among graphics pipeline 180, command processor 200, and display controller / video interface unit 164.
[0030]
As shown in FIG. 4, graphics pipeline 180 may include:
-Conversion unit 1300,
-Setup / rasterizer 400,
-Texture part 500,
-Texture environment unit 600, and
Pixel engine unit 700.
[0031]
The conversion unit 300 performs various processes 300a such as 2D and 3D conversion (see FIG. 5). The conversion unit 300 may include one or more matrix memories 300b that store a matrix used for the conversion process 300a. The conversion unit 300 converts the shape input for each vertex from the object space to the screen space, converts the input texture coordinates, and calculates the projected texture coordinates (300c). The conversion unit 300 may perform polygon clipping / culling (300d). Further, in one embodiment, the lighting calculation for the eight independent lights is performed for each vertex by the lighting processing 300e performed by the conversion unit 300b. The conversion unit 300 can also perform texture coordinate generation (300c) for producing an embossed bump mapping effect and polygon clipping / culling processing (300d).
[0032]
The setup / rasterizer 400 includes a setup unit. The setup unit receives vertex data from the conversion unit 300 and transmits triangle setup information to one or more rasterizers (400b) to perform edge rasterization, texture coordinate rasterization, and color rasterization.
[0033]
A texture unit 500 (which may include an on-chip texture memory (TMEM) 502), performs various tasks related to texturing. The tasks include, for example, the following.
Extract texture 504 from main memory 112,
Texture processing (500a), including, for example, multi-texture processing, post-cache texture extension, texture filtering, embossing, shadows and lighting with projected textures, and BLIT with alpha transparency and depth,
Bump map processing (500b) for calculating a texture coordinate conversion amount for bump mapping, pseudo texture, texture tiling effect, and
Indirect texture processing (500c).
[0034]
6 to 29 show examples of texture processing for performing normal (non-indirect) and indirect texture lookup processing. For a graphics pipeline circuit and a procedure for performing normal and indirect texture lookup processing, see commonly assigned co-pending patent application No. 60 / 226,891, named “Method for Processing Direct and Indirect Textures in Graphics Systems. And device "(attorney docket number 723-849). The entire contents of this application are incorporated by reference.
[0035]
The texture unit 500 outputs the transmitted texture value to the texture environment unit 600 to perform texture environment processing (600a). The texture environment unit 600 blends the polygon and the texture color / alpha / depth and also performs texture fog processing (600b) to achieve a fog effect based on the inverse range. Texture environment 600 provides multiple stages to provide a variety of other intriguing environment-related, for example, based on color / alpha modulation, embossing, detail texturing, texture swapping, clamping, and depth blending. The function can be performed. For further details regarding the texture environment 600, see commonly assigned copending patent application No. 60 / 226,888, named “Recirculating Shade Tree Blender for Graphics Systems” (Attorney Docket No. 723-851). . The contents of this application are incorporated herein.
[0036]
The pixel engine 700 performs depth (z) comparison (700a) and pixel blending (700b). In this example, the pixel engine 700 stores data in an embedded (on-chip) frame buffer memory 702. Graphics pipeline 180 may include one or more embedded DRAM memories 702 and stores the contents of the frame buffer and / or texture information locally. Depending on the currently available rendering mode, the Z comparison 700a ′ can be done early in the graphics pipeline (eg, if no alpha blending is needed, the z comparison can be done early). The pixel engine 700 includes a copy process 700c. This is to periodically write the contents of the on-chip frame buffer to the main memory and allow the display / video interface unit 164 to access. Using this copy process 700c, the contents from the embedded frame buffer 702 to the texture can be copied to the main memory 112, and a dynamic texture synthesis effect can be obtained. Anti-aliasing and other filtering can be done during the copy-out process. The frame buffer output of the graphics pipeline 180 (which is finally stored in the main memory 112) is read by the display / video interface unit 164 for each frame. The display controller / video interface 164 gives digital RGB pixel values and displays them on the display 102.
[0037]
<Outline of texture tiling procedure example>
The present invention provides two different tiling methods, both preferably using indirect texture tile maps. The first method provides an indirect texture tiling method. In the second method, unique texture tiles can be created by blending between multiple tiles to achieve, for example, a pseudo 3D texture effect.
[0038]
FIG. 30 shows the procedure of the indirect texture tiling method of the present invention. According to this first example procedure, texture coordinates are generated from the surface parameters of the rendered object (block 1400). The tile index map is used to obtain a tile selection offset that is used to modify the texture coordinates (block 1402). The modified texture coordinates are then used to select a texture tile from the texture definition map (block 1404). The texture tile may include any type of texture that one desires to use in the tiling process, and may be any suitable pattern or large pattern portion, such as brick, glass, for example. The resulting tile textured image is then displayed (block 1406).
[0039]
FIG. 31 shows a procedure example of the texture blending or pseudo three-dimensional texture method. According to this second example procedure, texture coordinates are also generated from the surface parameters (block 1410). Thereafter, the texture coordinates are used to obtain at least one texture selection offset that is used to modify the texture coordinates (block 1412). Thereafter, a plurality of texture tiles are selected from the tile definition map using the modified texture coordinates (block 1414). The tiles are then blended to form a composite tile texture (block 1416). The resulting composite tile texturing image is then displayed (block 1418).
[0040]
In the following, the above-described both tiling methods of the present invention will be described in more detail separately. Both tiling methods described individually are preferably implemented by using the indirect texture processing system described in the above-mentioned co-pending application. However, according to the present invention, it is also possible to use a suitable processing system incorporating, for example, recirculation, multiple parallel channels, or other processing circuitry.
[0041]
<Indirect texture tiling example (first tiling method)>
FIG. 32 is an example of a more detailed block diagram of the indirect texture tiling method as shown in FIG. According to this method, an indirect tile index map and a tile definition map are defined (blocks 1500 and 1501). The tile definition map holds basic definitions of various tiles. The indirect tile index map identifies a specific position of a specific tile on the surface of the textured object. In order to map tiles onto the object in this way, an indirect texture coordinate pair (S0, T0) is generated (block 1504). In this example, the indirect texture coordinates are based on the scale of the textured surface, not the index map. Thereby, there is an advantage that it is possible to use the texture coordinates in which the direct texture coordinates and the indirect texture coordinates are the same. Thus, the indirect texture coordinates are appropriately scaled to an index map, for example, by dividing the coordinates by each dimension of the tile used (block 1506). The scaled texture coordinates are then used to perform a lookup process in the texture index map to obtain an appropriate tile selection offset of the current texture coordinates (ΔS, ΔT) (block 1508). The tile selection offset is then rescaled to the target texture scale. This is done, for example, by multiplying each dimension of the tile used by an offset (block 1510).
[0042]
A set of direct texture coordinates (S1, T1) is also defined (block 1512). As described above, in this embodiment, the indirect and direct texture coordinates are actually the same. A wrapping process is performed on the direct texture coordinates (block 1514). In this example, the wrapping process is a wrap modulo n, where n is the dimension of the tile used.
[0043]
Having obtained the appropriately scaled tile offset (ΔS, ΔT) and the wrapped texture coordinates (S1, T1), they are combined (block 1516) to produce the modified texture coordinates (S ′, T ′). Arise. The modified texture coordinates (S ′, T ′) are then used for lookup processing in the tile definition map (block 1518). This is done for the purpose of obtaining the desired texture tile for the current texture coordinate. The selected texture tile is then output for display (or for use in further texture processing operations) (block 1520).
[0044]
FIG. 33 shows a first example of the indirect tiling method of the present invention. As shown in FIG. 33, the texture tile index map 1600 identifies a specific tile in the tile definition map 1602 for each tile position on the texture 1604 after processing. In this example, a two-dimensional (2 × 2) tile definition map 1602 is used. Thus, the tile definition map includes four tiles, and in this example, each tile constitutes a different complementary part of the more widely assumed texture pattern. In this example, the size of the processed pattern 1604 is 512 × 512 texels. The indirect tile index map 1600 is a 4 × 4 matrix, and each matrix component identifies one of the four tiles in the tile definition map 1602. The size of each tile in the tile definition map is 128 × 128 texels. Thus, by mapping tiles using each of the 16 indexes in the index map 1600, the processed image 1604 has 16 tiles (512 in a desired configuration as determined by the tile index map). × 512 texels). As can be seen from FIG. 33, the tile pattern 1604 after processing in this example includes a pattern composed of four squares composed of 16 texture tiles.
[0045]
As described above, certain scaling, wrapping, and / or additional processing is performed on the direct and indirect coordinates, as indicated by the bump section (OP) block 1606 of FIG. In this example, the indirect texture is first reduced by dividing the indirect texture coordinates by 128 (the dimension of the tile). This is done to obtain a specific texture coordinate offset, corresponding to a 4 × 4 index matrix 1600. The offset is then expanded by multiplying by 128 (tile dimension). The enlarged offset is then combined with the wrapping result for the texture coordinates. This is done to obtain the modified texture coordinates and use it to obtain the texture from the tile definition map 1602.
[0046]
FIG. 34 shows a second example of the indirect tiling method of the present invention. Reference numerals correspond to similar parts described above. In this example, the tile definition map 1602 is not a two-dimensional map used in the first example of FIG. 33 but a one-dimensional map. As a result, the indirect texture map 1600 uses only a single offset value, not a pair of offset values as in the first example. Thus, depending on how the tile definition map is constructed (vertically or horizontally stacked), either a wrapped S1 or T1 value (with a specific selected offset value) In this example, S1) can be corrected. In this example, the size of the texture tile is 64 × 64 tiles. Therefore, the lapping and scaling parameters used in the bump part 1606 (OP) are 64 instead of 128 as in the first example. It should be noted that any suitable size texture tile can be used depending on the particular application in which the present invention is used. Furthermore, any suitable sized indirect texture map and processed texture can be defined using the present invention.
[0047]
FIG. 35 shows a third example of the indirect tiling method of the present invention. Similarly, reference numerals are used to designate similar parts as described above. In this example, a 2 × 4 tile definition map 1602 composed of eight 18 × 18 texel tiles is used. The indirect tile index map 1600 is the same as the index map of the first example. However, in this example, the processed tile pattern 1604 is created using only 16 × 16 texels of 18 × 18 texel tiles. Thus, as this example shows, any suitable tile size can be used regardless of the size of the tile definition.
[0048]
FIG. 36 is a logic block diagram of the example indirect tiling method described above with respect to FIGS. 32 and 33-35. As can be seen from FIG. 36, in this tiling method, the same initial texture coordinates can be used for the direct coordinates and the indirect coordinates (that is, S1 = S0, T1 = T0). However, other configurations where the coordinates are not identical are possible. For example, indirect texture coordinates that do not need to be scaled to properly accommodate the tile index map may be used. However, when using the same texture coordinates as in this example, the indirect texture coordinates 1700 (S0, T0) are first scaled, as shown in scaling blocks 1702a and 1702b. This is done to match the scale of the indirect texture index map 1600. Thereafter, lookup processing in the tile index map is performed using the appropriately scaled indirect coordinates. This is done to obtain a tile selection offset 1704 (ΔS, ΔT). To tile the desired texture, the coordinate scale is the tile size multiplied by the size of the indirect index map. The tile size is then divided and used to access the indirect map.
[0049]
The tile selection offset is scaled up to the original scale, as indicated by multipliers 1706a and 1706b, to directly correspond to the scale of texture coordinates. Then, as shown in wrapping blocks 1708a and 1708b modulo n, after the direct coordinates are wrapped, the offset can be combined with normal texture coordinates 1701 (S1, T1). The wrapped direct coordinates and scaled offset are then combined by adders 1710a and 1710b. As a result, corrected texture coordinates 1712 (S ″, T ″) are generated. Thereafter, a normal texture lookup in the tile definition map 1602 is performed using the modified texture coordinates, and thereby a tile to be output as a texture to the TEV unit is selected. The logical block diagram of FIG. 36 shows an embodiment in which the offset is given to both S1 and T1, and in this example, a two-dimensional tile definition map can be used. However, other configurations according to the present invention are possible, such as using only a one-dimensional tile index map, as in the example of FIG.
[0050]
<Example of pseudo three-dimensional texture tiling (second tiling method)>
FIG. 37 shows a more detailed block diagram of the second indirect tiling method of the present invention (see FIG. 31), referred to as a pseudo 3D texture. According to this second method, a plurality of indirectly indexed tiles can be blended together to form a composite tile that is mapped to the surface. In other words, in this method, it is possible to extend the tiling mapping to provide a pseudo 3D effect. In this way, all tiles are considered part of the stack. Rather than selecting a single tile from the tile definition map as in the first example, this example selects multiple tiles (in the example below, two adjacent tiles) and blends the tiles. Composite texture tiles can be generated. This approach can be used, for example, to cover large surfaces with discontinuous patterns that blend smoothly with one another. By allowing blending of texture tiles, the programmer is not limited to specific tiles in the tile definition map when covering the surface. Alternatively, by combining new tiles with existing tiles, the number of texture tiles available to cover the surface can be greatly increased without the need for a large texture definition map. By using synthetic tiles, the appearance of repeated texture patterns can be avoided, thereby improving the realism of the image. This method can be used for covering a beach with various layers in appearance, such as fine sand, small pebbles, and large rocks, with a tiled texture. A blending function can be used to give a pseudo three-dimensional appearance to the texture after processing.
[0051]
As shown in FIG. 37, an indirect tile index map is defined to include an index to tiles in the tile definition stack (block 1800). Indirect texture coordinates are defined (block 1802), and texture selection offsets and blending coefficients are obtained (block 1804). Texture tile definitions are defined in the form of a stack (block 1806). If a pseudo three-dimensional effect is desired, in this example, the tiles are preferably defined such that adjacent tiles are well blended together to give a hierarchical effect. This will be better understood from the following description. Of course, as described above, when it is desired to make the indirect coordinates and the direct coordinates the same, the indirect coordinates may be scaled before the indirect lookup processing.
[0052]
Direct coordinates are defined (block 1808) and combined with the offset to generate a first modified texture coordinate (s, t ′) (block 1810). The offset is then modified (biased) in a predetermined manner, such as incrementing by one tile, and then the second modified texture coordinate (s, t ″) (block 1812) is defined. Thereafter, using the first modified texture coordinates (s, t ′), the first texture is looked up in the tile definition stack to obtain a first texture tile (block 1814). Thereafter, using the second modified texture coordinates (s, t ″), the second texture is looked up in the tile definition stack to obtain a second texture tile (block 1816). The first and second texture tiles are then blended to create a composite texture (block 1818). In this example, the blending coefficient used for the blending process is acquired together with the tile selection offset from the tile index map. The composite texture is then output for display (or for use in further texture processing operations) (block 1820).
[0053]
FIG. 38 shows an example of the pseudo 3D texturing method of the present invention. In this example, texture tile index map 1900 includes an index into tile stack 1902 and a blending factor. Specifically, in this example, the tile index map includes an index that includes an integer component and a fractional component. For example, the lower left corner component of the index map 1900 is “4.9”. In this example, the integer component (ie, “4”) provides the layer selection offset and the fractional component (ie, “.9”) provides the blending factor. Thus, the indirect texture coordinates are used to look up the layer selection offset and blending coefficient. The offset is then scaled (if necessary in a particular implementation) and combined directly with the texture coordinates (after being wrapped) using bump block 1904 to produce a first modified set of texture coordinates. . The first modified texture coordinate set is then used for lookup processing in the tile definition stack 1902 to obtain the first texture tile. The bump unit also performs a bias process on the tile selection offset and generates a second modified coordinate by combining the biased offset with the wrapped direct texture coordinates. This bias processing may simply increase the offset by a specific amount, for example, for one tile, and the processed tile is different from the processed tile when no bias is applied. Any other suitable process for offset may be performed. A second tile is then looked up from the tile definition stack 1902 using the second modified set of texture coordinates. The two selected tiles are then blended together using the blending coefficients given by the indirect index tile index map 1900, thereby producing a composite texture tile that is used for the processed texture 1906. In this example, the processed texture 4.9 indicates that layer definition 4 and layer definition 5 have been blended together using a blending factor of 0.9, ie, 4.9 = 0.1 * (Layer 4 definition) + 0 · 9 * (Layer 5 definition). In this example, only one offset is given. Thus, in this example, the tile definition map is treated as a one-dimensional stack, and the offset is used to directly modify the S1 or T1 component of the texture coordinates. Other configurations are possible where the index map provides an offset pair with blending factors. In other embodiments, the blending factor may be constant or otherwise defined in a manner other than by the tile index map 1900. However, by making the blending coefficients programmable in the tile index map, it is possible to easily define other blending coefficients and generate highly diverse composite tiles. In this example, the offset bias coefficient is one tile. Thus, when the first tile is defined, the second tile is defined as the next tile in the stack. Other configurations are possible in which the bias causes the second tile to have a different relationship to the first tile.
[0054]
FIG. 39 shows an example of a logical block diagram of this second tiling method described above in connection with FIGS. As shown in FIG. 39, indirect coordinates (S0, T0) are determined and then scaled appropriately as indicated by scaling blocks 1910a and 1910b. Scaling is done for the same reasons as described above in connection with the first method of the present invention. In this example, the same value is used for the direct and indirect texture coordinates. However, as noted above, other configurations are possible, and depending on the particular implementation, the scaling process may or may not be adjusted. In this example, the scaled indirect coordinates 1908 (S0, T0) are used to perform a look-up process in the indirect texture index map 1900, and an integer 1918a representing a tile selection offset and a decimal (1918b) representing a blending coefficient, To get. Thereafter, as indicated by multiplier 1922, the integer (offset) is rescaled and sent to adder 1916a to be used directly as a texture coordinate modifier. Direct texture coordinates 1912 (S1, T1) are wrapped, as indicated by wrap blocks 1914a and 1914b modulo n. The offset is then combined with the t component of the wrapped coordinates to generate a first modified set of texture coordinates (s, t ′) and is used to look up the look in the tile definition stack 1902 Up is performed and the first texture tile (Tex1) is obtained.
[0055]
Also, a second modified set of texture coordinates is obtained using the tile selection offset given by the integer 1918a. This is done by biasing the offset, as indicated by block 1926. In this example, at the time of bias, 1 is added to the offset before the rescaling of the offset is performed by the multiplier 1922b. The biased offset is then sent to adder 1916b. The biased offset is combined by the adder 1916b directly with the wrapped t component of the texture coordinates to generate a second modified set of texture coordinates (s, t ″). The second modified set of texture coordinates is then used to perform a second lookup in the 1902 tile definition map to obtain a second texture tile (Tex2).
[0056]
Thereafter, the first texture tile (tex1) and the second texture tile (tex2) are sent to the blending block 1920. The fractional component (1918b) obtained from the indirect texture index map 1900 is carried to the blending block 1920 via the multiplexers 1924a and 1924b. Thus, thereafter, the blender has two texture tiles and a proper blending factor. A blending process is then performed and the two texture tiles are combined based on the blending coefficients to generate a composite tile that is output for display (or for use in further texture processing operations).
[0057]
<Example of API indirect texture tiling function command>
As shown in FIGS. 7-10, it is preferred to set up and activate indirect texture lookup processing and indirect texture processing using one or more graphics API functions. The API function for setting indirect texture processing as described above, and parameters for performing indirect texture tiling and pseudo 3D texture tiling may be defined as follows.
[0058]
<GXSetTevIndTile>
This function may be used to perform tiled texturing using indirect textures. Note that a normal texture map only specifies a tile definition. The actual number of texels added to the polygon is a function of the size of the base tile and the size of the indirect map. To set the proper texture coordinate scale, GXSetTexCoordScaleManually must be called. In addition, in order to use the same texture coordinates as the normal TEV stage for the indirect stage, GxSetIndTexScale is used.
[0059]

[0060]

[0061]
The above functions can be used to specify the indirect texture tiling method or the pseudo 3D texture tiling method described above. Note that the tile size and spacing can be individually specified. An example of the reason for using an interval larger than the tile size is to have a boundary for mip mapping. Depending on the height of the mipmap stack, texels outside the tile may be included in the filtering calculation for the mipmap. This function sets the matrix and scale values appropriately based on predetermined inputs. You only need to specify which matrix slot to use. The biasSel and alphaSel parameters are used only in the case of a pseudo three-dimensional lookup. These are set to GX_ITB_NONE and GX_ITBA_OFF (respectively) in the case of normal two-dimensional tiling. Note that texture tiling can use the same texture coordinates for the indirect map and the normal (direct) map. However, the desired scale value of normal texture coordinates is not directly related to the size of the normal map containing the tile definition. Usually, the size of the scale of the texture coordinates is set to the size of the map to be looked up, and when the texture coordinates are shared, the size of the normal map is preferable. Because texture tiling requires different scales, the following function can be used.
[0062]

[0063]
When GXSetCoordScaleManual is called and enable is set to GX_True, the predetermined texture coordinate scale value is fixed until the function is called again. When the function is called and enable is set to GX_False, automatic texture coordinate scaling takes over again for that texture coordinate. For texture tiling, the desired texture coordinate scale is the product of the size of the tile and the size of the indirect map. Then, using GXSetIndTexCoordScale, the tile size is divided and used to access the indirect map.
[0064]
In order to support pseudo 3D texture lookup, in this example GXSetTevIndTile must be called for two adjacent TEV stages. The first stage is similar to the normal two-dimensional tiling specification. In the second stage, bias selection and alpha selection are specified. A bias is used to select the tile stack direction. When the next tile is an S-dimensional offset, GX_ITB_S is used, and when the next tile is a T-dimensional offset, GX_ITB_T is used. A bump alpha is then selected to blend the tile from the first lookup and the tile from the second lookup. In this example, the 8-bit format cannot be used for the pseudo three-dimensional texture. Alternatively, 3, 4, and 5 bit formats can be used. Such a format uses a bias value of +1 instead of -128. Use the +1 bias to get the “next” tile of the second stage.
[0065]
<Other compatible examples>
Some of the system components 50 described above may be implemented other than the home video game console described above. For example, software such as a graphics application written for the system 50 may be run on a platform using other configurations that emulate or are compatible with the system 50. If other platforms can successfully emulate, mimic and / or provide some or all of the hardware and software resources of system 50, the other platforms will be able to successfully execute the software. Let's go.
[0066]
As an example, the emulator may provide a hardware and / or software configuration (platform) that is different from the hardware and / or software configuration (platform) of the system 50. The emulator system may include hardware and / or software components that emulate some or all of the system hardware and / or software components to which application software is written. For example, the emulator system can comprise a general purpose digital computer such as a personal computer, which executes a software emulator program that mimics the hardware and / or firmware of the system 50.
[0067]
Some general-purpose digital computers (eg, IBM or Macintosh personal computers and compatibles) currently have 3D graphics cards that provide a graphics pipeline that supports DirectX3D and other standard graphics command APIs. There are also things. They may also have a stereo sound card that provides high quality stereo sound based on standard sound commands. A computer equipped with such multimedia hardware that runs emulator software may have sufficient performance to approximate the graphics and sound performance of the system 50. The emulator software controls the hardware resources on the personal computer platform and controls the processing performance, 3D graphics performance, sound performance, peripheral performance, etc. of the home video game game console platform to which game programmers write game software. To imitate.
[0068]
FIG. 40 shows an example of the entire emulation process, which uses a host platform 1201, an emulator component 1303, and game software capable of executing a binary image provided on the storage medium 62. The host 1201 may be a general purpose or dedicated digital computing device, such as a platform with sufficient computing power, such as a personal computer or a video game console. The emulator 1303 may be software and / or hardware executed on the host platform 1201 and converts information from the storage medium 62 such as commands and data in real time into a format that can be processed by the host 1201. can do. For example, the emulator 1303 takes the “source” binary image program instructions that the system 50 is to execute from the storage medium 62 and converts the program instructions into an executable format or a format that can be processed by the host 1201.
[0069]
As an example, if the software is written to run on a platform using a specific processor such as IBM PowerPC and the host 1201 is a personal computer using a different (eg, Intel) processor, an emulator 1303 retrieves one or a sequence of binary image program instructions from the storage medium 1305 and converts these program instructions into those corresponding to Intel's binary image program instructions. In addition, the emulator 1303 can extract and / or generate graphics commands and voice commands to be processed by the graphics audio processor 114 and process them using hardware and / or software graphics and audio processing resources available on the host 1201. Convert these commands to the correct format. As an example, emulator 1303 translates these commands into commands that can be processed by specific graphics and / or sound hardware of host 1201 (eg, using DirectX, OpenGL, and / or sound APIs).
[0070]
When the specific graphics-compatible hardware in the emulator does not include the indirect texture reference function or the functions shown in FIGS. 7 to 39, the emulator designer makes one of the following selections.
Convert indirect texture reference commands into other graphics API commands that can be interpreted by graphics-capable hardware.
-Indirect texture reference is implemented in the software. In response to this, there is a possibility that performance may be reduced depending on the processing speed of the processor. Or
• “Stub” the command for indirect texture references (ie, ignore) to provide a rendered image that does not include effects using indirect texture references.
[0071]
The logical diagrams of FIGS. 36 and 39 can be implemented by all software, all hardware, and a combination of hardware and software, but in the preferred embodiment, most calculations are hard (using bump 500b). To gain speed performance and other benefits. Nevertheless, in other embodiments (eg, when a very fast processor is available), some of the processing described herein is performed in software to produce similar or identical image results. You may make it obtain.
[0072]
An emulator 1303 used to provide some or all of the functions of the video game system described above includes a graphical user interface (GUI) that simplifies or automates the selection of various options and screen modes performed using the emulator. ) May be given. As an example, such an emulator 1303 may further include extended functions compared to the host platform that the software was originally intended for.
[0073]
FIG. 41 shows an emulation host system 1201 suitable for use with the emulator 1303. The system 1201 includes a processing unit 1203 and a system memory 1205. A system bus 1207 couples various system components including the system memory 1205 to the processing unit 1203. The system 1207 may be any of several bus configurations, including those using any of a variety of bus architectures, such as a memory bus or memory controller, a peripheral bus, a local bus, and the like. The system memory 1207 includes a read only memory (ROM) 1252 and a random access memory (RAM) 1254. A basic input / output system (BIOS) 1256 includes basic routines that help to transfer information between elements within the personal computer system 1201 and is stored in ROM 1252. System 1201 further includes various drives and associated computer readable media. The hard disk drive 1209 performs reading from and writing to a magnetic hard disk 1211 (typically fixed). An additional (selectable) magnetic disk drive 1213 reads from and writes to a magnetic disk 1215 such as a removable “floppy”. The optional disk drive 1217 reads from or writes to a removable optical disk 1219 such as an optional medium such as a CDROM. The hard disk drive 1209 and the optical disk drive 1217 are connected to the system bus 1207 by a hard disk drive interface 1221 and an optical drive interface 1225, respectively. Data for the personal computer system 1201 such as instructions, data structures, program modules, and game programs that can be read by the computer is stored in a nonvolatile manner by a drive and a computer-readable medium associated therewith. In other configurations, other types of computer readable media may be used, such as media that can store data accessible by the computer (eg, magnetic cassette, flash memory card, digital video disk, Bernoulli cartridge). Random access memory (RAM), read only memory (ROM), etc.).
[0074]
Many program modules including emulator 1303 may be stored in hard disk 1211, removable magnetic disk 1215, optical disk 1219, and / or ROM 1252 and / or RAM 1254 in system memory 1205. Such program modules may include an operating system that provides graphics and sound APIs, one or more application programs, other program modules, program data, and game data. A user inputs commands and information to the personal computer system 1201 through input devices such as a keyboard 1227, a pointing device 1229, a microphone, a joystick, a game controller, a satellite antenna, and a scanner. Such an input device can be connected to the processing unit 1203 via a serial port interface 1231 coupled to the system bus 1207, but can be connected to a parallel port, a game port fire wire bus, or a universal serial bus ( USB) may be used for connection. A display device such as a monitor 1233 is also connected to the system bus 1207 via an interface such as a video adapter 1235.
[0075]
The system 1201 may also include network interface means, such as a modem 1154, for establishing communications over a network 1152, such as the Internet. The modem 1154 may be internal or external and is connected to the system bus 123 via the serial port interface 1231. Also, the local computing device 1150 (e.g., another network device 1150 (e.g., other communication path such as a wide area network 1152, dial-up, or other communication means) via the local area network 1158 may be used by the system 1201. A network interface 1156 may be provided so that it can communicate with the system 1201). System 1201 typically includes other peripheral output devices such as standard peripherals such as printers.
[0076]
In one example, the video adapter 1235 is a graphics spy that provides high-speed 3D graphics rendering in response to 3D graphics commands issued based on a standard 3D graphics application programmer interface, such as a version such as Microsoft DirectX 7.0. It may include a pipeline chipset. The stereo sound speaker set 1237 is also connected to the system bus 1207 via a sound generation interface such as a conventional “sound card”. Such an interface provides support for hardware or embedded software to generate high-quality stereophonic sounds based on sound commands provided from the bus 1207. Such hardware capabilities allow system 1201 to provide sufficient graphics and acoustic speed performance to execute software stored on storage medium 62.
[0077]
Although the present invention has been described in connection with what is presently considered to be the most realistic and optimal embodiments, the present invention is not limited to the disclosed embodiments, and is not limited by the scope of the appended claims. Should be construed as including various modifications and equivalent mechanisms included in the above.
[Brief description of the drawings]
FIG. 1 is a schematic diagram of an example of an interactive computer graphics system.
FIG. 2 is a block diagram of an example of the computer graphics system of FIG.
FIG. 3 is a block diagram of an example of the graphics and audio processor shown in FIG.
4 is a block diagram of an example of the 3D graphics processor shown in FIG.
FIG. 5 is an example of a logic flow diagram for the graphics and audio processor of FIG. 4;
FIG. 6 is a block diagram showing a logical outline of indirect texture processing according to the present invention.
FIG. 7 is a functional block diagram illustrating a simple basic example of normal (non-indirect) texture lookup.
FIG. 8 is a functional block diagram illustrating a simple basic example of indirect texture lookup.
FIG. 9 is a block diagram illustrating an outline of a physical configuration example for performing indirect texture processing according to the present invention.
FIG. 10 is a block diagram showing a logical outline of texture address (coordinate / data) processor processing.
FIG. 11 is a group of block diagrams illustrating the relative course of pixel direct coordinate data and pixel indirect texture data that are the result of interleaved direct and indirect texture processing in an example of a texturing pipeline.
FIG. 12 is a block diagram illustrating the relative course of pixel direct coordinate data and pixel indirect texture data that are the result of interleaved direct and indirect texture processing in an example of a texturing pipeline.
FIG. 13 is a group of block diagrams illustrating the relative course of pixel direct coordinate data and pixel indirect texture data that are the result of interleaved direct and indirect texture processing in an example of a texturing pipeline.
FIG. 14 is a block diagram illustrating the relative course of pixel direct coordinate data and pixel indirect texture data that are the result of interleaved direct and indirect texture processing in an example of a texturing pipeline.
FIG. 15 is a group of block diagrams illustrating the relative course of pixel direct coordinate data and pixel indirect texture data that are the result of interleaved direct and indirect texture processing in an example of a texturing pipeline.
FIG. 16 is a group of block diagrams illustrating the relative course of pixel direct coordinate data and pixel indirect texture data that are the result of interleaved direct and indirect texture processing in an example of a texturing pipeline.
FIG. 17 is a block diagram illustrating the relative course of pixel direct coordinate data and pixel indirect texture data that are the result of interleaved direct and indirect texture processing in an example of a texturing pipeline.
FIG. 18 is a block diagram illustrating the relative course of pixel direct coordinate data and pixel indirect texture data that is the result of interleaved direct and indirect texture processing in an example of a texturing pipeline.
FIG. 19 is a group of block diagrams illustrating the relative course of pixel direct coordinate data and pixel indirect texture data that are the result of interleaved direct and indirect texture processing in an embodiment of a texturing pipeline.
FIG. 20 is a group of block diagrams illustrating the relative course of pixel direct coordinate data and pixel indirect texture data that are the result of interleaved direct and indirect texture processing in an example of a texturing pipeline.
FIG. 21 is a group of block diagrams illustrating the relative course of pixel direct coordinate data and pixel indirect texture data that are the result of interleaved direct and indirect texture processing in an example of a texturing pipeline.
FIG. 22 is a flowchart showing an example of steps for performing indirect texture processing according to the present invention.
FIG. 23 is a functional processing diagram showing an example of normal (non-indirect) texture processing according to the present invention.
FIG. 24 is a functional processing diagram showing an example of both normal (non-indirect) and indirect texture processing according to the present invention.
25 is a block diagram showing a detailed example of a texture coordinate / bump processing unit shown in FIG.
26 is a block diagram illustrating a detailed example of the indirect texture lookup data / coordinate processing logic (proc) shown in FIG. 25. FIG.
FIG. 27 shows an example of a texture offset matrix used by the processing logic circuit (proc) of FIG.
FIG. 28 shows an example of a texture offset matrix used by the processing logic circuit (proc) of FIG.
29 is a block diagram showing an example of a data field format of a control logic register for controlling processing in the processing circuit of FIG. 26. FIG.
FIG. 30 is a general functional block diagram of a first tiling method according to a preferred embodiment of the present invention.
FIG. 31 is a general functional block diagram of a second tiling method according to a preferred embodiment of the present invention.
32 is a more detailed functional block diagram of the first tiling method of FIG. 30. FIG.
FIG. 33 shows three examples of the first tiling method of the present invention.
FIG. 34 shows three examples of the first tiling method of the present invention.
FIG. 35 shows three examples of the first tiling method of the present invention.
FIG. 36 is an example of the first tiling method of the present invention.
37 is a flowchart of the second tiling method of FIG. 25. FIG.
FIG. 38 is an example of a second tiling method of the present invention.
FIG. 39 is an example of a logical block diagram of a second tiling method of the present invention.
FIG. 40 illustrates another alternative embodiment.
FIG. 41 shows another alternative embodiment.

Claims (18)

A texture image having a plurality of identically sized texture elements (hereinafter referred to as texture tiles) arranged one-dimensionally or two-dimensionally, and an indirect tile index map defining a correspondence relationship between texture coordinates and the texture tiles; A method for performing texture tiling by a control unit in a graphics system accessible to storage means storing
The step of the control unit generates texture coordinates,
A correction step in which the control unit corrects the texture coordinates using the indirect tile index map;
Wherein the control unit, by using the corrected texture coordinates, step selecting the texture tile and,
The method comprising the step of the controller displaying the selected texture tile. Wherein the control unit further comprises an access step of accessing the indirect tile index map using the indirect texture coordinates A method according to claim 1. Wherein the control unit, Ru using the same values in the texture coordinates and the indirect texture coordinates A method according to claim 2. In the access step, the control section, prior to using the indirect texture coordinates, by scaling the indirect texture coordinates, that access to the indirect tile index map The method of claim 3. The indirect tile index map includes an offset value for converting the texture coordinates to coordinates in a texture tile corresponding to the texture coordinates;
In the access step, the control unit obtains an offset value by accessing the indirect tile index map using the indirect texture coordinates,
  In the correction step, the control unit corrects the texture coordinates using the offset value.
  The method according to claim 2. In the correction step, the control unit performs wrap processing on the texture coordinates, and corrects the texture coordinates by adding the texture coordinates after the wrap processing and the offset value.
  The method of claim 5. One-dimensional or two-dimensionally arranged plurality of texture elements of the same size (hereinafter, referred to as texture tile) texture tiling by the control unit in the accessible graphics system in a storage means for storing a texture image having A way to do ,
The controller directly defining a set of texture coordinates;
The controller defining a set of indirect texture coordinates;
The controller obtains an offset value using the indirect texture coordinates;
The controller combines the offset value with at least one of the direct texture coordinates to generate a first modified texture coordinate; and
The method includes the step of the controller obtaining a first texture tile from the texture image using the first modified set of texture coordinates. The storage means further stores an indirect tile index map that defines a correspondence relationship between the indirect texture coordinates and the offset value,
Wherein the control unit, you get the offset value from the indirect tile index map The method of claim 7. The method of claim 7 , wherein the indirect texture coordinates are the same as the direct texture coordinates. The controller biasing the offset value ;
The controller combines the biased offset value with at least one of the direct texture coordinates to generate a second modified set of texture coordinates;
Wherein the control unit, using the second set of modified texture coordinates, further comprising the step of acquiring the second texture tiles texture image, The method of claim 7. Wherein the control unit, the first texture tile and a blend of the second texture tiles, further comprising the step of generating a composite texture tile method according to claim 10. Wherein the control unit, blending the first texture tile and the second texture tiles using a blending factor that determines the blend ratio of the first texture tile and the second texture tiles to claim 11 The method described. The storage means further stores an indirect tile index map that defines a correspondence relationship between the indirect texture coordinates and the offset value,
Wherein the control unit obtains the offset value from the indirect tile index map, you also get the blending factor from the indirect tile index map The method of claim 12. The method according to claim 7 , wherein each texture tile included in the texture image represents a texture of each layer of a plurality of layers . A texture image having a plurality of texture elements of the same size (hereinafter referred to as texture tiles) arranged one-dimensionally or two-dimensionally, and an indirect tile index map defining a correspondence relationship between texture coordinates and the texture tiles; Is a device that can access the storage means storing the texture and performs texture tiling,
Means for generating texture coordinates,
Means for modifying the texture coordinates using the indirect tile index map;
Means for selecting the texture tile using the modified texture coordinates; and
Means for displaying the selected texture tile
With a device. A device that can access a storage means storing texture images having a plurality of texture elements of the same size (hereinafter referred to as texture tiles) arranged one-dimensionally or two-dimensionally and performs texture tiling. And
Means to directly define a set of texture coordinates ,
A means to define a set of indirect texture coordinates ,
Means for obtaining an offset value using the indirect texture coordinates ;
Means for combining the offset value with at least one of the direct texture coordinates to generate a first modified texture coordinate; and
Means for obtaining a first texture tile from the texture image using the first modified set of texture coordinates
With a device. A texture image having a plurality of texture elements of the same size (hereinafter referred to as texture tiles) arranged one-dimensionally or two-dimensionally, and an indirect tile index map defining a correspondence relationship between texture coordinates and the texture tiles; A program for causing a computer in a graphics system accessible to storage means storing the texture tiling,
  Generating texture coordinates;
  Modifying the texture coordinates using the indirect tile index map;
  Selecting the texture tile using the modified texture coordinates; and
  Displaying the selected texture tile;
  For causing the computer to execute. One-dimensional or two-dimensionally arranged plurality of texture elements of the same size (hereinafter, referred to as texture tiles) perform texture tiling storage means for storing a texture image having the computer in the accessible graphics system A program for
Defining a set of texture coordinates directly,
Defining a set of indirect texture coordinates;
Using the indirect texture coordinates to obtain an offset value;
Combining the offset value with at least one of the direct texture coordinates to generate a first modified texture coordinate; and
Obtaining a first texture tile from the texture image using the first modified set of texture coordinates ;
For causing the computer to execute.

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