JP5019059B2 - Integration circuit using switched capacitor circuit, low-pass filter, and electronic equipment - Google Patents

Description

  The present invention relates to an integrating circuit using a switched capacitor circuit, a low-pass filter, an electronic device, and the like.

The switched capacitor circuit is described in Patent Document 1, for example. Non-Patent Document 1 describes a secondary switched capacitor filter (SCF) that suppresses the spread of element values.
Japanese Patent Laid-Open No. 06-061793 IEICE technical report CAS89-163 // CS89-123 // DSP89-62 "Secondary SCF with suppressed spread of device values" Ishikawa, Anzai, Fujii

  The cut-off frequency fc of the RC integration circuit (low-pass filter: LPF) using the time constant of the input resistance (R) and the capacitance (C) is expressed as follows. fc = (1 / (2πCiR)). Ci is a feedback capacitance (integration capacitance) provided in the feedback loop of the operational amplifier. Here, it is assumed that the cut-off frequency is extremely low (for example, about 1 Hz). In this case, the capacitance value of the feedback capacitor Ci increases, and the area occupied by the circuit increases dramatically. Therefore, it is desirable to increase the resistance R.

  When the input resistor R is composed of a switched capacitor circuit, the resistance value of the resistor R is expressed as follows.

  R = 1 / (fs · Cs) (fs: sampling clock frequency, Cs: capacitance of switched capacitor). If the sampling clock frequency fs is reduced, the equivalent resistance R of the switched capacitor circuit can be increased.

  However, in practice, since the sampling clock leaks, in order to remove this, it is usual to provide a prefilter and a postfilter before and after the switched capacitor circuit. If the sampling clock frequency fs is lowered, it is necessary to narrow the band of the pre-filter and post-filter in order to remove the leakage component of the sampling clock. Then, from the above equation, it is necessary to increase the feedback capacitance Ci after all. And the area occupied by the pre-filter and post-filter increases. Therefore, the occupied area of the entire circuit including the switched capacitor circuit, the prefilter, and the postfilter cannot be reduced.

  Therefore, if a high resistance R is to be realized using a switched capacitor circuit, the capacitance value of the capacitor Cs of the switched capacitor circuit must be reduced. However, if the capacitance value of the capacitor Cs is reduced, the charge / discharge current is reduced. There is a limit because the amount is reduced and directly affected by noise.

  That is, in the integration circuit (SC integration circuit) using the switch capacitor, when the cut-off frequency fc is extremely low, the ratio (Cs / Ci) between the capacitance of the switch and the capacitor Cs and the capacitance value of the feedback capacitance Ci is set. It needs to be extremely small. However, if the size of the feedback capacitor Ci is increased, the area occupied by the circuit increases dramatically. On the other hand, when the size of the feedback capacitor Ci is reduced, there is a limit in reducing the size because the minimum size of the circuit in the IC is determined.

  The above-mentioned Non-Patent Document 1 describes that the area expansion of the switched capacitor circuit can be suppressed, but it is described that the effect of area reduction is about the square root, and there is a limit to the area expansion suppression. is there.

  The present invention has been made based on such consideration. According to some embodiments of the present invention, for example, a switched capacitor integrating circuit having a very low cutoff frequency can be realized with high accuracy without increasing the ratio of the input capacitance of the operational amplifier and the feedback capacitance of the operational amplifier. it can.

  (1) One embodiment of the present invention is an integration circuit using a switched capacitor circuit, and includes an operational amplifier, a feedback capacitor provided in a feedback path of the operational amplifier, and a signal input node and an input node of the operational amplifier. An input portion of the integration circuit provided, the input portion of the integration circuit comprising: a first switch provided between the signal input node and the first node; the first node and a reference potential; A second switch provided between the first node and the second node, and a third switch provided between the signal input node and the third node. A fourth switch provided between the third node and the reference potential, a second capacitor unit provided between the third node and the fourth node, the second node, and the second node 4 And a sixth switch provided between the fourth node and the reference potential, and provided between the second node and the input node of the operational amplifier. A first switch, wherein the first capacitor section includes a first capacitor and a second capacitor provided in series between the first node and the second node, and the first and second capacitors. A third capacitor provided between a common connection point of the two capacitors and the reference potential, and the second capacitor unit is connected in series between the third node and the fourth node. A fourth capacitor and a fifth capacitor provided; and a sixth capacitor provided between a common connection point of the fourth and fifth capacitors and the reference potential.

  In the SC circuit of the input section of the operational amplifier of the integration circuit (SC integration circuit) configured using a switched capacitor (SC) circuit, a configuration in which a plurality of capacitors are combined is employed as the capacitor circuit configuration. For example, a configuration in which one capacitor is connected between two capacitors connected in series (columns) in a signal transmission line, and a common connection node (common connection point) of these capacitors and a reference potential (for example, ground potential). Is adopted. Since this composite capacitor configuration can be regarded as a configuration in which three capacitors are connected in a T shape, it is referred to as a T configuration for convenience (however, it is not limited to the T shape).

  In a conventional switched capacitor circuit (SC circuit), for example, when first and second clocks having opposite phases are used, electric charge is accumulated in the capacitor at the timing of the first clock, and the capacitor at the timing of the second clock. The accumulated charge is discharged (discharged), and the charge transfer due to the discharge is integrated using an operational amplifier and a feedback capacitor. The charge stored in the capacitor and the charge released from the capacitor are the same.

  Here, if only a part of the charge accumulated in the capacitor is discharged and the remaining charge remains in the capacitor without being released, the amount of charge flowing into the operational amplifier is reduced. In other words, the amount of charge passing through the switched capacitor circuit is reduced, and the capacity can be made smaller when the entire input portion of the SC integration circuit is considered.

  In the T-type capacitor, the potential of one electrode of each of the two capacitors connected in series (column) to the signal transmission path can be controlled by turning on / off the switch. The potential at the connection point cannot be controlled directly. For example, if the total amount of charges at the common connection point does not change regardless of the on / off state of the switch (this is desirable, but not limited to this point), The charge accumulated in the capacitor connected between the common connection point and the reference potential does not participate in the discharge of the capacitor due to the on / off of the switch. In other words, out of all the charges accumulated in each capacitor of the T-type configuration, the charge (at least a part) accumulated in the capacitor connected between the common connection point of each capacitor and the reference potential is supplied to the integrator. It does not flow in and continues to be retained. The ratio of the amount of charge held to the total amount of charge stored in the T-type capacitor is controlled by the capacitance ratio of each capacitor if the amount of charge flowing from the input end and the output end is constant ( Change).

  By using this principle, an apparently smaller capacitance can be realized with high accuracy without using an extremely small capacitor (using a capacitor with a margin). Therefore, in the SC integration circuit of this aspect, a switched capacitor integration circuit having an extremely low cutoff frequency can be realized with high accuracy without increasing the ratio (element coefficient) between the input capacitance of the operational amplifier and the feedback capacitance of the operational amplifier. it can.

  However, when a configuration in which a plurality of capacitors are connected in a T-shape (T-type configuration) is used, it is easily affected by the parasitic capacitance because the plurality of capacitors are connected. Therefore, in order to design with higher accuracy, it is necessary to fully consider the influence of the parasitic capacitance of each capacitor. That is, when the parasitic capacitance is added to the regular capacitance, the charge amount of the total charge of the T-type capacitor changes, so that it is important to make it less susceptible to the parasitic capacitance.

  For example, a simple SC integrator circuit configuration (a circuit configuration in which one SC circuit is provided at the input of one operational amplifier) realizes a configuration that is insensitive to parasitic capacitance when a T-type capacitor is used. There is a limit in doing. Also, for example, when a circuit configuration in which a reset switch is provided to reset one of the T-type capacitors is used, when the reset switch is in an OFF state, the reset switch itself becomes a parasitic capacitance. The configuration is not insensitive to capacity.

  Therefore, in this aspect, as the circuit configuration of the SC integration circuit, two signal transmission paths are provided between the signal input node and the input node of the operational amplifier, a switched capacitor circuit is provided in each signal transmission path, and each signal transmission is performed. A configuration is adopted in which connection / non-connection between the paths is controlled by a switch, and connection / non-connection between one of the signal transmission paths and the input node of the operational amplifier is controlled by the switch. According to this circuit configuration, it is possible to compensate for the influence of parasitic capacitance by using two signal transmission paths. That is, the influence of parasitic capacitance can be minimized. Further, the circuit characteristics are completed only by the capacitance element coefficient (that is, the ratio between the input capacitance and the feedback capacitance), and the SC integration circuit itself is independent of other circuit elements, and thus, for example, Even when a high-order filter is formed, there is an advantage that circuit design is easy.

  Then, by adopting a T-type capacitor in the SC circuit of the input part of the SC integration circuit having such two signal transmission paths (at least two signal transmission paths in a broad sense), as described above. In addition, it is possible to control the movement of charges so as not to move (keep holding) a part of the total charges accumulated in the capacitor, and apparently a smaller capacity can be realized with high accuracy. Therefore, even when the cutoff frequency of the SC integration circuit is extremely low (for example, about 1 Hz), the area occupied by the circuit can be greatly suppressed.

  In addition, if an SC integration circuit having two signal transmission paths (in the broad sense, at least two signal transmission paths) is used, the influence of parasitic capacitance is minimized even when a T-type capacitor is used. Characteristics can be realized.

  In this way, the characteristics of each circuit are effectively exhibited, and by the synergistic effect, an apparently smaller capacity can be realized with high accuracy using a T-type capacitor, and the input capacity of the operational amplifier and the feedback capacity of the operational amplifier. In addition, it is possible to realize a circuit configuration that more effectively suppresses the spread of the ratio (element coefficient) and suppresses the influence of parasitic capacitance to a minimum even when a T-type configuration is employed. In addition, since the circuit characteristics are completed with the element coefficients, it is possible to obtain an effect that the circuit can be easily designed even when a high-order filter is used.

  (2) In another aspect of the present invention, each of the first switch, the fourth switch, and the fifth switch operates with a first clock, and the second switch and the third switch Each of the sixth switch and the seventh switch circuit is operated by a second clock having a phase opposite to that of the first clock.

  It is clarified whether each of the first to seventh switches operates with the first clock and the second clock that are out of phase with each other.

  (3) In another aspect of the present invention, areas of the first capacitor and the second capacitor included in the first capacitor unit are set to be the same, and the first capacitor unit includes the second capacitor unit. The areas of the fourth capacitor and the fifth capacitor are set to be the same.

  When the state of the switch changes and the potential of one electrode of each of the two capacitors connected in series to the signal transmission line among the capacitors of the T-type configuration changes, the two capacitors are accumulated. The charge moves. At this time, if the size (area) of the two capacitors is the same, the amount of charge movement of each capacitor is the same, and the movement of the charge seen from the signal input node and the movement of the charge seen from the input node of the operational amplifier are the same. Equilibrate. In this case, the total amount of charge at the common connection point of the three capacitors of the T-type configuration does not change before and after the change of the switch state, but is accumulated in the capacitor connected between the common connection point and the reference potential. The amount of charge that remains is not changed before and after the change of the switch state. The total amount of charge accumulated in each capacitor of the T-type configuration does not change before and after the change of the switch state, and the charge is preserved (that is, the charge conservation law is established). In this embodiment, the ratio of the amount of charge that is continuously held (the amount of charge accumulated in the capacitor connected between the common connection point and the reference potential) to the total amount of charge accumulated in the T-type capacitor. Can be controlled with high accuracy by the capacitance ratio of each capacitor.

  (4) In another aspect of the present invention, the shape and area of the first capacitor and the second capacitor included in the first capacitor unit are set to be the same, and the first capacitor and the The second capacitor is manufactured by a common manufacturing process, and the shape and area of the fourth capacitor and the fifth capacitor included in the second capacitor unit are set to be the same, and the fourth capacitor The fifth capacitor is manufactured by a common manufacturing process.

  By transmitting not only the capacitor area (occupied area) but also the shape (for example, the shape of the electrode, the shape of the wiring connected to the electrode, etc.) and making the manufacturing process (manufacturing process) common, signal transmission It is possible to control the relative accuracy of the two capacitors connected in series to the path with higher accuracy. Therefore, circuit design with higher accuracy is possible.

  (5) In another aspect of the invention, the areas of the first capacitor and the fourth capacitor are set to be the same, and the areas of the second capacitor and the fifth capacitor are set to be the same, The areas of the third capacitor and the sixth capacitor are set to be the same.

  Each capacitor connected in a T-type is provided in one of the two signal transmission lines, and each capacitor connected in a T-type is also provided in the other signal transmission line. In two T-type configurations, the size of capacitors at the same position is the same. As a result, the two T-type configurations can be balanced, and for example, the transfer function of the circuit can be derived by treating each SC circuit as having the same characteristics, and the circuit design is facilitated. Further, it becomes easy to compensate for the influence of the parasitic capacitance, and a circuit configuration can be obtained in which the influence of the parasitic capacitance is minimized.

  (6) In another aspect of the present invention, the first capacitor and the fourth capacitor have the same shape and area, and the first capacitor and the fourth capacitor have a common manufacturing process. The shape and area of the second capacitor and the fifth capacitor are set to be the same, and the second capacitor and the fifth capacitor are manufactured by a common manufacturing process, and the third capacitor The capacitor and the sixth capacitor have the same shape and area, and the third capacitor and the sixth capacitor are manufactured by a common manufacturing process.

  Not only the area (occupied area) of the capacitor but also the shape (for example, the shape of the electrode, the shape of the wiring connected to the electrode, etc.) and the same manufacturing process (manufacturing process) It is possible to control the relative accuracy of the capacitor at the corresponding position in the T-type configuration with higher accuracy. Therefore, circuit design with higher accuracy is possible.

  (7) In another aspect of the present invention, the sizes of the first to seventh switches are set to be the same.

  Thereby, the capacitance values of the parasitic capacitances connected to the switches can be made uniform. Therefore, for example, the transfer function of the circuit can be derived by treating each switch as the same characteristic. Therefore, it becomes easy to realize a circuit configuration that is so small that the influence of the parasitic capacitance can be ignored.

  (8) In another aspect of the invention, each of the first capacitor, the second capacitor, the third capacitor, the fourth capacitor, the fifth capacitor, and the sixth capacitor includes: A first electrode provided at a position close to the substrate and a second electrode provided at a position far from the substrate, and each of the first capacitor, the second capacitor, and the third capacitor. The second electrodes are connected in common, and the second electrodes of the fourth capacitor, the fifth capacitor, and the sixth capacitor are connected in common.

  The second electrode is located farther from the substrate (for example, a semiconductor substrate) than the first electrode. Therefore, it is difficult to be affected by parasitic capacitance caused by the substrate, the insulating film formed on the substrate, and the like. Since the potential at the common connection point of each capacitor of the T-type configuration greatly affects the amount of charges accumulated in each capacitor of the T-type configuration, the parasitic capacitance is as much as possible when trying to realize circuit characteristics with high accuracy. It is necessary to avoid the influence of. Therefore, the second electrodes of the capacitors are connected in common. On the other hand, since a low impedance node (for example, an input node (for example, an inverting terminal), a signal input node, or a ground line) of an operational amplifier is connected to the first electrode, a parasitic capacitance connected to the first electrode. Does not affect the circuit characteristics.

  (9) In another aspect of the present invention, the low-pass filter is configured using an integration circuit using the above-described switched capacitor circuit.

  In this aspect, for example, the circuit area in a low-pass filter having a low cut-off frequency can be greatly reduced. In addition, a highly accurate low-pass filter that is not easily affected by parasitic capacitance is realized.

  (10) In another aspect of the present invention, an integrating circuit using the switched capacitor circuit is mounted on an electronic device.

  Thereby, a small and high-performance electronic device can be obtained.

  Next, embodiments of the present invention will be described with reference to the drawings. Note that the present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are as means for solving the present invention. It is not always essential.

(First embodiment)
In the present embodiment, an exemplary circuit configuration and operation of an integration circuit using a switched capacitor (SC) circuit (hereinafter referred to as an SC integration circuit) will be described.

(overall structure)
FIG. 1 is a circuit diagram showing a circuit configuration of an example of an integration circuit (SC integration circuit) using a switched capacitor circuit according to the present invention.

  The SC integration circuit 50 includes an operational amplifier OPA, a feedback capacitor Ci, an input unit (SC circuit) 100 of the integration circuit, a signal input node P1 to which the input signal Vin is input, and a signal output node that outputs the output voltage signal Vout. P2.

  The input unit 100 of the integration circuit is provided with a first signal transmission path (path a) and a second signal transmission path (path b). The first signal transmission path (path a) and the second signal transmission path (path b) are connected by a node NQ. A signal transmission path between the node NQ and the inverting terminal of the operational amplifier OPA (input node of the operational amplifier) is a third signal transmission path (path c).

  Note that this circuit configuration is an example, and for example, the detailed configuration of the circuit may be modified. Further, the configuration of the capacitor portion (T-type configuration including a plurality of capacitors connected in a T shape) can be applied to a circuit different from the above-described circuit configuration. For example, the present invention can be applied to the case where two circuit configurations similar to the input part of the SC integration circuit are input in parallel.

  Further, in FIG. 1, in order to be able to accurately identify the position of each of the plurality of switches and the position of the capacitor unit (consisting of a plurality of capacitors connected in a T shape), on the signal transmission path, The first node (first node) to the fifth node (fifth node) are set. These nodes are used for convenience of explanation.

  In the SC integration circuit of FIG. 1, a plurality of switches are provided, and there are two types of switches, “1” and “2”. The switch denoted by “1” is a switch (first phase switch) that operates with the first clock CLK1. The switch denoted by “2” is a switch (second phase switch) that operates with the second clock CLK2.

  In FIG. 1, for example, a reference code such as “Sa1 (1)” is used as a switch reference code. “A” in “Sa1 (1)” indicates that it is provided in the path a, “(1)” at the end indicates that it is a first phase switch, and “1” indicates the first that is provided in the path a. This represents the first switch among the one-phase switches. The same applies to other switches.

  The switched capacitor circuit (SC circuit) included in the input unit 100 of the integrating circuit 50 includes a first switch circuit SW1, a first capacitor unit TS (1), a second switch circuit SW2, and a second capacitor. Unit TS (2), third switch circuit SW3, and fourth switch circuit SW4, and first capacitor unit TS (1) includes capacitors GA1, GA2 and GA3 connected in a T-shape. The second capacitor unit TS (2) has capacitors GB1, GB2 and GB3 connected in a T-shape. A common connection node (common connection point) of the capacitors GA1, GA2, and GA3 connected in a T shape is defined as NA1. A common connection node (common connection point) of capacitors GB1, GB2, and GB3 connected in a T shape is denoted as NB1.

  The first switch circuit SW1 and the first capacitor unit TS (1) constitute a switched capacitor (SC) circuit provided in the first signal transmission path (path a). The second switch circuit SW2 and the second capacitor unit TS (2) constitute a switched capacitor (SC) circuit provided in the second signal transmission path (path b). The third switch circuit SW3 controls connection / disconnection between the fourth node N4 and the second node N2, and connection / disconnection between the fourth node and a reference potential (for example, ground potential). The fourth switch SW4 controls connection / disconnection of the second node N2 and the fifth node (op-amp input node: inverting terminal) N5.

  In FIG. 1, in a state where the first phase switch “1” is turned on, Vin is applied to the first node N1, the second node N2 and the fourth node N4 are connected, and the third node N3 is connected to the reference potential (here, Ground potential). In this case, the first and second capacitor sections TS (1) and TS (2) are connected in series between Vin and the ground potential (GND). On the other hand, when the second phase switch “2” is turned on, the first node N1 is at the ground potential (GND) with respect to the first capacitor unit TS (1), and the second node N2 is the input node of the operational amplifier OPA. (Fifth node) Connected to N5, at this time, charge transfer occurs between the first capacitor unit TS (1) and the operational amplifier OPA. For the second capacitor unit TS (2), Vin is applied to the third node N3, and the fourth node N4 is grounded. This operation is repeated.

  More specifically, the input unit 100 of the integration circuit 50 includes a first switch (Sa1 (1)) provided between the signal input node (P1) and the first node (N1), and a first node ( N1) and a reference potential (GND), a second switch (Sa1 (2)) provided between the first node (N1) and the second node (N2) (TS (1)), the third switch (Sb1 (2)) provided between the signal input node (P1) and the third node (N3), the third node (N3) and the reference potential (GND) ) And the fourth capacitor (TS (2)) provided between the third node (N3) and the fourth node (N4). , A fifth switch provided between the second node (N2) and the fourth node (N4) (Sb2 (1)), a sixth switch (Sb2 (2)) provided between the fourth node (N4) and the reference potential (GND), the second node (N2), and an input node of the operational amplifier ( N5) and a seventh switch (Sc1 (2)).

  The first capacitor section (TS (1)) includes a first capacitor (GA1) and a second capacitor (GA2) provided in series between the first node (N1) and the second node (N2). ) And a third capacitor (GA0) provided between the common connection point (NA1) of the first and second capacitors and the reference potential (GND) (T-type circuit configuration) Configuration).

  Similarly, the second capacitor section (TS (2)) includes a fourth capacitor (GB1) and a fifth capacitor (in series) provided in series between the third node (N3) and the fourth node (N4). GB2), and a sixth capacitor (GB0) provided between the common connection point (NB1) of the fourth and fifth capacitors and the reference potential (GND) (T-type configuration (T-type) Configuration).

(Clock circuit clock)
As described above, in the SC integrator 50 of FIG. 1, the first clock (CLK1) and the first clock having the phase opposite to that of the first clock are used as the operation clocks of the first switch circuit SW1 to the fourth switch circuit SW4. Two clocks (CLK2) are used.

  Each of the first switch (Sa1 (1)), the fourth switch (Sb1 (1)), and the fifth switch (Sb2 (1)) is operated by the first clock (CLK1). Each of the second switch (Sa1 (2)), the third switch (Sb1 (2)), the sixth switch (Sb2 (2)) and the seventh switch circuit (Sc1 (2)) The clock (CLK2) is used.

(Description of the principle of the SC integration circuit of FIG. 1)
In the SC circuit 100 of the input part of the operational amplifier OPA of the integrating circuit (SC integrating circuit) 50 configured using a switched capacitor (SC) circuit, there are a plurality of circuit configurations of the capacitor units TS (1) and TS (2). A circuit configuration in which capacitors (GA0 to GA2, GB0 to GB2) are combined is employed. For example, a configuration in which one capacitor is connected between two capacitors connected in series (columns) in a signal transmission line, and a common connection node (common connection point) of these capacitors and a reference potential (for example, ground potential). Is adopted. Since this composite capacitor configuration can be regarded as a configuration in which three capacitors are connected in a T shape, it is referred to as a T configuration for convenience (however, it is not limited to the T shape).

  In a conventional switched capacitor circuit (SC circuit), for example, when first and second clocks having opposite phases are used, electric charge is accumulated in the capacitor at the timing of the first clock, and the capacitor at the timing of the second clock. The accumulated charge is discharged (discharged), and the charge transfer due to the discharge is integrated using an operational amplifier and a feedback capacitor. The charge stored in the capacitor and the charge released from the capacitor are the same.

  Here, if only a part of the charge accumulated in the capacitor is discharged and the remaining charge remains in the capacitor without being released, the amount of charge flowing into the operational amplifier is reduced. In other words, the amount of charge passing through the switched capacitor circuit is reduced, and the capacity can be made smaller when the entire input portion of the SC integration circuit is considered.

  In the T-type capacitor, one electrode (that is, the first node N1, the second node N2, the third node) of each of the two capacitors connected in series (column) to the signal transmission path by turning on / off the switch. Although the potential of the node N3 and the fourth node N4) can be controlled, the potential of the common connection point (NA1, NB1) of the three capacitors (GA0 to GA2, GB0 to GB2) cannot be directly controlled. .

  If the potential of the common connection point (NA1, NB1) does not change, for example, regardless of the on / off state of the switch (this is desirable, it is not necessarily limited to this point). The charges accumulated in the capacitors (GA0, GB0) connected between the common connection points (NA1, NB1) of each capacitor and the reference potential (for example, GND) are the switches Sa1 (1) to Sc1 (2). ) Is not involved in the discharge of the capacitor with each on / off. That is, among all the charges accumulated in the T-type capacitors (GA0 to GA2, GB0 to GB2), they are connected between the common connection point (NA1, NB1) of each capacitor and the reference potential (for example, GND). The charge (at least a part of) stored in the capacitor does not flow into the integrator (the operational amplifier OPA and the feedback capacitor ci) and continues to be held.

  The ratio of the amount of charge held to the total amount of charge stored in the T-type capacitor is determined by the input terminal (for example, the first node N1 in the case of the capacitor unit TS (1)) and the output terminal (capacitor unit). In the case of TS (1), if the amount of charge flowing from the second node N2) into the capacitor unit (for example, TS (1)) is constant, it can be freely set according to the capacitance ratio of each capacitor (for example, GA0 to GA2). Can be controlled.

  By using this principle, an apparently smaller capacitance can be realized with high accuracy without using an extremely small capacitor (using a capacitor with a margin). Further, it is possible to freely design circuit characteristics (for example, when the SC integration circuit 50 having an extremely low cutoff frequency is configured, the cutoff frequency).

  Therefore, in the SC integration circuit 50 of the present embodiment, the switched capacitor integration circuit 50 having an extremely low cutoff frequency is replaced with the ratio (element) of the input capacitance of the operational amplifier (the capacitor used in the input unit 100) and the feedback capacitance Ci of the operational amplifier OPA. It can be realized with high accuracy without increasing the coefficient.

  However, when a configuration in which a plurality of capacitors are connected in a T-shape (T-type configuration) is used, it is easily affected by the parasitic capacitance because the plurality of capacitors are connected. Therefore, in order to design with higher accuracy, it is necessary to fully consider the influence of the parasitic capacitance of each capacitor. That is, when the parasitic capacitance is added to the regular capacitance, the charge amount of the total charge of the T-type capacitor changes, so that it is important to make it less susceptible to the parasitic capacitance.

  For example, a simple SC integrator circuit configuration (a circuit configuration in which one SC circuit is provided at the input of one operational amplifier) realizes a configuration that is insensitive to parasitic capacitance when a T-type capacitor is used. There is a limit in doing. Also, for example, when a circuit configuration in which a reset switch is provided to reset one of the T-type capacitors is used, when the reset switch is in an OFF state, the reset switch itself becomes a parasitic capacitance. The configuration is not insensitive to capacity.

  Therefore, in this embodiment, as the circuit configuration of the SC integration circuit 50, for example, two signal transmission paths (path a and path b) are provided between the signal input node P1 and the input node N5 of the operational amplifier OPA. A switched capacitor (SC) circuit is provided in the signal transmission path (path a, path b), and connection / disconnection between the signal transmission paths is controlled by a switch (third switch SW3). A configuration is adopted in which connection / disconnection between the signal transmission path (second node N2 in FIG. 1) and the input node N5 of the operational amplifier (OPA) is controlled by a switch (fourth switch SW4).

  According to this circuit configuration, it is possible to compensate for the influence of parasitic capacitance by using two signal transmission paths (path a and path b). That is, the influence of parasitic capacitance can be minimized. For example, if it can be considered that the parasitic capacitance for the first capacitor unit TS (1) and the parasitic capacitance for the second capacitor unit TS (2) are the same, this can be used to make a circuit. The effect of parasitic capacitance can be made invisible.

  Further, the circuit characteristics are completed only by the capacitance element coefficient (that is, when the input capacitance is Cs and the feedback capacitance is Ci, the ratio of each capacitance (Cs / Ci)), and the SC integration circuit 50 itself Is independent of other circuit elements and is independent, and therefore has an advantage that circuit design is easy even when, for example, a high-order filter is formed.

  For example, when the SC biquad type second-order low-pass filter is configured by applying the present invention, it is necessary to change the circuit configuration of the A portion and the G portion to a configuration using a T-type capacitor. The change in the circuit configuration means that a switch and a capacitor are added to the conventional circuit in view of the entire circuit. For example, in the SC biquad type second-order low-pass filter, for example, the circuit of the G part is connected to the element D, the element C, and the element E. May be affected. That is, the transfer function may change.

  However, in the case of the SC integration circuit 50 of the present invention, when the coefficient of the conventional G portion is G and the coefficient of the G portion of the present invention is G ′, G ′ = G · k (k is an arbitrary integer). Therefore, if the coefficient is replaced from G to G ′ in the transfer function of the conventional circuit, a transfer function of a high-order low-pass filter configured using the SC integration circuit of the present invention can be obtained. Since the SC integration circuit of the present invention does not essentially change the transfer function of the conventional SC integration circuit, it only changes its coefficient, and the influence of parasitic capacitance is minimized. The characteristics of the SC integration circuit are completed with only the capacitance element coefficient and are independent, which facilitates circuit design.

  Then, by adopting a T-type capacitor in the SC circuit of the input unit 100 of the SC integrating circuit 50 having such two signal transmission paths (at least two signal transmission paths in a broad sense), As described above, it is possible to control the movement of charges so as not to move (keep holding) a part of the total charges accumulated in the capacitor, and apparently a smaller capacity can be realized with high accuracy. Therefore, even when the cutoff frequency of the SC integration circuit is extremely low (for example, about 1 Hz), the area occupied by the circuit can be greatly suppressed.

  In addition, if the SC integration circuit 50 having two signal transmission paths (in the broad sense, at least two signal transmission paths) is used, a characteristic insensitive to parasitic capacitance is realized even when a T-type capacitor is used. be able to.

  In this way, the characteristics of each circuit are effectively demonstrated, and by the synergistic effect, apparently smaller capacitance can be realized with high accuracy using a T-type capacitor, and the input capacitance of the operational amplifier and the operational amplifier Of the feedback capacitance ratio (element coefficient) can be more effectively suppressed, and even when a T-type configuration is adopted, a circuit configuration that minimizes the influence of parasitic capacitance is realized. Can do. In addition, since the circuit characteristics are completed with the element coefficients, it is possible to obtain an effect that the circuit can be easily designed even when a high-order filter is realized.

(Considerations on favorable conditions for configuring the circuit)
Hereinafter, preferable conditions for configuring the SC integration circuit of FIG. 1 will be described. FIG. 2 is a diagram for explaining an example of preferable conditions for configuring the SC integration circuit of FIG.

  In FIG. 2, the areas (sizes) of the first capacitor (GA1) and the second capacitor (GA2) included in the first capacitor part (TS (1)) are set to be the same, and the second capacitor part ( The areas (sizes) of the fourth capacitor (GB1) and the fifth capacitor (GB2) included in TS (2) are preferably set to be the same.

  That is, when the state of the switch changes and the potential of one electrode of each of the two capacitors (GA1 and GA2, GB1 and GB2) connected in series to the signal transmission path among the capacitors of the T-type configuration changes, The charge stored in each of the two capacitors moves. At this time, if the size (area) of the two capacitors (GA1 and GA2, GB1 and GB2) is the same, the amount of charge movement of each capacitor is the same, and the movement of the charge viewed from the signal input node P1 and the operational amplifier The charge movement viewed from the input node N5 is balanced.

  In this case, the potential of the common connection point (NA1, NB1) of the three capacitors of the T-type configuration does not change before and after the change of the switch state, and the common connection point (NA1, NB1) and the reference potential (for example, GND) ) Does not change before and after the change in the switch state.

  The total amount of charge accumulated in each capacitor of the T-type configuration does not change before and after the change of the switch state, and the charge is preserved (that is, the charge conservation law is established). In this case, the ratio of the charge amount that is continuously held (the charge amount of the charge accumulated in the capacitor connected between the common connection point and the reference potential) to the total charge amount accumulated in the T-type capacitor is: It is possible to control with high accuracy by the capacitance ratio of each capacitor (GA0 to GA2, GB0 to GB2).

  More preferably, the shape and area of the first capacitor (GA1) and the second capacitor (GA2) included in the first capacitor unit (TS (1)) are set to be the same, and the first capacitor ( GA1) and the second capacitor (GA2) are manufactured by a common manufacturing process, and the shapes of the fourth capacitor (GB1) and the fifth capacitor (GB2) included in the second capacitor unit (TS (2)). The fourth capacitor (GB1) and the fifth capacitor (GB2) are preferably manufactured by a common manufacturing process.

  By transmitting not only the capacitor area (occupied area) but also the shape (for example, the shape of the electrode, the shape of the wiring connected to the electrode, etc.) and making the manufacturing process (manufacturing process) common, signal transmission It is possible to control the relative accuracy of two capacitors (GA1 and GA2, GB1 and GB2) connected in series in the path with higher accuracy. Therefore, circuit design with higher accuracy is possible.

  Further, the areas of the first capacitor (GA1) and the fourth capacitor (GB1) are set to be the same, the areas of the second capacitor (GA2) and the fifth capacitor (GB2) are set to be the same, and the third The areas of the capacitor (GA0) and the sixth capacitor (GB0) are preferably set to be the same.

  Each capacitor part (TS1) connected in a T-type is provided in one signal transmission path (path a) of the two signal transmission paths, and the other signal transmission path (path b) is also in a T-type. Each connected capacitor part (TS2) is provided. In the two T-type capacitor sections, the size of capacitors at the same position is the same. As a result, the two T-type configurations can be balanced, and for example, the transfer function of the circuit can be derived by treating each SC circuit as having the same characteristics, and the circuit design is facilitated. Further, it becomes easy to compensate for the influence of the parasitic capacitance, and a circuit configuration can be obtained in which the influence of the parasitic capacitance is minimized.

  More preferably, the shape and area of the first capacitor (GA1) and the fourth capacitor (GB1) are set to be the same, and the first capacitor (GA1) and the fourth capacitor (GB1) are commonly manufactured. The shape and area of the second capacitor (GA2) and the fifth capacitor (GB2) are set to be the same, and the second capacitor (GA2) and the fifth capacitor (GB2) are common. The shape and area of the third capacitor (GA0) and the sixth capacitor (GB0) are set to be the same, and the third capacitor (GA0) and the sixth capacitor (GB0) are common. It is good to be manufactured by the manufacturing process.

  Not only the area (occupied area) of the capacitor but also the shape (for example, the shape of the electrode, the shape of the wiring connected to the electrode, etc.) and the same manufacturing process (manufacturing process) It is possible to control the relative accuracy of the capacitor at the corresponding position in the T-type configuration with higher accuracy. Therefore, circuit design with higher accuracy is possible.

  The first to seventh switches (Sa1 (1) to Sc1 (2)) are preferably set to have the same size.

  Thereby, the capacitance values of the parasitic capacitors connected to the switches (Sa1 (1) to Sc1 (2)) can be made uniform. Therefore, for example, the transfer function of the circuit can be derived by treating each switch as the same characteristic. Therefore, it becomes easy to realize a circuit configuration that is so small that the influence of the parasitic capacitance can be ignored.

  FIGS. 3A and 3B are diagrams for explaining the existence of a first electrode having a large parasitic capacitance and a second electrode having a small parasitic capacitance due to the structure of the capacitor. The first electrode ME1 is an electrode to which a large parasitic capacitance is connected, and the second electrode ME2 is an electrode having a smaller parasitic capacitance.

  That is, the second electrode ME2 is located farther from the substrate (for example, a semiconductor substrate) 98 than the first electrode ME1. Therefore, it is difficult to be affected by parasitic capacitance (Cppa, Cppb, Cpcc) caused by the substrate 98, the insulating film (field oxide film or the like) 102 formed on the substrate, and the like. Note that Cx in FIG. 3A indicates a normal capacity.

  In order to distinguish between the first electrode ME1 and the second electrode ME2, one capacitor is represented as shown in FIG.

  FIG. 4A and FIG. 4B are diagrams for explaining an example of a preferable connection in a capacitor portion having a T-type configuration. In FIG. 4A, capacitors C1, C2, and C3 constitute a T-type capacitor section. Parasitic capacitances Cpx, Cpy, Cpz are connected to the common connection point NR of the capacitors C1 to C3 having the T-type configuration. There are also parasitic capacitances Cpp1 to Cpp3.

  Here, the potential of the common connection point (NR) of the capacitors (C1 to C3) of the T-type configuration greatly influences the charge amount of the total charges accumulated in the capacitors of the T-type configuration. When achieving accuracy, it is preferable to avoid the influence of parasitic capacitance as much as possible.

  Therefore, as shown in FIG. 4B, the second electrodes ME2 of the capacitors (C1 to C3) are connected in common. On the other hand, a low-impedance node (for example, an input node (for example, an inverting terminal), a signal input node, or a ground line) of an operational amplifier is connected to the first electrode ME1, and thus is connected to the first electrode ME1. The parasitic capacitances (Cpp1 to Cpp3) do not affect the circuit characteristics and can be ignored.

  That is, in the SC integration circuit 50 of FIG. 1, the first capacitor (GA1), the second capacitor (GA2), the third capacitor (GA0), the fourth capacitor (GB1), and the fifth capacitor (GB2). ) And the sixth capacitor (GB0) each include a first electrode ME1 provided at a position close to the substrate 98 and a second electrode provided at a position far from the substrate 98. In this case, The second electrodes ME2 of the first capacitor (GA1), the second capacitor (GA2), and the third capacitor (GA0) are connected in common, and the fourth capacitor (GB1) and the fifth capacitor (GB2). ) And the second electrodes ME2 of the sixth capacitors (GB0) are connected in common.

(Description of transfer function of input unit in SC integration circuit of FIG. 1)
The transfer function of the SC circuit included in the input unit 100 of the SC integration circuit 50 of FIG. 1 will be described with reference to FIGS. If an attempt is made to design a circuit with high accuracy in consideration of the influence of parasitic capacitance, it is necessary to obtain an accurate transfer function of the circuit to be designed. In order to obtain the transfer function, sample value analysis (analysis of charge transfer between capacitors) is necessary.

1. FIG.
FIG. 5 is a diagram showing a model of the SC circuit used for deriving the transfer function of the SC circuit. In FIG. 5, C _p1 and C _p2 are parasitic capacitances of the switch, and C _p3 and C _p4 are parasitic capacitances of the capacitance.

2. FIG.
FIG. 6 is a diagram illustrating a state of the SC circuit when the first clock CLK1 is at an active level (on level). A circuit transfer function with the clock CLK1 turned on is calculated.
In FIG. 6, the potentials at the common connection point of the three capacitors connected in a T shape with respect to the reference potential (GND) are V _x1 and V _x2 , and the charges at the common connection point are Q ₀₁ , Q _Suppose that it is ₀₂ . When the charge amount of the charge Q ₀₁ is obtained, the following expressions (1) and (2) are obtained. For example, when a notation such as V _x1 ⁽¹⁾ is used, (1) on the right shoulder indicates a voltage when the first phase switch “1” is turned on. When the second phase switch “2” is in the ON state, similarly, (2) is written on the right shoulder.

Similarly, when the charge of charge Q ₀₂ is obtained, it becomes as shown in Expression (3). Further, when the charge of -Q ₁ is calculated, the equation (4) is obtained.

Here, (n-1) of -Q ₁ (n-1) in the formula (4) represents the time at (n-1) hours. When Q ₁ is obtained from the following equation (5), equation (6) is obtained.

When also calculated for Q ₂ in the same way, so that the following equation (7).

3. FIG.
FIG. 7 is a diagram illustrating a state of the SC circuit when the second clock CLK2 is at an active level (on level). A circuit transfer function with the first clock CLK1 turned on is calculated. _{Similarly, when} the charges of Q ₀₁ and Q ₀₂ are obtained, equations (8) and (9) are obtained.

When V _x1 and V _x2 at this time are obtained, they are as shown in Expression (10) and Expression (11).

Here, when Q ₁ ′ is obtained, Equation (12) is obtained.

Similarly, when Q ₂ ′ is obtained, it becomes as shown in Expression (13).

4). FIG.
FIG. 8 is a diagram for explaining a change in the circuit state when the state is shifted from the state where the first clock CLK1 is turned on to the state where the second clock CLK2 is turned on.
Consider a case where the first clock CLK1 is shifted from the on state to the second clock CLK2. Since the stored charge is stored, the following equation (14) is established.

Here, when V _x0 is solved from the equations (6), (7), (12), and (13) calculated earlier, the following equation (15) is obtained. However, in Formula (15), substitution as shown in Formula (16) and Formula (17) is performed.

5. FIG.
FIG. 9 is a diagram for explaining a change in the circuit state when the state is changed from the state in which the second clock CLK2 is turned on to the state in which the first clock CLK1 is turned on.
Conversely, consider a case where the second clock CLK2 shifts from the on state to the first clock CLK1. From the law of conservation of charge, the following formula (18) is established, and thus formula (19) is obtained.

Here, since the following formulas (20) to (22) are established, formula (23) is obtained, and formula (24) is obtained.

  Here, Expression (25) is obtained from Expression (24) and Expression (15) described above.

  Here, assuming that the same size of the capacitor and the same size of the switch are given, Equation (26) is established.

In this case, equation (27) is obtained from equation (25).

Therefore, it is only necessary to connect the capacitors so that the influence of C _p3 and C _p4 is minimized so that the capacitance is minimized at the Tx-connected Vx point. In other words, the capacitance created on the IC is composed of an electrode surface close to the substrate that is easily affected by the parasitic capacitance and an electrode surface provided at a location far from the substrate that is not easily affected by the parasitic capacitance. The Vx points to be connected are preferably connected to electrode surfaces provided at locations far from the substrate. Here, under the condition of the following formula (29), the formula (30) is established.

  Q when the technique of Non-Patent Document 1 described above is used is expressed by Expression (31).

  The expression (30) according to the present embodiment is compared with the expression (31) according to the conventional technique. Here, for example, it is assumed that the following equation (32) is established.

  For example, when the above equation (32) is established, it is possible to reduce the ratio of the feedback capacitance and the input capacitance of the integrator as compared with Non-Patent Document 1.

(Second Embodiment)
FIG. 10 is a circuit diagram showing a configuration example of a second-order low-pass filter 200 configured using the SC integration circuit of FIG.

The secondary low-pass filter 200 includes two SC integration circuits. That is, the operational amplifier OPA1, the feedback capacitor D (Ci), and the SC circuit 100 of the input unit constitute a first integration circuit. The operational amplifier OPA2, the feedback elements F and B, and the SC circuit 100 ′ of the input unit constitute a second integrating circuit. The circuit configurations of the SC circuit 100 and the SC circuit 100 ′ are basically the same.
However, in the circuit of FIG. 10, the type of switch (that is, the first phase switch “1” or the first phase switch “1”) is arranged in the upper and lower signal paths (path a and path b) in the input units 100 and 100 ′. 2 phase switch “2”) is reversed. Although this point is different from the description of FIGS. 5 to 9 (the upper and lower paths are described as being configured by the same type of switch), this difference does not affect the essence of the circuit. .

  That is, in the derivation of the transfer function, there is only a difference between V1 = V4 = 0 or V2 = V3 = 0 (circuit configuration in FIG. 10). The type of switch to be used is only reversed depending on where the transfer function is derived with reference voltage (eg, GND). Simply shift the time by half a cycle.

(Third embodiment)
FIG. 11 is a diagram for explaining an example of an electronic device equipped with the LPF 200 by the SC integrator of the present invention.

  The electronic device 1000 includes a sensor circuit 400, a display unit 550, a clock generation circuit 510, a processing unit 520 such as a CPU, a memory 530, and an operation unit 540. The sensor circuit 400 includes a sensor element 402, a low-pass filter (LPF) 200 having the circuit configuration of FIG. 10, and an A / D converter 406. Each part is mutually connected by a bus (BUS).

  The area occupied by the low-pass filter (LPF) 200 is suppressed, and as described above, highly accurate filter characteristics can be realized. For example, even when the cutoff frequency is set to an extremely low frequency (for example, 1 Hz), a small and high-performance IC can be realized. Therefore, the electronic device 1000 on which the IC (that is, the SC integration circuit in FIG. 10) is mounted is a small and high-performance electronic device.

Thus, according to some embodiments of the present invention, for example, the following effects can be obtained. However, the following effects are not always obtained at the same time, and the enumeration of the following effects should not be the basis for unduly limiting the technical scope of the present invention.
(1) It is possible to reduce the capacity ratio as compared with the prior art. If the minimum dimension of the capacity is determined, the maximum capacity value can be reduced. Therefore, the total area can be reduced.
(2) If the clock frequency is reduced, the necessary post filter or prefilter before and after the SCF is increased. However, in the present invention, the clock frequency is not changed, so that the area can be reduced even if the area of the peripheral circuit is included. is there.
(3) Since it is completed only by the capacitance element coefficient, it is independent without relation to other circuit elements, and circuit design (transfer function derivation, etc.) is easy.
(4) A switched capacitor integrating circuit with an extremely low cutoff frequency can be realized with high accuracy without increasing the ratio of the input capacitance input to the operational amplifier and the feedback capacitance fed back from the output of the operational amplifier.
(5) An apparently smaller capacitor can be realized without using an extremely small capacitor (using a capacitor with a sufficient size).
(6) Even when a T-type capacitor is used, it is possible to easily realize a circuit that minimizes the influence of parasitic capacitance.
(7) An SC integration circuit having an extremely low cutoff frequency can be realized with high accuracy.

  In addition, although this embodiment was explained in full detail, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. For example, fine adjustment of the circuit configuration such as changing the type of switch provided in the signal transmission path or slightly changing the arrangement of the elements can be performed as appropriate. As a switch, a MOS transistor switch or another type of switch can be used as appropriate. Therefore, all such modifications are included in the present invention. The T-type capacitor can be applied to various circuits (for example, an SC integrator having a general configuration).

The circuit diagram which shows the circuit structure of an example of the integration circuit (SC integration circuit) using the switched capacitor circuit of this invention The figure for demonstrating an example of the preferable conditions in comprising the SC integration circuit of FIG. FIGS. 3A and 3B are diagrams for explaining that a first electrode having a large parasitic capacitance and a second electrode having a small parasitic capacitance exist on the capacitor structure. 4A and 4B are diagrams for explaining examples of preferable connections in the capacitor portion having a T-type configuration. The figure which shows the model of SC circuit used in order to derive | lead-out the transfer function of SC circuit FIG. 6 is a diagram showing a state of the SC circuit when the first clock CLK1 is at an active level (on level). FIG. 7 is a diagram illustrating a state of the SC circuit when the second clock is at an active level (on level). The figure for demonstrating the change of the circuit state at the time of transfering from the state in which the 1st clock is on to the state in which the 2nd clock is on. The figure for demonstrating the change of a circuit state at the time of transfering from the state in which the 2nd clock is on to the state in which the 1st clock is on. The circuit diagram which shows the structural example of the secondary low pass filter comprised using the SC integration circuit of FIG. The figure for demonstrating the example of the electronic device carrying the low pass filter comprised using the SC integrator of this invention

Explanation of symbols

50 integration circuit using switched capacitor circuit, 100 operational amplifier input,
SW1 first switch circuit, TS (1) first capacitor unit,
SW2 second switch circuit, TS (2) second capacitor unit,
SW3 third switch circuit, SW4 fourth switch circuit, OPA operational amplifier,
Ci feedback capacitor, P1 signal input node, P2 signal output node

Claims (10)

An integrating circuit using a switched capacitor circuit,
An operational amplifier,
A feedback capacitor provided in the feedback path of the operational amplifier;
An input section of the integration circuit provided between a signal input node and an input node of the operational amplifier,
The input part of the integration circuit is:
A first switch provided between the signal input node and the first node; a second switch provided between the first node and a reference potential;
A first capacitor unit provided between the first node and the second node;
A third switch provided between the signal input node and a third node; a fourth switch provided between the third node and the reference potential;
A second capacitor unit provided between the third node and the fourth node;
A fifth switch provided between the second node and the fourth node; a sixth switch provided between the fourth node and the reference potential;
A seventh switch provided between the second node and the input node of the operational amplifier;
Including
The first capacitor unit includes:
A first capacitor and a second capacitor provided in series between the first node and the second node;
A third capacitor provided between a common connection point of the first and second capacitors and the reference potential;
The second capacitor unit includes:
A fourth capacitor and a fifth capacitor provided in series between the third node and the fourth node;
A sixth capacitor provided between a common connection point of the fourth and fifth capacitors and the reference potential;
An integration circuit using a switched capacitor circuit. An integrating circuit using the switched capacitor circuit according to claim 1,
Each of the first switch, the fourth switch, and the fifth switch is operated by a first clock;
Each of the second switch, the third switch, the sixth switch, and the seventh switch circuit is operated by a second clock having a phase opposite to that of the first clock.
An integration circuit using a switched capacitor circuit. An integration circuit using the switched capacitor circuit according to claim 1 or 2,
The areas of the first capacitor and the second capacitor included in the first capacitor unit are set to be the same,
The areas of the fourth capacitor and the fifth capacitor included in the second capacitor unit are set to be the same.
An integration circuit using a switched capacitor circuit. An integration circuit using the switched capacitor circuit according to claim 1 or 2,
The first capacitor and the second capacitor included in the first capacitor unit have the same shape and area, and the first capacitor and the second capacitor are manufactured by a common manufacturing process. And
The shape and area of the fourth capacitor and the fifth capacitor included in the second capacitor unit are set to be the same, and the fourth capacitor and the fifth capacitor are formed by a common manufacturing process. Manufactured,
An integration circuit using a switched capacitor circuit. An integrating circuit using the switched capacitor circuit according to any one of claims 1 to 4,
The areas of the first capacitor and the fourth capacitor are set to be the same,
The areas of the second capacitor and the fifth capacitor are set to be the same,
The areas of the third capacitor and the sixth capacitor are set to be the same.
An integration circuit using a switched capacitor circuit. An integrating circuit using the switched capacitor circuit according to any one of claims 1 to 4,
The shape and area of the first capacitor and the fourth capacitor are set to be the same, and the first capacitor and the fourth capacitor are manufactured by a common manufacturing process,
The shape and area of the second capacitor and the fifth capacitor are set to be the same, and the second capacitor and the fifth capacitor are manufactured by a common manufacturing process,
The shape and area of the third capacitor and the sixth capacitor are set to be the same, and the third capacitor and the sixth capacitor are manufactured by a common manufacturing process.
An integration circuit using a switched capacitor circuit. An integration circuit using the switched capacitor circuit according to any one of claims 1 to 6,
An integrating circuit, wherein the first to seventh switches have the same size. An integration circuit using the switched capacitor circuit according to any one of claims 1 to 7,
Each of the first capacitor, the second capacitor, the third capacitor, the fourth capacitor, the fifth capacitor, and the sixth capacitor is provided at a position close to the substrate. And a second electrode provided at a position far from the substrate,
The second electrodes of each of the first capacitor, the second capacitor, and the third capacitor are connected in common,
The second electrodes of the fourth capacitor, the fifth capacitor and the sixth capacitor are connected in common;
An integration circuit using a switched capacitor circuit.   A low-pass filter configured using the integration circuit using the switched capacitor circuit according to any one of claims 1 to 8.   The electronic device carrying the integration circuit using the switched capacitor circuit in any one of Claims 1-8.

Images