JP5018053B2 - Semiconductor wafer evaluation method - Google Patents

Description

  The present invention relates to a method for evaluating a semiconductor wafer such as a silicon wafer, and more particularly to a method for evaluating quality from electrical characteristics.

  Recently, for further miniaturization and higher performance of electronic devices, higher quality semiconductor wafers such as silicon wafers have been demanded. Along with such a trend, there is a demand for a method capable of more accurate evaluation in a semiconductor wafer evaluation method.

As a method for evaluating a semiconductor wafer, various methods are known as physical and chemical analyses, and an extremely wide range is used, and various evaluation methods are used.
Among these, the electrical property evaluation is a method close to an actual device, and is also promising from the viewpoint of sensitivity.

As a method for evaluating the electrical characteristics of, for example, a silicon wafer as a device material, GOI, lifetime, DLTS, and the like are known. In particular, GOI is an important evaluation method with sensitivity to COP and oxygen precipitation existing in CZ silicon crystals. However, in this GOI, the outermost surface of a silicon wafer is oxidized by about 20 nm, and an electrode is formed on this to evaluate the dielectric breakdown characteristics.
Although this GOI can evaluate the surface layer of the silicon wafer, there is a junction leakage current characteristic as one of the evaluation methods for the device active region (near the surface).

  Here, a general method using junction leakage current characteristics will be described. FIG. 5 is an explanatory diagram for explaining an example of a conventional evaluation method. Here, a description will be given by taking the silicon wafer 21 of P type and polished as an example.

  As shown in FIG. 5, an oxide film 22 is formed on the surface of the silicon wafer 21. After that, a part of the oxide film 22 of the silicon wafer 21 is removed to open a window, and the window 25 has a conductivity type (in this case, N type) different from the conductivity type of the semiconductor to be evaluated (eg, P type) A diffusion portion 23 is formed by diffusing the dopant, and a PN junction is formed. Then, an electrode 24 is formed on the diffusion portion 23, the back side of the silicon wafer 21 is set to GND, and a reverse bias (in this case, a positive electric field) is applied to the electrode 24. As a result, a depletion layer (space charge region) is formed toward the P-type region. At this time, the presence of defects such as heavy metals in the depletion layer generates carriers, and leakage current (leakage current) is detected by the applied voltage (see Non-Patent Document 1). The semiconductor wafer is evaluated based on this leakage current.

  However, the leakage current is usually so small that a shielded system is essential for measurement, and is easily affected by noise from the measurement system. Satisfying the measurement level of accuracy is difficult with the conventional evaluation method.

VLSI process control engineering Chapter 2 Hideki Tsuya (Maruzen, 1995)

  The present invention has been made in view of the above problems, and provides a semiconductor wafer evaluation method capable of performing junction leakage current measurement simply and more accurately and evaluating a semiconductor wafer with higher accuracy. With the goal.

In order to solve the above problems, the present invention provides a method for evaluating a semiconductor wafer, wherein at least an oxide film is formed on the surface of the semiconductor wafer, a part of the oxide film is removed to open a window, and the window is opened. A dopant having a conductivity type different from the conductivity type of the semiconductor to be evaluated is diffused, a diffusion portion is formed in the semiconductor to be evaluated to form a PN junction, and then a leakage current value I ₀ at 0 V bias and reverse bias application of leak current value I ₁ of the time, and calculates a difference [Delta] I = I ₁ -I ₀ the leakage current value I ₀ at the 0V bias leakage current value I ₁ when the reverse bias is applied, the calculated that provides method for evaluating a semiconductor wafer and evaluating the semiconductor wafer on the basis of the [Delta] I.

As described above, the present invention is an evaluation method using junction leakage current characteristics. At least, after forming an oxide film on the surface of a semiconductor wafer, a window is opened, and the conductivity type of the semiconductor to be evaluated is determined from the window. A dopant having a different conductivity type is diffused, and a diffusion portion is formed in the semiconductor to be evaluated to form a PN junction. Then, the leakage current value I ₀ at 0 V bias and the leakage current value I ₁ at the time of reverse bias application are measured, and ΔI which is a difference (I ₁ −I ₀ ) between them is calculated.

The leak current value obtained by the conventional method includes noise from the measurement system, but as described above, the leak current value I ₁ at the time of 0 V bias from the leak current value I ₁ at the time of reverse bias application. By subtracting ₀ , a value excluding noise from the measurement system can be obtained. That is, the leakage current generated by the metal contamination and defects can be measured more accurately except for the influence from the measurement system that is not related to the influence of metal contamination and the presence of defect species in the semiconductor to be evaluated. Moreover, it is extremely simple because it is only necessary to subtract the leak current value I ₀ at 0 V bias from the leak current value I ₁ at the time of reverse bias application.
Since the semiconductor wafer is evaluated based on the more accurate leakage current value ΔI, the quality of the semiconductor wafer can be evaluated with higher accuracy than the conventional evaluation method.

Then, the depletion layer width is calculated from the substrate resistance of the semiconductor to be evaluated, the depletion layer volume ΔV is calculated from the depletion layer width and the line width and line length of the diffusion portion, and the depletion layer volume ΔV, ΔI / ΔV is calculated from the difference ΔI between the leak current value I ₁ when the reverse bias is applied and the leak current value I ₀ when 0 V bias is applied, and the semiconductor wafer is evaluated from the calculated ΔI / ΔV. can Ru.

  In the first place, the leakage current value is easily affected by the size of the depletion layer, and the size of the depletion layer depends on the substrate resistance. That is, for example, if the substrate resistance of the semiconductor to be evaluated is large, the depletion layer region (volume ΔV) is also increased accordingly, and the value of the measured leakage current is accordingly increased. As described above, the value of the obtained leakage current also varies depending on the size of the substrate resistance in the semiconductor to be evaluated and the volume (measurement region) of the depletion layer.

  Thus, if the measured ΔI is normalized by the volume of the depletion layer (ΔI / ΔV) and the semiconductor wafer is evaluated from this ΔI / ΔV, the difference in leakage current due to the difference in the measurement region can be obtained. It is possible to eliminate the influence of the difference in the size of the depletion layer, and it is possible to evaluate.

At this time, the depletion layer width is calculated using the following equation (1a) and (1b), the volume ΔV of the depletion layer Ru can be calculated using the following formula (1c).

(W is the width of the depletion layer, ε _s is the dielectric constant of the semiconductor to be evaluated, V _bi is the internal potential, V is the applied voltage when measuring the leakage current, and q is the elementary charge. N _D indicates the dopant concentration of the semiconductor to be evaluated.
k represents a Boltzmann constant. T indicates temperature. N _A indicates the dopant concentration of the diffusion portion. ni represents the intrinsic carrier concentration.
ΔV represents the volume of the depletion layer. L indicates the line width and line length of the diffusion part. )

Thus, the volume ΔV of the depletion layer can be calculated using the above formulas (1a) to (1c), and ΔI / ΔV can be calculated to evaluate the semiconductor wafer. The equation (1a) is an equation for calculating the depletion layer width W, and the equation (1b) is an equation for calculating the internal potential Vbi in the above equation (1a).
Further, the expression (1c) is an expression for calculating the volume ΔV of the depletion layer from the depletion layer width W calculated by the above expression (1a) and the line width and line length (both L) of the diffusion part. .

  According to the present invention, the leakage current due to metal contamination and the presence of defect species can be estimated more accurately and easily. Furthermore, for example, it becomes possible to estimate the amount of defects / contamination by preparing a calibration curve, which is effective in improving the quality of a semiconductor wafer.

Hereinafter, embodiments of the present invention will be described, but the present invention is not limited thereto.
In recent years, higher quality semiconductor wafers have been demanded, and accordingly, a more accurate semiconductor wafer evaluation method is desired.
One method of evaluating this semiconductor wafer is to measure junction leakage current, but since the value of leakage current is usually small, it is easily affected by parasitic resistance. Due to noise from the measurement system, it is difficult to accurately measure a very small amount of leakage current by the conventional evaluation method, and it has been difficult to sufficiently satisfy the high measurement accuracy level and evaluation level that have been required in recent years.

Therefore, as a result of intensive studies on the semiconductor wafer evaluation method using the junction leakage current measurement, the present inventors have obtained a leakage current value I ₀ at 0 V bias from a leakage current value I ₁ at the time of reverse bias application. It has been found that if a semiconductor wafer is evaluated based on the subtracted value ΔI, a leak current value excluding noise caused by a measurement system that is not related to the quality in the semiconductor can be obtained. That is, the present inventors have found that a leak current value more accurate than that of the conventional method can be obtained by a simple method and a semiconductor wafer can be evaluated with higher accuracy, and the present invention has been completed.

Hereinafter, the semiconductor wafer evaluation method of the present invention will be described in detail with reference to the drawings, but the present invention is not limited thereto.
FIG. 1 is an explanatory diagram for explaining a semiconductor wafer evaluation method of the present invention. Here, a silicon wafer is taken as an example for evaluation.
In the evaluation method of the present invention, the semiconductor wafer to be evaluated is not particularly limited. For example, a polished wafer (PW) may be an evaluation target or an epitaxial wafer (EPW). In addition, for example, an SOI wafer can be an evaluation target by devising a measurement structure.

First, as shown in FIG. 1, a semiconductor wafer (here, silicon wafer 1) to be evaluated in the evaluation method of the present invention will be described.
As described above, the type of semiconductor wafer to be evaluated is not limited, and various types such as PW, EPW, and SOI wafer can be used.

When performing leakage current measurement, as shown in FIG. 1, the diffusion portion 3 is formed in the semiconductor to be evaluated, that is, in this case, in the silicon wafer. The diffusion portion 3 has a dopant having a conductivity type different from that of the silicon wafer 1 from the window 5 formed in the oxide film 2 using the oxide film 2 formed on the surface of the silicon wafer 1 as a mask. It is formed by being diffused inside the silicon wafer 1, thereby forming a PN junction.
Further, in FIG. 1, the probes are brought into contact with these diffusion parts 3 via the electrodes 4, but the probes can also be directly brought into contact with the diffusion parts 3. For example, it is possible to determine the presence or absence of an electrode in accordance with the concentration of the dopant on the surface of the diffusion portion 3.

  And the measuring apparatus 6 used for the leakage current measurement at the time of implementing the evaluation method of this invention is not specifically limited, The thing similar to what was used conventionally can be used. An example is 4200 manufactured by Keithley. It is a measuring instrument capable of measuring a minute current, and preferably has a wafer prober with noise countermeasures.

Next, the procedure of the evaluation method of the present invention will be described.
First, a semiconductor wafer to be evaluated is prepared. As described above, the type is not particularly limited, and a semiconductor wafer whose characteristics are to be evaluated can be prepared.

Then, after preparing the semiconductor wafer to be evaluated as described above, that is, the silicon wafer 1 here, the oxide film 2 is first formed on the surface of the silicon wafer 1.
This oxide film 2 serves as a mask in the subsequent dopant diffusion step. For example, a thermal oxide film may be formed, or a CVD oxide film may be stacked.

The thickness of the oxide film 2 is not particularly limited, but may be a thickness that can mask the dopant diffused by implantation thereafter, and more preferably 500 nm or more. This is because with such a thickness, the diffusion of the dopant in the oxide film can be more effectively suppressed even when glass deposition or the like is used for the diffusion of the dopant.
In accordance with various conditions, an appropriate method for forming the oxide film 2 can be appropriately determined each time.

Next, a part of the oxide film 2 is removed to form a window 5 for dopant diffusion.
For example, a window opening pattern of the oxide film 2 is formed on the resist by photolithography, and the oxide film in the window 5 portion is removed by etching using the pattern as a mask.
Etching of the oxide film 2 may be dry etching or wet etching based on HF. If it is dry etching, it can process to a finer pattern. On the other hand, the wet etching can prevent plasma damage.
Such a window opening process of the oxide film 2 can also be performed by an appropriate method according to each condition.

And if the opening to the oxide film 2 is completed, the dopant is diffused.
A dopant different from the conductivity type of the semiconductor to be evaluated is diffused into the silicon wafer 1 through the window 5 and annealed to form a PN junction. This diffusion can be performed using various methods such as ion implantation, glass deposition, coating diffusion, and the diffusion method is not particularly limited.

Since the PN junction depth depends on the annealing conditions, the junction depth can be adjusted, for example, by conducting a preliminary experiment and adjusting the time so that the desired depth is obtained.
Further, when the outermost surface concentration after diffusion is set to a high concentration of, for example, about 1E20 / cm ³ , the diffusion outermost layer remains as it is without forming the electrode 4 for the subsequent leakage current measurement. There is an advantage that it can be used as an electrode. Of course, the electrode 4 may be formed on the diffusion portion 3.

The leakage current is actually measured after the diffusion part 3 and the PN junction are formed in the silicon wafer 1 by the above procedure.
The back side of the silicon wafer 1 is connected to GND, and the other side is connected to the measuring device 6. At this time, for example, contact is made by contacting the surface of the diffusion portion 3 using a probe. As described above, the electrode 4 formed on the diffusion portion 3 can also be interposed.

For example, first, a leakage current (measurement system current level) in the 0 V state is measured (measurement of I ₀ ).
Thereafter, actual leakage current measurement is started. That is, a voltage is applied so as to be a reverse bias, and the leakage current at this time is measured (measurement of I ₁ ). The procedure for measuring the leakage current itself can be performed by a method similar to the conventional method. Further, the order of measurement is not particularly limited.
From I ₀ and I ₁ obtained as described above, a difference (I ₁ −I ₀ ) between them is calculated to calculate ΔI, and the silicon wafer 1 is evaluated based on the value of ΔI.

As described above, since the leak current value I ₀ in the 0V state is subtracted from the leak current value I ₁ when the reverse bias is applied, ΔI calculated thereby eliminates the influence of noise and the like from the measurement system. This is the leakage current value, that is, the leakage current value obtained with higher accuracy. Since the silicon wafer 1 is evaluated based on such a highly accurate leak current value ΔI, the evaluation is naturally excellent.
In this way, the leakage current due to metal contamination and defect species in the depletion layer can be captured more accurately, and the leakage current value I ₀ in the 0V state only needs to be subtracted from the measured value I ₁ when reverse bias is applied. Therefore, highly accurate evaluation can be performed very easily.

Further, in order to eliminate, for example, a measurement difference or a difference in evaluation caused by a difference in substrate resistance, it is preferable that the leakage current value be normalized by the volume of the depletion layer and evaluated.
As described above, for example, if the substrate resistance of the semiconductor to be evaluated is large, the region of the depletion layer also increases, and accordingly, the value of the leakage current also increases. Therefore, when the substrate resistance of the semiconductor to be evaluated is different, for example, even if the state of metal contamination in the semiconductor is the same for each sample, the difference in the substrate resistance has an effect, and the leakage current value differs for each sample. It is difficult to accurately grasp the contamination status.

  The inventors of the present invention have also eliminated the difference in leakage current value caused by the difference in substrate resistance by further normalizing the leakage current value ΔI obtained in the present invention with the volume ΔV of the depletion layer. And found that it can be evaluated. That is, it is possible to obtain a leak current value in which noise of the measurement system is removed, and in addition, the influence of the difference in the depletion layer region (measurement region difference) is eliminated.

An example of a method for calculating ΔI / ΔV will be described below.
ΔV can be calculated using the above-described mathematical formulas (1a) to (1c) (Japanese version of semiconductor device (Industry Books, 2004)) (Semiconductor Devices, S. M. Sze (John Wiley & Sons, Inc., 2002). ))reference).
The volume of the diffusion part is obtained from the line width, line length, and depth of the junction, and the depletion layer width W is calculated from the substrate resistance (see pages 87-88 of the Japanese version of the semiconductor device). The volume ΔV of the depletion region can be calculated from a model as shown on the page etc. (line width L ₁ and line length L _{2 of the} diffusion part (in this case, line width L ₁ = line length L ₂ = window 5 Each side length L) is determined using the depletion layer width W. An example of a depletion region is shown in FIG.

  As described above, if the evaluation method of the present invention is used, a leakage current can be obtained more accurately than before, and a semiconductor wafer can be evaluated with high accuracy. Thereby, the high evaluation level desired in recent years can be satisfied. Further, for example, by preparing a calibration curve from the evaluation result using the present invention, it becomes possible to estimate the amount of defects / contamination, which can be used for improving the quality of the semiconductor wafer.

The present invention will be described in detail below with reference to examples of the present invention, but these examples do not limit the present invention.
Example 1
The semiconductor wafer was evaluated using the evaluation method of the present invention.
As a wafer to be measured, a silicon wafer having a conductivity type P type, a diameter of 200 mm, and a crystal orientation <100> was used. In addition, boron was used as a dopant for making this silicon wafer P-type, and two types of a substrate having a low resistance of 1 Ω · cm and a high resistance of 400 Ω · cm were prepared.
In addition, the wafer is intentionally contaminated with Fe in advance. Contamination concentrations of 1E11 / cm ³ , 5E11 / cm ³ and 1E13 / cm ³ were prepared.

These silicon wafers were pyrooxidized at 1000 ° C. to form a 1 μm oxide film on the wafer surface.
Thereafter, photolithography is performed using a mask in which a large number of 0.5 mm square patterns are arranged, and window etching is performed on the oxide film with buffered HF, and openings of 0.5 mm square are formed in the oxide film at intervals of 10 mm. Formed.

  Phosphorous glass was laminated on this silicon wafer using POCL3 as a raw material. Subsequently, nitrogen annealing was performed at 1000 ° C. for 2 hours, and then the phosphorous glass was removed with HF. As a result, a PN junction was formed. At this time, the diffusion depth of phosphorus was about 2 μm.

Then, each sample wafer is set on the prober, and the leakage current is measured. This time, +3 V was applied to measure the leakage current.
Further, the leakage current value at 0V bias (that is, ΔI ₀ ) is measured, and the leakage current value I ₀ at the time of 0V bias is calculated from the leakage current value measured when + 3V is applied (that is, ΔI ₁ ). Subtraction was performed to obtain ΔI (ΔI = ΔI ₁ −ΔI ₀ ).
Note that Keithley 4200 and Vector VX-3000 were used as devices for measuring leakage current.

The results of Example 1 are shown in FIG. The leakage current value is plotted for each sample of each substrate resistance and Fe contamination concentration. It can be confirmed that the leakage current value ΔI increases as the Fe contamination concentration increases.
Then, as in the evaluation method of the present invention, it is possible to measure the leak current value ΔI more accurately by eliminating the influence of the parasitic resistance due to the measurement system by normalizing with the leak current value I ₀ at 0V bias. did it. Compared to a leakage current value I ₁ before normalization described later (see Comparative Example 1, FIG. 4), the relationship with the amount of Fe contamination can be made clearer.

(Example 2)
For the first embodiment, the maximum depletion width is calculated by using the above formulas (1a) to (1c), the volume ΔV of the depletion layer is estimated, and the leakage current value ΔI of the first embodiment is calculated as the volume ΔV of the depletion layer. (ΔI / ΔV).
In addition, ΔV calculated by the mathematical expressions (1a) to (1c) at this time is
The low resistance product had ΔV = 506313 μm ³ (depletion layer width W = 2 μm), and the high resistance product had ΔV = 2661187 μm ³ (depletion layer width W = 10 μm).

The results of Example 2 are shown in FIG.
As can be seen by comparing FIG. 2 of the first embodiment and FIG. 3 of the second embodiment, the difference in the volume ΔV of the depletion layer, that is, the difference in the substrate resistance is obtained by normalizing ΔI with the volume ΔV of the depletion layer. The result of eliminating the influence on the leak level can be obtained. It can be seen from FIG. 3 that the leak levels are almost the same in the case of high resistance and low resistance.
In this way, it can be concluded that the influence of Fe on the leakage current is about the same in the present sample wafers having different resistivity because they are almost at the same level.

(Comparative Example 1)
The leak current was measured in the same manner as in Example 1 except that the leak current value I ₀ at ₀ V bias was normalized. That is, as a measurement result, the leakage current value I ₁ measured when +3 V was applied was simply plotted. The result is shown in FIG.

  As shown in FIG. 4, it can be confirmed that the leakage current value increases as the Fe contamination concentration increases. However, as described above, the leakage current value obtained by such a conventional method includes noise from the measurement system. Such an influence should be included, and it is difficult to satisfy the high level of accuracy required in recent years in the evaluation of semiconductor wafers only from the results of such simple measurements.

In particular, when the current value is extremely small, as can be seen from the case of the low resistance in FIG. 2 of Example 1 and FIG. 4 of Comparative Example 1, the ratio of the influence from the measurement system increases and a large difference occurs in the leakage current value. End up. Naturally, such a difference in measurement accuracy of the leakage current affects the evaluation of the sample wafer performed based on the leakage current value. As in the evaluation method of the present invention, it is possible to evaluate the sample wafer with higher accuracy by eliminating the noise due to the measurement system and obtaining a more accurate leak current value, and at the time of 0 V bias. Since it is only necessary to normalize with the current value I ₀ in FIG.

  The present invention is not limited to the above embodiment. The above-described embodiment is an exemplification, and the present invention has substantially the same configuration as the technical idea described in the claims of the present invention, and any device that exhibits the same function and effect is the present invention. It is included in the technical scope of the invention.

It is explanatory drawing for demonstrating the evaluation method of the semiconductor wafer of this invention. 4 is a graph showing measurement results in Example 1. 6 is a graph showing measurement results in Example 2. 10 is a graph showing measurement results in Comparative Example 1. It is explanatory drawing for demonstrating the evaluation method of the conventional semiconductor wafer. It is explanatory drawing which shows the model of a depletion area | region when calculating | requiring the volume (DELTA) V of a depletion area | region.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Silicon wafer, 2 ... Oxide film, 3 ... Diffusion part, 4 ... Electrode,
5 ... Window, 6 ... Measuring instrument.

Claims (1)

A method for evaluating a semiconductor wafer,
At least an oxide film is formed on the surface of the semiconductor wafer, a part of the oxide film is removed to open a window, and a dopant having a conductivity type different from the conductivity type of the semiconductor to be evaluated is diffused from the window, and the evaluation is performed. After forming a diffusion part in a semiconductor to form a PN junction, a leakage current value I ₀ at 0 V bias and a leakage current value I ₁ at the time of applying a reverse bias are measured, and the leakage current value at the time of applying the reverse bias When calculating a difference ΔI = I ₁ −I ₀ between I ₁ and the leakage current value I ₀ at the time of 0V bias and evaluating the semiconductor wafer based on the calculated ΔI ,
The depletion layer width is calculated from the substrate resistance of the semiconductor to be evaluated using the following formulas (1a) and (1b), and the volume ΔV of the depletion layer is calculated from the depletion layer width and the line width and line length of the diffusion portion as follows: Calculated using the equation (1c), ΔI / ΔV from the volume ΔV of the depletion layer and the difference ΔI between the calculated leak current value I ₁ when reverse bias is applied and the leak current value I ₀ when 0 V bias is applied And evaluating the semiconductor wafer from the calculated ΔI / ΔV .

(W is the width of the depletion layer, ε _s is the dielectric constant of the semiconductor to be evaluated, V _bi is the internal potential, V is the applied voltage when measuring the leakage current, and q is the elementary charge. N _D indicates the dopant concentration of the semiconductor to be evaluated.
k represents a Boltzmann constant. T indicates temperature. N _A indicates the dopant concentration of the diffusion portion. ni represents the intrinsic carrier concentration.
ΔV represents the volume of the depletion layer. L indicates the line width and line length of the diffusion part. )

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