JP5017946B2 - Evaluation method of SOI wafer - Google Patents

Description

  The present invention relates to a technique applied when evaluating an SOI layer and a BOX layer of a semiconductor silicon wafer having an SOI structure and their interfaces.

  Recently, higher-quality SOI wafers are required for further miniaturization and higher performance of electronic devices. Therefore, the quality of SOI wafers such as SOI layers has been actively evaluated. As a conventional evaluation method for evaluating a semiconductor silicon wafer having an SOI structure, for example, a pseudo-MOSFET (Pseudo-MOSFET) method has been proposed (see, for example, Patent Documents 1 and 2 and Non-Patent Documents 1 and 2).

  In this evaluation method, as shown in FIG. 6, a needle probe is directly contacted as an electrode for evaluation as an FET on the surface of the SOI wafer W including the SOI layer 21, the BOX layer 22, and the base wafer 23, that is, on the SOI layer 21 side. Or contact mercury electrodes to make them source and drain electrodes. Then, the wafer back surface is vacuum-sucked on a stage that is also used as an electrode, or a needle probe is brought into contact with the back surface to form a gate electrode 24, and various electrical characteristics are obtained by applying a voltage between these electrodes. It is an evaluation method.

  On the other hand, in recent years, an attempt has been made to improve the carrier mobility (hole mobility) by producing an SOI layer having a plane orientation different from that of the base wafer on the BOX layer in the SOI structure. Such an effect cannot be evaluated at the wafer level by the evaluation method using only a contact of the needle or a mercury electrode.

JP 2001-60676 A JP 2001-267384 A S. Cristaleveanu et al. "A Review of the Pseudo-MOS Transistor in SOI Wafers: Operation, Parameter Extraction, and Applications" IEEE Trans. Electron Dev, 47 1018 (2000). H. J. et al. Hovel, “Si film electrical charac- terization in SOI substrates by HgFET technologies” Solid-State Electronics, 47, 1311 (2003).

  The present invention has been made in view of the above problems, and the present invention provides an evaluation method capable of stably and accurately evaluating electrical characteristics along a predetermined direction, in particular, a predetermined plane orientation. There is.

  In order to achieve the above object, the present invention is a method for evaluating an SOI wafer using a pseudo MOSFET, wherein an SOI layer of an SOI wafer is processed to produce a MESA structure at least along a predetermined direction, A metal electrode is formed on both ends of the MESA structure along the predetermined direction, a measurement probe is brought into contact with the metal electrode, and a current path is limited by the MESA structure along the predetermined direction. An SOI wafer evaluation method is provided, wherein the evaluation is performed by flowing along a predetermined direction (Claim 1).

In this way, if the SOI layer of the SOI wafer is processed, a MESA structure is formed at least along a predetermined direction, metal electrodes are formed at both ends, measurement probes are brought into contact, and measurement is performed using a pseudo MOSFET. The current path can be limited by the MESA structure along the predetermined direction, and the drain current can flow only in the predetermined direction. For this reason, it is possible to obtain directly the electrical characteristic along a predetermined direction.
Further, in the conventional method in which, for example, the needle probe is simply applied to the SOI layer, even if the source electrode and the drain electrode can be arranged in a predetermined direction, an extra direction other than the predetermined direction is provided. Since current also flows to the surface, the measurement accuracy decreases. On the other hand, in the evaluation method of the present invention, since current can be passed only in a predetermined direction to be reliably measured by the MESA structure, more accurate data can be obtained.

The predetermined direction is not particularly limited and can be appropriately determined according to the purpose and condition of measurement. In particular, the predetermined direction is set as a predetermined plane orientation of the SOI layer. (Claim 2).
In this way, if the predetermined direction is a predetermined plane orientation of the SOI layer, that is, a plane orientation to be evaluated (for example, plane orientation <110>), current can flow along the plane orientation. Electrical characteristics can be evaluated directly. In this way, electrical characteristics of a predetermined plane orientation can be measured with high accuracy, and accurate evaluation according to the plane orientation can be provided in response to recent demand.

At this time, it is preferable that the MESA structure along the predetermined direction is manufactured based on the orientation flat or the notch.
Thus, if the MESA structure along a predetermined direction is manufactured based on the orientation flat or the notch, the MESA structure can be manufactured easily and surely along the desired direction. Electrical characteristics along the direction can be accurately measured.

The metal electrode is preferably made of a metal material that forms ohmic contact with the SOI layer.
As described above, the metal electrodes formed at both ends of the MESA structure are made of a metal material that forms ohmic contact with the SOI layer, thereby enabling a good contact with less contact resistance and reducing measurement errors. can do. Therefore, it is possible to stably and accurately obtain electrical characteristics along a predetermined direction.

  As described above, according to the present invention, electrical characteristics along a predetermined direction can be obtained accurately and stably. In particular, by producing a MESA structure along a predetermined plane orientation, electrical characteristics along the plane orientation can be obtained directly, and accurate evaluation can be provided.

Hereinafter, embodiments of the present invention will be described, but the present invention is not limited thereto.
In recent years, for example, in an SOI structure, an attempt has been made to improve carrier mobility by forming an SOI layer having a plane orientation different from that of a base wafer on a BOX layer.
However, as an evaluation method of an SOI wafer, for example, as described above, there is an evaluation method in which a needle probe is simply brought into contact with an SOI layer as a source electrode or a drain electrode, or a mercury electrode is brought into contact. In the conventional method, the effect of improving the carrier mobility described above could not be evaluated.

  Therefore, as a result of the inventors' diligent research on the evaluation method of SOI wafers, in the conventional evaluation method, when the drain current is measured by applying a voltage to each electrode, the direction in which the drain current flows is determined. It is not considered, and more specifically, it is not measured in consideration of the relationship between the plane orientation and the direction in which the drain current flows. Even if the contact direction of the needle probe is narrowed, the drain current is allowed to flow only in a predetermined direction. It was not possible to measure accurately. For this reason, the conventional evaluation method cannot accurately evaluate the characteristics of the plane orientation.

In order to accurately evaluate the electrical characteristics according to a predetermined plane orientation, the inventors of the present invention processed the SOI layer to produce a MESA structure along the direction to be evaluated, that is, the predetermined plane orientation. Then, if metal electrodes are formed at both ends of the MESA structure, and these metal electrodes are used as a source electrode and a drain electrode, the MESA structure along the predetermined plane direction becomes a drain current path. It was considered that current can be passed only in a predetermined plane orientation, and electrical characteristics along the plane orientation can be obtained directly and evaluated accurately.
The present inventors found these things and completed the present invention.

Hereinafter, an SOI wafer evaluation method of the present invention will be described in detail with reference to the drawings.
In the evaluation method of the present invention, for example, an evaluation element as shown in FIG. 1 is produced, and an SOI wafer is evaluated using the element.
As shown in the cross-sectional view of FIG. 1A, this evaluation element 7 is manufactured by processing an SOI wafer W having an SOI structure, and includes a MESA structure 8 and a BOX layer 2 formed by processing the SOI layer 1. , The base wafer 3, the gate electrode 4 formed on the back surface of the base wafer, the drain electrode and the source electrode (metal electrode 5) formed on the MESA structure 8.

  Here, as shown in the plan view of FIG. 1B, the MESA structure 8 can be formed, for example, in an H shape when the evaluation element 7 is viewed from above. The H-shaped MESA structure 8 includes a horizontal bar portion 8a and vertical bar portions 8b positioned at both ends of the MESA structure 8, and the horizontal bar portion 8a is used when measuring by applying a voltage to each electrode. A metal electrode 5 serving as a source electrode and a drain electrode is formed on the upper surface of the vertical bar portion 8b, which is a portion serving as a drain current path.

  The horizontal bar portion 8a is formed along a predetermined direction to be measured, and therefore, the drain current can flow along the predetermined direction. For example, when measuring the drain current flowing along a certain plane orientation of the SOI layer 1, the direction of the horizontal bar portion 8a (that is, the direction connecting the vertical bar portions 8b on both sides) is along the plane orientation to be evaluated. An H-shaped MESA structure 8 is fabricated.

  More specifically, for example, in the case of FIG. 1C, the horizontal bar portion 8a has a surface orientation <110> so that the drain current flowing along the surface orientation <110> to be evaluated can be measured. The MESA structure 8 is fabricated along This is because, for example, the orientation of the orientation flat portion 9 parallel to the orientation <110> is produced by making the horizontal bar portion 8a of the MESA structure 8 have a predetermined angle (in this case, parallel), and the orientation to be evaluated. It can be produced along <110>.

  Further, for example, as shown in FIG. 1D, the horizontal bar portion 8a ′ is in that direction so that the drain current flowing along the direction to be evaluated, that is, the direction of 45 degrees from the plane orientation <110> can be measured. A MESA structure 8 ′ is produced along For example, a direction to be evaluated by making the horizontal bar portion 8a ′ of the MESA structure 8 ′ at a predetermined angle (45 degrees in this case) with respect to the orientation flat portion 9 ′ parallel to the plane orientation <110>. It can be produced along (the direction from the plane orientation <110> to 45 degrees).

In the above example, the orientation relationship between the predetermined direction (plane orientation) to be evaluated (the orientation of the horizontal bar portions 8a and 8a 'of the MESA structures 8 and 8') and the orientation flat portions 9 and 9 'is parallel, 45 degrees, etc. However, it is not limited to this direction and can be set as appropriate depending on the direction to be measured, the manufacturing conditions of the SOI wafer, and the like. The MESA structures 8 and 8 ′ may be formed along a predetermined direction to be accurately evaluated.
In addition, an example is described in which the orientation flat is used as a reference so as to be along a predetermined plane orientation, but it is naturally possible to make it along a predetermined plane orientation according to another reference. However, if the orientation flat or notch is used as a reference, the MESA structure can be produced in a desired direction relatively easily and accurately.

  FIG. 2 shows an example of the size of the horizontal bar portion 8a. The size of the horizontal bar 8a is not limited to that shown in FIG. 2, but the width W and the length L are necessary for the later FET characteristic analysis, so this size changes with each measurement. It is necessary to manage not to. In this way, if the size and the like of the horizontal bar portion 8a are managed, the evaluation can be performed with a constant condition, and stable and accurate data can be provided.

The MESA structure 8 is not limited to the H-shaped shape as shown in FIG. Another shape may be an I-shape as shown in FIG. Also in the case of this I shape, electrodes 5 ″ are formed on the upper surfaces of both end portions of the MESA structure 8 ″, and the drain current path is limited by the MESA structure 8 ″, and the drain current is supplied in a predetermined direction. It can be shed.
As described above, the shape of the MESA structure 8 is not particularly limited as long as the shape allows the drain current to flow only in a predetermined direction. It can be freely determined each time according to the processing conditions.

And the MESA structure 8 should just be produced according to the predetermined direction which a shape and direction want to evaluate as mentioned above, The production method is not specifically limited. For example, in the case of the shape of FIG. 1, a MESA structure 8 can be manufactured by forming an H-shaped pattern in the SOI layer 1 by etching and etching it.
As described above, the method for manufacturing the MESA structure 8 can be appropriately determined in consideration of cost, process time, and the like, and it is sufficient that the MESA structure 8 can be manufactured in a desired shape and direction.

Next, the metal electrode 5 will be described.
As described above, the metal electrodes 5 are formed at both ends of the MESA structure 8 manufactured by processing the SOI layer 1, and serve as a source electrode and a drain electrode, respectively. In the H-type MESA structure 8 as shown in FIG. 1, the metal electrode 5 is formed on the upper surface of the vertical bar portion 8b.

  And as a material of this metal electrode 5, Al etc. are mentioned. For example, if the metal electrode 5 is formed of Al, ohmic contact with the SOI layer 1 can be formed, and handling is easy. Of course, other metal materials can be used, but if they are in ohmic contact with the SOI layer 1, a better contact can be obtained and stable measurement can be performed.

In selecting such a metal material that can make ohmic contact with the SOI layer 1, that is, silicon, for example, non-patent literature, edited by Takashi Katoda: Semiconductor Evaluation Technology (Industry Books, Inc., 1989) pages 142-143. Can be helpful.
Moreover, the formation method of the metal electrode 5 is not specifically limited, For example, it can form by sputtering or vapor deposition. The formation method can be determined each time in consideration of cost, process time, and the like.

As described above, the metal electrode 5 can be freely selected for its formation method and material in consideration of the cost and process time required for formation, as well as ensuring ohmic contact and obtaining more stable and accurate measurement data. It can be made as. By using such a metal electrode 5, it becomes possible to perform measurement with high accuracy and stability.
The same can be said for the gate electrode 4 formed on the back surface of the base wafer.

Then, in the evaluation method of the present invention, the evaluation element 7 as described above is manufactured, the measurement probes are brought into contact with the electrode portions 4 and 5 of the evaluation element 7, and the MESA structure 8 ( In particular, in FIG. 1, the drain current flowing through the horizontal bar portion 8a) is measured, and the electrical characteristics of the SOI layer 1 in a predetermined direction to be evaluated are evaluated.
For example, the drain current is monitored by changing the drain voltage to 0.2 V and changing the gate voltage from 0 V to −20 V. The measurement of the Id-Vg characteristic can be performed by a method similar to the conventional method.
Then, from the Id-Vg characteristics obtained by the measurement, for example, by using the mathematical formulas shown in Non-Patent Document 1 and Non-Patent Document 2, the hole mobility, electron mobility, and the like of the SOI layer 1 are obtained. Can be evaluated.

  As described above, in the present invention, since the MESA structure 8 is fabricated by processing the SOI layer 1 in advance before measuring the Id-Vg characteristic, the drain current path can be limited. For example, in the example shown in FIG. 1, the MESA structure 8 is formed so that the H-shaped horizontal bar portion 8a is along a predetermined direction to be evaluated, so that the drain current is limited to the predetermined direction to be evaluated. Is possible. Therefore, the electrical characteristics in a predetermined direction can be evaluated directly and with high accuracy.

  On the other hand, the current path cannot be limited by the MESA structure 8 as described above in the case of a conventional evaluation method using a mercury electrode or simply contacting a needle probe as a drain electrode and a source electrode to the SOI layer. It is not possible to directly obtain electrical characteristics according to a predetermined direction. In addition, even if the direction connecting the contact positions of the needle probe as the drain and the source is along a predetermined direction, when the measurement is performed by actually applying a voltage, the current may flow in an extra direction other than the predetermined direction. The current that flows and flows only in a predetermined direction cannot be measured accurately. Therefore, the measurement accuracy is lowered and an accurate evaluation result cannot be obtained.

On the other hand, in the evaluation method of the present invention, for example, by producing the H-type MESA structure 8, the drain current can surely flow only in a predetermined direction, so that the electrical characteristics in the predetermined direction can be accurately obtained. be able to. In particular, it is preferable because data in a predetermined plane orientation can be obtained.
As described above, as a method for improving the carrier mobility, a method of manufacturing an SOI layer having a plane orientation different from that of the base wafer has been performed in recent years, but the effect of the conventional method could not be evaluated. However, according to the present invention, it is possible to accurately evaluate the electrical characteristics along a predetermined plane orientation, that is, to capture the characteristics of the plane orientation, and to sufficiently evaluate the above effects.

(Example 1, Example 2)
As a sample wafer, two silicon SOI wafers having a P type, a diameter of 200 mm, and the same plane orientation of the SOI layer were prepared. The dopant of this P-type wafer is boron. The thicknesses of the SOI layer / BOX layer are about 100 nm / 145 nm, respectively.

These two types of sample wafers were evaluated by the method of the present invention.
The following processing is performed to measure the Id-Vg characteristics.
First, photolithography is performed so as to be along a predetermined plane orientation and direction of the SOI layer to be evaluated with respect to the orientation flat, that is, in parallel with <110> in the first embodiment, and in the second embodiment. Then, after preparing an H-shaped resist pattern with an offset of <110> by 45 degrees, an H-shaped MESA structure was fabricated using TMAH. The size of the H type is as shown in FIG. Further, the orientation relationship between the orientation flat and the MESA structure, each plane orientation, and the like are as shown in FIG. 1C in the first embodiment and as shown in FIG. 1D in the second embodiment.
Thereafter, Al is vapor-deposited by an evaporation method, patterned so that the Al layer remains only at both ends and the back electrode portion of the H-type MESA structure, and then subjected to sintering treatment with a gas containing hydrogen at 400 ° C. for 30 minutes. It was.

The electrodes at both ends of the H-type MESA structure formed in this way were connected to the source and drain sides of the tester, respectively. Further, the electrode on the back surface of the sample wafer formed in the same manner was connected to the gate side of the tester.
In this state, the drain voltage was set to 0.2 V, and the drain voltage was monitored when the gate voltage was scanned from 0 V to −20 V in the negative direction. The measurement result of the Id-Vg characteristic thus obtained is shown in FIG.

As shown in FIG. 4, different Id-Vg curves such as Id1 (Example 1) and Id2 (Example 2) are obtained.
By performing the analysis shown in Non-Patent Document 1 from the Id-Vg characteristics, the electron mobility at the SOI layer / BOX layer interface and the interface state can be evaluated. The hole mobility is Id1: 120 (Example 1), Id2: 150 (Example 2) (cm ² V ⁻¹ s ⁻¹ ).
As described above, the evaluation method of the present invention was able to reliably capture the characteristics of the plane orientation and evaluate the electrical characteristics corresponding to the predetermined plane orientation.

(Example 3, Comparative Example 1)
A silicon SOI wafer similar to that in Example 2 was prepared as a sample wafer. The dopant of the P-type wafer is boron, and the SOI layer / BOX layer has a thickness of about 100 nm / 145 nm, respectively.

These sample wafers are offset by 45 degrees in a predetermined direction in which the H-type MESA structure is to be evaluated, that is, in the same way as in the evaluation method of the present invention (Example 3: Example 2), that is, in the plane orientation <110>. And a MESA structure in a circular shape, that is, the current path is not limited, and the evaluation is performed by the conventional evaluation method (Comparative Example 1) using a pseudo MOSFET in which a metal probe is just in contact. went.
The Id-Vg characteristic was measured by monitoring the drain voltage when the drain voltage was 0.2 V and the gate voltage was scanned from 0 V to -20 V in the negative direction. The measurement result of the Id-Vg characteristic thus obtained is shown in FIG.

As shown in FIG. 5, different Id-Vg curves are obtained as Id3 (Comparative Example 1) and Id4 (Example 3).
By performing the analysis shown in Non-Patent Document 1 based on the Id-Vg characteristics, the electron mobility at the SOI layer / BOX layer interface and the interface state can be evaluated. The hole mobility is Id3: 125 (Comparative Example 1), Id4: 150 (Example 3) (cm ² V ⁻¹ s ⁻¹ ).

Thus, in Example 3 in which the same sample wafer as in Example 2 was evaluated in the same manner using the evaluation method of the present invention, the characteristics in the same plane direction were reliably captured. It can be seen that the mobility is the same value, and that the electrical characteristics of a predetermined plane orientation can be obtained very accurately and stably by the evaluation method of the present invention.
On the other hand, in Comparative Example 1, the two probes were simply brought into contact with the circular MESA structure, and the measurement was performed without considering the plane orientation, and the two probes were linearly connected. Since a current flows in a direction other than the connecting direction, a measurement error is likely to occur, and the values are different from those in the second and third embodiments. Such a conventional measurement method cannot capture the characteristics of the plane orientation and cannot obtain a stable evaluation according to the plane orientation.

  The present invention is not limited to the above embodiment. The above-described embodiment is an exemplification, and the present invention has substantially the same configuration as the technical idea described in the claims of the present invention, and any device that exhibits the same function and effect is the present invention. It is included in the technical scope of the invention.

It is a schematic block diagram which shows an example of the element for evaluation used with the evaluation method of the SOI wafer of this invention. (A) It is sectional drawing. (B) It is a top view. (C) It is a perspective view which shows an example of the relationship between a MESA structure and orientation flat when measuring the drain current which flows into the direction along a surface orientation <110>. (D) It is a perspective view which shows an example of the relationship between a MESA structure and orientation flat when measuring the drain current which flows into the direction of 45 degree | times from a surface orientation <110>. It is a top view which shows an example of the size of a H-type MESA structure. It is a schematic block diagram which shows another example (I type shape) of the element for evaluation used with the evaluation method of SOI wafer of this invention. (A) It is sectional drawing. (B) It is a top view. . It is a graph which shows the Id-Vg characteristic in Example 1 and Example 2. FIG. It is a graph which shows the Id-Vg characteristic in Example 3 and Comparative Example 1. It is explanatory drawing explaining the evaluation method of the conventional SOI wafer.

Explanation of symbols

1, 21 ... SOI layer, 2, 22 ... BOX layer, 3, 23 ... Base wafer,
4, 24 ... gate electrode, 5, 5 '' ... metal electrode (drain electrode, source electrode),
7 ... evaluation element, 8, 8 ', 8''... MESA structure,
8a, 8a '... H-shaped horizontal bar part, 8b ... H-shaped vertical bar part, 9, 9' ... Orientation flat,
W ... SOI wafer.

Claims (4)

  A method for evaluating an SOI wafer using a pseudo MOSFET, wherein an SOI layer of an SOI wafer is processed, a MESA structure is formed at least along a predetermined direction, and both ends of the MESA structure along the predetermined direction are formed. Forming a metal electrode, bringing a measurement probe into contact with the metal electrode, and limiting the current path with the MESA structure along the predetermined direction, thereby evaluating the drain current flowing along the predetermined direction. A method for evaluating a featured SOI wafer.   The SOI wafer evaluation method according to claim 1, wherein the predetermined direction is a predetermined plane orientation of the SOI layer.   3. The SOI wafer evaluation method according to claim 1, wherein the MESA structure along the predetermined direction is formed with reference to an orientation flat or a notch. 4. The method for evaluating an SOI wafer according to claim 1, wherein the metal electrode is made of a metal material that forms an ohmic contact with the SOI layer. 5.

Images